Semiconductor device including vertical channel region

Abstract

A semiconductor device is provided. The semiconductor device comprises: a substrate; a first gate structure and a second gate structure spaced apart from each other on the substrate; a back gate structure disposed between the first gate structure and the second gate structure and spaced apart from the first and second gate structures; a first structure including a first vertical channel region extending in a vertical direction; and a second structure including a second vertical channel region extending in the vertical direction and spaced apart from the first structure. At least a portion of the first vertical channel region is disposed between the first gate structure and the back gate structure, and at least a portion of the second vertical channel region is disposed between the second gate structure and the back gate structure.

Description

Technology Field

[0001] The present invention relates to a semiconductor device including a vertical channel region and a method for manufacturing the same. Background Technology

[0003] Research is underway to reduce the size of the components constituting semiconductor devices and improve their performance. For example, in DRAM, research is being conducted to reliably and stably form reduced-size components; however, as the size of these components decreases, it is becoming increasingly difficult to implement transistors with the desired performance. The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved performance. means of solving the problem

[0007] A semiconductor device according to one embodiment of the technical concept of the present invention is provided. The semiconductor device comprises: a substrate; a first gate structure and a second gate structure spaced apart from each other on the substrate; a back gate structure disposed between the first gate structure and the second gate structure and spaced apart from the first and second gate structures; a first structure including a first vertical channel region extending in a vertical direction; and a second structure including a second vertical channel region extending in the vertical direction and spaced apart from the first structure. At least a portion of the first vertical channel region is disposed between the first gate structure and the back gate structure, and at least a portion of the second vertical channel region is disposed between the second gate structure and the back gate structure.

[0008] A semiconductor device according to one embodiment of the technical concept of the present invention is provided. The semiconductor device comprises: a substrate; a first structure on the substrate comprising a first horizontal portion and a pair of first vertical portions extending vertically from the first horizontal portion and spaced apart from each other; a second structure on the substrate comprising a second horizontal portion and a pair of second vertical portions extending vertically from the second horizontal portion and spaced apart from each other; a pair of first gate structures disposed between the pair of first vertical portions on the first horizontal portion and each extending horizontally; a pair of second gate structures disposed between the pair of second vertical portions on the second horizontal portion and each extending horizontally; and a back gate structure disposed between the first structure and the second structure.

[0009] A semiconductor device according to one embodiment of the technical concept of the present invention is provided. The semiconductor device comprises: a first memory cell array; a second memory cell array spaced apart from the first memory cell array; and a back gate control circuit disposed on at least one side of each of the first and second memory cell arrays. Each of the first and second memory cell arrays comprises transistors, word lines, bit lines, information storage structures, and back gate lines, wherein the back gate lines cross the first and second memory cell arrays and are electrically connected to the back gate control circuit, wherein the bit lines extend in a first direction, wherein the word lines and the back gate lines are parallel to each other, spaced apart from each other, and extend in a second direction perpendicular to the first direction, wherein the transistors comprise a first pair of transistors sharing a first lower source / drain and a second pair of transistors sharing a second lower source / drain, wherein a first back gate line of one of the back gate lines is disposed between the first pair of transistors and the second pair of transistors, and each of the first pair of transistors further comprises a vertical channel region on the first lower source / drain and an upper source / drain on the vertical channel region. Effects of the invention

[0011] According to embodiments, a semiconductor device may be provided comprising vertical channel regions that may be floating bodies, and a back gate line disposed between such vertical channel regions. Since the back gate line can suppress or prevent the floating body effect, the electrical characteristics of the semiconductor device can be improved. The back gate line can minimize or prevent fluctuations in the threshold voltage of the transistors comprising the vertical channel regions. Therefore, the back gate line can enable the transistors to operate stably. Accordingly, by disposing of a back gate line between the vertical channel regions, a semiconductor device can be provided that improves electrical characteristics and enhances integration density.

[0012] According to embodiments, a gate electrode covering at least three sides of each of the vertical channel regions, i.e., a gate electrode of a tri-gate structure, may be disposed. Such a semiconductor device may include transistors that are tri-gate structures and may be FinFETs of vertical channel structures, and may include the back gate line, thereby improving performance.

[0013] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0015] FIGS. 1, FIGS. 2a, and FIGS. 2b are conceptual drawings illustrating a semiconductor device according to an embodiment of the present invention. FIG. 3a is a top view conceptually showing a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 3b is a top view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 3c is a top view conceptually showing a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 3d is a top view conceptually showing a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 4a is a top view conceptually showing a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 4b is a top view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 4c is a top view conceptually showing a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 4d is a top view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 5a is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 5b is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 5c is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 5d is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 6a is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 6b is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 7a is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 7b is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 8a is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 8b is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a conceptual perspective view showing an example of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a conceptual perspective view showing another example of a semiconductor device according to one embodiment of the present invention. FIGS. 11 and FIGS. 12 are conceptual drawings illustrating modified examples of a semiconductor device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. FIGS. 14a to 14j are cross-sectional views conceptually illustrating exemplary examples of a method for forming a semiconductor device according to one embodiment of the present invention. FIG. 15a is a circuit diagram conceptually showing an example of a semiconductor device according to one embodiment of the present invention. FIG. 15b is a circuit diagram conceptually showing a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 16 is a circuit diagram conceptually showing a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 17 is a circuit diagram conceptually showing a modified example of a semiconductor device according to one embodiment of the present invention. FIG. 18 is a circuit diagram conceptually illustrating a modified example of a semiconductor device according to one embodiment of the present invention. Specific details for implementing the invention

[0016] In the following, terms such as "upper," "middle," and "lower" may be replaced with other terms, such as "first," "second," and "third," to describe the components of the specification. While terms such as "first," "second," and "third" may be used to describe various components, they are not limited by these terms, and "first component" may be named "second component."

[0017] With reference to FIGS. 1, 2a, and 2b, a semiconductor device according to an embodiment of the present invention will be described. In FIGS. 1, 2a, and 2b, FIG. 1 is a conceptual perspective view of a semiconductor device according to an embodiment of the present invention, FIG. 2a is a top view of the perspective view of FIG. 1, and FIG. 2b is a conceptual cross-sectional view showing an area taken along the line A-A' of FIG. 1.

[0018] Referring to FIGS. 1, FIGS. 2a and FIGS. 2b, a semiconductor device (1) according to one embodiment may include a substrate (5), structures (20a, 20b), gate structures (30), and a back gate structure (40).

[0019] The substrate (5) may be a semiconductor substrate. For example, the substrate (5) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (5) may be provided as a bulk semiconductor wafer, a semiconductor substrate including an epitaxial layer, a Silicon On Insulator (SOI) substrate, or a Semiconductor On Insulator (SeOI) substrate, etc.

[0020] The semiconductor device (1) may further include a device isolation region (10) that defines active regions (15a, 15b). The device isolation region (10) may be formed of an insulating material. The active regions (15a, 15b) may have a P-type conductivity. The active regions (15a, 15b) may be formed in a shape that protrudes in a vertical direction (Z) from the substrate (5).

[0021] In one example, the substrate (5) may be a single-crystal silicon substrate. The active regions (15a, 15b) may extend vertically from the substrate (5) and may be formed of single-crystal silicon.

[0022] The structures (20a, 20b) may be placed on the substrate (5). The structures (20a, 20b) may be placed on the active regions (15a, 15b).

[0023] The above structures (20a, 20b) may be spaced apart from each other. The above structures (20a, 20b) may be arranged repeatedly with regularity along a first direction (X) and a second direction (Y). The first direction (X) may be parallel to the upper surface of the substrate (5). The second direction (Y) may be parallel to the upper surface of the substrate (5) and intersect with the first direction (X).

[0024] The above structures (20a, 20b) may also be described as "semiconductor structure," "channel semiconductor structure," "channel structure," or "body structure."

[0025] The above structures (20a, 20b) may include a material that can be used as a channel of a transistor, for example, a semiconductor material. For example, the above structures (20a, 20b) may be formed of a semiconductor material such as silicon. The above structures (20a, 20b) may be formed of single-crystal silicon or polysilicon. However, the above structures (20a, 20b) are not limited to semiconductor materials such as silicon, but may be formed of other semiconductor materials that can be used as a channel region of a transistor. For example, the above structures (20a, 20b) may include an oxide semiconductor layer or a two-dimensional material layer that can be used as a channel region of a transistor.

[0026] The oxide semiconductor layer above may be IGZO (indium gallium zinc oxide). However, the examples are not limited thereto. For example, the oxide semiconductor layer comprises IWO (Indium Tungsten Oxide), ITGO (Indium Tin Gallium Oxide), Indium Aluminum Zinc Oxide (IAGO), Indium Gallium Oxide (IGO), Indium Tin Zinc Oxide (ITZO), ZTO (zinc tin oxide), IZO (indium zinc oxide), ZnO, IGSO (indium gallium silicon oxide), Indium Oxide (InO), Tin Oxide (SnO), Titanium Oxide (TiO), Zinc Oxide (ZnON), Magnesium Zinc Oxide (MgZnO), Indium Zinc Oxide (InZnO), Indium Gallium Zinc Oxide (InGaZnO), Zirconium Indium Zinc Oxide (ZrInZnO), Hafnium Indium Zinc Oxide (HfInZnO), Tin Indium Zinc Oxide (SnInZnO), Aluminum Tin Indium Zinc Oxide (AlSnInZnO), Silicon Indium Zinc Oxide (SiInZnO), and zinc. It may include at least one of tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO).

[0027] The above two-dimensional material layer may include at least one of a TMD material layer (Transition Metal Dichalcogenide material layer), a black phosphorous material layer, and an hBN material layer (hexagonal Boron-Nitride material layer). For example, the above two-dimensional material layer may include at least one of BiOSe, Crl, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P(black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D materials capable of forming a two-dimensional material.

[0028] Each of the above structures (20a, 20b) may be formed of a single semiconductor layer or a plurality of semiconductor layers. For example, each of the above structures (20a, 20b) may include at least one of a silicon semiconductor layer, an oxide semiconductor layer, and a two-dimensional material layer.

[0029] The above structures (20a, 20b) may include a first structure (20a) and a second structure (20b) adjacent to each other in one direction, for example, a first direction (X).

[0030] Each of the above structures (20a, 20b) may include a horizontal portion and at least one vertical portion extending in the vertical direction (Z) from at least a portion of the horizontal portion. Here, each of the above structures (20a, 20b) may include one vertical portion extending upward from at least one side in the longitudinal direction of one of the horizontal portions, but is not limited thereto. For example, each of the above structures (20a, 20b) may include a pair of vertical portions extending upward from both sides in the longitudinal direction of one of the horizontal portions.

[0031] In the following description, the invention is described with reference to a vertical portion extending upward from at least one side in the longitudinal direction of one of the horizontal portions, but the invention is not limited thereto and may include a pair of vertical portions extending upward from both sides in the longitudinal direction of one of the horizontal portions. For example, the first structure (20a) may include a first horizontal portion (20H1) and a first vertical portion (20V1) extending upward from one side in the longitudinal direction of the first horizontal portion (20H1), and the first structure (20a) may further include another first vertical portion having the same structure and shape as the first vertical portion (20V1) extending upward from the other side in the longitudinal direction of the first horizontal portion (20H1). Likewise, the second structure (20b) may include a second horizontal portion (20H2) and a second vertical portion (20V2) extending upward from a part of the second horizontal portion (20H2). The first vertical portion (20V1) and the second vertical portion (20V2) may be adjacent to each other in the second direction (Y).

[0032] Each of the above structures (20a, 20b) may include a vertical channel region extending in a vertical direction (Z) perpendicular to the upper surface of the substrate (5). For example, the first structure (20a) may include a first vertical channel region (20c1) extending in the vertical direction (Z), and the second structure (20b) may include a second vertical channel region (20c2) extending in the vertical direction (Z).

[0033] Each of the above structures (20a, 20b) may further include source / drains. The source / drains may have an N-type conductivity. For example, the first structure (20a) may further include a first source / drain (20sd1) and a second source / drain (20sd2) spaced apart from each other, and the second structure (20b) may further include a third source / drain (20sd3) and a fourth source / drain (20sd4) spaced apart from each other. The first source / drain (20sd1) may be placed below the first vertical channel region (20c1), and the second source / drain (20sd2) may be placed on the first vertical channel region (20c1). The third source / drain (20sd3) may be positioned below the second vertical channel area (20c2), and the fourth source / drain (20sd4) may be positioned on the second vertical channel area (20c2).

[0034] The first source / drain (20sd1) is positioned within the first horizontal section (20H1) and may extend into the lower region of the first vertical section (20V1). The second source / drain (20sd2) may be positioned within the upper region of the first vertical section (20V1). The first vertical channel region (20c1) may be positioned within the first vertical section (20V1) between the first source / drain (20sd1) and the second source / drain (20sd2). The third source / drain (20sd3) is positioned within the second horizontal section (20H2) and may extend into the lower region of the second vertical section (20V2). The fourth source / drain (20sd4) may be positioned within the upper region of the second vertical section (20V2). The second vertical channel region (20c2) may be positioned between the third source / drain (20sd3) and the fourth source / drain (20sd4) within the second vertical portion (20V2).

[0035] The above gate structures (30) may include a first gate structure (30a) and a second gate structure (30b) spaced apart from each other.

[0036] The gate structures (30) may intersect the horizontal portions (20H1, 20H2) of the structures (20a, 20b). For example, the gate structures (30) may extend across the horizontal portions (20H1, 20H2) of the structures (20a, 20b). For example, in a top view, the first gate structure (30a) may extend across the first horizontal portion (20H1), and the second gate structure (30b) may extend across the second horizontal portion (20H2).

[0037] Each of the above gate structures (30) may include a gate dielectric layer (32) and a gate electrode (34) on the gate dielectric layer (32). For example, the first gate structure (30a) may include a first gate dielectric layer (32) and a first gate electrode (34), and the second gate structure (30b) may include a second gate dielectric layer (32) and a second gate electrode (34).

[0038] The gate dielectric layer (32) may include at least one of a low-k dielectric, silicon oxide, and a high-k dielectric. Here, the low-k dielectric may be a dielectric having a dielectric constant lower than that of silicon oxide, and the high-k dielectric may be a dielectric having a dielectric constant higher than that of silicon oxide. The high-k dielectric may be composed of a metal oxide or a metal oxynitride. For example, the high-k dielectric may be composed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto. The gate dielectric layer (32) may be formed as a single layer or a multilayer of the aforementioned materials.

[0039] The gate electrode (34) may comprise Dought polysilicon, a metal, a conductive metal nitride, a metal-semiconductor compound, a conductive metal oxide, graphene, a carbon nanotube, or a combination thereof. For example, the gate electrode (34) may comprise Dought polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiAlC, TaAlC, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be made of graphene, carbon nanotubes, or a combination thereof, but is not limited thereto. The gate electrode (34) may be formed as a single layer or multiple layers of the aforementioned materials.

[0040] The first gate dielectric layer (32) of the first gate structure (30a) may be positioned between the first gate electrode (34) of the first gate structure (30a) and the first vertical portion (20V1). For example, the first gate dielectric layer (32) of the first gate structure (30a) may be positioned between the first gate electrode (34) of the first gate structure (30a) and the first vertical channel region (22c1) of the first vertical portion (20V1). The first gate dielectric layer (32) of the first gate structure (30a) may be in contact with a portion of the side of the first gate electrode (34) of the first gate structure (30a) and the first vertical channel region (22c1) of the first vertical portion (20V1).

[0041] The second gate dielectric layer (32) of the second gate structure (30b) may be positioned between the second gate electrode (34) of the second gate structure (30b) and the second vertical portion (20V2). For example, the second gate dielectric layer (32) of the second gate structure (30b) may be positioned between the second gate electrode (34) of the second gate structure (30b) and the second vertical channel region (22c2) of the second vertical portion (20V2). The second gate dielectric layer (32) of the second gate structure (30b) may be in contact with a portion of the side of the second gate electrode (34) of the second gate structure (30b) and the second vertical channel region (22c2) of the second vertical portion (20V2).

[0042] The back gate structure (40) may be positioned between the first and second gate structures (30a, 30b). The back gate structure (40) may extend between the first and second gate structures (30a, 30b) and between the first and second vertical sections (20V1, 20V2). One back gate structure (40) may be positioned between the first and second vertical sections (20V1, 20V2). That is, one back gate structure (40) may be positioned between the first and second gate structures (30a, 30b) that are adjacent to each other.

[0043] The back gate structure (40) may include a back gate electrode (44) and a back gate dielectric layer (42). The back gate dielectric layer (42) may include a first portion (42 located on the left in FIG. 2a and 2b) positioned between the back gate electrode (44) and the first vertical portion (20V1), and a second portion (42 located on the right in FIG. 2a and 2b) positioned between the back gate electrode (44) and the second vertical portion (20V2).

[0044] The back gate dielectric layer (42) may include at least one of a low-k dielectric, silicon oxide, and a high-k dielectric. The high-k dielectric may be composed of a metal oxide or a metal oxynitride. For example, the high-k dielectric may be composed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto. The back gate dielectric layer (42) may be formed as a single layer or multiple layers of the aforementioned materials.

[0045] In one example, the back gate dielectric layer (42) may be formed of the same material as the gate dielectric layer (32).

[0046] In another example, at least a portion of the back gate dielectric layer (42) may be formed of a material different from the material of the gate dielectric layer (32).

[0047] In one example, the back gate dielectric layer (42) can be formed with substantially the same thickness as the gate dielectric layer (32).

[0048] In another example, the back gate dielectric layer (42) may be formed with a thickness different from that of the gate dielectric layer (32).

[0049] The back gate electrode (44) may comprise Dought polysilicon, a metal, a conductive metal nitride, a metal-semiconductor compound, a conductive metal oxide, graphene, a carbon nanotube, or a combination thereof. For example, the back gate electrode (44) may comprise Dought polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiAlC, TaAlC, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be made of graphene, carbon nanotubes, or a combination thereof, but is not limited thereto. The back gate electrode (44) may be formed as a single layer or multiple layers of the aforementioned materials.

[0050] In one example, the back gate electrode (44) may be formed of the same material as the gate electrode (34).

[0051] In another example, at least a portion of the back gate electrode (44) may be formed of a material different from the material of the gate electrode (34).

[0052] In another example, the back gate electrode (44) may have a different work function than the gate electrode (34). For example, the gate electrode (34) may be formed of a conductive material having a first work function, and the back gate electrode (44) may be formed of a conductive material having a different work function than the first work function. For example, the gate electrode (34) may include an NMOS work function metal layer, and the back gate electrode (44) may include a PMOS work function metal layer. In another example, the gate electrode (34) may include a first NMOS work function metal layer, and the back gate electrode (44) may include a second NMOS work function metal layer having a different work function than the first NMOS work function metal layer. Here, "NMOS work function metal layer" can be defined as a metal layer capable of adjusting or controlling the threshold voltage of an NMOS transistor, and "PMOS work function metal layer" can be defined as a metal layer capable of adjusting or controlling the threshold voltage of a PMOS transistor.

[0053] In one example, the back gate electrode (44) can be formed with substantially the same thickness as the gate electrode (34).

[0054] In another example, the back gate electrode (44) may be formed with a thickness different from that of the gate electrode (34).

[0055] The back gate structure (40) may come into contact with the first and second vertical portions (20V1, 20V2). For example, in the back gate dielectric layer (42) of the back gate structure (40), the first portion (42 located on the left in FIG. 2a and 2b) may come into contact with a portion of the side of the first vertical channel region (22c1) of the first vertical portion (20V1), and the second portion (42 located on the right in FIG. 2a and 2b) may come into contact with a portion of the side of the second vertical channel region (22c2) of the second vertical portion (20V2).

[0056] The gate structures (30) may be vertically overlapped with the horizontal portions (20H1, 20H2) of the structures (20a, 20b), and the back gate structure (40) may not be vertically overlapped with the structures (20a, 20b). The gate structures (30) may be vertically overlapped with the first and third source / drains (22sd1, 22sd3) located within the horizontal portions (20H1, 20H2), and the back gate structure (40) may not be vertically overlapped with the first and third source / drains (22sd1, 22sd3) located within the horizontal portions (20H1, 20H2).

[0057] Each of the first and second vertical parts (20V1, 20V2) may include first and second sides (20S1, 20S2) facing each other in the first direction (X), and third and fourth sides (20S3, 20S4) facing each other in the second direction (Y). In each of the first and second vertical parts (20V1, 20V2), the side in contact with the gate structures (30) may be referred to as the first side (20S1), and the side in contact with the back gate structure (40) may be referred to as the second side (20S2). Alternatively, the first vertical portion (20V1) may be described as including the first to fourth sides (20S1, 20S2, 20S3, 20S4), and the second vertical portion (20V2) may be described as including fifth to eighth sides corresponding to each of the first to fourth sides (20S1, 20S2, 20S3, 20S4). For example, the first side (20S1) of the first vertical part (20V1) may be in contact with the first gate structure (30a), the second side (20S2) of the first vertical part (20V1) may be in contact with the back gate structure (40), the fifth side of the second vertical part (20V2) may be in contact with the second gate structure (30b), and the sixth side of the second vertical part (20V2) may be in contact with the back gate structure (40).

[0058] The first and second source / drains (22sd1, 22sd2), the first vertical channel region (22c1), and the first gate structure (30a) can form a first transistor, and the third and fourth source / drains (22sd3, 22sd4), the second vertical channel region (22c2), and the second gate structure (30b) can form a second transistor.

[0059] The above back gate structure (40) can adjust or control the threshold voltage of the first and second transistors.

[0060] The back gate electrode (44) and the gate electrodes (34) may be spaced apart from each other and electrically separated. The back gate electrode (44) may be electrically insulated or isolated from the gate electrodes (34).

[0061] In FIGS. 1 and 2a, the gate electrodes (34) and the back gate electrode (44) are shown extending in the second direction (Y), and the length direction of each of the horizontal parts (20H1, 20H2) is shown as being in the first direction (X), but is not limited thereto. For example, the length direction of each of the horizontal parts (20H1, 20H2) may be perpendicular to the second direction (Y), but is not limited thereto, and the length direction of each of the horizontal parts (20H1, 20H2) may be a slanted direction that is not perpendicular to the second direction (Y). Accordingly, in the various embodiments below, even if the length direction of each of the horizontal parts (20H1, 20H2) is shown as being perpendicular to the second direction (Y), it can be described that the length direction of each of the horizontal parts (20H1, 20H2) may be a slanted direction that is not perpendicular to the second direction (Y).

[0063] In the above-described embodiment, the semiconductor device (1) may include, on the substrate (5), the first gate structure (30a) and the second gate structure (30b) spaced apart from each other; one back gate structure (40) disposed between the first gate structure (30a) and the second gate structure (30b) and spaced apart from the first and second gate structures (30a, 30b); the first structure (20a) including the first vertical channel region (22c1) extending in the vertical direction (Z); and the second structure (20b) including the second vertical channel region (22c2) extending in the vertical direction (Z) and spaced apart from the first structure (20a). At least a portion of the first vertical channel region (22c1) may be disposed between the first gate structure (20a) and the back gate structure (40), and at least a portion of the second vertical channel region (22c2) may be disposed between the second gate structure (30b) and the back gate structure (40). The first gate structure (30a) may include a first gate electrode (34) and a first gate dielectric layer (32) interposed between at least the first gate electrode (34) and the first structure (20a), the second gate structure (30b) may include a second gate electrode (34) and a second gate dielectric layer (32) interposed between at least the second gate electrode (34) and the second structure (20b), and the back gate structure (40) may include a back gate electrode (44) and a back gate dielectric layer (42) covering the sides of the back gate electrode (44).

[0064] In the case where the semiconductor device (1) is a memory device, the gate electrodes (34) may be word lines, and the back gate electrode (44) may be a back gate electrode. In the case where the semiconductor device (1) is a memory device, the semiconductor device (1) may be a DRAM, and the first and second transistors may be cell transistors of memory cells of the DRAM. Accordingly, the gate structures (30) may be described as cell gate structures, the gate electrode (34) may be described as a cell gate electrode, and the gate dielectric layer (32) may be described as a cell gate dielectric layer.

[0065] The semiconductor device (1) may be a DRAM, but is not limited thereto. For example, the semiconductor device (1) may be a memory device other than a DRAM, such as an MRAM or FeRAM.

[0066] The back gate structure (40) can control charges accumulated within the first and second vertical channel regions (22c1, 22c2) during the operation of the first and second transistors. Thus, the back gate structure (40) can suppress or prevent a floating body effect. For example, the first and second vertical channel regions (22c1, 22c2) may be floating bodies because they are positioned between source / drains that are spaced apart from each other in the vertical direction (Z). Therefore, the back gate structure (40) can minimize or prevent the threshold voltage of the first and second transistors from fluctuating as charges, e.g. holes, accumulate within the floating bodies of the first and second vertical channel regions (22c1, 22c2) during the operation of the first and second transistors. Thus, the back gate structure (40) can enable the first and second transistors to operate stably.

[0067] By placing one back gate structure (40) between the first and second gate structures (30a, 30b) that are adjacent to each other, the overall planar area of ​​the semiconductor device (1) can be reduced and the integration density improved. Accordingly, the back gate structure (40) can improve the electrical performance of the semiconductor device (1) and increase the integration density of the semiconductor device (1).

[0069] Hereinafter, various modified examples of the components of the semiconductor device (1) described above will be explained. The various modified examples of the components of the semiconductor device (1) described below will be explained focusing on the modified components or the replaced components. In addition, the modified or replaceable components described below will be explained with reference to their respective drawings, but the modified components may be combined with each other or combined with the components described above to form the semiconductor device (1) according to the embodiment of the present invention.

[0070] First, various modified examples of a semiconductor device (1) according to an embodiment of the present invention will be described with reference to FIGS. 3a, 3b, 3c, 3d, 4a, 4b, 4c, 4d, 5a, 5b, 5c, 5d, 6a, 6b, 7a, 7b, 8a, and 8b, respectively. In FIGS. 3a to 8b, FIGS. 3a to 3d and FIGS. 4a to 4d are top views corresponding to the top view of FIG. 2a, and are drawings for explaining components that can be modified from the top view of FIG. 2a.

[0071] In a modified example, referring to FIG. 3a, in each of the first and second gate structures (30a, 30b), the gate dielectric layer (32 in FIG. 2a) and the gate electrode (34 in FIG. 2a) described above can be modified as the gate dielectric layer (32a) and gate electrode (34a) in FIG. 3a.

[0072] The gate electrode (34a) may be extended to cover at least a portion of each of the third and fourth sides (20S3, 20S4) while covering the first side (20S1) of each of the first and second vertical portions (20V1, 20V2). Accordingly, the gate electrode (34a) may include a first electrode portion (34_1) covering the first side (20S1) of each of the first and second vertical portions (20V1, 20V2), and a second electrode portion (34_2) covering at least a portion of each of the third and fourth sides (20S3, 20S4). The gate dielectric layer (32a) may include a first dielectric portion (32_1) in contact with the first side (20S1) of each of the first and second vertical portions (20V1, 20V2), and a second dielectric portion (32_2) in contact with at least a portion of each of the third and fourth sides (20S3, 20S4).

[0073] The first to fourth aspects (20S1, 20S2, 20S3, 20S4) may also be described as aspects of the respective first and second vertical channel regions (22c1, 22c2) of FIG. 1 and FIG. 2b.

[0074] In one example, the second electrode portion (34_2) may cover half of each of the third and fourth sides (20S3, 20S4) or cover a portion smaller than half of each of the third and fourth sides (20S3, 20S4). For example, the second electrode portion (34_2) may cover half or a portion smaller than half of the third side (20S3) and half or a portion smaller than half of the fourth side (20S4).

[0075] Accordingly, the first gate structure (30a) can cover three faces of the first vertical part (20V1), namely the first face (20S1), the third face (20S3), and the fourth face (20S4), and the second gate structure (30b) can cover three faces of the second vertical part (20V2), namely the first face (20S1), the third face (20S3), and the fourth face (20S4). Accordingly, the first and second gate structures (30a, 30b) may be tri-gate structures capable of improving gate controllability.

[0076] Accordingly, the transistors comprising the first and second gate structures (30a, 30b) and the first and second vertical channel regions (22c1, 22c2 in FIG. 1 and FIG. 2b) may be FinFETs of a vertical channel structure in which a channel between the source and the drain is formed in a vertical direction. Accordingly, the semiconductor device (1) may include transistors that are FinFETs of a tri-gate structure and a vertical channel structure, and may include the back gate structure (40), thereby improving performance.

[0078] In a modified example, referring to FIG. 3b, in each of the first and second gate structures (30a, 30b), the second electrode portion (34_2) described in FIG. 3a can be modified as the second electrode portion (34_2') in FIG. 3b. The second electrode portion (34_2') can cover a portion larger than half of each of the third and fourth sides (20S3, 20S4). For example, the second electrode portion (34_2') can cover a portion larger than half of the third side (20S3) and a portion larger than half of the fourth side (20S4). Thus, the second electrode portion (34_2') can further improve the gate controllability of the first and second gate structures (30a, 30b).

[0080] In a modified example, referring to FIG. 3c, in the back gate structure (40), the back gate dielectric layer (42 in FIG. 2a) and the gate electrode (44 in FIG. 2a) described above can be modified as the back gate dielectric layer (42a) and back gate electrode (44a) in FIG. 3c.

[0081] The back gate electrode (44a) may be extended to cover the second side (20S2) of each of the first and second vertical portions (20V1, 20V2) and to cover a portion of each of the third and fourth sides (20S3, 20S4). Thus, the back gate electrode (44a) may include a portion covering the second side (20S2) of each of the first and second vertical portions (20V1, 20V2), and a portion covering a portion of each of the third and fourth sides (20S3, 20S4). The gate dielectric layer (42a) may be disposed between the back gate electrode (44a) and the first vertical portion (20V1), and between the back gate electrode (44a) and the second vertical portion (20V2).

[0082] The back gate electrode (44a) can cover three sides of the first and second vertical portions (20V1, 20V2), that is, the first and second vertical channel regions (22c1, 22c2 in FIG. 1 and FIG. 2b). Thus, since the control capability of the back gate electrode (44a) over the first and second vertical channel regions (22c1, 22c2 in FIG. 1 and FIG. 2b) can be improved, the floating body effect can be more effectively suppressed or prevented, and the threshold voltage of the transistors can be more effectively prevented from fluctuating.

[0083] In one example, the area (or size) of the gate electrode (34a) covering the third and fourth sides (20S3, 20S4) in FIG. 3a and 3b may be different from the area (or size) of the back gate electrode (44a) covering the third and fourth sides (20S3, 20S4) in FIG. 3c. For example, the area (or size) of the gate electrode (34a) covering the third and fourth sides (20S3, 20S4) may be larger than the area (or size) of the back gate electrode (44a) covering the third and fourth sides (20S3, 20S4) in FIG. 3c.

[0084] In another example, where the gate electrode (34a) in FIG. 3a covers an area smaller than half of each of the third and fourth sides (20S3, 20S4), the area (or size) of the gate electrode (34a) covering the third and fourth sides (20S3, 20S4) may be substantially the same as the area (or size) of the back gate electrode (44a) covering the third and fourth sides (20S3, 20S4) in FIG. 3c.

[0086] In a modified example, referring to FIG. 3d, each of the first and second vertical portions (20V1, 20V2) may include the first to fourth sides (20S1, 20S2, 20S3, 20S4) as described above. The corner (20V_b) between the first side (20S1) and the third side (20S3) that can be covered by the first and second gate structures (30a, 30b), and the corner (20V_b) between the first side (20S1) and the third side (20S3) may be rounded. That is, the corners (20V_b) between the third and fourth sides (20S3, 20S4) and the first side (20S1) may be curved. By including the curved corners (20V_b) in the first and second vertical portions (20V1, 20V2), the performance degradation of transistors due to electric field concentration can be suppressed or prevented.

[0088] In a modified example, referring to FIG. 4a, in the gate structures (30) and the back gate structure (40), the gate dielectric layer (32 in FIG. 1 to 2b, and 32a in FIG. 3a to 3d) described above can be modified into a gate dielectric layer (32b) having a thickness greater than the thickness of the back gate dielectric layer (42).

[0090] In a modified example, referring to FIG. 4b, in the gate structures (30) and the back gate structure (40), the gate dielectric layer (32 in FIG. 1 to 2b, and 32a in FIG. 3a to 3d) described above can be modified into a gate dielectric layer (32c) having a thickness smaller than the thickness of the back gate dielectric layer (42).

[0092] In a modified example, referring to FIG. 4c, in each of the gate structures (30), the gate dielectric layers (32a, 32b, 32c) in FIG. 3a to 3d and FIG. 4a to 4c, which may have substantially uniform thickness, may be modified into a gate dielectric layer (32d) having non-uniform thickness. For example, the first dielectric portion (32_1) and the second dielectric portion (32_2) in the gate dielectric layers (32a, 32b, 32c) in FIG. 3a to 3d and FIG. 4a to 4c may have substantially the same thickness, and the gate dielectric layer (32d) in FIG. 4c may include a first dielectric portion (32_1a) and a second dielectric portion (32_2a) having different thicknesses. The gate dielectric layer (32d) may be in contact with the first side (20S1), and the second dielectric portion (32_2a) may be in contact with at least a portion of each of the third and fourth sides (20S3, 20S4). In the gate dielectric layer (32d), the first dielectric portion (32_1a) may have a thickness greater than the thickness of the second dielectric portion (32_2a).

[0094] In a modified example, referring to FIG. 4d, the gate dielectric layer (32d) described in FIG. 4c can be modified into a gate dielectric layer (32e) as in FIG. 4d. The gate dielectric layer (32e) may include a first dielectric portion (32_1b) in contact with the first side (20S1) and a second dielectric portion (32_2b) in contact with at least a portion of each of the third and fourth sides (20S3, 20S4) and having a thickness greater than that of the first dielectric portion (32_1b).

[0096] In a modified example, referring to FIG. 5a, the gate electrode (34) and the back gate electrode (44) may be located at substantially the same height level as the first and second vertical channel regions (22c1, 22c2) as in FIG. 1 and FIG. 2b, but are not limited thereto, and may be modified into a gate electrode (34aa) and a back gate electrode (44aa) located at a lower level than the upper surfaces of the first and second vertical channel regions (22c1, 22c2) and at a higher level than the lower surfaces of the first and second vertical channel regions (22c1, 22c2) as in FIG. 5a. Accordingly, the gate electrode (34, 34a) and the back gate electrode (44, 44a) described with reference to FIG. 1 to 4d may be modified into the gate electrode (34aa) and the back gate electrode (44aa).

[0097] The vertical thickness of each of the first and second vertical channel regions (22c1, 22c2) may be greater than the vertical thickness of each of the gate electrode (34aa) and the back gate electrode (44aa).

[0098] The upper surfaces of the first and second vertical channel regions (22c1, 22c2) may be the lower surfaces of the second and fourth source / drains (22sd2, 22sd4), and the lower surfaces of the first and second vertical channel regions (22c1, 22c2) may be the upper surfaces of the first and third source / drains (22sd1, 22sd3) within the vertical portions (20V1, 20V2).

[0100] In a modified example, with reference to FIG. 5b, the gate electrode (34, 34a) and the back gate electrode (44, 44a) described with reference to FIG. 1 to FIG. 4d can be modified into a gate electrode (34b) and a back gate electrode (44b) located at a level higher than the upper surfaces of the first and second vertical channel regions (22c1, 22c2) and at a level lower than the lower surfaces of the first and second vertical channel regions (22c1, 22c2).

[0101] The vertical thickness of each of the first and second vertical channel regions (22c1, 22c2) may be smaller than the vertical thickness of each of the gate electrode (34aa) and the back gate electrode (44aa).

[0102] The gate electrode (34b) of the first gate structure (30a) may cover a portion of the side of the first source / drain (22sd1) and a portion of the side of the second source / drain (22sd2) located within the first vertical portion (20V1). The gate electrode (34b) of the second gate structure (30b) may cover a portion of the side of the third source / drain (22sd3) and a portion of the side of the fourth source / drain (22sd4) located within the second vertical portion (20V2). The back gate electrode (44b) may cover a portion of the side of each of the first to fourth sources / drains (22sd1, 22sd2, 22sd3, 22sd4) located within the second vertical portion (20V2).

[0104] In a modified example, with reference to FIG. 5c, the gate electrode (34, 34a) and the back gate electrode (44, 44a) described with reference to FIG. 1 to 4d can be modified into a gate electrode (34c) and a back gate electrode (44c) located at a lower level than the upper surfaces of the first and second vertical channel regions (22c1, 22c2) and at a lower level than the lower surfaces of the first and second vertical channel regions (22c1, 22c2).

[0106] In a modified example, with reference to FIG. 5d, the gate electrode (34, 34a) and the back gate electrode (44, 44a) described with reference to FIG. 1 to FIG. 4d can be modified into a gate electrode (34d) and a back gate electrode (44d) which are located at a higher level than the upper surfaces of the first and second vertical channel regions (22c1, 22c2) and at a higher level than the lower surfaces of the first and second vertical channel regions (22c1, 22c2).

[0108] In a modified example, referring to FIG. 6a, in the cross-sectional structure of FIG. 2b, the width of the gate electrode (34) and the width of the back gate electrode (44) may be substantially the same, but are not limited thereto. For example, in a cross-sectional structure in which the first and second horizontal portions (20H1, 20H2) are cut along the longitudinal direction, i.e., the first direction (X), the gate electrodes (34, 34a, 34aa, 34b, 34c, 34d) and the back gate electrodes (44, 44a, 44aa, 44b, 44c, 44d) described in FIG. 1 to 5d may have the same width as each other, but are not limited thereto. For example, in a cross-sectional structure in which the first and second horizontal portions (20H1, 20H2) are cut along the longitudinal direction, i.e., the first direction (X), the gate electrodes (34, 34a, 34aa, 34b, 34c, 34d) and the back gate electrodes (44, 44a, 44aa, 44b, 44c, 44d) described in FIGS. 1 to 5d can be modified into a gate electrode (34e) and a back gate electrode (44e) having different widths. For example, in a cross-sectional structure in which the first and second horizontal portions (20H1, 20H2) are cut along the longitudinal direction, i.e., the first direction (X), the gate electrode (44e) can have a first width, and the back gate electrode (44e) can have a second width greater than the first width. Here, the portion having the first width of the gate electrode (44e) may be a portion covering the first side (20S1) of the first vertical portion (20V1), and the portion having the second width of the back gate electrode (44e) may be a portion covering the second side (20S2) of the first vertical portion (20V1).

[0110] In a modified example, referring to FIG. 6b, the gate electrode (34e) and the back gate electrode (44e) as in FIG. 6a can be modified into the gate electrode (34f) and the back gate electrode (44f) as in FIG. 6b. For example, in a cross-sectional structure in which the first and second horizontal portions (20H1, 20H2) are cut along the longitudinal direction, i.e., the first direction (X), the width of the gate electrode (44f) may be greater than the width of the back gate electrode (44e).

[0112] In a modified example, referring to FIG. 7a, the gate electrodes (34, 34a, 34aa, 34b, 34c, 34d, 34e, 34f) and the back gate electrodes (44, 44a, 44aa, 44b, 44c, 44d, 44e, 44f) described with reference to FIG. 1 to 6b may have substantially the same vertical thickness, but are not limited thereto. For example, the gate electrode (34, 34a, 34aa, 34b, 34c, 34d, 34e, 34f) and the back gate electrode (44, 44a, 44aa, 44b, 44c, 44d, 44e, 44f) described with reference to FIGS. 1 to 6b can be modified into a gate electrode (34g) and a back gate electrode (44g) having different vertical thicknesses. The vertical thickness of the gate electrode (34g) may be greater than the vertical thickness of the back gate electrode (44g). The upper surface of the gate electrode (34g) may be located at a higher level than the upper surface of the back gate electrode (44g), and the lower surface of the gate electrode (34g) may be located at a lower level than the lower surface of the back gate electrode (44g).

[0114] In a modified example, referring to FIG. 7b, the gate electrode (34, 34a, 34aa, 34b, 34c, 34d, 34e, 34f) and the back gate electrode (44, 44a, 44aa, 44b, 44c, 44d, 44e, 44f) described with reference to FIG. 1 to 6b can be modified into a gate electrode (34h) and a back gate electrode (44h) as in FIG. 7b. The vertical thickness of the gate electrode (34h) may be smaller than the vertical thickness of the back gate electrode (44h). The upper surface of the gate electrode (34h) may be located at a lower level than the upper surface of the back gate electrode (44g), and the lower surface of the gate electrode (34h) may be located at a higher level than the lower surface of the back gate electrode (44h).

[0116] In a modified example, referring to FIG. 8a, the gate electrode (34, 34a, 34aa, 34b, 34c, 34d, 34e, 34f) and the back gate electrode (44, 44a, 44aa, 44b, 44c, 44d, 44e, 44f) described with reference to FIG. 1 to 6b can be modified into a gate electrode (34i) and a back gate electrode (44i) as in FIG. 8a. The upper surface of the gate electrode (34i) can be located at a higher level than the upper surface of the back gate electrode (44i), and the lower surface of the gate electrode (34i) can be located at a higher level than the lower surface of the back gate electrode (44i).

[0118] In a modified example, referring to FIG. 8b, the gate electrode (34, 34a, 34aa, 34b, 34c, 34d, 34e, 34f) and the back gate electrode (44, 44a, 44aa, 44b, 44c, 44d, 44e, 44f) described with reference to FIG. 1 to 6b can be modified into a gate electrode (34j) and a back gate electrode (44j) as in FIG. 8b. The upper surface of the gate electrode (34j) can be located at a lower level than the upper surface of the back gate electrode (44j), and the lower surface of the gate electrode (34j) can be located at a lower level than the lower surface of the back gate electrode (44j).

[0120] The semiconductor device (1) described in FIGS. 1 to 8b may be a memory device. As described in FIGS. 1 to 2b, the length direction of each of the horizontal parts (20H1, 20H2) may be perpendicular to the second direction (Y) or inclined to the second direction (Y). Referring to FIGS. 9 and FIGS. 10, a semiconductor device that may be a memory device will be described. FIG. 9 is a conceptual perspective view showing an example in which the length direction of each of the horizontal parts (20H1, 20H2) is perpendicular to the second direction (Y) and the semiconductor device (1) described above is a memory device, and FIG. 10 is a conceptual perspective view showing an example in which the length direction of each of the horizontal parts (20H1, 20H2) is inclined to the second direction (Y) and the semiconductor device (1) described above is a memory device.

[0121] In one example, referring to FIG. 9, the semiconductor device (100) may include a substrate (105), a peripheral circuit structure (110) on the substrate (105), and bit lines (BL_a) on the peripheral circuit structure (110).

[0122] The semiconductor device (100) may further include the first and second structures (20a, 20b) as shown in FIGS. 1 to 8b. As shown in FIGS. 1 to 8b, the first structure (20a) may include the first horizontal portion (20H1) and the first vertical portion (20V1), and the second structure (20b) may include the second horizontal portion (20H2) and the second vertical portion (20V2). As shown in FIGS. 1 to 8b, the first structure (20a) may include the first and second source / drains (20sd1, 20sd2) and the first vertical channel region (22c1), and the second structure (20b) may include the third and fourth source / drains (20sd3, 20sd4) and the second vertical channel region (22c2).

[0123] The bitlines (BL_a) may be electrically connected to the first and third source / drains (20sd1, 20sd3) of the first and second structures (20a, 20b). The bitlines (BL_a) may come into contact with the first and third source / drains (20sd1, 20sd3) of the first and second structures (20a, 20b). The first and second structures adjacent to each other on one of the bitlines (BL_a).

[0124] Waters (20a, 20b) can be placed.

[0125] At least a portion of each of the above bit lines (BL_a) may be placed at a higher level than the vertical portions (20V1, 20V2).

[0126] The semiconductor device (100) may further include the gate structures (30) and the back gate structure (40) as described in FIGS. 1 to 8b. For example, each of the gate structures (30) may include the gate electrode (34) as in FIG. 1, and the back gate structure (40) may include the back gate electrode (44) as in FIG. 1. The gate electrodes (34) may be word lines (WL) of the memory device, and the back gate electrode (44) may be a back gate line (BG) for controlling the vertical channel regions (22c1, 22c2) in the memory device.

[0127] The substrate (105) may be a semiconductor substrate. The bit lines (BL_a) may be formed of a conductive material. The peripheral circuit structure (110) may be a peripheral circuit area in a memory device in which a circuit for operating at least one of the word lines (WL), the bit lines (BL_a), and the back gate line (BG) may be disposed.

[0128] In the top view, the bit lines (BL_a) can intersect perpendicularly with the gate structures (30) and the back gate structure (40).

[0129] The semiconductor device (100) may further include an information storage structure (DS) on the second and fourth source / drains (20sd2, 20sd4), and contact structures (CNTa) that electrically connect the second and fourth source / drains (20sd2, 20sd4) and the information storage structure (DS) between the second and fourth source / drains (20sd2, 20sd4) and the information storage structure (DS).

[0130] The information storage structure (DS) may be an information storage structure of a DRAM, for example, memory cell capacitors that store information in a DRAM, but is not limited thereto. For example, the information storage structure (DS) may be an information storage structure of an MRAM or an information storage structure of a FeRAM.

[0132] In another example, referring to FIG. 10, the semiconductor device (200) may include the substrate (5), the active regions (15b), and the device isolation region (10) as in FIG. 1 and FIG. 2b.

[0133] The semiconductor device (200) may further include first and second structures (20a', 20b') that are substantially identical or similar to the first and second structures (20a, 20b) described in FIGS. 1 to 8b. As in FIGS. 1 to 8b, the first structure (20a') may include the first horizontal portion (20H1) and the first vertical portion (20V1), and the second structure (20b') may include the second horizontal portion (20H2) and the second vertical portion (20V2). As in FIGS. 1 to 8b, the first structure (20a') may include the first and second source / drains (20sd1, 20sd2) and the first vertical channel region (22c1), and the second structure (20b') may include the third and fourth source / drains (20sd3, 20sd4) and the second vertical channel region (22c2).

[0134] The semiconductor device (200) may further include gate structures (30) and back gate structures (40) as described in FIGS. 1 to 8b. For example, each of the gate structures (30) may include a gate electrode (34a) of a tri-gate structure as in FIG. 3a, and the back gate structure (40) may include a back gate electrode (44) as in FIG. 3a. The gate electrodes (34a) may be word lines (WL) of a memory device, and the back gate electrode (44) may be a back gate line (BG) for controlling the vertical channel regions (22c1, 22c2) in the memory device.

[0135] The semiconductor device (200) may further include bitline contact plugs (CNTb) that are in contact with the first and second horizontal portions (20H1, 20H2) on the first and second horizontal portions (20H1, 20H2) and are electrically connected to the first and second horizontal portions (20H1, 20H2). The bitline contact plugs (CNTb) may be electrically connected while in contact with the first and third source / drains (20sd1, 20sd3).

[0136] The bitline contact plugs (CNTb) may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof, but are not limited thereto. For example, the bitline contact plugs (CNTb) may include a conductive two-dimensional semiconductor material, and such a two-dimensional semiconductor material may include graphene, carbon nanotube, or a combination thereof.

[0137] The semiconductor device (200) may further include bit lines (BL_b) electrically connected to the bit line contact plugs (CNTb) on the bit line contact plugs (CNTb).

[0138] In the top view, the bit lines (BL_b) can intersect perpendicularly with the gate structures (30) and the back gate structure (40).

[0139] In the top view, the longitudinal direction of the first and second horizontal portions (20H1, 20H2) of the first and second structures (20a', 20b') may intersect obliquely rather than perpendicularly with the bit lines (BL_b) and may intersect obliquely rather than perpendicularly with the gate structures (30) and the back gate structure (40).

[0140] The semiconductor device (200) may further include, as shown in FIG. 8, the information storage structure (DS) on the second and fourth source / drains (20sd2, 20sd4), and the contact structures (CNTa) that electrically connect the second and fourth source / drains (20sd2, 20sd4) and the information storage structure (DS) between the second and fourth source / drains (20sd2, 20sd4) and the information storage structure (DS).

[0142] The semiconductor device (1, 100, 200) according to the embodiments described above is described as including a first vertical part (20V1) extending upward from one side of the longitudinal direction of a horizontal part, for example, the first horizontal part (20H1), but is not limited thereto. For example, as described in FIGS. 1, 2a, and 2b, each of the structures (20a, 20b) may include a pair of vertical parts extending upward from both sides of the longitudinal direction of a horizontal part. An example in which a pair of vertical parts extending upward from both sides of the longitudinal direction of a horizontal part is arranged in this manner will be described with reference to FIGS. 11 and 12. FIGS. 11 and FIGS. 12 are drawings for illustrating an example in which a pair of vertical sections extending upward from both sides in the longitudinal direction of a horizontal section (20H1) are arranged in each of the first and second structures (20a', 20b') as in FIG. 9. FIG. 11 is a top view conceptually showing an example of a semiconductor device according to an embodiment of the present invention, and FIG. 12 is a cross-sectional view showing regions taken along the lines I-I', II-II', and III-III' of FIG. 11.

[0143] Referring to FIGS. 11 and 12, a semiconductor device (300) according to one embodiment may include a substrate (301) and device isolation layers (306, 343) defining active regions (309a) on the substrate (301). The device isolation layers (306, 343) may include a first device isolation layer (306) and a second device isolation layer (343). The substrate (301) may be a semiconductor substrate. The device isolation layers (306, 343) may be formed of an insulating material.

[0144] The semiconductor device (300) may further include structures (ST) disposed on the active regions (309a). The structures (ST) may include first structures (ST1) and second structures (ST2). Each of the first and second structures (ST1, ST2) may include a horizontal portion (ST_H) and vertical portions (ST_V) extending upward from both sides in the longitudinal direction (D) of the horizontal portion (ST_H). Thus, each of the first and second structures (ST1, ST2) may include one horizontal portion (ST_H) and two vertical portions (ST_V).

[0145] Each of the first and second structures (ST1, ST2) may include a lower source / drain (SD1) positioned within the horizontal portion (ST_H) and extending into the lower region of each of the vertical portions (ST_V), upper source / drains (SD2) positioned within the upper regions of the vertical portions (ST_V), and vertical channel regions (CH) positioned between the lower source / drain (SD1) and the upper source / drains (SD2) within the vertical portions (ST_V). Each of the vertical portions (ST_V) may be substantially identical to the vertical portion described above, for example, the first and second vertical portions (20V1, 20V2) described in FIGS. 1 to 2b.

[0146] The semiconductor device (300) may further include gate structures (330) and back gate structures (360). The gate structures (330) may include a pair of gate structures spaced apart from each other, positioned between a pair of vertical parts (ST_V) on any one of the horizontal parts (ST_H). On any one of the horizontal parts (ST_H), each of the pair of gate structures (330) may include a gate dielectric layer (332) in contact with the vertical channel regions (CH) of the vertical parts (ST_V) and a gate electrode (334) on the gate dielectric layer (332). The gate dielectric layer (332) may cover the bottom surface of the gate electrode (334) while covering the side surface covering the vertical channel regions (CH) of the gate electrode (334). The gate electrodes (334) of the gate structures (330) may be word lines.

[0147] The gate electrodes (334) may have substantially the same structure and / or shape as any one of the gate electrodes of the various examples described in FIGS. 1 to 10. The gate dielectric layer (332) may have substantially the same structure and / or shape as any one of the gate dielectric layers of the various examples described in FIGS. 1 to 10.

[0148] The above back gate structure (360) can pass between the first structures (ST_1) and the second structures (ST_2) that are adjacent to each other in the longitudinal direction (D) of the horizontal portions (ST_H).

[0149] The back gate structure (360) may include a back gate electrode (364) and a back gate dielectric layer (362) covering the sides and bottom surface of the back gate electrode (364). The back gate electrode (364) may be a back gate (BG).

[0150] The back gate electrode (364) may have substantially the same structure and / or shape as any one of the back gate electrodes of the various examples described in FIGS. 1 to 10. The back gate dielectric layer (362) may have substantially the same structure and / or shape as any one of the back gate dielectric layers of the various examples described in FIGS. 1 to 10.

[0151] The semiconductor device (300) may further include an insulating layer (321a) on the horizontal portions (ST_H), an insulating layer (337) disposed between the vertical portions (ST_V) on the insulating layer (321a) on the horizontal portions (ST_H) and covering the gate structures (330), and an insulating layer (365) on the back gate structure (360). The gate structures (330) may be disposed on the insulating layer (321a).

[0152] The semiconductor device (300) may further include contact plugs (340) that penetrate the insulating layers (337, 321a) and contact the lower source / drain (SD1) of the horizontal portions (ST_H).

[0153] The semiconductor device (300) may further include an insulating layer (370) on the upper source / drains (SD2), the insulating layers (337, 365), and the contact plugs (340), and conductive lines (381) including plug portions disposed on the insulating layer (370) and penetrating the insulating layer (370). The conductive lines (381) may be bit lines (BL).

[0154] The semiconductor device (300) may further include bitline capping layers (378) on the bitlines (BL), insulating spacers (382) covering the sides of the bitlines (BL) and the bitline capping layers (378), and an insulating layer (384) filling the space between the bitlines (BL). The bitline capping layers (378) may be formed of an insulating material.

[0155] The semiconductor device (300) may further include contact plugs (392) that penetrate the insulating layers (384, 370) and contact and are electrically connected to the upper source / drain (SD2), conductive pads (394) electrically connected to the contact plugs (392) on the contact plugs (392), an insulating layer (396) between the conductive pads (394), and an information storage structure (DS) on the conductive pads (394).

[0156] In an embodiment, the longitudinal direction (D) of the horizontal portions (ST_V) may intersect obliquely without being perpendicular to the bit lines (BL) and obliquely without being perpendicular to the word lines (WL), substantially the same as described in FIG. 10.

[0157] In an embodiment, the lower source / drain (SD1) may be the first and third source / drains (20sd1, 20sd3) in FIGS. 1 to 10, and the upper source / drain (SD2) may be the second and fourth source / drains (20sd2, 20sd4) in FIGS. 1 to 10. Accordingly, the first and third source / drains (20sd1, 20sd3) in FIGS. 1 to 10 may be referred to as lower source / drains, and the second and fourth source / drains (20sd2, 20sd4) may be referred to as upper source / drains.

[0158] As previously explained, the gate structures (330) may have substantially the same structure and / or shape as any one of the various gate structures (30) described in FIGS. 1 to 10, and the back gate structure (360) may have substantially the same structure and / or shape as any one of the various back gate structures (40) described in FIGS. 1 to 10. For example, the gate electrodes (334) of the gate structures (330) may have the same structure and / or shape as the gate electrodes (34a) of the tri-gate structure as in FIG. 10. For example, each of the gate electrodes (334) may include a first gate portion (334_1) and a second gate portion (334_2) corresponding to the first gate portion (34_1) and the second gate portion (34_2) described in FIG. 3a, respectively.

[0159] With reference to FIG. 13, the back gate structure (360) in FIG. 12 is to be described as an exemplary example in which it can be modified to substantially the same structure and / or shape as any one of the various back gate structures (40) described in FIG. 1 through 10. FIG. 13 is a cross-sectional view corresponding to FIG. 12, which conceptually illustrates an example in which the back gate structure (360) in FIG. 12 is modified.

[0160] In a modified example, referring to FIG. 13, the back gate structure (360) in FIG. 12 can be modified to substantially the same shape as the back gate structure (40) including the back gate electrode (44g) as in FIG. 7a. For example, the back gate structure (360a) modified as in FIG. 7a may have a vertical thickness smaller than the vertical thickness of each of the gate structures (330), an upper surface at a lower level than the upper surfaces of the gate structures (330), and a lower surface at a higher level than the lower surfaces of the gate structures (330). In this way, the gate structures (330) of FIG. 12 can be modified to have a structure and / or shape substantially identical to any one of the various gate structures (30) described in FIG. 1 to 10, and the back gate structure (360) of FIG. 12 can be modified to have a structure and / or shape substantially identical to any one of the various back gate structures (40) described in FIG. 1 to 10.

[0162] Next, with reference to FIG. 11 and FIG. 14a to 14j, an exemplary example of a method for forming a semiconductor device according to an embodiment of the present invention will be described. FIG. 14a to 14j are drawings for explaining a method for forming a semiconductor device of FIG. 11 and FIG. 12, and FIG. 14a to 14j are cross-sectional views conceptually showing regions taken along the lines I-I', II-II', and III-III' of FIG. 11.

[0163] Referring to FIG. 11 and FIG. 14a, a mask pattern (303) can be formed on a substrate (301). The substrate (301) may be a semiconductor substrate. A trench can be formed by etching the substrate (301) using the mask pattern (303) as an etching mask, and a first device isolation layer (306) that fills the trench can be formed. A preliminary lower active region (309) can be defined below the mask pattern (303) by the first device isolation layer (306).

[0164] Referring to FIG. 11 and FIG. 14b, trenches (312) can be formed across the mask pattern (303), the first device isolation layer (306), and the preliminary lower active region (309). The trenches (312) penetrate the mask pattern (303) and can lower the height of the first device isolation layer (306) and the preliminary lower active region (309). The remaining preliminary lower active region (309) located at a level higher than the bottom surface of the trenches (312) can be defined as a preliminary upper active region (315). Each of the trenches (312) may be line-shaped.

[0165] Referring to FIG. 11 and FIG. 14c, lower source / drains (SD1) may be formed in the upper region of the preliminary lower active region (309) and the lower region of the preliminary upper active region (315) adjacent to the bottom surface of the trenches (312). Forming the lower source / drains (SD1) may include implanting impurities by an ion implantation process into the upper region of the preliminary lower active region (309) exposed by the bottom surfaces of the trenches (312), and carrying out an impurity diffusion process to diffuse the impurities to the lower region of the preliminary upper active region (315).

[0166] Referring to FIG. 11 and FIG. 14d, an insulating layer (321) that partially fills the trenches (312) can be formed. The insulating layer (321) may include at least one of a low dielectric and silicon oxide.

[0167] Referring to FIG. 11 and FIG. 14e, when forming a gate structure of a tri-gate structure as described in FIG. 3a, the first device isolation layer (306) covering the side of the insulating layer (321) and the preliminary upper active region (315) can be isotropically etched to form an insulating layer (321a) with reduced height and at the same time expose a portion of the side of the preliminary upper active region (315).

[0168] Referring to FIG. 11 and FIG. 14f, on the insulating layer (321a), gate structures (330) can be formed that cover both side walls of the trenches (312), are spaced apart from each other, and have an upper surface at a lower level than the upper surface of the preliminary upper active region (315). Each of the gate structures (330) may include a gate electrode (334) and a gate dielectric layer (332) disposed between the gate electrode (334) and the side of the preliminary upper active region (315) and covering the lower surface of the gate electrode (334). An insulating layer (337) can be formed that covers the gate structures (330) and fills the trenches (312).

[0169] Referring to FIG. 11 and FIG. 14g, contact plugs (340) can be formed that penetrate the insulating layer (337) and the insulating layer (321a) and contact the lower source / drain (SD1).

[0170] Referring to FIG. 11 and FIG. 14h, a second device isolation layer (343) can be formed penetrating the mask pattern (303), the preliminary upper active region (315), and the preliminary lower active region (309). The second device isolation layer (343) can be formed in a line shape. The second device isolation layer (343) can be formed of an insulating material.

[0171] The preliminary upper active region (315) can be separated into upper active patterns (350) by the second device isolation layer (343), and the preliminary lower active region (309) can be separated into active regions (309a). Accordingly, the first and second device isolation layers (306, 343) may be device isolation regions that define the active regions (309a).

[0172] Referring to FIGS. 11 and 14i, the second device isolation layer (343) can be partially etched to form an opening that exposes the upper active patterns (350) and to form a back gate structure (360) that partially fills the opening. Forming the back gate structure (360) may include forming a back gate dielectric layer (362), forming a back gate electrode (364) on the back gate dielectric layer (362), and at least partially etching the back gate electrode (364). The upper surface of the back gate electrode (364) may be formed at a lower level than the upper surfaces of the upper active patterns (350). The back gate dielectric layer (362) may cover the sides and bottom surface of the back gate electrode (364).

[0173] Referring to FIG. 11 and FIG. 14j, an insulating layer (365) covering the upper part of the back gate structure (360) can be formed. While forming the insulating layer (365), or after forming the insulating layer (365), the mask pattern (303) can be removed.

[0174] Upper source / drains (SD2) can be formed within the upper regions of the upper active patterns (350). Within the upper active patterns (350), regions located between the lower source / drains (SD1) and the upper source / drains (SD1) can be defined as vertical channel regions (CH).

[0175] Again, referring to FIGS. 11 and 12, a buffer insulating layer (370) covering the upper source / drains (SD2) and the contact plugs (340) is formed, holes are formed penetrating the buffer insulating layer (370) and exposing the upper source / drains (D1), a conductive material layer is formed covering the buffer insulating layer (370) and filling the holes, a bitline capping layer (378) is formed on the conductive material layer, and conductive lines (381) can be formed by etching the conductive material layer using the bitline capping layer (378) as an etching mask. The conductive lines (381) may be bitlines (BL).

[0176] Insulating spacers (382) can be formed to cover the sides of the bit lines (BL) and the bit line capping layer (378). An insulating layer (384) can be formed between the bit lines (BL). Contact plugs (392) can be formed penetrating the insulating layer (384) and electrically connected to the upper source / drain (SD2). Conductive pads (394) electrically connected to the contact plugs (392) can be formed on the contact plugs (392). An insulating layer (396) can be formed between the conductive pads (394).

[0177] An information storage structure (DS) can be formed on the conductive pads (394). The information storage structure (DS) may be an information storage structure of a DRAM, for example, memory cell capacitors that store information in a DRAM, but is not limited thereto. For example, the information storage structure (DS) may be an information storage structure of an MRAM or an information storage structure of a FeRAM.

[0179] Next, with reference to FIG. 15a, a circuit of a semiconductor device according to an embodiment of the present invention will be described. FIG. 15a is a circuit diagram conceptually showing an example of a semiconductor device according to an embodiment of the present invention, and can represent the semiconductor device (100) of FIG. 9 circuitly.

[0180] Referring to FIG. 15a, the semiconductor device (100) may include transistors (TR), word lines (WL), back gate lines (BG), bit lines (BL), and information storage structures (DS).

[0181] The word lines (WL) and the back gate lines (BG) may be parallel to each other and spaced apart from each other. A pair of word lines (WL) may be placed between a pair of adjacent back gate lines (BG). A back gate line (BG) may be placed between two adjacent word lines (WL).

[0182] The above transistors (TR) may include a first pair of transistors (TR1) located on the left side when viewed with respect to a back gate line (BG) and a second pair of transistors (TR2) located on the right side.

[0183] The first pair of transistors (TR1) may include a first transistor (TR1a) and a second transistor (TR1b) that share a lower source / drain (SD1). The first and second transistors (TR1a, TR1b) may include upper sources / drains (SD2) that are spaced apart from each other.

[0184] The second pair of transistors (TR2) may include a third transistor (TR2a) and a fourth transistor (TR2b) that share a lower source / drain (SD1). The third and fourth transistors (TR2a, TR2b) may include upper source / drains (SD2) that are spaced apart from each other. The lower source / drains (SD1) may be the first and third source / drains (22sd1, 22sd3) in FIG. 9, and the upper source / drains (SD2) may be the second and fourth source / drains (22sd2, 22sd4) in FIG. 9.

[0185] FIG. 9 may be a perspective view showing the first transistor (TR1a) among the first pair of transistors (TR1) and the third transistor (TR2a) among the second pair of transistors (TR2). The first transistor (TR1a) and the third transistor (TR2a) may be adjacent to each other with one back gate line (BG) in between.

[0186] In the first pair of transistors (TR1), the first and second transistors (TR1a, TR1b) may have a mirror-symmetric structure centered on the middle portion of a shared lower source / drain (SD1).

[0187] In the second pair of transistors (TR2), the third and fourth transistors (TR2a, TR2b) may have a mirror-symmetric structure centered on the middle portion of a shared lower source / drain (SD1).

[0188] The bit lines (BL) can be positioned as shown in FIG. 9, that is, below the first and third source / drains (20sd1, 20sd3), that is, below the lower source / drains (SD1).

[0189] The bit lines (BL) may be line-shaped extending in a first direction (X), and the word lines (WL) and the back gate lines (BG) may be line-shaped extending in a second direction (Y) perpendicular to the first direction (X). The transistors (TR) may be arranged along the first direction (X) and the second direction (Y).

[0190] The above information storage structure (DS) may be an information storage structure of a DRAM, for example, cell capacitors of a DRAM, but is not limited thereto, and may also be an information storage structure of another memory, for example, MRAM or FeRAM.

[0192] Next, with reference to FIG. 15b, a circuit of a semiconductor device according to an embodiment of the present invention will be described. FIG. 15b is a circuit diagram conceptually showing an example of a semiconductor device according to an embodiment of the present invention, and can circuitly represent the semiconductor device (200) of FIG. 10 and the semiconductor device (300) of FIG. 11 and FIG. 12.

[0193] Referring to FIG. 15b, the semiconductor device (200) may include transistors (TR), word lines (WL), back gate lines (BG), bit lines (BL), and an information storage structure (DS). The word lines (WL) and the back gate lines (BG) may be parallel to each other and spaced apart from each other. A pair of word lines (WL) may be placed between a pair of adjacent back gate lines (BG). A back gate line (BG) may be placed between two adjacent word lines (WL).

[0194] The above transistors (TR) may include a first pair of transistors (TR1) located on the left side when viewed with respect to a back gate line (BG) and a second pair of transistors (TR2) located on the right side.

[0195] The first pair of transistors (TR1) may include a first transistor (TR1a) and a second transistor (TR1b) that share a single lower source / drain (SD1). The first and second transistors (TR1a, TR1b) may include upper source / drains (SD2) that are spaced apart from each other. The second pair of transistors (TR2) may include a third transistor (TR2a) and a fourth transistor (TR2b) that share a single lower source / drain (SD1). The third and fourth transistors (TR2a, TR2b) may include upper source / drains (SD2) that are spaced apart from each other.

[0196] The lower source / drains (SD1) may be the first and third source / drains (22sd1, 22sd3) in FIG. 10 or the lower source / drains (SD1) as in FIG. 12, and the upper source / drains (SD2) may be the second and fourth source / drains (22sd2, 22sd4) in FIG. 9 or the upper source / drains (SD2) as in FIG. 12.

[0197] FIG. 10 may be a perspective view showing the first transistor (TR1a) among the first pair of transistors (TR1) and the third transistor (TR2a) among the second pair of transistors (TR2). The first transistor (TR1a) and the third transistor (TR2a) may be adjacent to each other with one back gate line (BG) in between.

[0198] The bit lines (BL) may be line-shaped extending in a first direction (X), and the word lines (WL) and the back gate lines (BG) may be line-shaped extending in a second direction (Y) perpendicular to the first direction (X). The bit lines (BL) may be placed on the second and fourth source / drains (20sd2, 20sd4), i.e., the upper source / drains (SD2), as in FIG. 10 and FIG. 12.

[0199] In the first pair of transistors (TR1), the first and second transistors (TR1a, TR1b) may be mirror-symmetric in the inclination direction (D) with respect to the center of a shared lower source / drain (SD1). The inclination direction (D) may be the longitudinal direction of the horizontal portions (20H1, 20H2) in FIG. 10 and the longitudinal direction of the horizontal portions (ST_H) in FIG. 11 and FIG. 12. The inclination direction (D) may be a direction inclined with respect to the first direction (X) and the second direction (Y), respectively. Here, the inclination direction (D) may be a direction that is not 90 degrees with respect to the first direction (X) and the second direction (Y).

[0200] The above information storage structure (DS) may be an information storage structure of a DRAM, for example, cell capacitors of a DRAM, but is not limited thereto, and may also be an information storage structure of another memory, for example, MRAM or FeRAM.

[0202] Depending on the operating conditions of the semiconductor device (1, 100, 200, 300) described above, or the desired optimized required performance, a negative voltage, 0V, or a positive voltage may be applied to the back gate lines (BG) described above with reference to FIGS. 1 to 15b. For example, when a first positive voltage is applied to the word lines (WL), a positive voltage lower than the first positive voltage may be applied to the back gate lines (BG).

[0204] In the semiconductor device (1, 100, 200, 300) described above, the back gate lines (BG) described in FIGS. 1 to 15b may be controlled individually or multiple back gate lines (BG) may be controlled simultaneously. Hereinafter, examples of controlling the back gate lines (BG) will be described with reference to FIGS. 16, FIG. 17, and FIG. 18, respectively. FIG. 16 is a conceptual circuit diagram for explaining the control of the back gate lines (BG) individually, FIG. 17 is a conceptual circuit diagram for explaining the control of the back gate lines (BG) in multiple units, and FIG. 18 is a conceptual circuit diagram for explaining the control of all the back gate lines (BG) simultaneously.

[0205] Referring to FIGS. 16, 17, and 18, the above-described semiconductor device (1, 100, 200, 300) may include a plurality of memory cell arrays (MCA1, MCA2) that are spaced apart from each other and exist independently. When the above-described semiconductor device (1, 100, 200, 300) is a DRAM, the plurality of memory cell arrays (MCA1, MCA2) may form a Bank. In the above-described semiconductor device (1, 100, 200, 300), a plurality of Banks may be arranged.

[0206] Each of the plurality of memory cell arrays (MCA1, MCA2) may include transistors (TR), word lines (WL), back gate lines (BG), bit lines (BL), and information storage structures (DS) as described in FIG. 15a and FIG. 15b. The circuit of each of the plurality of memory cell arrays (MCA1, MCA2) may be the same as the circuit of FIG. 15a or the circuit of FIG. 15b.

[0207] A back gate control circuit (BG_Ca in FIG. 16, BG_Cb in FIG. 17, BG_Cc in FIG. 18) for controlling and / or driving the back gate lines (BG) may be disposed on at least one side of the plurality of memory cell arrays (MCA1, MCA2).

[0208] In one example, referring to FIG. 16, the back gate control circuit (BG_Ca of FIG. 16) can control or operate the back gate lines (BG) individually. For example, the same voltage may be applied to all of the back gate lines (BG), or a different voltage may be applied to some of the back gate lines (BG) compared to other back gate lines. For example, in a memory cell array (MCA), a different voltage may be applied to some of the back gate lines (BG) compared to other back gate lines.

[0209] In another example, referring to FIG. 17, the back gate control circuit (BG_Cb) can simultaneously control and drive a plurality of the back gate lines (BG). For example, the back gate control circuit (BG_Cb) can control or drive the back gate lines (BG) in units of each of the plurality of memory cell arrays (MCA1, MCA2) or in units of banks. For example, the back gate control circuit (BG_Ca in FIG. 16) can apply a first voltage to the back gate lines (BG) within the first memory cell array (MCA1) among the plurality of memory cell arrays (MCA1, MCA2), and apply a second voltage different from the first voltage to the back gate lines (BG) of the second memory cell array (MCA2) that exists independently of the first memory cell array (MCA1). Alternatively, the back gate control circuit (BG_Ca of FIG. 16) may apply a first voltage to the back gate lines (BG) of a plurality of memory cell arrays (MCA1) included in a first bank among a plurality of banks, and apply a second voltage different from the first voltage to the back gate lines (BG) of a plurality of memory cell arrays (MCA2) included in a second bank among the plurality of banks.

[0210] In another example, referring to FIG. 18, the back gate control circuit (BG_Cc) can simultaneously control or operate the back gate lines (BG) of an entire memory chip. For example, the back gate control circuit (BG_Cc) can apply the same voltage to the back gate lines (BG) of an entire memory chip.

[0211] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A substrate; a first gate structure and a second gate structure spaced apart from each other on the substrate; a back gate structure disposed between the first gate structure and the second gate structure and spaced apart from the first and second gate structures; a first structure including a first vertical channel region extending in a vertical direction, and a second structure including a second vertical channel region extending in the vertical direction and spaced apart from the first structure, wherein at least a portion of the first vertical channel region is disposed between the first gate structure and the back gate structure, and at least a portion of the second vertical channel region is disposed between the second gate structure and the back gate structure, wherein the first vertical channel region includes a first side and a second side facing each other in a first direction, and a third side and a fourth side facing each other in a second direction intersecting the first direction, and the second vertical channel region includes a fifth side and a sixth side facing each other in the first direction, and a seventh side and an eighth side facing each other in the second direction, wherein the first gate structure covers the first side, and the second gate A semiconductor device in which a structure covers the fifth side, the back gate structure covers the second side and the sixth side, the first gate structure has a first width in the portion covering the first side, and the back gate structure has a second width different from the first width in the portion covering the second side. Claim 2 A semiconductor device according to claim 1, wherein the first structure further comprises a first source / drain below the first vertical channel region and a second source / drain above the first vertical channel region, and the second structure further comprises a third source / drain below the second vertical channel region and a fourth source / drain above the second vertical channel region. Claim 3 delete Claim 4 delete Claim 5 A substrate; a first gate structure and a second gate structure spaced apart from each other on the substrate; a back gate structure disposed between the first gate structure and the second gate structure and spaced apart from the first and second gate structures; a first structure including a first vertical channel region extending in a vertical direction, and a second structure including a second vertical channel region extending in the vertical direction and spaced apart from the first structure, wherein at least a portion of the first vertical channel region is disposed between the first gate structure and the back gate structure, and at least a portion of the second vertical channel region is disposed between the second gate structure and the back gate structure, wherein the first vertical channel region includes a first side and a second side facing each other in a first direction, and a third side and a fourth side facing each other in a second direction intersecting the first direction, and the second vertical channel region includes a fifth side and a sixth side facing each other in the first direction, and a seventh side and an eighth side facing each other in the second direction, wherein the first gate structure covers the first side, and the second gate A semiconductor device in which a structure covers the fifth side, the back gate structure covers the second side and the sixth side, the first gate structure covers the first portion of each of the third and fourth sides, the second gate structure covers the second portion of each of the seventh and eighth sides, and the back gate structure covers the third portion of each of the third and fourth sides and the fourth portion of each of the seventh and eighth sides. Claim 6 A semiconductor device according to claim 5, wherein in each of the third and fourth aspects, the first part is larger than the third part, and in each of the seventh and eighth aspects, the second part is larger than the fourth part. Claim 7 A semiconductor device according to claim 1, wherein the first gate structure comprises a first gate electrode and a first gate dielectric layer between the first gate electrode and the first structure, the second gate structure comprises a second gate electrode and a second gate dielectric layer between the second gate electrode and the second structure, the back gate structure comprises a back gate dielectric layer and a back gate electrode, and the back gate dielectric layer comprises a first back gate dielectric portion interposed between the back gate electrode and the first structure and a second back gate dielectric portion interposed between the back gate electrode and the second structure. Claim 8 A semiconductor device according to claim 7, wherein the first gate electrode has a first vertical thickness and the back gate electrode has a second vertical thickness different from the first vertical thickness. Claim 9 delete Claim 10 A substrate; a first gate structure and a second gate structure spaced apart from each other on the substrate; a back gate structure disposed between the first gate structure and the second gate structure and spaced apart from the first and second gate structures; a first structure including a first vertical channel region extending in a vertical direction, and a second structure including a second vertical channel region extending in the vertical direction and spaced apart from the first structure, wherein at least a portion of the first vertical channel region is disposed between the first gate structure and the back gate structure, and at least a portion of the second vertical channel region is disposed between the second gate structure and the back gate structure, the first structure includes a first horizontal portion and a first vertical portion extending in the vertical direction from a portion of the first horizontal portion and including the first vertical channel region, and the second structure includes a second horizontal portion and a second vertical portion extending in the vertical direction from a portion of the second horizontal portion and including the second vertical channel region, at least a portion of the first gate structure is disposed on the first horizontal portion, and at least a portion of the second gate structure is disposed on the second horizontal portion, and the A semiconductor device further comprising: a first contact plug on a first vertical portion; a second contact plug on a first horizontal portion; an information storage structure on the first contact plug; and a bit line on the second contact plug, wherein the first gate structure includes a region disposed between the second contact plug and the first vertical portion, and at least a portion of the bit line is disposed at a higher level than the first vertical portion. Claim 11 A substrate; a first gate structure and a second gate structure spaced apart from each other on the substrate; a back gate structure disposed between the first gate structure and the second gate structure and spaced apart from the first and second gate structures; a first structure including a first vertical channel region extending in a vertical direction, and a second structure including a second vertical channel region extending in the vertical direction and spaced apart from the first structure, wherein at least a portion of the first vertical channel region is disposed between the first gate structure and the back gate structure, and at least a portion of the second vertical channel region is disposed between the second gate structure and the back gate structure, the first structure includes a first horizontal portion and a first vertical portion extending in the vertical direction from a portion of the first horizontal portion and including the first vertical channel region, and the second structure includes a second horizontal portion and a second vertical portion extending in the vertical direction from a portion of the second horizontal portion and including the second vertical channel region, at least a portion of the first gate structure is disposed on the first horizontal portion, and at least a portion of the second gate structure is disposed on the second horizontal portion, and the A semiconductor device further comprising: a contact plug on a first vertical portion; an information storage structure on the contact plug; and a bit line below the first horizontal portion. Claim 12 A substrate; a first structure comprising, on the substrate, a first horizontal portion and a pair of first vertical portions extending vertically from the first horizontal portion and spaced apart from each other; a second structure comprising, on the substrate, a second horizontal portion and a pair of second vertical portions extending vertically from the second horizontal portion and spaced apart from each other; a pair of first gate structures disposed between the pair of first vertical portions on the first horizontal portion and each extending horizontally; a pair of second gate structures disposed between the pair of second vertical portions on the second horizontal portion and each extending horizontally; and a back gate structure disposed between the first structure and the second structure, wherein contact structures disposed respectively on the pair of first vertical portions; a contact plug electrically connected to the first horizontal portion on the first horizontal portion; and an information storage structure electrically connected to the contact structures on the contact structures. and further comprising a bit line electrically connected to the contact plug on the contact plug, wherein the contact plug is disposed between the pair of first gate structures. Claim 13 A semiconductor device according to claim 12, wherein, among the pair of first gate structures and the pair of first vertical parts, the first gate structure and the first vertical part in contact with each other, the first vertical part comprises a first vertical channel region, the first vertical channel region comprises a first side and a second side facing each other, and a third side and a fourth side facing each other, the first gate structure covers at least a portion of each of the third and fourth sides and the first side, and the back gate structure covers at least the second side. Claim 14 In claim 13, in the first vertical channel region, the corner between the first side and the third side and the corner between the first side and the fourth side are rounded semiconductor devices. Claim 15 A semiconductor device according to claim 12, further comprising a device isolation region defining a first active region and a second active region on the substrate, wherein the first structure is disposed on the first active region and the second structure is disposed on the second active region. Claim 16 delete Claim 17 A first memory cell array; a second memory cell array spaced apart from the first memory cell array; A semiconductor device comprising a back gate control circuit disposed on at least one side of each of the first and second memory cell arrays, wherein each of the first and second memory cell arrays comprises transistors, word lines, bit lines, information storage structures, and back gate lines, wherein the back gate lines traverse the first and second memory cell arrays and are electrically connected to the back gate control circuit, wherein the bit lines extend in a first direction, and the word lines and the back gate lines are parallel to each other, spaced apart from each other, and extend in a second direction perpendicular to the first direction, wherein the transistors comprise a first pair of transistors sharing a first lower source / drain and a second pair of transistors sharing a second lower source / drain, wherein a first back gate line of one of the back gate lines is disposed between the first pair of transistors and the second pair of transistors, and each of the first pair of transistors further comprises a vertical channel region on the first lower source / drain and an upper source / drain on the vertical channel region. Claim 18 In claim 17, the wordlines constitute the gate electrodes of the first pair of transistors, and the first gate electrode among the gate electrodes covers at least three sides of the vertical channel region. Claim 19 In claim 18, the first back gate line covers at least three sides of the vertical channel region, and the vertical channel region is disposed between the first back gate line and the first gate electrode. Claim 20 In claim 17, the back gate control circuit is a semiconductor device that simultaneously controls a plurality of the back gate lines.

Images