Semiconducotr device and electronic system including the same

Abstract

A semiconductor device according to one embodiment of the present invention comprises: a first substrate, circuit elements disposed on the first substrate, and a peripheral circuit region including a first wiring structure electrically connected to the circuit elements; and a memory cell region comprising a second substrate disposed on the peripheral circuit region and having a first region and a second region, gate electrodes stacked spaced apart from each other along a first direction perpendicular to the upper surface of the second substrate on the first region, interlayer insulating layers stacked alternately with the gate electrodes, and a channel structure extending perpendicularly on the second substrate and including a channel layer penetrating the gate electrodes, wherein the gate electrodes include first gate electrodes, second gate electrodes on the first gate electrodes, third gate electrodes on the second gate electrodes, fourth gate electrodes on the third gate electrodes, and fifth gate electrodes on the fourth gate electrodes, and the interlayer insulating layers include first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, third interlayer insulating layers on the second interlayer insulating layers, fourth interlayer insulating layers on the third interlayer insulating layers, and fifth interlayer insulating layers on the fourth interlayer insulating layers, and the fourth gate electrodes Each has a thickness greater than each of the third gate electrodes, and each of the second interlayer insulating layers has a thickness greater than each of the third interlayer insulating layers.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and an electronic system including the same. Background Technology

[0003] In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. The problem to be solved

[0005] One of the technical problems that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and reliability.

[0006] One of the technical problems that the present invention aims to solve is to provide an electronic system including a semiconductor device with improved electrical characteristics and reliability. means of solving the problem

[0008] A semiconductor device according to one embodiment of the present invention comprises: a first substrate, circuit elements disposed on the first substrate, and a peripheral circuit region including a first wiring structure electrically connected to the circuit elements; and a memory cell region comprising a second substrate disposed on the peripheral circuit region and having a first region and a second region, gate electrodes stacked spaced apart from each other along a first direction perpendicular to the upper surface of the second substrate on the first region, interlayer insulating layers stacked alternately with the gate electrodes, and a channel structure extending perpendicularly on the second substrate and including a channel layer penetrating the gate electrodes, wherein the gate electrodes include first gate electrodes, second gate electrodes on the first gate electrodes, third gate electrodes on the second gate electrodes, fourth gate electrodes on the third gate electrodes, and fifth gate electrodes on the fourth gate electrodes, and the interlayer insulating layers include first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, third interlayer insulating layers on the second interlayer insulating layers, fourth interlayer insulating layers on the third interlayer insulating layers, and fifth interlayer insulating layers on the fourth interlayer insulating layers, and the fourth gate electrodes Each has a thickness greater than each of the third gate electrodes, and each of the second interlayer insulating layers has a thickness greater than each of the third interlayer insulating layers.

[0010] A semiconductor device according to one embodiment of the present invention comprises: a stacked structure including gate electrodes and interlayer insulating layers that are alternately and repeatedly stacked in a vertical direction; and a channel structure penetrating the stacked structure, wherein the gate electrodes include first gate electrodes, second gate electrodes on the first gate electrodes, and third gate electrodes on the second gate electrodes, each of the first gate electrodes has a first thickness, each of the second gate electrodes has a second thickness greater than the first thickness, and each of the third gate electrodes has a third thickness smaller than the second thickness.

[0012] An electronic system according to one embodiment of the present invention comprises: a peripheral circuit region including a first substrate, circuit elements disposed on the first substrate, and a first wiring structure electrically connected to the circuit elements; a memory cell region including a second substrate disposed on the peripheral circuit region and having a first region and a second region, gate electrodes stacked spaced apart from each other along a first direction perpendicular to the upper surface of the second substrate on the first region, interlayer insulating layers stacked alternately with the gate electrodes, and a channel structure penetrating the gate electrodes and extending perpendicularly on the second substrate and including a channel layer. A semiconductor device comprising an input / output pad electrically connected to the circuit elements, wherein the gate electrodes include first gate electrodes, second gate electrodes on the first gate electrodes, third gate electrodes on the second gate electrodes, fourth gate electrodes on the third gate electrodes, and fifth gate electrodes on the fourth gate electrodes, and the interlayer insulating layers include first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, third interlayer insulating layers on the second interlayer insulating layers, fourth interlayer insulating layers on the third interlayer insulating layers, and fifth interlayer insulating layers on the fourth interlayer insulating layers, wherein each of the fourth gate electrodes has a thickness greater than each of the third gate electrodes, and each of the second interlayer insulating layers has a thickness greater than each of the third interlayer insulating layers; and a controller electrically connected to the semiconductor device through the input / output pad and controlling the semiconductor device. Effects of the invention

[0014] By making the gate electrodes have different thicknesses and the interlayer insulating layers have different thicknesses, a semiconductor device with improved electrical characteristics and reliability and an electronic system including the same can be provided.

[0015] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0017] FIG. 1a is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 1b is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 2a is a partial enlarged view of a semiconductor device according to one embodiment of the present invention. FIG. 2b is a table describing a semiconductor device according to one embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a semiconductor device according to one embodiment of the present invention. FIG. 4a is a partial enlarged view of a semiconductor device according to one embodiment of the present invention. FIG. 4b is a table describing a semiconductor device according to one embodiment of the present invention. FIG. 5a is a partial enlarged view of a semiconductor device according to one embodiment of the present invention. FIG. 5b is a table describing a semiconductor device according to one embodiment of the present invention. FIGS. 6a to 6g are schematic cross-sectional views for illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 7 is a schematic diagram of an electronic system including a semiconductor device according to one embodiment of the present invention. FIG. 8 is a schematic perspective view of an electronic system including a semiconductor device according to one embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a semiconductor package according to one embodiment of the present invention. Specific details for implementing the invention

[0018] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0020] FIGS. 1a and FIGS. 1b are schematic cross-sectional views of a semiconductor device according to one embodiment of the present invention.

[0021] FIG. 2a is a partial enlarged view of a semiconductor device according to one embodiment of the present invention. FIG. 2a shows an enlarged view of region 'D' of FIG. 1a.

[0022] FIG. 2b is a table describing a semiconductor device according to one embodiment of the present invention.

[0023] FIG. 3 is a schematic circuit diagram of a semiconductor device according to one embodiment of the present invention.

[0024] Referring to FIGS. 1a through 3, the semiconductor device (100) may include a peripheral circuit region (PERI) including a first substrate (201), a memory cell region (CELL) including a second substrate (101), a through-wire region (TR) including a first through-via (165) electrically connecting the peripheral circuit region (PERI) and the memory cell region (CELL), and a ground wiring structure (GI) connecting the first substrate (201) and the second substrate (101). The memory cell region (CELL) may be positioned on the peripheral circuit region (PERI). Conversely, according to an embodiment, the cell region (CELL) may be positioned below the peripheral circuit region (PERI). The through-wire region (TR) may be positioned to extend from the memory cell region (CELL) to the peripheral circuit region (PERI). The ground wiring structure (GI) may be positioned to extend from a lower region of the memory cell region (CELL) to the peripheral circuit region (PERI).

[0025] The peripheral circuit region (PERI) may include a first substrate (201), source / drain regions (205) and device isolation layers (210) within the first substrate (201), circuit elements (220) disposed on the first substrate (201), a peripheral region insulating layer (290), a lower protection layer (295), and a first wiring structure (LI).

[0026] The first substrate (201) may have an upper surface extending in the x and y directions. An active region may be defined in the first substrate (201) by device isolation layers (210). Source / drain regions (205) containing impurities may be disposed in a portion of the active region. The first substrate (201) may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate (201) may be provided as a bulk wafer or an epitaxial layer.

[0027] The circuit elements (220) may include planar transistors. Each circuit element (220) may include a circuit gate dielectric layer (222), a spacer layer (224), and a circuit gate electrode (225). Source / drain regions (205) may be disposed within the first substrate (201) on both sides of the circuit gate electrode (225).

[0028] The peripheral region insulating layer (290) may be disposed on the circuit element (220) on the first substrate (201). The peripheral region insulating layer (290) may include first and second peripheral region insulating layers (292, 294), and the first and second peripheral region insulating layers (292, 294) may each include a plurality of insulating layers. The peripheral region insulating layer (290) may be made of an insulating material.

[0029] The lower protection layer (295) may be disposed on the upper surface of the third lower wiring lines (286) between the first and second peripheral area insulation layers (292, 294). According to an embodiment, the lower protection layer (295) may be further disposed on the upper surface of the first and second lower wiring lines (282, 284). The lower protection layer (295) may be a layer to prevent contamination by metallic material of the lower wiring lines (280) disposed below. The lower protection layer (295) may be made of an insulating material different from the peripheral area insulation layer (290), and may include, for example, silicon nitride.

[0030] The first wiring structure (LI) may be a wiring structure electrically connected to circuit elements (220) and source / drain regions (205). The first wiring structure (LI) may include cylindrical lower contact plugs (270) and line-shaped lower wiring lines (280). The lower contact plugs (270) may include first to third lower contact plugs (272, 274, 276). The first lower contact plugs (272) may be placed on the circuit elements (220) and source / drain regions (205), the second lower contact plugs (274) may be placed on the first lower wiring lines (282), and the third lower contact plugs (276) may be placed on the second lower wiring lines (284). The lower wiring lines (280) may include first to third lower wiring lines (282, 284, 286). The first lower wiring lines (282) may be placed on the first lower contact plugs (272), the second lower wiring lines (284) may be placed on the second lower contact plugs (274), and the third lower wiring lines (286) may be placed on the third lower contact plugs (276). The first wiring structure (LI) may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include a diffusion barrier layer. According to the embodiment, the number of layers and arrangement of the lower contact plugs (270) and lower wiring lines (280) constituting the first wiring structure (LI) may be varied.

[0031] A memory cell region (CELL) may include a second substrate (101) having a first region (A) and a second region (B), first and second horizontal conductive layers (102, 104) on the second substrate (101), gate electrodes (130) stacked on the second substrate (101), first and second separation regions (MS1, MS2) extending through the stacked structure of the gate electrodes (130), upper separation regions (SS) penetrating a part of the stacked structure, channel structures (CH) arranged to penetrate the stacked structure, and a second wiring structure (UI) electrically connected to the gate electrodes (130) and the channel structures (CH). The memory cell region (CELL) may further include substrate insulating layers (105i, 105o), interlayer insulating layers (120) alternately stacked with gate electrodes (130) on the second substrate (101), gate contacts (162) connected to the gate electrodes (130), substrate contacts (164) connected to the second substrate (101), a cell region insulating layer (190) covering the gate electrodes (130), and an upper protective layer (195). The memory cell region (CELL) may further have a third region (C) outside the second substrate (101), and a through-wiring structure, such as a second through-via (167) connecting the memory cell region (CELL) and the peripheral circuit region (PERI), may be disposed in the third region (C).

[0032] The first region (A) of the second substrate (101) may be a region where memory cells are arranged, in which gate electrodes (130) are vertically stacked and channel structures (CH) are arranged, and the second region (B) may be a region where the gate electrodes (130) extend at different lengths and may correspond to a region for electrically connecting the memory cells to a peripheral circuit region (PERI). The second region (B) may be arranged at least one end of the first region (A) in at least one direction, for example, in the x direction.

[0033] The second substrate (101) may have an upper surface extending in the x and y directions. The second substrate (101) may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate (101) may further include impurities. The second substrate (101) may be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or as an epitaxial layer. The second substrate (101) may have a substantially flat upper surface and a non-flat lower surface protruding by an upper via (GV).

[0034] The first and second horizontal conductive layers (102, 104) may be stacked and disposed on the upper surface of the second substrate (101). At least a portion of the first and second horizontal conductive layers (102, 104) may function as part of a common source line of the semiconductor device (100), for example, as a common source line together with the second substrate (101). As shown in the enlarged view of FIG. 1b, the first horizontal conductive layer (102) may be directly connected to the channel layer (140) around the channel layer (140). The first and second horizontal conductive layers (102, 104) may include a semiconductor material, for example, polycrystalline silicon. In this case, at least the first horizontal conductive layer (102) may be a doped layer, and the second horizontal conductive layer (104) may be a doped layer or a layer containing impurities diffused from the first horizontal conductive layer (102).

[0035] A horizontal insulating layer (110) may be disposed on a second substrate (101) in parallel with a first horizontal conductive layer (102) in at least a portion of a second region (B). The horizontal insulating layer (110) may be layers remaining after a portion of the first horizontal conductive layer (102) is replaced during the manufacturing process of the semiconductor device (100). The horizontal insulating layer (110) may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The horizontal insulating layer (110) may include first to third horizontal insulating layers stacked in sequence, wherein the first and third horizontal insulating layers are silicon oxide layers and the second horizontal insulating layer is a silicon nitride layer.

[0036] The substrate insulating layers (105i, 105o) may be disposed in an area where a portion of the second substrate (101), the first and second horizontal conductive layers (102, 104), and the horizontal insulating layer (110) has been removed, and may be disposed to be in contact with the side of the second substrate (101), the first and second horizontal conductive layers (102, 104), and the horizontal insulating layer (110). The lower surface of the substrate insulating layers (105i, 105o) may be co-plane with the lower surface of the second substrate (101) or may be located at a lower level than the lower surface of the second substrate (101). The substrate insulating layers (105i, 105o) may be made of an insulating material and may include, for example, silicon oxide, silicon oxynitride, or silicon nitride.

[0037] Gate electrodes (130) may be stacked vertically spaced apart on the second substrate (101) to form a stacked structure. The gate electrodes (130) may include a ground selection gate electrode (130L) forming a ground selection transistor, a memory cell gate electrode (130M) forming memory cells, and a string selection gate electrode (130U) forming a string selection transistor, sequentially formed from the second substrate (101). According to an embodiment, the ground selection gate electrode (130L) and the string selection gate electrode (130U) may each be one or two or more, and may have the same or different structure as the memory cell gate electrode (130M). The number of memory cell gate electrodes (130M) may be determined according to the capacity of the semiconductor device (100). The memory cell gate electrode (130M) may include first gate electrodes (130M1), second gate electrodes (130M2) on the first gate electrodes (130M1), third gate electrodes (130M3) on the second gate electrodes (130M2), fourth gate electrodes (130M4) on the third gate electrodes (130M3), and fifth gate electrodes (130M5) on the fourth gate electrodes (130M4). Additionally, the gate electrodes (130) may further include an erase gate electrode (130E) which is disposed on the string select gate electrode (130U) or below the ground select gate electrode (130L) and forms an erase transistor used for an erase operation utilizing the Gate Induced Drain Leakage (GIDL) phenomenon. Some gate electrodes (130), for example, gate electrodes (130) adjacent to string select gate electrode (130U) and ground select gate electrode (130L), may be dummy gate electrodes.

[0038] Each of the first to fifth gate electrodes (130M1, 130M2, 130M3, 130M4, 130M5) may have a horizontal area that decreases as it moves away from the second substrate (101). This may be because the horizontal area of ​​the channel structures (CH) surrounded by the first to fifth gate electrodes (130M1, 130M2, 130M3, 130M4, 130M5) increases as it moves away from the second substrate (101). Each of the first to fifth gate electrodes (130M1, 130M2, 130M3, 130M4, 130M5) may have a resistance value that increases as it moves away from the second substrate (101). This may be due to the fact that the horizontal area of ​​each of the first to fifth gate electrodes (130M1, 130M2, 130M3, 130M4, 130M5) decreases as they move further away from the second substrate (101). In this embodiment, the thickness of each of the first to fifth gate electrodes (130M1, 130M2, 130M3, 130M4, 130M5) may vary. Each of the fourth gate electrodes (130M4) may have a greater thickness than each of the first, second, third, and fifth gate electrodes (130M1, 130M2, 130M3, 130M5), for example, each of the fourth gate electrodes (130M4) may have a thickness of about 1.005 to about 1.1 times greater than each of the first, second, third, and fifth gate electrodes (130M1, 130M2, 130M3, 130M5). This may be because the thickness of each of the fourth gate electrodes (130M4) is increased in order to lower the resistance value of each of the fourth gate electrodes (130M4). However, the thickness of each of the fifth gate electrodes (130M5) may not be increased, and each of the fifth gate electrodes (130M5) may have substantially the same thickness as each of the first to third gate electrodes (130M1, 130M2, 130M3). This may be to prevent the total thickness of the first to fifth gate electrodes (130M1, 130M2, 130M3, 130M4, 130M5) from becoming too large.Additionally, the length of overlap between each of the fourth gate electrodes (130M4) and the channel structures (CH) along the first direction may be greater than the length of overlap between each of the first, second, third, and fifth gate electrodes (130M1, 130M2, 130M3, 130M5) and the channel structures (CH) along the first direction. Additionally, the area of ​​each of the fourth gate electrodes (130M4) surrounding the channel structures (CH) may be greater than the area of ​​each of the first, second, third, and fifth gate electrodes (130M1, 130M2, 130M3, 130M5) surrounding the channel structures (CH). Each of the string select gate electrode, ground select gate electrode, and erase gate electrode may have a greater thickness than each of the first, second, third, and fifth gate electrodes (130M1, 130M2, 130M3, 130M5). Each of the first, second, third, and fifth gate electrodes (130M1, 130M2, 130M3, 130M5) may have substantially the same thickness as each other.

[0039] Gate electrodes (130) are stacked vertically spaced apart from each other on a first region (A) and may extend from the first region (A) to a second region (B) by different lengths to form a stepped structure. The gate electrodes (130) may form a stepped structure between the gate electrodes (130) along the x direction, as shown in FIG. 1a. According to an embodiment, at least some of the gate electrodes (130) may form a gate group with a certain number, for example, two to six gate electrodes (130), to form a stepped structure between the gate groups along the x direction. In this case, the gate electrodes (130) forming one gate group may be arranged to have a stepped structure between each other in the y direction as well. Due to the stepped structure, the gate electrodes (130) may form a stepped shape in which the lower gate electrode (130) extends longer than the upper gate electrode (130) and provide ends exposed upward from the interlayer insulating layers (120). According to the embodiment, at the ends, the gate electrodes (130) may have an increased thickness.

[0040] The gate electrodes (130) may comprise a metallic material, for example, tungsten (W). According to an embodiment, the gate electrodes (130) may comprise polycrystalline silicon or a metal silicide material. According to an embodiment, the gate electrodes (130) may further comprise a diffusion barrier layer, for example, the diffusion barrier layer may comprise tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0041] Interlayer insulating layers (120) may be disposed between gate electrodes (130). The interlayer insulating layers (120), like the gate electrodes (130), may also be disposed spaced apart from each other in a direction perpendicular to the upper surface of the second substrate (101) and extended in the x-direction. The interlayer insulating layers (120) may comprise an insulating material such as silicon oxide or silicon nitride. The interlayer insulation layers (120) may include first interlayer insulation layers (120M1), second interlayer insulation layers (120M2) on the first interlayer insulation layers (120M1), third interlayer insulation layers (120M3) on the second interlayer insulation layers (120M2), fourth interlayer insulation layers (120M4) on the third interlayer insulation layers (120M3), and fifth interlayer insulation layers (120M5) on the fourth interlayer insulation layers (120M4).

[0042] In this embodiment, each of the first and second interlayer insulating layers (120M1, 120M2) may have a greater thickness than each of the third to fifth interlayer insulating layers (120M3, 120M4, 120M5), for example, each of the first and second interlayer insulating layers (120M1, 120M2) may have a thickness about 1.005 times to about 1.1 times greater than each of the third to fifth interlayer insulating layers (120M3, 120M4, 120M5). This may be such that the thickness of each of the first and second interlayer insulating layers (120M1, 120M2) is increased in order to improve the critical read window of each of the first and second gate electrodes (130M1, 130M2) in contact with the first and second interlayer insulating layers (120M1, 120M2). Additionally, the length of overlap between each of the first and second interlayer insulating layers (120M1, 120M2) and the channel structures (CH) along the first direction may be greater than the length of overlap between each of the third to fifth interlayer insulating layers (120M3, 120M4, 120M5) and the channel structures (CH) along the first direction. Additionally, the area of ​​each of the first and second interlayer insulating layers (120M1, 120M2) surrounding the channel structures (CH) may be larger than the area of ​​each of the third to fifth interlayer insulating layers (120M3, 120M4, 120M5) surrounding the channel structures (CH). Each of the third to fifth interlayer insulating layers (120M3, 120M4, 120M5) may have substantially the same thickness.

[0043] The first and second separation regions (MS1, MS2) may be arranged to extend along the x-direction through the gate electrodes (130) in the first region (A) and the second region (B). The first and second separation regions (MS1, MS2) may be arranged parallel to each other. The first and second separation regions (MS1, MS2) may be connected to the second substrate (101) by penetrating the entire gate electrodes (130) stacked on the second substrate (101), as shown in FIG. 1B. The first separation regions (MS1) may extend as one along the first region (A) and the second region (B), and the second separation regions (MS2) may extend only to a part of the second region (B) or be arranged intermittently in the first region (A) and the second region (B). Depending on the embodiment, the arrangement order, arrangement spacing, etc. of the first and second separation regions (MS1, MS2) may be varied.

[0044] A separation insulating layer (108) may be disposed in the first and second separation regions (MS1, MS2). According to an embodiment, the separation insulating layer (108) may have a shape in which its width decreases toward the second substrate (101) due to a high aspect ratio. According to an embodiment, a conductive layer may be further disposed between the separation insulating layer (108) in the first and second separation regions (MS1, MS2). In this case, the conductive layer may function as a common source line of the semiconductor device (100) or as a contact plug connected to the common source line.

[0045] The upper separation regions (SS) may extend in the x-direction between the first separation regions (MS1) and the second separation region (MS2). The upper separation regions (SS) may be positioned in part of the second region (B) and the first region (A) so as to penetrate some of the gate electrodes (130), including the uppermost gate electrode (130) among the gate electrodes (130). The upper separation regions (SS) may separate a total of three gate electrodes (130) from each other in the y-direction, for example, as illustrated in FIG. 1b. Depending on the embodiment, the number of gate electrodes (130) separated by the upper separation regions (SS) may vary. The upper separation regions (SS) may include an upper separation insulating layer (107).

[0046] Channel structures (CH) each form a single memory cell string and can be spaced apart from each other in rows and columns on the first region (A). The channel structures (CH) can be arranged to form a grid pattern in the xy plane or arranged in a zigzag shape in one direction. The channel structures (CH) have a columnar shape and can have inclined sides that become narrower as they approach the second substrate (101) according to the aspect ratio. According to an embodiment, dummy channels that do not substantially form a memory cell string may be further arranged at the end of the first region (A) adjacent to the second region (B) and in the second region (B).

[0047] As illustrated in the enlarged view of FIG. 1b, a channel layer (140) may be disposed within the channel structures (CH). Within the channel structures (CH), the channel layer (140) may be formed in an annular shape surrounding an internal channel insulating layer (150), but according to the embodiment, it may have a columnar shape such as a cylinder or a prismatic column without a channel insulating layer (150). The channel layer (140) may be connected to a first horizontal conductive layer (102) at the bottom. The channel layer (140) may include a semiconductor material such as polycrystalline silicon or single-crystal silicon. Channel structures (CH) disposed in a straight line in the y-direction between the first or second separation regions (MS1, MS2) and the upper separation region (SS) may be electrically separated from each other by a second wiring structure (UI) connected to channel pads (155).

[0048] Channel pads (155) may be disposed on the upper surface of the channel layer (140) in the channel structures (CH). The channel pads (155) may be disposed to cover the upper surface of the channel insulating layer (150) and to be electrically connected to the channel layer (140). The channel pads (155) may comprise, for example, doped polycrystalline silicon.

[0049] Each of the channel structures (CH) may further include memory cells facing each of the gate electrodes (130). In this embodiment, the second memory cells (MC_U), the third memory cells (MC_M), and the fourth memory cells (MC_L) facing each of the second to fourth gate electrodes (130M2, 130M3, 130M4) among the memory cells store n bit data, and the first memory cells (MC_DU) and the fifth memory cells (MC_DL) facing each of the first and fifth gate electrodes (130M1, 130M5) among the memory cells store m bit data, and n and m may be different natural numbers. Specifically, the second memory cells (MC_U), the third memory cells (MC_M), and the fourth memory cells (MC_L) are triple-level cells that store three bits of data, and the first memory cells (MC_DU) and the fifth memory cells (MC_DL) may be multi-level cells that store two bits of data. This may be intended to improve the cell operation speed.

[0050] A gate dielectric layer (145) may be disposed between the gate electrodes (130) and the channel layer (140). Although not specifically illustrated, the gate dielectric layer (145) may include a tunneling layer, a charge storage layer, and a blocking layer stacked sequentially from the channel layer (140). The tunneling layer may tunnel charge to the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. According to an embodiment, at least a portion of the gate dielectric layer (145) may extend horizontally along the gate electrodes (130).

[0051] The cell region insulating layer (190) may be disposed to cover the second substrate (101), the gate electrodes (130) on the second substrate (101), and the peripheral region insulating layer (290). The cell region insulating layer (190) may include first and second cell region insulating layers (192, 194), and the first and second cell region insulating layers (192, 194) may each include a plurality of insulating layers. The cell region insulating layer (190) may be made of an insulating material.

[0052] An upper protective layer (195) may be disposed on the upper surface of the first upper wiring lines (182) between the first and second cell region insulating layers (192, 194). According to an embodiment, the upper protective layer (195) may be further disposed on the upper surface of the second upper wiring lines (184). The upper protective layer (195) may be a layer to prevent contamination by the metallic material of the upper wiring lines (180) disposed below. The upper protective layer (195) may be made of an insulating material different from that of the cell region insulating layer (190), and may include, for example, silicon nitride.

[0053] Gate contacts (162) may be connected to gate electrodes (130) in the second region (B). Gate contacts (162) may be arranged to penetrate at least a portion of the first cell region insulating layer (192) and be connected to each of the gate electrodes (130) exposed to the top. Gate contacts (162) may include first to fifth gate contacts connected to each of the first to fifth gate electrodes (130M1, 130M2, 130M3, 130M4, 130M5). In the present embodiment, the height difference between adjacent fourth gate contacts among the fourth gate contacts may be greater than the height difference between adjacent third gate contacts among the third gate contacts. The height difference between adjacent first and second gate contacts among the first and second gate contacts may be greater than the height difference between adjacent third gate contacts among the third gate contacts.

[0054] A substrate contact (164) can be connected to a second substrate (101) at an end of the second region (B). The substrate contact (164) can be connected to the second substrate (101) by penetrating at least a portion of the first cell region insulating layer (192) and penetrating the first and second horizontal conductive layers (102, 104) exposed to the top. The substrate contact (164) can apply an electrical signal to a common source line including, for example, the second substrate (101).

[0055] The second wiring structure (UI) may be a wiring structure electrically connected to the gate electrodes (130) and channel structures (CH). The second wiring structure (UI) may include cylindrical upper contact plugs (170) and line-shaped upper wiring lines (180). The upper contact plugs (170) may include first to third upper contact plugs (172, 174, 176). The first upper contact plugs (172) may be placed on the channel pads (155) and gate contacts (162), the second upper contact plugs (174) may be placed on the first upper contact plugs (172), and the third upper contact plugs (176) may be placed on the first upper wiring lines (182). The upper wiring lines (180) may include the first and second upper wiring lines (182, 184). The first upper wiring lines (182) may be placed on the second upper contact plugs (174), and the second upper wiring lines (184) may be placed on the third upper contact plugs (176). The second wiring structure (UI) may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each may further include a diffusion barrier layer. According to the embodiment, the number of layers and arrangement of the upper contact plugs (170) and upper wiring lines (180) constituting the second wiring structure (UI) may be varied.

[0056] The through-wire region (TR) may be a region including a through-wire structure for electrically connecting a memory cell region (CELL) and a peripheral circuit region (PERI) to each other. The through-wire region (TR) may include a first through-via (165) extending in the z-direction through the second substrate (101) from the top of the memory cell region (CELL) and an insulating region surrounding the first through-via (165). The insulating region may include sacrificial insulating layers (118), interlayer insulating layers (120) arranged perpendicularly to the sacrificial insulating layers (118), and a substrate insulating layer (105). Depending on the embodiment, the size, arrangement form, and shape of the through-wire region (TR) may be varied. In FIG. 1a, the through-wire region (TR) is shown as being arranged in the second region (B), but is not limited thereto and may also be arranged in the first region (A) at a predetermined interval. The through-wiring region (TR) may be spaced apart from the first and second separation regions (MS1, MS2). For example, the through-wiring region (TR) may be positioned in the center of a pair of adjacent first separation regions (MS1) along the y-direction. With such a position, sacrificial insulating layers (118) may remain in the through-wiring region (TR).

[0057] The first through-via (165) may extend vertically to the upper surface of the second substrate (101) by penetrating from the top a portion of the first cell region insulating layer (192), the insulating region, the lower protective layer (295), and the second peripheral region insulating layer (294). The upper end of the first through-via (165) may be connected to the second wiring structure (UI), and the lower end may be connected to the first wiring structure (LI). According to the embodiment, the number, arrangement, and shape of the first through-via (165) within a single through-wiring region (TR) may vary. The first through-via (165) may include a conductive material and may include a metallic material such as, for example, tungsten (W), copper (Cu), or aluminum (Al).

[0058] Sacrificial insulating layers (118) may be positioned at the same height level and thickness as the gate electrodes (130) and may be arranged so as to be in contact with the gate electrodes (130) on the side at the boundary of the through-wiring region (TR). Depending on the embodiment, a barrier structure may be further disposed between the sacrificial insulating layers (118) and the gate electrodes (130). The sacrificial insulating layers (118) may be stacked alternately with the interlayer insulating layers (120) to form the insulating region. The sacrificial insulating layers (118) may be disposed with the same or different width as the lower inner substrate insulating layers (105i). The sacrificial insulating layers (118) may be made of an insulating material different from that of the interlayer insulating layers (120), and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0059] The second through-via (167) may extend through the outer substrate insulating layer (105o) placed in the outer region (C) to the peripheral circuit structure (PERI). The second through-via (167) may be positioned to connect the upper wiring structure (UI) and the lower wiring structure (LI) similarly to the first through-via (165) of the through-wiring region (TR). The second through-via (167) may include a conductive material and may include a metallic material such as, for example, tungsten (W), copper (Cu), aluminum (Al).

[0060] A ground wiring structure (GI) may be placed across a peripheral circuit area (PERI) and a memory cell area (CELL) to connect a first substrate (201) and a second substrate (101). The ground wiring structure (GI) may perform the function of grounding the second substrate (101) during the manufacturing process of the semiconductor device (100). The ground wiring structure (GI) may include lower contact plugs (270) and lower wiring lines (280), which are lower wiring structures corresponding to the first wiring structure (LI), and may further include an upper via (GV) connected to a third lower wiring line (286) at the top of the lower wiring lines (280).

[0061] The upper via (GV) can be directly connected to the third lower wiring line (286) by penetrating the second peripheral region insulating layer (294) and the lower protective layer (295). The upper via (GV) may have a form integrated with the second substrate (101) of the memory cell region (CELL). The upper via (GV) may be formed together with the second substrate (101) and may contain the same material as the second substrate (101), and there may be no interface between it and the second substrate (101).

[0063] FIG. 4a is a partial enlarged view of a semiconductor device according to one embodiment of the present invention.

[0064] FIG. 4b is a table describing a semiconductor device according to one embodiment of the present invention.

[0065] Referring to FIGS. 4a and 4b, unlike the embodiments of FIGS. 1a through 3, each of the fifth gate electrodes (130M5) may have a greater thickness than each of the first, second, and third gate electrodes (130M1, 130M2, 130M3), for example, each of the fifth gate electrodes (130M5) may have a thickness about 1.005 times to about 1.1 times greater than each of the first, second, and third gate electrodes (130M1, 130M2, 130M3). This may be because the thickness of each of the fifth gate electrodes (130M5) is increased in order to lower the resistance value of each of the fifth gate electrodes (130M5).

[0066] The thickness of each of the first interlayer insulating layers (120M1) may not be increased, and each of the first interlayer insulating layers (120M1) may have substantially the same thickness as each of the third to fifth interlayer insulating layers (120M3, 120M4, 120M5). This may be to prevent the total thickness of the first to fifth interlayer insulating layers (120M1, 120M2, 120M3, 120M4, 120M5) from becoming too large.

[0068] FIG. 5a is a partial enlarged view of a semiconductor device according to one embodiment of the present invention.

[0069] FIG. 5b is a table describing a semiconductor device according to one embodiment of the present invention.

[0070] Referring to FIGS. 5a and 5b, unlike the embodiments of FIGS. 1a through 3, each of the fifth gate electrodes (130M5) may have a greater thickness than each of the first, second, and third gate electrodes (130M1, 130M2, 130M3), for example, each of the fifth gate electrodes (130M5) may have a thickness about 1.005 times to about 1.1 times greater than each of the first, second, and third gate electrodes (130M1, 130M2, 130M3). This may be because the thickness of each of the fifth gate electrodes (130M5) is increased in order to lower the resistance value of each of the fifth gate electrodes (130M5).

[0072] FIGS. 6a to 6g are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 6a to 6g illustrate a region corresponding to the region shown in FIG. 1a.

[0073] Referring to FIG. 6a, circuit elements (220) and a first wiring structure (LI) can be formed on a first substrate (201).

[0074] First, device isolation layers (210) may be formed within the first substrate (201), and a circuit gate dielectric layer (222) and a circuit gate electrode (225) may be sequentially formed on the first substrate (201). The device isolation layers (210) may be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer (222) and the circuit gate electrode (225) may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer (222) may be formed of silicon oxide, and the circuit gate electrode (225) may be formed of at least one of polycrystalline silicon or a metal silicide layer, but is not limited thereto. Next, a spacer layer (224) and source / drain regions (205) can be formed on both side walls of the circuit gate dielectric layer (222) and the circuit gate electrode (225). According to an embodiment, the spacer layer (224) may be composed of a plurality of layers. Next, an ion implantation process can be performed to form the source / drain regions (205).

[0075] The lower contact plugs (270) of the first wiring structure (LI) can be formed by forming a portion of the first peripheral region insulating layer (292), then etching and removing a portion of it, and burying a conductive material. The lower wiring lines (280) can be formed, for example, by depositing a conductive material and then patterning it. When forming the first wiring structure (LI), a lower wiring structure forming part of the ground wiring structure (GI) (see FIG. 1a) can be formed together. Thus, the lower wiring structure can have the same stacked structure as the first wiring structure (LI).

[0076] The first peripheral area insulating layer (292) may be composed of multiple insulating layers. The first peripheral area insulating layer (292) may be part of each step of forming the first wiring structure (LI). A lower protective layer (295) covering the upper surface of the third lower wiring line (286) may be formed on the first peripheral area insulating layer (292).

[0078] Referring to FIG. 6b, a second peripheral region insulating layer (294) can be formed on the lower protective layer (295), and a second substrate (101) of the memory cell region and an upper via (GV) of the ground wiring structure (GI) can be formed on the peripheral circuit region (PERI).

[0079] By forming the second peripheral region insulating layer (294), the entire peripheral circuit region (PERI) can be formed.

[0080] A via hole can be formed by partially removing the second peripheral area insulating layer (294). The via hole may be a through hole for forming an upper via (GV) (see FIG. 1a) of the ground wiring structure (GI). The via hole may be formed by removing the second peripheral area insulating layer (294) and the lower protective layer (295) using a separate mask layer so that the third lower wiring line (286) of the lower wiring structure forming the ground wiring structure (GI) is exposed.

[0081] The second substrate (101) may be made of polycrystalline silicon, for example, and may be formed by a CVD process. When the second substrate (101) is formed, the material forming the second substrate (101) may fill the via hole to form an upper via (GV). The polycrystalline silicon forming the second substrate (101) may contain impurities, for example, n-type impurities. After the second substrate (101) is formed over the entire second peripheral region insulating layer (294), it may be patterned and removed from a portion of the memory cell region (CELL), including the third region (C). In the area where the second substrate (101) is removed, the barrier layer (103) below the second substrate (101) may also be removed together.

[0083] Referring to FIG. 6c, a horizontal insulating layer (110) and a second horizontal conductive layer (104) are formed, and then substrate insulating layers (105i, 105o) are formed, and then sacrificial insulating layers (118) and interlayer insulating layers (120) can be alternately stacked.

[0084] First and second horizontal insulating layers (111, 112) forming a horizontal insulating layer (110) may be formed on a second substrate (101). The first and second horizontal insulating layers (111, 112) may be laminated on the second substrate (101) such that the first horizontal insulating layers (111) are positioned above and below the second horizontal insulating layer (112). The first and second horizontal insulating layers (111, 112) may comprise different materials. For example, the first horizontal insulating layers (111) may be made of the same material as the interlayer insulating layers (120), and the second horizontal insulating layer (112) may be made of the same material as the sacrificial insulating layers (118). The horizontal insulating layer (110) may be layers that are replaced by the first horizontal conductive layer (102) of FIG. 1a through a subsequent process. The horizontal insulating layer (110) can be removed in some areas by a patterning process.

[0085] A second horizontal conductive layer (104) is formed on the first and second horizontal insulating layers (111, 112) and can be in contact with the second substrate (101) in the area where the horizontal insulating layer (110) is removed. Accordingly, the second horizontal conductive layer (104) is bent along the ends of the horizontal insulating layer (110) and can extend over the ends and onto the second substrate (101).

[0086] The substrate insulating layers (105i, 105o) can be formed by partially removing the first and second horizontal insulating layers (111, 112), the second horizontal conductive layer (104), and the second substrate (101), and filling them with insulating material. After filling with the insulating material, a planarization process can be further performed using a Chemical Mechanical Polishing (CMP) process. By doing so, the upper surface of the substrate insulating layers (105i, 105o) can substantially co-plane with the upper surface of the second horizontal conductive layer (104).

[0087] Next, sacrificial insulating layers (118) and interlayer insulating layers (120) can be formed alternately stacked on the second horizontal conductive layer (104). The sacrificial insulating layers (118) may be layers in which a portion is replaced by gate electrodes (130) (see FIG. 2a) through a subsequent process. The sacrificial insulating layers (118) may be made of a material different from the interlayer insulating layers (120) and may be formed of a material that can be etched with etch selectivity with respect to the interlayer insulating layers (120) under specific etching conditions. For example, the interlayer insulating layers (120) may be made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layers (118) may be made of a material different from the interlayer insulating layers (120) selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In the embodiments, the thickness of the interlayer insulating layers (120) may not all be the same. The thickness of the interlayer insulating layers (120) and the sacrificial insulating layers (118) and the number of constituent films can be varied from that shown.

[0088] In order for the upper sacrificial insulating layers (118) to extend shorter than the lower sacrificial insulating layers (118) on the second region (B), photolithography and etching processes can be repeated on the sacrificial insulating layers (118) using a mask layer. By doing so, the sacrificial insulating layers (118) can form a stepped structure in a predetermined unit.

[0089] Next, a first cell region insulating layer (192) covering the stacked structure of sacrificial insulating layers (118) and interlayer insulating layers (120) can be formed.

[0091] Referring to FIG. 6d, channel structures (CH) can be formed that penetrate the stacked structure of sacrificial insulating layers (118) and interlayer insulating layers (120).

[0092] First, upper separation regions (SS) (see FIG. 1b) can be formed by removing a portion of the sacrificial insulating layers (118) and interlayer insulating layers (120). The upper separation regions (SS) can be formed by using a separate mask layer to expose the area where the upper separation regions (SS) are to be formed, removing a predetermined number of sacrificial insulating layers (118) and interlayer insulating layers (120) from the top, and then depositing an insulating material.

[0093] Channel structures (CH) can be formed by anisotropically etching sacrificial insulating layers (118) and interlayer insulating layers (120), and by forming hole-shaped channel holes and then filling them. Due to the height of the stacked structure, the sidewalls of the channel structures (CH) may not be perpendicular to the upper surface of the second substrate (101). The channel structures (CH) may be formed to recess a portion of the second substrate (101). Next, at least a portion of the gate dielectric layer (145), the channel layer (140), the channel insulating layer (150), and the channel pads (155) may be sequentially formed within the channel structures (CH).

[0094] The gate dielectric layer (145) can be formed to have a uniform thickness using an ALD or CVD process. In this step, the gate dielectric layer (145) may be formed in whole or in part, and a portion extending perpendicularly to the second substrate (101) along the channel structures (CH) may be formed in this step. The channel layer (140) may be formed on the gate dielectric layer (145) within the channel structures (CH). The channel insulating layer (150) is formed to fill the channel structures (CH) and may be an insulating material. However, depending on the embodiments, the channel layers (140) may be filled with a conductive material instead of the channel insulating layer (150). The channel pad (155) may be made of a conductive material, for example, polycrystalline silicon.

[0096] Referring to FIG. 6e, openings can be formed penetrating the stacked structure of sacrificial insulating layers (118) and interlayer insulating layers (120) in regions corresponding to the first and second separation regions (MS1, MS2) (see FIG. 1b), and tunnel regions (LT) can be formed by removing a portion of the sacrificial insulating layers (118) through the openings.

[0097] First, separate sacrificial spacer layers can be formed within the openings, and then the second horizontal insulating layers (112) can be selectively removed, and then the first horizontal insulating layers (111) can be removed. The first and second horizontal insulating layers (111, 112) can be removed, for example, by a wet etching process. During the removal process of the first horizontal insulating layers (111), a portion of the gate dielectric layer (145) exposed in the area where the second horizontal insulating layers (112) were removed can also be removed. After forming the first horizontal conductive layer (102) by depositing a conductive material in the area where the first and second horizontal insulating layers (111, 112) were removed, the sacrificial spacer layers can be removed within the openings.

[0098] Next, the sacrificial insulating layers (118) can be removed from the outside of the through-wire area (TR) (see FIG. 1a). In the through-wire area (TR), the sacrificial insulating layers (118) may remain to form an insulating area of ​​the through-wire area (TR) together with the interlayer insulating layers (120). The sacrificial insulating layers (118) can be selectively removed from the interlayer insulating layers (120), for example, using wet etching. Accordingly, a plurality of tunnel sections (LT) can be formed between the interlayer insulating layers (120).

[0099] The area where the through-wiring area (TR) is formed may be an area spaced apart from the openings, where the sacrificial insulating layers (118) remain because the etchant does not reach. Accordingly, the through-wiring area (TR) may be formed in the center of the first and second separation areas (MS1, MS2) between the adjacent first and second separation areas (MS1, MS2).

[0101] Referring to FIG. 6f, gate electrodes (130) can be formed by burying a conductive material in the tunnel sections (LT) from which the sacrificial insulating layers (118) have been partially removed.

[0102] The conductive material forming the gate electrodes (130) can fill the tunnel portions (LT). The sides of the gate electrodes (130) can come into contact with the sides of the sacrificial insulating layers (118) of the through-wiring region (TR). The conductive material may include a metal, polycrystalline silicon, or metal silicide material. After forming the gate electrodes (130), the conductive material deposited within the openings can be removed through an additional process, and then an insulating material can be filled to form a separating insulating layer (108) (see FIG. 1b).

[0104] Referring to FIG. 6g, gate contacts (162), substrate contacts (164), and first and second through vias (165, 167) can be formed through the first cell region insulating layer (192).

[0105] Gate contacts (162) may be formed to be connected to gate electrodes (130) in the second region (B), and substrate contacts (164) may be formed to be connected to the second substrate (101) at the end of the second region (B). A first through-via (165) may be formed to be connected to a first wiring structure (LI) of a peripheral circuit region (PERI) in a through-wiring region (TR), and a second through-via (167) may be formed to be connected to a first wiring structure (LI) of a peripheral circuit region (PERI) in a third region (C).

[0106] The gate contacts (162), substrate contacts (164), and first and second through-vias (165, 167) are formed at different depths, but can be formed by simultaneously forming contact holes using an etch stop layer or the like and then filling the contact holes with a conductive material. However, in some embodiments, it may be possible for some of the gate contacts (162), substrate contacts (164), and first and second through-vias (165, 167) to be formed in different process steps.

[0108] Next, referring again to FIG. 1a, a second cell region insulating layer (194), an upper protective layer (195), and an upper wiring structure (UI) can be formed.

[0109] The upper contact plugs (170) of the upper wiring structure (UI) can be formed by forming a portion of the cell region insulating layer (290), then etching and removing a portion of it, and burying a conductive material. The upper wiring lines (180) can be formed, for example, by depositing a conductive material and then patterning it.

[0110] By doing so, the semiconductor device (100) of FIGS. 1a to 3 can finally be manufactured.

[0112] FIG. 7 is a schematic diagram showing an electronic system including a semiconductor device according to one embodiment of the present invention.

[0113] Referring to FIG. 7, the electronic system (1000) may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more semiconductor devices (1100). According to an embodiment, the electronic system (1000) may be an electronic system that stores data.

[0114] The semiconductor device (1100) may be a non-volatile memory device, for example, a NAND flash memory device described above with reference to FIGS. 1a through 9. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). According to an embodiment, the first structure (1100F) may be placed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure comprising bit lines (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit lines (BL) and the common source line (CSL).

[0116] In the second structure (1100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to bit lines (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0117] According to an embodiment, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The gate lower lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2).

[0118] According to an embodiment, the lower transistors (LT1, LT2) may include a lower erase control transistor (LT1) and a ground select transistor (LT2) connected in series. The upper transistors (UT1, UT2) may include a string select transistor (UT1) and an upper erase control transistor (UT2) connected in series. At least one of the lower erase control transistor (LT1) and the upper erase control transistor (UT2) may be used for an erase operation to delete data stored in memory cell transistors (MCTs) using the GIDL phenomenon.

[0119] The common source line (CSL), the first and second gate lower lines (LL1, LL2), the word lines (WL), and the first and second gate upper lines (UL1, UL2) can be electrically connected to the decoder circuit (1110) through first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). The bit lines (BL) can be electrically connected to the page buffer (1120) through second connecting wires (1125) extending from the first structure (110F) to the second structure (1100S).

[0120] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit (1110) and the page buffer (1120) can be controlled by the logic circuit (1130). The semiconductor device (1100) may further include an input / output pad (1101). The semiconductor device (1100) can communicate with the controller (1200) through the input / output pad (1101) which is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0122] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the electronic system (1000) may include a plurality of semiconductor devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor devices (1100).

[0123] The processor (1210) can control the operation of the entire electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a controller interface (1221) that handles communication with the semiconductor device (1100). Through the controller interface (1221), control commands for controlling the semiconductor device (1100), data to be written to the memory cell transistors (MCT) of the semiconductor device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor device (1100), etc., may be transmitted. The host interface (1230) may provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

[0125] FIG. 8 is a schematic perspective view of an electronic system including a semiconductor device according to one embodiment of the present invention.

[0126] Referring to FIG. 8, an electronic system (2000) according to one embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by wiring patterns (2005) formed on the main board (2001).

[0127] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. According to an embodiment, the electronic system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). According to an embodiment, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0128] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0129] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the electronic system (2000) includes the DRAM (2004), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0131] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), semiconductor chips (2200) on the package substrate (2100), adhesive layers (2300) disposed on the lower surface of each of the semiconductor chips (2200), a connecting structure (2400) electrically connecting the semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0132] The package substrate (2100) may be a printed circuit board including package upper pads (2130). Each semiconductor chip (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 7. Each of the semiconductor chips (2200) may include a gate stacking structure (3210) and a memory channel structure (3220). Each of the semiconductor chips (2200) may include the semiconductor device described above with reference to FIGS. 1a through 9.

[0133] According to an embodiment, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pads (2130). Accordingly, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (2130) of the package substrate (2100). According to an embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0134] According to an embodiment, the controller (2002) and the semiconductor chips (2200) may be included in a single package. According to an embodiment, the controller (2002) and the semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0136] FIG. 9 is a schematic cross-sectional view of a semiconductor package according to one embodiment of the present invention. FIG. 9 describes the semiconductor package (2003) of FIG. 8 and conceptually shows the region of the semiconductor package (2003) of FIG. 8 cut along the cutting line III-III'.

[0137] Referring to FIG. 9, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120) (see FIG. 8), package lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and internal wiring (2135) electrically connecting the package upper pads (2130) and the package lower pads (2125) inside the package substrate body portion (2120). The package upper pads (2130) may be electrically connected to connection structures (2400). The lower pads (2125) can be connected to the wiring patterns (2005) of the main board (2001) of the electronic system (2000) through conductive connections (2800) as shown in FIG. 8.

[0139] Each of the semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including peripheral wiring (3110). The second structure (3200) may include a common source line (3205), a gate stacking structure (3210) on the common source line (3205), memory channel structures (3220) penetrating the gate stacking structure (3210) and separation regions, bit lines (3240) electrically connected to the memory channel structures (3220), and gate contact plugs (3235) electrically connected to the word lines (WL, see FIG. 7) of the gate stacking structure (3210).

[0140] Each of the semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to the peripheral wiring (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may be positioned outside the gate stack structure (3210) and may be further positioned to penetrate the gate stack structure (3210). Each of the semiconductor chips (2200) may further include an input / output pad (2210) (see FIG. 8) that is electrically connected to the peripheral wiring (3110) of the first structure (3100).

[0142] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, changes, and combinations of embodiments may be made by those skilled in the art without departing from the technical spirit of the invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0144] CH: Channel structure GV: Upper via LI: 1st wiring structure MS1, MS2: Separation area TR: Through-wiring area UI: Second wiring structure 101: Substrate 102: First horizontal conductive layer 103: Barrier layer 104: Second horizontal conductive layer 108: Separating insulation layer 118: Sacrificial insulation layer 120: Interlayer insulation layer 130: Gate electrode 140: Channel layer 145: Gate dielectric layer 150: Channel insulation layer 155: Channel pad 162: Gate contact 164: Substrate contact 165: 1st penetrating via 167: 2nd penetrating via 170: Upper contact plug 180: Upper wiring line 190: Cell region insulating layer 290: Peripheral region insulating layer

Claims

Claim 1 A peripheral circuit region comprising a first substrate, circuit elements disposed on the first substrate, and a first wiring structure electrically connected to the circuit elements; and a memory cell region comprising a second substrate disposed on the peripheral circuit region and having a first region and a second region, gate electrodes stacked spaced apart from each other along a first direction perpendicular to the upper surface of the second substrate on the first region, interlayer insulating layers stacked alternately with the gate electrodes, and a channel structure extending perpendicularly on the second substrate and including a channel layer penetrating the gate electrodes, wherein the gate electrodes include a ground selection gate electrode forming a ground selection transistor, memory cell gate electrodes forming memory cells, and a string selection gate electrode forming a string selection transistor sequentially from the second substrate, wherein the memory cell gate electrodes include first gate electrodes, second gate electrodes on the first gate electrodes, third gate electrodes on the second gate electrodes, fourth gate electrodes on the third gate electrodes, and fifth gate electrodes on the fourth gate electrodes, and the interlayer insulating layers include first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, and the second interlayer insulating layers A semiconductor device comprising third interlayer insulating layers, fourth interlayer insulating layers on the third interlayer insulating layers, and fifth interlayer insulating layers on the fourth interlayer insulating layers, wherein each of the fourth gate electrodes has a greater thickness than each of the third gate electrodes and each of the fifth gate electrodes, and each of the second interlayer insulating layers has a greater thickness than each of the third interlayer insulating layers. Claim 2 A semiconductor device according to claim 1, wherein each of the fourth gate electrodes has a thickness 1.005 to 1.1 times greater than each of the third gate electrodes, and each of the second interlayer insulating layers has a thickness 1.005 to 1.1 times greater than each of the third interlayer insulating layers. Claim 3 A semiconductor device according to claim 1, wherein the channel structure further comprises memory cells facing each of the gate electrodes, wherein the first memory cells facing each of the second to fourth gate electrodes store n bit data, the second memory cells facing each of the first and fifth gate electrodes store m bit data, and n and m are different natural numbers. Claim 4 A semiconductor device according to claim 3, wherein the first memory cells are triple-level cells and the second memory cells are multi-level cells. Claim 5 A semiconductor device according to claim 1, wherein the memory cell region further comprises first to fifth gate contacts connected to each of the first to fifth gate electrodes in the second region. Claim 6 A semiconductor device according to claim 5, wherein the height difference between adjacent fourth gate contacts among the fourth gate contacts is greater than the height difference between adjacent third gate contacts among the third gate contacts. Claim 7 A semiconductor device comprising: a stacked structure including gate electrodes and interlayer insulating layers alternately and repeatedly stacked in a vertical direction; and a channel structure penetrating the stacked structure, wherein the gate electrodes sequentially include a ground select gate electrode forming a ground select transistor, memory cell gate electrodes forming memory cells, and a string select gate electrode forming a string select transistor, wherein the memory cell gate electrodes include first gate electrodes, second gate electrodes on the first gate electrodes, third gate electrodes on the second gate electrodes, fourth gate electrodes on the third gate electrodes, and fifth gate electrodes on the fourth gate electrodes, wherein each of the third gate electrodes has a first thickness, each of the fourth gate electrodes has a second thickness greater than the first thickness, and each of the fifth gate electrodes has a third thickness smaller than the second thickness. Claim 8 A semiconductor device according to claim 7, wherein the interlayer insulating layers comprise first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, and third interlayer insulating layers on the second interlayer insulating layers, each of the third interlayer insulating layers having a fourth thickness, each of the second interlayer insulating layers having a fifth thickness greater than the fourth thickness, and each of the first interlayer insulating layers having a sixth thickness greater than the fourth thickness. Claim 9 A semiconductor device according to claim 7, wherein the length of overlap between each of the fourth gate electrodes and the channel structure along the vertical direction is greater than the length of overlap between each of the third gate electrodes and the channel structure along the vertical direction, and the length of overlap between each of the fifth gate electrodes and the channel structure along the vertical direction is smaller than the length of overlap between each of the fourth gate electrodes and the channel structure along the vertical direction. Claim 10 A peripheral circuit region comprising a first substrate, circuit elements disposed on the first substrate, and a first wiring structure electrically connected to the circuit elements; a memory cell region comprising a second substrate disposed on the first substrate and having a first region and a second region, gate electrodes stacked spaced apart from each other along a first direction perpendicular to the upper surface of the second substrate in the first region and extending in a stepped shape along a second direction perpendicular to the first direction in the second region, interlayer insulating layers stacked alternately with the gate electrodes, channel structures extending perpendicularly on the second substrate penetrating the gate electrodes and including a channel layer, and a second wiring structure electrically connected to the gate electrodes and the channel structures; A semiconductor device comprising an input / output pad electrically connected to the circuit elements, wherein the gate electrodes sequentially form a ground selection gate electrode forming a ground selection transistor, memory cell gate electrodes forming memory cells, and string selection gate electrodes forming a string selection transistor on the second substrate, wherein the memory cell gate electrodes sequentially form first to fifth gate electrodes from the bottom, and the interlayer insulating layers sequentially form first to fifth interlayer insulating layers from the bottom, wherein each of the fourth gate electrodes has a thickness greater than each of the third gate electrodes and the fifth gate electrodes, and each of the second interlayer insulating layers has a thickness greater than each of the third interlayer insulating layers; and an electronic system comprising a controller electrically connected to the semiconductor device through the input / output pad and controlling the semiconductor device.

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