Integration of semiconductor devices and additional gate devices

Abstract

The semiconductor structure includes a first rear-side source / drain region and a second rear-side source / drain region within a substrate, which are associated with an additional gate device and disposed within a rear-side region of the semiconductor structure.

Description

Technology Field

[0001] The present invention relates to the integration of a semiconductor device and an additional gate device. Background Technology

[0002] With the continuing trend toward the miniaturization of integrated circuits (ICs), transistors need to have higher driving currents in increasingly smaller dimensions. For example, the use of non-planar semiconductor devices, such as nanowire and nanosheet transistors, could be the next stage in the evolution of complementary metal oxide semiconductor (CMOS) devices. Prior art literature

[65535] U.S. Patent Application Publication US2007 / 0296002 (December 27, 2007)

[0003] Exemplary embodiments of the present application include techniques for use in semiconductor manufacturing. In an exemplary embodiment, the semiconductor structure comprises a first rear-side source / drain region and a second rear-side source / drain region within a substrate, associated with an extra gate device disposed within a rear-side region of the semiconductor structure.

[0004] A semiconductor structure of an exemplary embodiment advantageously has an additional gate device in a rear-side region of the semiconductor structure and a logic device region having nanosheet channel layers on the front-side of the semiconductor structure. Additionally, since the additional gate device occupies a large amount of space on the semiconductor structure, forming the additional gate device on the rear-side of the semiconductor structure provides an area reduction.

[0005] In one or more additional exemplary embodiments, as may be combined with the preceding paragraphs, the semiconductor structure further comprises a first rear-side source / drain contact connecting a first rear-side source / drain region to a rear-side power delivery network, and a second rear-side source / drain contact connecting a second rear-side source / drain region to a rear-side power delivery network.

[0006] In one or more additional exemplary embodiments, as may be combined with the preceding paragraphs, the first rear-side source / drain region and the second rear-side source / drain region comprise the ion-implanted first rear-side source / drain region and the ion-implanted second rear-side source / drain region.

[0007] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, the first rear-side source / drain region and the second rear-side source / drain region in the substrate are planar devices.

[0008] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, additional gate devices are co-integrated with logic devices.

[0009] In one or more additional exemplary embodiments, as may be combined with the preceding paragraphs, an additional gate device is integrated with a logic device, and the logic device includes a front-side source / drain region connected to a rear-side power delivery network by a third rear-side source / drain contact.

[0010] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, the logic device further comprises a plurality of nanosheet channel layers disposed on opposite sidewalls of the front side source / drain region.

[0011] According to another exemplary embodiment, the semiconductor structure includes a gate extension extending from a gate region associated with an additional gate device within the front side of the semiconductor structure. The gate extension is disposed between the two sidewalls of a second shallow trench region and a first shallow trench region disposed on a substrate. A gate dielectric layer is disposed between the gate extension and the upper surface of the substrate.

[0012] A semiconductor structure of an exemplary embodiment advantageously has an additional gate device in a rear-side region of the semiconductor structure and a logic device region having nanosheet channel layers on the front-side of the semiconductor structure. Additionally, the additional gate device further comprises a metal gate having a gate extension on the front-side having a gate dielectric layer disposed between a channel and a gate extension on the rear-side of the semiconductor structure. Additionally, since the additional gate device occupies a large amount of space on the semiconductor structure, forming the additional gate device on the rear-side of the semiconductor structure provides an area reduction.

[0013] In one or more additional exemplary embodiments, as may be combined with the preceding paragraphs, the semiconductor structure further comprises a middle-of-the-line contact connecting a gate region to a back-end-of-the-line interconnect.

[0014] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, the gate region and the gate extension share the same conductive material.

[0015] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, the gate dielectric layer is additionally disposed between the gate extension and the first shallow trench region and the second shallow trench region, and on a portion of the upper surfaces of the first shallow trench region and the second shallow trench region below the gate region.

[0016] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, the semiconductor structure further comprises a first rear-side source / drain region and a second rear-side source / drain region in a substrate associated with an additional gate device disposed within a rear-side region of the semiconductor structure.

[0017] In one or more additional exemplary embodiments, as may be combined with the preceding paragraph, the semiconductor structure further comprises a first rear-side source / drain contact connecting a first rear-side source / drain region to a rear-side power delivery network, and a second rear-side source / drain contact connecting a second rear-side source / drain region to a rear-side power delivery network.

[0018] In one or more additional exemplary embodiments, as may be combined with the preceding paragraphs, the first rear-side source / drain region and the second rear-side source / drain region comprise the ion-implanted first rear-side source / drain region and the ion-implanted second rear-side source / drain region.

[0019] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, an additional gate device is integrated with a logic device, and the logic device is located in a front-side region of a semiconductor structure and includes a front-side source / drain region connected to a rear-side power delivery network by a rear-side source / drain contact.

[0020] In a further exemplary embodiment, the semiconductor structure comprises: an additional gate device disposed within a rear side region of the semiconductor structure and comprising a first ion-implanted rear side source / drain region and a second ion-implanted rear side source / drain region within a substrate; a logic device disposed within a front side of the semiconductor structure and comprising a stack of first nanosheet channel layers and a stack of second nanosheet channel layers adjacent to the stack of first nanosheet channel layers; and an epitaxial growth source / drain region between the stack of first nanosheet channel layers and the stack of second nanosheet channel layers. The additional gate device is integrated with the logic device.

[0021] A semiconductor structure of an exemplary embodiment advantageously has an additional gate device in a rear-side region of the semiconductor structure and a logic device region having nanosheet channel layers on the front-side of the semiconductor structure. Additionally, the additional gate device further comprises a metal gate having a gate extension on the front-side having a gate dielectric layer disposed between a channel and a gate extension on the rear-side of the semiconductor structure. Additionally, since the additional gate device occupies a large amount of space on the semiconductor structure, forming the additional gate device on the rear-side of the semiconductor structure provides an area reduction.

[0022] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, the upper surface of each of the first ion-implanted rearward source / drain region and the second ion-implanted rearward source / drain region is coplanar with the upper surface of the substrate, and the upper surface of the epitaxial growth source / drain region is on the upper surface of each of the stack of the first nanosheet channel layers and the stack of the second nanosheet channel layers.

[0023] In one or more additional exemplary embodiments, as may be combined with the preceding paragraphs, the semiconductor structure further comprises: a first rear-side source / drain contact connecting a first ion-implanted rear-side source / drain region to a rear-side power transfer network; and a second rear-side source / drain contact connecting a second ion-implanted rear-side source / drain region to a rear-side power transfer network.

[0024] In one or more additional exemplary embodiments, as can be combined with the preceding paragraphs, the epitaxial growth source / drain region is connected to a rear side power transfer network by a third rear side source / drain contact.

[0025] Another exemplary embodiment includes an integrated circuit comprising one or more semiconductor structures. At least one of the one or more semiconductor structures is a semiconductor structure according to one or more of the exemplary embodiments described above.

[0026] An integrated circuit of an exemplary embodiment advantageously enables a semiconductor structure having an additional gate device in a rear-side region of the semiconductor structure and a logic device region having nanosheet channel layers in a front-side region of the semiconductor structure. Additionally, the additional gate device further comprises a metal gate having a gate extension in the front-side region having a gate dielectric layer disposed between a channel and a gate extension on the rear-side of the semiconductor structure. Additionally, since the additional gate device occupies a large amount of space on the semiconductor structure, forming the additional gate device on the rear-side of the semiconductor structure provides an area reduction.

[0027] In an additional exemplary embodiment, the method comprises the step of implanting ions into a first rear-side source / drain region and a second rear-side source / drain region within a substrate, associated with an additional gate device disposed within a rear-side region of a semiconductor structure.

[0028] The method of an exemplary embodiment advantageously enables the formation of a semiconductor structure having an additional gate device in a rear-side region of the semiconductor structure and a logic device region having nanosheet channel layers in a front-side region of the semiconductor structure. Additionally, the additional gate device further comprises a metal gate having a gate extension in the front-side region, having a gate dielectric layer disposed between a channel and a gate extension on the rear-side of the semiconductor structure. Furthermore, since the additional gate device occupies a large amount of space on the semiconductor structure, forming the additional gate device on the rear-side of the semiconductor structure provides an area reduction.

[0029] These embodiments and other exemplary embodiments will be described or made clear from the following detailed exemplary embodiments, which should be read together with the accompanying drawings. Brief explanation of the drawing

[0030] The embodiments will be described in more detail below with reference to the attached drawings. FIG. 1a is a top view of the logic device region and high voltage device region of a semiconductor structure at an intermediate step of a method for manufacturing a nanosheet transistor structure according to an embodiment of the present invention. FIG. 1b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a according to an exemplary embodiment. FIG. 1c is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a according to an exemplary embodiment. FIG. 1d is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a according to an exemplary embodiment. FIG. 2a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after patterning of a sacrificial layer, sacrificial layers and nanosheet channel layers according to an exemplary embodiment. FIG. 2b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after patterning of a sacrificial layer, sacrificial layers and nanosheet channel layers according to an exemplary embodiment. FIG. 2c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after patterning of a sacrificial layer, sacrificial layers and nanosheet channel layers according to an exemplary embodiment. FIG. 3a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the formation of a mask layer according to an exemplary embodiment. FIG. 3b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the deposition of a mask layer according to an exemplary embodiment. FIG. 3c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the deposition of a mask layer according to an exemplary embodiment. FIG. 4a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the removal of the mask layer and the formation of the gate dielectric layer and the dummy gate layer, according to an exemplary embodiment. FIG. 4b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the removal of the mask layer and the formation of the gate dielectric layer and the dummy gate layer, according to an exemplary embodiment. FIG. 4c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the removal of the mask layer and the formation of the gate dielectric layer and the dummy gate layer, according to an exemplary embodiment. FIG. 5a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the formation of a dummy gate stack according to an exemplary embodiment. FIG. 5b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the formation of a dummy gate stack according to an exemplary embodiment. FIG. 5c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the formation of a dummy gate stack according to an exemplary embodiment. FIG. 6a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the removal of a sacrificial layer according to an exemplary embodiment. FIG. 6b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the removal of a sacrificial layer according to an exemplary embodiment. FIG. 6c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the removal of a sacrificial layer, according to an exemplary embodiment. FIG. 7a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the formation of an internal spacer, a sacrificial placeholder, a buffer semiconductor layer, and a source / drain region according to an exemplary embodiment. FIG. 7b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the formation of an internal spacer, a sacrificial placeholder, a buffer semiconductor layer, and a source / drain region according to an exemplary embodiment. FIG. 7c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the formation of an internal spacer, a sacrificial placeholder, a buffer semiconductor layer, and a source / drain region according to an exemplary embodiment. FIG. 8a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after removing a gate hardmask layer and a gate sidewall spacer in contact with the sidewall of the gate hardmask layer, according to an exemplary embodiment. FIG. 8b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after removing a gate hardmask layer and a gate sidewall spacer in contact with the sidewall of the gate hardmask layer, according to an exemplary embodiment. FIG. 8c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the removal of a gate hardmask layer and a gate sidewall spacer adjacent to the sidewall of the gate hardmask layer, according to an exemplary embodiment. FIG. 9a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the removal of a dummy gate layer and the deposition of a mask layer, according to an exemplary embodiment. FIG. 9b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the removal of a dummy gate layer and the deposition of a mask layer, according to an exemplary embodiment. FIG. 9c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the removal of a dummy gate layer and the deposition of a mask layer, according to an exemplary embodiment. FIG. 10a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the removal of the mask layer and the sacrificial layer and the deposition of the replacement gate structure according to an exemplary embodiment. FIG. 10b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the removal of the mask layer and the sacrificial layer and the deposition of the replacement gate structure according to an exemplary embodiment. FIG. 10c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the removal of the mask layer and the sacrificial layer and the deposition of the replacement gate structure according to an exemplary embodiment. FIG. 11a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the formation of a middle-of-the-line contact, a front-side BEOL (back-end-of-line) interconnect, and a carrier wafer according to an exemplary embodiment. FIG. 11b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the formation of a middle-of-the-line contact, a front-side BEOL (back-end-of-line) interconnect, and a carrier wafer according to an exemplary embodiment. FIG. 11c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the formation of a middle-of-the-line contact, a front-side BEOL (back-end-of-line) interconnect, and a carrier wafer according to an exemplary embodiment. FIG. 12a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after rearward processing of the substrate to remove portions of the substrate according to an exemplary embodiment. FIG. 12b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after rearward side processing of the substrate to remove portions of the substrate according to an exemplary embodiment. FIG. 12c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after rearward processing of the substrate to remove portions of the substrate according to an exemplary embodiment. FIG. 13a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after removal of an etching stop layer according to an exemplary embodiment. FIG. 13b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after removal of an etching stop layer according to an exemplary embodiment. FIG. 13c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after removal of an etching stop layer according to an exemplary embodiment. FIG. 14a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the deposition of a mask layer according to an exemplary embodiment. FIG. 14b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the deposition of a mask layer according to an exemplary embodiment. FIG. 14c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the deposition of a mask layer according to an exemplary embodiment. FIG. 15a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a, in which, according to an exemplary embodiment, after the deposition of an additional mask layer, the removal of the remaining portion of the substrate within the logic device regions follows. FIG. 15b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a, in which, according to an exemplary embodiment, after the deposition of an additional mask layer, the removal of the remaining portion of the substrate within the logic device regions follows. FIG. 15c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a, in which, according to an exemplary embodiment, after the deposition of an additional mask layer, the removal of the remaining portions of the substrate within the logic device regions follows. FIG. 16a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the removal of the mask layer and the deposition of the rear side ILD layer, according to an exemplary embodiment. FIG. 16b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the removal of the mask layer and the deposition of the rear side ILD layer, according to an exemplary embodiment. FIG. 16c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the removal of the mask layer and the deposition of the rear side ILD layer, according to an exemplary embodiment. FIG. 17a is a cross-sectional view of a semiconductor structure showing a logic device area taken along the X1-X1 axis of FIG. 1a after the formation of a rear side middle of the line contact opening according to an exemplary embodiment. FIG. 17b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the formation of a rear side middle of the line contact opening according to an exemplary embodiment. FIG. 17c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the formation of a rear-side middle-of-the-line contact opening according to an exemplary embodiment. FIG. 18a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the formation of a mask layer and an ion-implanted rearward source / drain region according to an exemplary embodiment. FIG. 18b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the formation of a mask layer and an ion-implanted rear-side source / drain region according to an exemplary embodiment. FIG. 18c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the formation of a mask layer and an ion-implanted rear-side source / drain region according to an exemplary embodiment. FIG. 19a is a cross-sectional view of a semiconductor structure showing a logic device region taken along the X1-X1 axis of FIG. 1a after the removal of a mask layer and the formation of a rear middle of the line contact, according to an exemplary embodiment. FIG. 19b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the removal of the mask layer and the formation of a rear middle of the line contact according to an exemplary embodiment. FIG. 19c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the removal of the mask layer and the formation of a rear middle of the line contact according to an exemplary embodiment. FIG. 20a is a cross-sectional view of a semiconductor structure showing a logic device area taken along the X1-X1 axis of FIG. 1a after the formation of a rear-side power transfer network according to an exemplary embodiment. FIG. 20b is a cross-sectional view of a semiconductor structure showing a logic device region taken along the Y1-Y1 axis of FIG. 1a after the formation of a rear-side power transfer network according to an exemplary embodiment. FIG. 20c is a cross-sectional view of a semiconductor structure showing a high-voltage device region taken along the X2-X2 axis of FIG. 1a after the formation of a rear-side power transfer network according to an exemplary embodiment. Specific details for implementing the invention

[0031] The present disclosure generally relates to semiconductor devices, and more specifically to a semiconductor structure having a logic device region and a high-voltage device region integrated with a rearward power transfer network, and a method for manufacturing the same. However, it should be understood that the embodiments of the present disclosure are not limited to exemplary methods, apparatuses, systems, and devices, but are instead more broadly applicable to other suitable methods, apparatuses, systems, and devices.

[0032] High-voltage devices for input / output (I / O) circuits (referred to as "additional gate devices" or "EG devices") require a supernormal gate dielectric compared to single gate (SG) devices used in logic devices used for logic circuits. For example, additional gate devices and single gate devices are integrated together in a complementary metal oxide semiconductor (CMOS) device.

[0033] The integration of additional gate devices presents a challenge for nanosheet technology. For example, forming additional gate devices on nanosheets requires large sheet-to-sheet spacing (i.e., Tsus) to accommodate thick gate dielectrics. Higher voltage devices for input / output circuits require thicker gate dielectrics compared to standard gate devices, such as those used in logic devices, which operate at lower voltages. However, the spacing between sheets must be small to realize capacitance advantages. Furthermore, forming both single gate devices (logic devices) and additional gate devices (high-voltage devices) on the front side of a semiconductor structure is undesirable because it requires more masking steps. Therefore, new device structures and methods are needed to construct structures that enable the integration of standard nanosheet devices with high-voltage or additional gate devices.

[0034] Accordingly, exemplary embodiments of the present disclosure overcome the aforementioned disadvantages by forming a logic device region having nanosheet channel layers on the front side of the substrate and a high-voltage device region on the rear side of the substrate, thereby saving the number of required masking steps. Furthermore, since high-voltage devices also occupy a large amount of space on the semiconductor structure, forming the high-voltage devices on the rear side can provide some area reduction. The increased gate dielectric thickness required for the high-voltage devices is thicker than the optimal space between the sheets.

[0035] Detailed embodiments of semiconductor structures and methods are disclosed herein. The method steps described below do not constitute a complete process flow for manufacturing integrated circuits, such as semiconductor devices. These embodiments may be practiced with integrated circuit manufacturing techniques currently used in the art and include only as many general process steps as are necessary to understand the described embodiments. These drawings represent cross-sections of semiconductor structures after manufacturing and are not drawn to actual size but are drawn to illustrate the features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting but should be construed as representative grounds for instructing those skilled in the art to adopt various methods and structures of the present disclosure. In the description, details of well-known features and technologies may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0036] As used herein, "height" refers to the vertical size of an element (e.g., floor, trench, hole, opening, etc.) and, in the cross-sectional views, is measured from the lower surface of the element to the upper surface and / or with respect to the surface on which the element is located. Conversely, "depth" refers to the vertical size of an element (e.g., floor, trench, hole, opening, etc.) and, in the cross-sectional views, is measured from the upper surface of the element to the lower surface.

[0037] As used herein, "transverse," "transverse side," and "transverse surface" refer to the side of an element (e.g., floor, opening, etc.), such as the left or right surface in the drawings.

[0038] As used herein, "width" or "length" refers to the size of an element (e.g., floor, trench, hole, opening, etc.) and is measured from the side of the element to the opposite surface in the drawings.

[0039] As used herein, "top," "bottom," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof should be broadly interpreted as relating to the disclosed structures and methods as oriented in the drawings, wherein these structures may be understood to have the same configuration (e.g., layers stacked in the same order) even if the structures are rotated at an angle different from that shown in the drawings.

[0040] Unless otherwise specified, terms such as “on top,” “placed on top,” “on top,” “placed on top,” and “located on top” as used herein mean that the first element exists on the second element, and an intermediate element may exist between the first element and the second element. As used herein, unless otherwise specified, the term “direct” used in relation to terms such as “on top,” “on top,” “on the upper part,” “on top,” “on top,” or “on top,” or “on top,” or “direct contact,” means that the first element and the second element are connected without any intervening elements, such as an intermediate conductive layer, insulating layer, or semiconductor layer existing between the first element and the second element.

[0041] It should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps illustrated and described herein. In particular, regarding semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to cover all processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, specific processing steps commonly used to form semiconductor devices, such as wet cleaning and annealing steps, are intentionally not described herein for the sake of economy of description. The terms “approximately” or “substantially” used herein in relation to thickness, width, percentage, range, etc., should be understood as indicating a close or approximate value, even if not precise. For example, the terms “approximately” or “substantially” as used herein imply that a small margin of error, such as 1% or less of the specified amount, may exist.

[0042] In this specification, references to “one embodiment” or “an embodiment of the present principle” and variations thereof mean that specific features, structures, characteristics, etc. described in relation to such embodiment are included in at least one embodiment of the present principle. Accordingly, the appearance of other variations of “one embodiment” or “one embodiment” together with them in various places throughout this specification does not necessarily refer to the same embodiment. The term “positioned on” means that a first element, such as a first structure, exists on a second element, such as a second structure, and an interposed element, such as an interface layer or an interface structure, may exist between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of these two elements without any intermediate conductive, insulating, or semiconductor layer.

[0043] It will be understood that while terms such as first, second, etc. may be used in this specification to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Accordingly, the first element discussed below may be referred to as the second element without departing from the scope of the concept.

[0044] As used herein, "height" refers to the vertical size of an element (e.g., floor, trench, hole, opening, etc.) and, in the cross-sectional views, is measured from the lower surface of the element to the upper surface and / or with respect to the surface on which the element is located. Conversely, "depth" refers to the vertical size of an element (e.g., floor, trench, hole, opening, etc.) and, in the cross-sectional views, is measured from the upper surface of the element to the lower surface. Terms such as "thick," "thickness," "thin," or derivatives thereof may be used instead of the indicated "height."

[0045] As used herein, “width” or “length” refers to the size of an element (e.g., floor, trench, hole, opening, etc.) and is measured from the side of the element to the opposite surface in the drawings. Terms such as “thick,” “thickness,” “thin,” or derivatives thereof may be used instead of “width” or “length” where indicated.

[0046] To avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some of the processing steps, materials, or operations known in the art may be combined for the purposes of presentation and illustration, and in some cases may not be described in detail. Additionally, to focus on the unique features of the elements of the present disclosure, the descriptions of the aforementioned materials, processes, and structures may not be repeated in the following drawings. In other cases, some known processing steps or operations may not be described. It should be understood that the following description focuses rather on the unique features or elements of the various embodiments of the present invention.

[0047] It should be understood that the various layers, structures, and / or regions shown in the attached drawings are schematic drawings and not drawn to actual size. Additionally, for ease of description, one or more layers, structures, and regions of types commonly used to form semiconductor devices or structures may not be explicitly depicted in the given drawings. This does not imply that any layers, structures, and regions not explicitly depicted are omitted from actual semiconductor structures.

[0048] Generally, the various processes used to form semiconductor chips can include four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Film deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available technologies include, among others, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), molecular beam epitaxy ("MBE"), and, more recently, atomic layer deposition ("ALD"). Another film deposition technology is plasma-enhanced chemical vapor deposition ("PECVD"), which is a process that uses energy within a plasma to induce reactions on the wafer surface that require high temperatures in conventional CVD. The electrical and mechanical properties of the film are also enhanced by the powerful ion bombardment during PECVD deposition.

[0049] Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate and then transferring that pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist. Patterns generated by lithography or photolithography are typically used to define or protect selected surfaces and parts of a semiconductor structure during a subsequent etching process.

[0050] Removal is any process, such as etching or chemical mechanical planarization ("CMP"), that removes material from a wafer. Examples of etching processes include wet (e.g., chemical) or dry etching processes. An example of a removal process or dry etching process is ion beam etching ("IBE"). Generally, IBE (or milling) refers to a dry plasma etching method that removes substrate material through physically inert gas and / or chemically reactive gas means using a remote wide-beam ion / plasma source. Like other dry plasma etching techniques, IBE can offer advantages such as etching speed, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry etching process is reactive ion etching ("RIE"). Generally, RIE uses a chemically reactive plasma to remove material deposited on a wafer. High-energy ions from the RIE plasma strike the wafer surface and react with the surface material to remove it.

[0051] Now, referring to drawings in which similar reference numerals denote identical elements, FIGS. 1a through 20c illustrate various processes for manufacturing semiconductor structures having logic device regions and high-voltage device region structures. It should be noted that the same reference numeral (100) is used to denote semiconductor structures through the various intermediate manufacturing stages illustrated in FIGS. 1a through 20c. Also, it should be noted that the semiconductor structures described herein may also be considered as semiconductor devices and / or integrated circuits, or parts thereof. For clarity, some manufacturing steps leading to the production of semiconductor structures as illustrated in FIGS. 1a through 20c are omitted. In other words, one or more well-known processing steps that are not illustrated but are well known to those skilled in the art are not included in the drawings. This is not intended to be interpreted as any specific embodiment, example, or limitation of the scope of the claims.

[0052] Now, referring to FIGS. 1a through 1d, FIG. 1a illustrates a top view illustrating a cross-sectional view taken in a logic device region and a high-voltage device region of a semiconductor structure (100). FIG. 1a illustrates a pin active region (101) for a logic device region, together with a gate region (103) for a logic device region and a high-voltage device region. FIGS. 1b and FIG. 1c illustrate a cross-sectional view of a logic device region taken along lines in the X1-X1 axis and the Y1-Y1 axis in the top view of FIG. 1a. FIG. 1d illustrates a cross-sectional view of a high-voltage device region taken along lines in the X2-X2 axis in the top view of FIG. 1a.

[0053] Now, referring to FIGS. 1b through 1d, a semiconductor structure (100) during intermediate steps of a method for manufacturing a nanosheet transistor structure according to an embodiment of the present invention is illustrated. The semiconductor structure (100) comprises a substrate (102). The substrate (102) may be formed from any suitable semiconductor material comprising silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and a plurality of layers thereof, but not limited thereto. While silicon is the semiconductor material primarily used in wafer manufacturing, alternative semiconductor materials such as germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), and zinc selenide (ZnSe) may be adopted as additional layers as non-limiting examples. In one exemplary embodiment, the substrate (102) is silicon.

[0054] An etching stop layer (104) is formed within the substrate (102). The etching stop layer (104) may include other suitable materials such as a buried oxide (BOX) layer, silicon germanium (SiGe), or a III-V semiconductor epitaxial layer.

[0055] Nanosheets are initially formed on a substrate (102), wherein the nanosheets comprise a sacrificial layer (106), sacrificial layers (108-1, 108-2 and 108-3) (collectively, sacrificial layer (108)), and nanosheet channel layers (110-1, 110-2 and 110-3) (collectively, nanosheet channel layers (110)). The sacrificial layers (106 and 108) are formed from different sacrificial materials, so that the sacrificial layers can be selectively etched or removed relative to one another. In some embodiments, the sacrificial layers (106 and 108) are formed from SiGe, but have different percentages of Ge. For example, a specific sacrificial layer among the sacrificial layers (106 and 108) may have a relatively higher percentage of Ge (e.g., 55% Ge), and another sacrificial layer among the sacrificial layers (106 and 108) may have a relatively lower percentage of Ge (e.g., 33% Ge or 25% Ge). In some embodiments, the sacrificial layer (106) has a relatively high percentage of Ge (e.g., 55% Ge), and the other sacrificial layers (108) have a relatively low percentage of Ge (e.g., 33% Ge). In other embodiments, different combinations of different sacrificial materials may be used. The nanosheet channel layer (110) may be formed of Si or other suitable material (e.g., a material similar to that used in the substrate (102)).

[0056] Now, referring to FIGS. 2a through 2c, a semiconductor structure (100) after patterning of a sacrificial layer (106), sacrificial layers (108), and nanosheet channel layers (110) according to an embodiment of the present invention is shown. For example, the sacrificial layer (106), sacrificial layers (108), and nanosheet channel layers (110) are patterned using known lithography, patterning, and etching processes to form a field-effect transistor (FET) stack (112a and 112b) as shown in FIG. 2b, and a shallow trench isolation (STI) region (114) in FIG. 2b and FIG. 2c. The STI region (114) can be formed from a dielectric material such as silicon dioxide (SiO2), silicon oxycarbon (SiOC), silicon oxynitride (SiON), etc., and is formed by a method known in the art. For example, in one exemplary embodiment, the STI region (114) is a shallow trench isolation oxide layer. Each of the FET stacks (112a, 112b) includes a FET device. The FET devices may include an nFET device or a pFET device for one FET device, and the other FET device may include a pFET device or an nFET device.

[0057] Now, referring to FIGS. 3a through 3c, a semiconductor structure (100) after forming a mask layer (116) according to an embodiment of the present invention is shown. The mask layer (116) [e.g., a diode mask that may be composed of photoresist, or other suitable protective material such as an organic planarization layer (OPL) or spin-on-carbon (SOC)] is formed on the semiconductor structure (100) using any conventional film-forming process, such as spin-on coating or any other suitable film-forming process. Next, an opening is formed through the STI region (114) within the high-voltage device region (see FIG. 3c) of the semiconductor structure (100) and within the mask layer (116) so that the upper surface of the substrate (102) is exposed. The opening can be formed by using conventional lithography and selective etching processes, such as wet or dry etching processes, in the mask layer (116) and STI region (114).

[0058] Now, referring to FIGS. 4a through 4c, a semiconductor structure (100) is illustrated after the removal of the mask layer (116) and the formation of the gate dielectric layer (118) and the dummy gate layer (120) according to an embodiment of the present invention. The mask layer (116) may be removed, for example, by an ash etching process. Next, before the formation of the dummy gate layer (120), a gate dielectric layer (118) is deposited on the top nanosheet channel layer (110-3) and on the STI region (114) as shown in FIGS. 4a and 4b, and on the substrate (102) and on the STI region (114) as shown in FIG. 4c. Suitable materials for the gate dielectric layer (118) include, for example, SiO2 or SiON. In some embodiments, the gate dielectric layer (118) may be a layer having a thickness in the range of about 2 nm to about 30 nm. In some embodiments, the gate dielectric layer (118) may be a so-called "extended gate (EG)" oxide. The gate dielectric layer (118) disposed between the rear side of the substrate (102) having a rear side channel, i.e., a source / drain region (160), and the gate extension (141) described later enables the formation of a thicker gate dielectric layer.

[0059] Next, a dummy gate layer (120) is formed on the gate dielectric layer (118) by depositing and flattening a layer of dummy gate material. In some embodiments, the dummy gate material may be polycrystalline Si. In some embodiments, the dummy gate material may be amorphous silicon (a-Si) or amorphous silicon germanium (a-SiGe). After deposition, the dummy gate material is flattened to a desired level (e.g., by CMP).

[0060] Now, referring to FIGS. 5a through 5c, a semiconductor structure (100) after the formation of dummy gate stacks (124a, 124b, and 124c) according to an embodiment of the present invention is shown. The dummy gate stacks (124a, 124b, and 124c) are formed by depositing a gate hard mask (HM) layer (122) on a dummy gate layer (120) using a conventional deposition technique such as ALD. Suitable materials for the gate HM layer (122) include oxide and nitride materials, such as silicon nitride (SiN), a multilayer of SiN and SiO2, or other suitable materials. Subsequently, a gate HM layer (122) is patterned, and then lithography processing is performed to obtain a dummy gate stack (124a, 124b, and 124c) consisting of the patterned gate HM layer (122) and the underlying dummy gate layer (120), as shown in FIG. 5a. The dummy gate layer (120) is selectively etched so that the portion of the dummy gate layer (120) not located beneath the gate HM layer (122) is removed. Additionally, known manufacturing operations may be used to selectively remove the portion of the gate dielectric layer (118) not located beneath the dummy gate layer (120), and diluted hydrofluoric acid (DHF) cleaning is performed to ensure that the entire gate dielectric layer (118) not located beneath the dummy gate layer (120) is removed.

[0061] Now, referring to FIGS. 6a through 6c, a semiconductor structure (100) after the removal of a sacrificial layer (106) according to an embodiment of the present invention is illustrated. The sacrificial layer (106) can be removed using known manufacturing operations, and the operation of depositing a dielectric material used to form a bottom dielectric insulator (BDI) layer (126) in the space occupied by the removed sacrificial layer (106), and to form gate sidewall spacers (128) on the sidewalls of the gate HM layer (122) and the dummy gate layer (120) by conformal dielectric liner deposition follows. In some embodiments, the dielectric material for forming the BDI layer (126) and the gate sidewall spacers (128) may independently be a dielectric material comprising, for example, silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials. In some embodiments, the dielectric material may be a low k dielectric material.

[0062] Now, referring to FIGS. 7a through 7c, a semiconductor structure (100) is shown after the formation of an internal spacer (130), a sacrificial placeholder (132), a buffer semiconductor layer (133), and a source / drain region (134) according to an embodiment of the present invention. The internal spacer (130) is formed by removing a portion of the sacrificial layer (108) and the nanosheet channel layer (110) using a known semiconductor device manufacturing process, and then forming the internal spacer (130) in an end region cavity (not shown) formed in the end region of the sacrificial layer (108), by removing an indent space (e.g., resulting from indent etching before the removal of the sacrificial layer (108)) (see FIG. 7a). In some embodiments, a conformal deposition process is used to deposit a dielectric material over an end region cavity so that the dielectric material is pinched off from the end region cavity to form an internal spacer (130). A subsequent isotropic or anisotropic etching back is performed to remove excess dielectric material on the exposed vertical and horizontal surfaces of the semiconductor structure (100). Suitable materials for the internal spacer (130) include, for example, silicon nitride (SiN), SiBCN, silicon carbide oxide (SiCO), SiOCN, or any other type of dielectric material (for example, a dielectric material having a dielectric constant k of less than about 5).

[0063] For example, a sacrificial placeholder (132) is formed on the substrate (102) using an RIE process to remove a portion of the substrate (102), and then a sacrificial material is deposited using a conventional film deposition technique such as ALD. The sacrificial placeholder (132) is, for example, SiGe, titanium oxide (TiO₂). x ), aluminum oxide (AlO x It can be formed from sacrificial materials such as silicon carbide (SiC).

[0064] A buffer semiconductor layer (133) may be formed on a sacrificial placeholder (132) to prevent source / drain epitaxial erosion during the placeholder removal process from the rear side, as discussed below. The buffer semiconductor layer (133) may be formed using known growth / film deposition techniques, such as epitaxial growth, ALD, etc. The buffer semiconductor layer (133) may be any material discussed above for the nanosheet channel layer (110).

[0065] Source / drain regions (134) may be formed on a buffer semiconductor layer (133). Source / drain regions (134) may be formed using an epitaxial growth process. Source / drain regions (134) may be suitably doped, such as using ion implantation, vapor phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, etc. n-type dopants may be selected from the group of phosphorus (P), arsenic (As), and antimony (Sb), and p-type dopants may be selected from the group of boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (Tl). In some embodiments, the epitaxy process involves in-situ doping (dopants are incorporated into the epitaxy material during epitaxy).

[0066] Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), or other suitable processes. Depending on the type of transistor to be formed, epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and / or carbon-doped silicon (Si:C) can be doped during film deposition by adding dopants such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium) (phosphorus Si:C doped). The dopant concentration in the source / drain region is 1×10⁻⁶. 19 cm -3 Up to 3×10 21 cm -3 , or preferably 2×10 20 cm -3 Up to 3×10 21 cm -3 It can be within the range of.

[0067] Now, referring to FIGS. 8a through 8c, a semiconductor structure (100) is shown after the removal of a gate HM layer (122) and a gate sidewall spacer (128) in contact with the sidewall of the gate HM layer (122) according to an embodiment of the present invention. The gate HM layer (122) and the gate sidewall spacer (128) in contact with the sidewall of the gate HM layer (122) can be removed using a selective etching process such as RIE. Next, an interlevel dielectric (ILD) layer (136) is formed on the source / drain region (134) and on the STI region (114). The ILD layer (136) can be formed from any suitable isolation material such as SiO2, SiOC, SiON, etc. using conventional film deposition techniques such as ALD, CVD, etc., followed by a planarization process such as CMP.

[0068] Now, referring to FIGS. 9a through 9c, a semiconductor structure (100) after the removal of a dummy gate layer (120) and the deposition of a mask layer (138) according to an embodiment of the present invention is illustrated. The dummy gate layer (120) is first removed using an optional etching process, such as an RIE or wet removal process. Next, a mask layer (138) is formed within the opening created by the removal of the dummy gate layer (120) shown in FIG. 9c to protect the gate dielectric layer (118) in the high-voltage device region. Then, the exposed gate dielectric layer (118) in the logic device region in FIG. 9a is removed using an optional wet or dry etching process to expose the top nanosheet channel layer (110-3). The mask layer (138) may be formed by a process and material similar to that of the mask layer (116).

[0069] Now, referring to FIGS. 10a through 10c, a semiconductor structure (100) after the removal of the mask layer (138) and the sacrificial layer (108) and the deposition of the replacement gate structure (140) according to an embodiment of the present invention is illustrated. The mask layer (138) may be removed, for example, by an ash etching process. Next, a known semiconductor manufacturing operation is used to remove the sacrificial layer (108) selectively from the nanosheet channel layer (110). In some embodiments, since the sacrificial layers (108) are formed from SiGe, they may be selectively etched from the nanosheet channel layers (110) formed from Si, for example, using a vapor phase hydrogen chloride (HCl) gas isotropic etching process.

[0070] The removed sacrificial layer (108) and the removed dummy gate layer (120) are replaced with a replacement gate structure (140) (shown in FIG. 10a), and the removed mask layer (138) is replaced with a replacement gate structure (140) (shown in FIG. 10c) using a known replacement high-k metal gate (HKMG) processing operation. FIG. 10c further illustrates a replacement gate structure (140) having a gate extension (141) extending from the bottom of the replacement gate structure (140) to the gate dielectric layer (118) on the substrate (102) and between the two sidewalls of the STI region (114). In some embodiments, the gate extension (141) will be formed of the same material as the replacement gate structure (140) as described below. In some embodiments, the replacement gate structure (140) may include a gate dielectric layer and a gate conductor layer. The gate dielectric layer (150) may be formed from a high-k dielectric material. Examples of high-k dielectric materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg).

[0071] The gate conductor layer may include a metal gate or a work function metal (WFM). The WFM for the gate conductor layer may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), combinations of Ti and Al alloys, a barrier layer (e.g., TiN, TaN, etc.), followed by a stack comprising one or more of the aforementioned WFM materials. It should be understood that various other materials may be used for the gate conductor layer as desired.

[0072] Now, referring to FIGS. 11a through 11c, a semiconductor structure (100) after the formation of a middle-of-the-line contact (142 and 144), a front-side BEOL (back-end-of-line) interconnect (146), and a carrier wafer (148) according to an embodiment of the present invention is shown. The middle-of-the-line contact (142 and 144), which may also be referred to as a gate contact (142) in a high-voltage device region (see FIG. 10c) and a source / drain contact (144) in a logic device region (see FIG. 10a and FIG. 10b), may be formed by any prior art. In some embodiments, middle-of-the-line contacts (142 and 144) may be formed by depositing an additional amount of ILD layer (136) and forming openings by utilizing conventional lithography and selective etching processes, such as a wet or dry etching process within the ILD layer (136). For example, a dry etching process may be implemented using an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasma, and / or a combination thereof. For example, a wet etching process may be implemented using DHF (diluted hydrofluoric acid); a KOH (potassium hydroxide) solution; ammonia; The method may include a step of etching with a solution containing HF (hydrofluoric acid), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchant.

[0073] Next, a highly conductive metal is deposited in the opening to form middle-of-the-line contacts (142 and 144). Suitable highly conductive metals may include conductive materials such as, for example, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), or any other suitable conductive material. In various embodiments, the highly conductive metal may be deposited by ALD, CVD, PVD, and / or plating. The highly conductive metal may be planarized using a planarization process such as, for example, CMP. Other planarization processes may include grinding and polishing.

[0074] Subsequently, a front-side BEOL interconnect (146) is formed, and subsequently, bonding of a structure (e.g., front-side BEOL interconnect (146)) to a carrier wafer (148) follows. The front-side BEOL interconnect (146) includes various BEOL interconnect structures. For example, the front-side BEOL interconnect (146) is a metal wiring structure comprising one or more metal layers disposed on the side of the semiconductor structure (100) opposite to the side where the rear-side BEOL metallization structure is disposed. Each metal layer of the front-side BEOL interconnect (146) has a metal line for forming an interconnect for a semiconductor device.

[0075] The carrier wafer (148) can be formed of a material similar to the material of the substrate (102) and can be formed on the front side BEOL interconnect (146) using a wafer bonding process such as dielectric-to-dielectric bonding.

[0076] Now, referring to FIGS. 12a through 12c, a semiconductor structure (100) after rearward side processing of a substrate (102) according to an embodiment of the present invention is illustrated. Rearward side processing can be performed, for example, by flipping the semiconductor structure (100) so that the rearward side (i.e., the rear surface) of the substrate (102) faces upward. First, portions of the substrate (102) can be removed from the rearward side using, for example, a combination of wafer grinding, CMP, dry etching, and / or wet etching, in order to selectively remove the substrate (102) until an etching stop layer (104) is reached.

[0077] Now, referring to FIGS. 13a through 13c, a semiconductor structure (100) after the removal of an etching stop layer (104) according to an embodiment of the present invention is shown. The etching stop layer (104) is selectively removed using wet etching to selectively remove the etching stop layer (104) until, for example, it reaches a substrate (102).

[0078] Now, referring to FIGS. 14a through 14c, a semiconductor structure (100) after the deposition of a mask layer (150) according to an embodiment of the present invention is shown. The mask layer (150) is deposited on the remaining portion of the substrate (102). The mask layer (150) may be formed by a process and material similar to that of the mask layer (116). Next, the mask layer (150) within the high-voltage device region shown in FIG. 14c is patterned and then selectively removed to the remaining portion of the substrate (102) using a selective etching process, such as wet etching, to expose a portion of the STI region (114).

[0079] Now, referring to FIGS. 15a through 15c, according to an embodiment of the present invention, a semiconductor structure (100) is shown in which, after the deposition of an additional mask layer (150), the removal of the remaining portion of the substrate (102) in the logic device region follows. The additional mask layer (150) is deposited on the exposed STI regions (114) within the high-voltage device region shown in FIG. 15c. Subsequently, the remaining portion of the substrate (102) within the logic device region shown in FIGS. 15a and 15b is removed using an optional etching process, such as wet etching, to expose the sacrificial placeholder (132) and the BDI layer (126).

[0080] Now, referring to FIGS. 16a through 16c, a semiconductor structure (100) is shown after the removal of the mask layer (150) and the deposition of the rear-side ILD layer (152) according to an embodiment of the present invention. The mask layer (150) in the high-voltage device region shown in FIG. 16c is removed, for example, by an ash etching process. Next, the rear-side ILD layer (152) is deposited on the removed portion of the substrate (102) in the logic device region shown in FIGS. 16a and 16b and on the removed mask layer (150) in the high-voltage device region shown in FIG. 16c. The rear-side ILD layer (152) may be formed with a process and material similar to that of the ILD layer (136). After the formation of the rear-side ILD layer (152), any overcharge may be removed by a planarization process such as CMP.

[0081] Now, referring to FIGS. 17a through 17c, a semiconductor structure (100) is shown after the formation of a rear-side middle-of-the-line contact opening (154) and a rear-side middle-of-the-line contact opening (156) according to an embodiment of the present invention. The rear-side middle-of-the-line contact opening (154) is formed within the logic device regions shown in FIGS. 17a and 17b, and the rear-side middle-of-the-line contact opening (156) is formed in the high-voltage device region shown in FIG. 17c. In some embodiments, to expose one of the sacrifice placeholders (132) within a logic device region using any suitable wet or dry etching, lines within the rear side ILD layer (152) may first be patterned and etched to form rear side middle of the line contact openings (154), and the removal of the exposed sacrifice placeholder among the sacrifice placeholders (132) is followed by removing the material of the selective sacrifice placeholders (132) from the rest of the material of the structure using any suitable etching process to expose the buffer semiconductor layer (133).

[0082] The rear side middle of the line contact opening (156) can be formed by first patterning and etching a line within the rear side ILD layer (152) to expose the substrate (102) in the high-voltage device area using any suitable wet or dry etching.

[0083] Now, referring to FIGS. 18a through 18c, according to an embodiment of the present invention, a semiconductor structure (100) is shown after the formation of a mask layer (158) and the formation of an ion-implanted rear-side source / drain region (160) within a substrate (102). The mask layer (158) is formed on a rear-side middle-of-the-line contact opening (154) within a logic device region shown in FIGS. 18a and 18b and on a rear-side ILD layer (152). The mask layer (158) may be formed by a process and material similar to that of the mask layer (116).

[0084] Next, the exposed substrate (102) within the rear-side middle-of-the-line contact opening (156) in the high-voltage device region illustrated in FIG. 18c undergoes ion implantation technology to form an ion-implanted rear-side source / drain region (160). In some embodiments, the exposed substrate (102) undergoes implantation of p-type ions (e.g., Be / F ions) so that the ion-implanted rear-side source / drain regions (160) become ion-implanted p-type rear-side source / drain regions. In some embodiments, the exposed substrate (102) undergoes implantation of n-type ions (e.g., Si / F ions) so that the ion-implanted rear-side source / drain regions (160) become ion-implanted n-type rear-side source / drain regions. The high-voltage device region on the rear side of the substrate (102) results in a planar device as described below. By using ion implantation technology, the upper surface of the ion-implanted rear-side source / drain region (160) is coplanar with the upper surface of the substrate (102), thereby forming a device channel for an additional gate device, and by using epitaxial growth technology, the upper surface of the source / drain region (134) is not coplanar with the upper surface of the top layer of the nanosheet channel layer (110).

[0085] Now, referring to FIGS. 19a through 19c, a semiconductor structure (100) is shown after the removal of the mask layer (158) and the formation of the rear middle-of-the-line contacts (162 and 164) according to an embodiment of the present invention. The mask layer (158) is removed in the logic device region shown in FIGS. 19a and 19b, for example, by an ash etching process. Next, subsequently, a suitable conductive metal is deposited within the rear-side middle-of-the-line contact opening (154) (as shown in FIG. 17a and 17b) and within the rear-side middle-of-the-line contact opening (156) (as shown in FIG. 17c), and CMP is followed to remove any metal from the top of the rear-side ILD layer (152) to form the rear-side middle-of-the-line contacts (162 and 164) [also referred to as the rear-side source / drain contact (162) and the rear-side source / drain contact (164)]. The suitable conductive metal may be deposited in a manner similar to that discussed above and with a similar conductive metal.

[0086] Now, referring to FIGS. 20a through 20c, a semiconductor structure (100) after the formation of a rear-side power transfer network (166) according to an embodiment of the present invention is illustrated. The rear-side power transfer network (166) is formed on a structure including rear-side middle-of-the-line contacts (162, 164) and is based on the creation of a wiring method disposed on both sides of the device layer (the front end of the line structure). In exemplary embodiments, a logic device region may be integrated together with a high-voltage device region through the rear-side power transfer network (166).

[0087] Accordingly, in an exemplary embodiment, the semiconductor structure (100) will include a logic device region including a transistor device and a high voltage device region including a planar device. The transistor device includes at least nanosheet channel layers (110), an alternate gate structure (140), source / drain regions (134), and one of the source / drain regions (134) and one of the rearward source / drain contacts (162) connecting one of the source / drain regions (134) to a rearward power transfer network (166). The planar device includes at least a substrate (102) having an ion-implanted rearward source / drain region (160) disposed on the rearward ILD layer (152) and respectively disposed within the rearward side of the substrate (102), and a rearward source / drain contact (164) connecting the ion-implanted rearward source / drain region (160) to a rearward power transfer network (166).

[0088] According to the technologies described above, semiconductor devices and methods for forming them may be used in various applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, as non-limiting examples, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cells and smartphones), solid-state media storage devices, functional circuits, etc. Systems and hardware integrating semiconductor devices are embodiments of the present invention. Considering the teachings provided herein, a person skilled in the art will be able to imagine other embodiments and applications of the embodiments of the present invention.

[0089] In some embodiments, the technologies described above are used in connection with semiconductor devices that require or can utilize, for example, CMOS, MOSFET, and / or FinFET. As a non-limiting example, semiconductor devices may include, but are not limited to, CMOS, MOSFET, and FinFET devices, and / or semiconductor devices using CMOS, MOSFET, and / or FinFET technology.

[0090] The various structures described above can be implemented as integrated circuits. The resulting integrated circuit chips may be distributed by the manufacturer in the form of a raw wafer (i.e., as a single wafer containing multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having either or both surface interconnects and embedded interconnects). In either case, the chip is subsequently integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product such as a motherboard or (b) a final product. The final product may be any product containing the integrated circuit chip, ranging from toys and other low-end applications to high-end computer products containing displays, keyboards or other input devices, and central processors.

[0091] According to an embodiment of the present invention, a semiconductor structure comprises a first rear-side source / drain region and a second rear-side source / drain region within a substrate, which are associated with an additional gate device and disposed within a rear-side region of the semiconductor structure.

[0092] In an embodiment, the semiconductor structure further includes a first rear-side source / drain contact connecting a first rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting a second rear-side source / drain region to a rear-side power transfer network.

[0093] In an embodiment, the first rear-side source / drain region and the second rear-side source / drain region include the ion-implanted first rear-side source / drain region and the ion-implanted second rear-side source / drain region.

[0094] In an embodiment, the first rear-side source / drain region and the second rear-side source / drain region within the substrate are planar devices.

[0095] In an embodiment, an additional gate device is integrated together with a logic device.

[0096] In an embodiment, an additional gate device is integrated with a logic device, and the logic device includes a front-side source / drain region connected to a rear-side power delivery network by a third rear-side source / drain contact.

[0097] In an embodiment, the logic device further includes a plurality of nanosheet channel layers disposed on both sidewalls of the front side source / drain region.

[0098] According to an embodiment of the present invention, a semiconductor structure includes a gate extension within the front side of the semiconductor structure, which extends from a gate region and is associated with an additional gate device. The gate extension is disposed between the sidewalls of a first shallow trench region and a second shallow trench region disposed on a substrate. A gate dielectric layer is disposed between the upper surface of the substrate and the gate extension.

[0099] In an embodiment, the semiconductor structure further includes a middle-of-the-line contact connecting a gate region to a back-end-of-the-line interconnect.

[0100] In an embodiment, the gate region and the gate extension include the same conductive material.

[0101] In an embodiment, the gate dielectric layer is also disposed between the gate extension and the first shallow trench region and the second shallow trench region, and on a portion of the upper surface of the second shallow trench region and the first shallow trench region below the gate region.

[0102] In an embodiment, the semiconductor structure further includes a first rear-side source / drain region and a second rear-side source / drain region within a substrate disposed within a rear-side region of the semiconductor structure and associated with an additional gate device.

[0103] In an embodiment, the semiconductor structure further includes a first rear-side source / drain contact connecting a first rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting a second rear-side source / drain region to a rear-side power transfer network.

[0104] In an embodiment, the first rear-side source / drain region and the second rear-side source / drain region include the ion-implanted first rear-side source / drain region and the ion-implanted second rear-side source / drain region.

[0105] In an embodiment, an additional gate device is integrated together with a logic device, and the logic device is located within a front-side region of a semiconductor structure and includes a front-side source / drain region connected to a rear-side power transfer network by a rear-side source / drain contact.

[0106] According to an embodiment of the present invention, the semiconductor structure comprises: an additional gate device disposed within a rear side region of the semiconductor structure and comprising a first ion-implanted rear side source / drain region and a second ion-implanted rear side source / drain region within a substrate; a logic device disposed within a front side region of the semiconductor structure and comprising a stack of first nanosheet channel layers and a stack of second nanosheet channel layers adjacent to the stack of first nanosheet channel layers; and an epitaxial growth source / drain region between the stack of first nanosheet channel layers and the stack of second nanosheet channel layers. The additional gate device is integrated with the logic device.

[0107] In an embodiment, the upper surface of each of the first ion-implanted rearward source / drain region and the second ion-implanted rearward source / drain region is coplanar with the upper surface of the substrate, and the upper surface of the epitaxial growth source / drain region is on the upper surface of each of the stack of the first nanosheet channel layers and the stack of the second nanosheet channel layers.

[0108] In an embodiment, the semiconductor structure further includes a first rear-side source / drain contact connecting a first ion-implanted rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting a second ion-implanted rear-side source / drain region to a rear-side power transfer network.

[0109] In an embodiment, the epitaxial growth source / drain region is connected to a rear-side power transfer network by a third rear-side source / drain contact.

[0110] According to an embodiment of the present invention, an integrated circuit comprises one or more semiconductor structures, and at least one of the one or more semiconductor structures comprises a first rear-side source / drain region and a second rear-side source / drain region within a substrate, which are associated with an additional gate device and disposed within a rear-side region of the semiconductor structure.

[0111] In an embodiment, at least one of the semiconductor structures further comprises a first rear-side source / drain contact connecting a first rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting a second rear-side source / drain region to a rear-side power transfer network.

[0112] In an embodiment, an additional gate device is integrated with a logic device, and the logic device includes a front-side source / drain region connected to a rear-side power delivery network by a third rear-side source / drain contact.

[0113] In an embodiment, at least one of the semiconductor structures further comprises a gate extension within the front side of the semiconductor structure, which extends from a gate region and is associated with an additional gate device, the gate extension is disposed between the side walls of a first shallow trench region and a second shallow trench region disposed on a substrate, and a gate dielectric layer is disposed between the upper surface of the substrate and the gate extension.

[0114] According to an embodiment of the present invention, the method comprises the step of implanting ions into a first rear-side source / drain region and a second rear-side source / drain region within a substrate disposed within a rear-side region of a semiconductor structure and associated with an additional gate device.

[0115] In an embodiment, the method further comprises the steps of forming a first rear-side source / drain contact on a first rear-side source / drain region, forming a second rear-side source / drain contact on a second rear-side source / drain region, and forming a rear-side power transfer network on the first rear-side source / drain contact and the second rear-side source / drain contact.

[0116] The description of various embodiments of the present invention is provided for illustrative purposes only, but is not intended to be comprehensive or limiting to the embodiments disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The technical terms used herein are chosen to best describe the principles of the embodiments, practical applications of technology found in the market, or technical improvements, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0117] Embodiments of the present invention include the following:

[0118] (1) The semiconductor structure includes a first rear-side source / drain region and a second rear-side source / drain region within the substrate, which are associated with an additional gate device and are disposed within the rear-side region of the semiconductor structure.

[0119] (2) The semiconductor structure according to clause (1) further includes a first rear-side source / drain contact connecting a first rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting a second rear-side source / drain region to a rear-side power transfer network.

[0120] (3) In the semiconductor structure according to clause (1), the first rear-side source / drain region and the second rear-side source / drain region include the ion-implanted first rear-side source / drain region and the ion-implanted second rear-side source / drain region.

[0121] (4) In the semiconductor structure according to clause (1), the first rear-side source / drain region and the second rear-side source / drain region within the substrate are planar devices.

[0122] (5) In the semiconductor structure according to clause (1), additional gate devices are integrated together with the logic devices.

[0123] (6) In a semiconductor structure according to clause (2), an additional gate device is integrated with a logic device, and the logic device includes a front side source / drain region connected to a rear side power delivery network by a third rear side source / drain contact.

[0124] (7) In a semiconductor structure according to clause (6), the logic device further comprises a plurality of nanosheet channel layers disposed on both sidewalls of the front side source / drain region.

[0125] (8) The semiconductor structure includes a gate extension within the front side of the semiconductor structure, which extends from the gate region and is associated with an additional gate device, and the gate extension is positioned between the side walls of the first shallow trench region and the second shallow trench region disposed on the substrate, and the gate dielectric layer is positioned between the upper surface of the substrate and the gate extension.

[0126] (9) A semiconductor structure according to clause (8) further includes a middle-of-the-line contact connecting a gate region to a back-end-of-the-line interconnect.

[0127] (10) In a semiconductor structure according to clause (8), the gate region and the gate extension share the same conductive material.

[0128] (11) In a semiconductor structure according to clause (8), the gate dielectric layer is also disposed between the gate extension and the first shallow trench region and the second shallow trench region, and on a portion of the upper surface of the second shallow trench region and the first shallow trench region below the gate region.

[0129] (12) In a semiconductor structure according to clause (8), the semiconductor structure further comprises a first rear-side source / drain region and a second rear-side source / drain region within a substrate that is associated with an additional gate device and disposed within a rear-side region of the semiconductor structure.

[0130] (13) A semiconductor structure according to clause (12) further includes a first rear-side source / drain contact connecting a first rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting a second rear-side source / drain region to a rear-side power transfer network.

[0131] (14) In a semiconductor structure according to clause (12), the first rear-side source / drain region and the second rear-side source / drain region include the first rear-side source / drain region and the second rear-side source / drain region that are ion-implanted.

[0132] (15) In a semiconductor structure according to clause (12), an additional gate device is integrated together with a logic device, and the logic device is located within a front side region of the semiconductor structure and includes a front side source / drain region connected to a rear side power transfer network by a third rear side source / drain contact.

[0133] (16) The semiconductor structure comprises: an additional gate device disposed within a rear side region of the semiconductor structure and comprising a first ion-implanted rear side source / drain region and a second ion-implanted rear side source / drain region within the substrate; a logic device disposed within a front side region of the semiconductor structure and comprising a stack of first nanosheet channel layers and a stack of second nanosheet channel layers adjacent to the stack of first nanosheet channel layers; and an epitaxial growth source / drain region between the stack of first nanosheet channel layers and the stack of second nanosheet channel layers, and the additional gate device is integrated with the logic device.

[0134] (17) In a semiconductor structure according to clause (16), the upper surface of each of the first ion-implanted rearward source / drain region and the second ion-implanted rearward source / drain region is coplanar with the upper surface of the substrate, and the upper surface of the epitaxially grown source / drain region is on the upper surface of each of the stack of the first nanosheet channel layers and the stack of the second nanosheet channel layers.

[0135] (18) A semiconductor structure according to clause (16) further comprises a first rear-side source / drain contact connecting a first ion-implanted rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting a second ion-implanted rear-side source / drain region to a rear-side power transfer network.

[0136] (19) In a semiconductor structure according to clause (18), the epitaxial growth source / drain region is connected to a rear side power transfer network by a third rear side source / drain contact.

[0137] (20) The integrated circuit comprises one or more semiconductor structures, and at least one of the semiconductor structures comprises a first rear-side source / drain region and a second rear-side source / drain region in a substrate, which are associated with an additional gate device and disposed within a rear-side region of at least one of the semiconductor structures.

[0138] (21) In the integrated circuit of clause (20), at least one of the semiconductor structures further comprises a first rear-side source / drain contact connecting a first rear-side source / drain region to a rear-side power delivery network, and a second rear-side source / drain contact connecting a second rear-side source / drain region to a rear-side power delivery network.

[0139] (22) In the integrated circuit of clause (20), additional gate devices are integrated together with logic devices, and the logic devices include a front-side source / drain area connected to a rear-side power delivery network by a third rear-side source / drain contact.

[0140] (23) In the integrated circuit of clause (20), at least one of the semiconductor structures further comprises a gate extension in the front side of the semiconductor structure, which extends from the gate region and is associated with an additional gate device, and the gate extension is disposed between the side walls of the first shallow trench region and the second shallow trench region disposed on the substrate, and the gate dielectric layer is disposed between the upper surface of the substrate and the gate extension.

[0141] (24) The method includes the step of implanting ions into a first rear-side source / drain region and a second rear-side source / drain region within a substrate that is associated with an additional gate device and is positioned within a rear-side region of a semiconductor structure.

[0142] (25) The method of clause (24) further comprises the steps of forming a first rear-side source / drain contact on a first rear-side source / drain region, forming a second rear-side source / drain contact on a second rear-side source / drain region, and forming a rear-side power transfer network on the first rear-side source / drain contact and the second rear-side source / drain contact.

Claims

Claim 1 A semiconductor structure comprising a first rear-side source / drain region and a second rear-side source / drain region within a substrate, said substrate, which are associated with an extra gate device and disposed within a rear-side region of said substrate, said extra gate device being integrated with a logic device, and said logic device comprising a front-side source / drain region connected to a rear-side power transfer network by a third rear-side source / drain contact. Claim 2 A semiconductor structure according to claim 1, further comprising a first rear-side source / drain contact connecting the first rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting the second rear-side source / drain region to the rear-side power transfer network. Claim 3 A semiconductor structure according to claim 1 or 2, wherein the first rear-side source / drain region and the second rear-side source / drain region comprise an ion-implanted first rear-side source / drain region and an ion-implanted second rear-side source / drain region. Claim 4 A semiconductor structure according to claim 1 or 2, wherein the first rear-side source / drain region and the second rear-side source / drain region within the substrate are planar devices. Claim 5 delete Claim 6 delete Claim 7 A semiconductor structure according to claim 1, wherein the logic device further comprises a plurality of nanosheet channel layers disposed on both sidewalls of the front side source / drain region. Claim 8 A semiconductor structure according to claim 1 or 2, comprising a gate extension within the front side of the semiconductor structure, extending from a gate region and associated with the additional gate device, wherein the gate extension is disposed between the side walls of a first shallow trench region and a second shallow trench region disposed on a substrate, and a gate dielectric layer is disposed between the upper surface of the substrate and the gate extension. Claim 9 A semiconductor structure according to claim 8, further comprising a middle-of-the-line contact connecting the gate region to a back-end-of-the-line interconnect. Claim 10 A semiconductor structure according to claim 8, wherein the gate region and the gate extension share the same conductive material. Claim 11 A semiconductor structure according to claim 8, wherein the gate dielectric layer is also disposed between the gate extension and the first shallow trench region and the second shallow trench region, and on a portion of the upper surfaces of the second shallow trench region and the first shallow trench region below the gate region. Claim 12 A semiconductor structure according to claim 1 or 2, comprising a logic device disposed within a front side region of the semiconductor structure—the logic device comprising a stack of first nanosheet channel layers, a stack of second nanosheet channel layers adjacent to the stack of first nanosheet channel layers, and an epitaxial growth source / drain region between the stack of first nanosheet channel layers and the stack of second nanosheet channel layers—wherein the first rear side source / drain region and the second rear side source / drain region comprise an ion-implanted first rear side source / drain region and an ion-implanted second rear side source / drain region; and wherein the additional gate device is integrated together with the logic device. Claim 13 A semiconductor structure according to claim 12, wherein the upper surface of each of the ion-implanted first rear-side source / drain region and the ion-implanted second rear-side source / drain region is coplanar with the upper surface of the substrate, and the upper surface of the epitaxial growth source / drain region is on the upper surface of each of the stack of the first nanosheet channel layers and the stack of the second nanosheet channel layers. Claim 14 A semiconductor structure according to claim 12, further comprising a first rear-side source / drain contact connecting the ion-implanted first rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting the ion-implanted second rear-side source / drain region to the rear-side power transfer network. Claim 15 A semiconductor structure according to claim 14, wherein the epitaxial growth source / drain region is connected to the rear side power transfer network by a third rear side source / drain contact. Claim 16 An integrated circuit comprising one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises the semiconductor structure according to claim 1 or 2. Claim 17 A semiconductor structure comprising a gate extension extending from a gate region, associated with an additional gate device, and located within the front side of the semiconductor structure, wherein the gate extension is located between the side walls of a first shallow trench region and a second shallow trench region disposed on a substrate, and a gate dielectric layer is disposed between the upper surface of the substrate and the gate extension, wherein the additional gate device is integrated with a logic device, wherein the logic device is located within the front side region of the semiconductor structure, and wherein the logic device comprises a front side source / drain region connected to a rear side power transfer network by a third rear side source / drain contact. Claim 18 A semiconductor structure comprising: an additional gate device disposed within a rear side region of a substrate and including a first ion-implanted rear side source / drain region and a second ion-implanted rear side source / drain region within the substrate; and a logic device disposed within a front side region of the semiconductor structure and including a stack of first nanosheet channel layers and a stack of second nanosheet channel layers adjacent to the stack of first nanosheet channel layers, and an epitaxial growth source / drain region between the stack of first nanosheet channel layers and the stack of second nanosheet channel layers, wherein the additional gate device is integrated together with the logic device. Claim 19 An integrated circuit comprising one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises a first rear-side source / drain region and a second rear-side source / drain region within the substrate, which are associated with an additional gate device and disposed within a rear-side region of the substrate, wherein the additional gate device is integrated together with a logic device, and the logic device comprises a front-side source / drain region connected to a rear-side power transfer network by a third rear-side source / drain contact. Claim 20 An integrated circuit according to claim 19, wherein at least one of the above-mentioned semiconductor structures further comprises a first rear-side source / drain contact connecting the first rear-side source / drain region to a rear-side power transfer network, and a second rear-side source / drain contact connecting the second rear-side source / drain region to the rear-side power transfer network. Claim 21 delete Claim 22 An integrated circuit according to claim 19 or 20, wherein at least one of the one or more semiconductor structures further comprises a gate extension within the front side of the semiconductor structure, which extends from a gate region and is associated with the additional gate device, wherein the gate extension is disposed between the side walls of a first shallow trench region and a second shallow trench region disposed on the substrate, and a gate dielectric layer is disposed between the upper surface of the substrate and the gate extension. Claim 23 delete Claim 24 delete

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