Semiconductor devices

Abstract

A semiconductor device is provided with contact plug structures arranged on a substrate and spaced apart from each other in a first direction. A fence insulation structure is arranged to fill the space between the contact plug structures in the first direction, insulates the contact plug structures from each other, and includes a barrier insulation pattern and a fence insulation pattern. In the fence insulation structure, the fence insulation pattern comprises an insulating material having an etch selectivity ratio with silicon oxide. The barrier insulation pattern comprises a material having a higher bandgap than the fence insulation pattern, which contacts at least a portion of the sidewalls of the fence insulation pattern and a portion of the sidewalls of the contact plug structures. The semiconductor device can reduce electron and hole tunneling between the contact plug structures, thereby reducing leakage current.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. More specifically, the present invention relates to a DRAM device. Background Technology

[0002] In a semiconductor device, some contact plugs may be repeatedly arranged with uniform spacing. As the semiconductor device becomes highly integrated, the spacing between the contact plugs decreases, and the arrangement density of the contact plugs can become very high. Consequently, electrical isolation between the contact plugs may not be easy. The problem to be solved

[0003] The objective of the present invention is to provide a semiconductor device comprising contact plugs. means of solving the problem

[0004] A semiconductor device according to an embodiment of the present invention for achieving the above-mentioned objective comprises contact plug structures arranged on a substrate and spaced apart from each other in a first direction. A fence insulation structure is arranged to fill the space between the contact plug structures in the first direction, insulates the contact plug structures from each other, and includes a barrier insulation pattern and a fence insulation pattern. In the fence insulation structure, the fence insulation pattern comprises an insulating material having an etch selectivity ratio with silicon oxide. The barrier insulation pattern comprises a material having a higher bandgap than the fence insulation pattern, which contacts at least a portion of the sidewall of the fence insulation pattern and a portion of the sidewall of the contact plug structure.

[0005] A semiconductor device according to an embodiment of the present invention for achieving the above-mentioned objective comprises bit line structures arranged on a substrate that extend in a first direction and are spaced apart in a second direction perpendicular to the first direction. Contact plug structures are arranged on the substrate between the bit line structures and spaced apart from each other in the first direction. A fence insulation structure is provided that is arranged to fill the opening between the first directions of the contact plug structures, insulates the contact plug structures from each other, and includes a barrier insulation pattern and a fence insulation pattern. In the fence insulation structure, the fence insulation pattern comprises an insulating material having an etch selectivity ratio with silicon oxide. The barrier insulation pattern surrounds the sidewalls and bottom surface of the fence insulation pattern and comprises a material having a higher bandgap than the fence insulation pattern.

[0006] A semiconductor device according to an embodiment of the present invention for achieving the above-mentioned objective comprises an active pattern on a substrate. Gate structures are provided that are embedded on the active pattern, spaced apart from each other in a first direction, and extend in a second direction perpendicular to the first direction. Bit line structures are provided on the substrate that extend in the first direction and are spaced apart from each other in the second direction. A spacer structure is formed on the sidewall of the bit line structure. Contact plug structures are arranged on the substrate, positioned within an opening between the bit line structures and spaced apart from each other in the first direction. A fence insulation structure is provided that includes a barrier insulation pattern and a fence insulation pattern, which is arranged to fill the area between the bit line structures and between the contact plugs to insulate the contact plug structures from each other. In the fence insulation structure, the fence insulation pattern comprises silicon nitride. The barrier insulation pattern comprises a material having a higher bandgap than silicon nitride, which contacts at least a portion of the sidewall of the fence insulation pattern and a portion of the sidewall of the contact plug structure. Effects of the invention

[0007] According to exemplary embodiments, the fence insulation structure that insulates adjacent contact plug structures of a semiconductor device may include a barrier insulation pattern having a high bandgap with respect to said contact plug structures. Accordingly, leakage current caused by hole and electron tunneling in said adjacent contact plug structures may be reduced. As a result, defects in the semiconductor device including said contact plug structures may be reduced and the electrical characteristics of the semiconductor device may be improved. Brief explanation of the drawing

[0008] FIG. 1 is a plan view of a semiconductor device according to an exemplary embodiment. FIG. 2 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. FIG. 3 is a plan view showing an enlarged portion of the semiconductor device. FIGS. 4 to 19 are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 20 and FIGS. 21 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 22 to 27 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 28 to 32 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIG. 33 is a plan view of a semiconductor device according to exemplary embodiments. FIG. 34 is an enlarged plan view of a portion of a semiconductor device according to exemplary embodiments. FIGS. 35 and 36 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIG. 37 is an enlarged plan view of a portion of a semiconductor device according to an exemplary embodiment. FIG. 38 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. FIG. 39 is an enlarged plan view of a portion of a semiconductor device according to an exemplary embodiment. FIG. 40 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. FIG. 41 shows the energy levels of the contact plug structure and the fence insulation structure in a semiconductor device according to an exemplary embodiment. Specific details for implementing the invention

[0009] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0010] FIG. 1 is a plan view of a semiconductor device according to an exemplary embodiment. FIG. 2 are cross-sectional views of a semiconductor device according to an exemplary embodiment. FIG. 3 is an enlarged plan view of a part of the semiconductor device.

[0011] Specifically, FIG. 3 is an enlarged view of the shape of section C in FIG. 1. FIG. 3 shows only the contact plug structure and the fence structure.

[0012] In the following description, the extension direction of the bit line structure is referred to as the first direction, and the direction perpendicular to the first direction (e.g., the extension direction of the gate structure) is referred to as the second direction. Additionally, the length direction of the active pattern is referred to as the third direction. The third direction may have an inclination with respect to each of the first and second directions.

[0013] Referring to FIGS. 1, 2 and 3, a device isolation trench (102) is included on the upper part of a substrate (100), and an active pattern (106) with a shape protruding from the substrate (100) can be formed between the device isolation trenches (102). The active pattern (106) may have a bar shape arranged such that a third direction is the longitudinal direction. A device isolation pattern (104) is provided within the device isolation trench (102).

[0014] A first recess (108) extending in the second direction may be formed on the upper portion of the active pattern (106) and the device isolation pattern (104). A gate structure (116) may be formed inside the first recess (108). A plurality of gate structures (116) may be arranged spaced apart in the first direction.

[0015] The gate structure (116) may include a first gate insulating film (110), a first gate electrode (112), and a first capping film pattern (114). In an exemplary embodiment, the first gate electrode (112) may include a barrier metal film pattern (112a), a metal film pattern (112b), and a polysilicon film pattern (112c).

[0016] A bit line structure (150) may be provided on the gate structure (116) and the substrate (100). The bit line structure (150) may extend in the first direction. A plurality of bit line structures (150) may be spaced apart in the second direction. The bit line structure (150) may include a lower conductive pattern (132a), a barrier film pattern (134a), a first metal pattern (136a), and a second capping film pattern (140a) that are stacked in sequence.

[0017] A portion of the bottom surface of the bit line structure (150) may come into contact with the central portion of the upper surface of the active pattern (106). Additionally, a first buffer insulation pattern (120a) and a second buffer insulation pattern (120b) may be laminated on the substrate (100) below the bottom surface of the bit line structure (150), and a portion of the bottom surface of the bit line structure (150) may come into contact with the second buffer insulation pattern (120b). A spacer structure (160) may be provided on the side wall of the bit line structure (150).

[0018] A contact plug structure (194) may be provided between the bit line structures (150) and in contact with both ends of the upper surface of the active pattern (106). The contact plug structure (194) may be positioned between the bit line structures (150) to be in contact with the upper surface of the active pattern (106) in the area between the gate structures (116).

[0019] The above contact plug structure (194) may include metal and / or polysilicon. If the contact plug structure (194) includes metal, the contact plug structure may have low resistance.

[0020] In an exemplary embodiment, the contact plug structure (194) may include a lower contact plug (170b) and an upper contact plug (190). The lower contact plug (170b) may include polysilicon, and the upper contact plug (190) may include a metallic material. As an example, the upper contact plug (190) may include a metal silicide pattern (190a), a barrier metal pattern (190b), and a metal pattern (190c). The metal silicide pattern (190a) may include, for example, cobalt silicide, nickel silicide, titanium silicide, etc. The barrier metal pattern (190b) may include, for example, titanium nitride, titanium, tantalum nitride, tantalum, etc. The metal pattern (190c) may include, for example, tungsten.

[0021] In some exemplary embodiments, the upper contact plug (190) containing metal may have a higher height than the lower contact plug (170b) containing polysilicon.

[0022] In some exemplary embodiments, the contact plug structure (194) may comprise only metallic materials. For example, the contact plug structure (194) may comprise a metal silicide pattern, a barrier metal pattern, and a metal pattern.

[0023] In some exemplary embodiments, the contact plug structure (194) may comprise only polysilicon.

[0024] A fence insulation structure (184) may be provided between the first direction of the contact plug structures (194). The contact plug structures (194) may be electrically insulated by the fence insulation structure (184).

[0025] The fence insulation structure (184) may include a barrier insulation pattern (180a) and a fence insulation pattern (182a). In an exemplary embodiment, the barrier insulation pattern (180a) may have a shape that surrounds the side walls and bottom surface of the fence insulation pattern (182a). The barrier insulation pattern (180a) may completely surround the outer wall of the fence insulation pattern (182a).

[0026] The above fence insulation structure (184) may each be formed inside an opening defined by adjacent contact plug structures (194) and adjacent bit line structures (150). A portion of the side wall of the spacer structure (160) may be exposed in the opening.

[0027] A barrier insulation pattern (180a) is provided along the inner surface of the opening, and a fence insulation pattern (182a) that fills the opening may be formed on the barrier insulation pattern (180a). Accordingly, the barrier insulation pattern (180a) may come into contact with a portion of the side wall of the spacer structure exposed by the opening.

[0028] The above fence insulation pattern (182a) may include an insulating material having an etch selectivity ratio with silicon oxide. The above barrier insulation pattern (180a) may include a material having a higher bandgap than the above fence insulation pattern (182a).

[0029] In an exemplary embodiment, the fence insulation pattern (182a) may comprise silicon nitride. In this case, the barrier insulation pattern (180a) may comprise a material having a higher bandgap than silicon nitride.

[0030] In some exemplary embodiments, the fence insulation pattern (182a) may include SiOCN, BN, or SiOC having a lower dielectric constant than silicon nitride.

[0031] In an exemplary embodiment, the barrier insulation pattern (180a) may use aluminum nitride, silicon oxide, aluminum oxide, aluminum oxynitride, silicon oxynitride, or BN, etc. For example, the barrier insulation pattern (180a) may be aluminum-doped silicon nitride or aluminum-doped silicon oxynitride.

[0032] The barrier insulation pattern (180a) may come into contact with a portion of the outer wall of the contact plug structure (194). The barrier insulation pattern (180a) may come into contact with each of the side walls of two contact plug structures (194) facing each other in a first direction.

[0033] As illustrated in FIG. 3, the contact plug structure (194) / fence insulation structure (184) / contact plug structure (194) / fence insulation structure (184) may be arranged to repeat in the first direction between the bit line structures (150).

[0034] When the spacing between the contact plug structures (194) is very narrow and the energy bandgap of the fence insulation structure (184) placed between the contact plug structures (194) is low, electrons and holes may tunnel through the fence insulation pattern (184), causing leakage current between the contact plug structures (194). In particular, if a metallic material is included in the contact plug structures (194) to have low resistance, the energy bandgap becomes lower, and a larger leakage current may occur.

[0035] However, as the fence insulation structure (184) is provided with a fence insulation pattern (182a) and a barrier insulation pattern (180a) having a higher bandgap than the fence insulation pattern (182a), the tunneling of electrons and holes through the fence insulation structure (184) between adjacent contact plug structures (194) can be suppressed. Therefore, leakage current between contact plug structures (194) can be prevented.

[0036] Meanwhile, as illustrated in FIG. 3, when a fence insulation structure is formed by performing an actual semiconductor manufacturing process (e.g., a photolithography process), each corner portion of the fence insulation structure may have a rounded shape. When viewed in a plan view, the fence insulation structure (184) may have a square or elliptical shape with rounded vertices. In this case, the barrier insulation pattern may be formed relatively thicker at the rounded corner portions. Therefore, leakage current that may occur at the rounded corner portions may be reduced.

[0037] In an exemplary embodiment, the upper surface of the contact plug structure (194) may be provided as a landing pad for connecting to a capacitor (198). In an exemplary embodiment, the uppermost surface of the contact plug structure (194) may be positioned higher than the upper surfaces of the bit line structure (150) and the fence insulation structure (184).

[0038] A capacitor (198) in contact with the upper surface of the above contact plug structure (194) may be provided. The capacitor (198) may have a structure in which a lower electrode (198a), a dielectric film (198b), and an upper electrode (198c) are stacked.

[0039] Below, the manufacturing method of the semiconductor device and each element of the semiconductor device are described in more detail.

[0040] FIGS. 4 to 19 are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

[0041] Specifically, FIGS. 4, 9, 12, and 16 are plan views, and FIGS. 5 to 8, FIGS. 10, 11, FIGS. 13 to 15, and FIGS. 17 to 19 are cross-sectional views. Each cross-sectional view includes a cross-section of the AA' and BB' portions of FIG. 4.

[0042] Referring to FIGS. 4 and 5, a portion of the substrate (100) is etched to form a device isolation trench (102) corresponding to a field region.

[0043] The substrate (100) may include, for example, a semiconductor material such as silicon, germanium, silicon-germanium, etc., or a Group III-V compound such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (100) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0044] The protruding portion of the substrate (100) where the above-mentioned device isolation trench (102) is not formed may be provided as an active pattern (106). The upper surface of the above-mentioned active pattern (106) may be provided as an active region, and the above-mentioned active region may be arranged such that the third direction is the longitudinal direction.

[0045] A device isolation pattern (104) is formed to fill the interior of the device isolation trench (102). The device isolation pattern (104) can be formed by forming an insulating film to completely fill the interior of the trench (102) and flattening the upper surface of the insulating film. The flattening process may include chemical mechanical polishing (CMP) and / or an etch-back process.

[0046] An impurity region (not shown) is formed on the above active pattern (106) and device isolation pattern (104) by, for example, performing an ion implantation process.

[0047] The active pattern (106) and the device isolation pattern (104) can be partially etched to form a first recess (108) extending in the second direction. Subsequently, a gate structure (116) is formed inside the first recess (108).

[0048] The gate structure (116) may be formed to include a first gate insulating film (110) conformally formed on the inner surface of the first recess (108), a first gate electrode (112) formed on the first gate insulating film (110) to fill the lower part of the first recess (108), and a first capping film pattern (114) formed on the first gate electrode (112) to fill the upper part of the first recess (108). In an exemplary embodiment, the first gate electrode (112) may include a barrier metal film pattern (112a), a metal film pattern (112b), and a polysilicon film pattern (112c).

[0049] The gate structure (116) can be extended along the second direction and can be formed in multiple units spaced apart from each other along the first direction.

[0050] Referring to FIG. 6, a first buffer insulating film (120) and a second buffer insulating film (122) are sequentially formed on the upper surface of the active pattern (106), the device isolation pattern (104), and the first capping film pattern (114). The first and second buffer insulating films (120, 122) may be formed to insulate between the active patterns (106) and the conductive patterns (e.g., bit line structures) formed on the upper surface. The first and second buffer insulating films (120, 122) may include insulating materials having an etch selectivity ratio relative to each other.

[0051] In an exemplary embodiment, the first buffer insulating film (120) may comprise silicon oxide, and the second buffer insulating film (122) may comprise silicon nitride.

[0052] A first conductive film (124) is formed on the second buffer insulating film (122). The first conductive film (124) may, for example, include polysilicon doped with impurities. A portion of the first conductive film (124), the second buffer insulating film (122), and the first buffer insulating film (120) is etched sequentially, and subsequently, the upper portions of the active pattern (106), the adjacent device isolation pattern (104), and the gate structure (116) are over-etched together to form a first opening (126). In an exemplary embodiment, the upper surface of the middle portion in the longitudinal direction of each active pattern (106) may be exposed on the bottom surface of the first opening (126).

[0053] A second conductive film pattern (130) is formed inside the first opening (126). The second conductive film pattern (130) may include a material substantially identical to the first conductive film (124), and, for example, may include polysilicon doped with impurities. The first conductive film (124) and the second conductive film pattern (130) may be combined to form a single lower conductive film (132).

[0054] A barrier film (134) and a first metal film (136) are sequentially formed on the lower conductive film (132). In exemplary embodiments, the first metal film (136) may include, for example, tungsten.

[0055] A second capping film (140) is formed on the first metal film (136). In an exemplary embodiment, the second capping film (140) may include silicon nitride.

[0056] Referring to FIG. 7, a first etching mask pattern (not shown) is formed on the second capping film (140). The process of forming the first etching mask pattern may include a photolithography process.

[0057] A second capping film pattern (140a) is formed by etching the second capping film (140) using the first etching mask patterns. The second capping film pattern (140a) can be used as an etching mask for forming a bit line structure.

[0058] The first metal film (136), barrier film (134), and lower conductive film (132) are sequentially etched using the second capping film pattern (140a) as an etching mask. Thus, a bit line structure (150) can be formed in which the lower conductive pattern (132a), barrier film pattern (134a), first metal pattern (136a), and second capping film pattern (140a) are stacked in sequence.

[0059] The bit line structure (150) may have a line shape extending in the first direction, and a plurality of bit line structures (150) may be arranged in the second direction while being spaced apart from each other at a constant interval.

[0060] A first portion of the bottom surface of the bit line structure (150) may contact the upper surface of the active pattern (106). The bit line structure (150) may contact the active pattern (106) at the bottom surface of the first opening (126). Additionally, a second portion of the bottom surface of the bit line structure (150) may contact the upper surface of the second buffer insulating film (122).

[0061] Referring to FIG. 8, a first spacer film can be formed conformally on a substrate (100) on which the bit line structure (150) is formed, and then a lower insulating film can be sequentially formed on the first spacer film. The lower insulating film can fill the remaining portion of the first opening (126).

[0062] The first spacer film may include a nitride, for example, silicon nitride. The lower insulating film may include, for example, a silicon oxide film and a silicon nitride film.

[0063] Subsequently, an etching process may be performed to etch the lower insulating film. In exemplary embodiments, the etching process may be performed by a wet etching process using, for example, phosphoric acid (H2PO3), SC1, and hydrofluoric acid (HF) as etchants, and all parts of the lower insulating film except for the part formed within the first opening (126) may be removed. Accordingly, most of the surface of the first spacer film, that is, the part of the first spacer film other than the part formed within the first opening (126), may be exposed, and the parts of the lower insulating film remaining within the first opening (126) may each form lower insulating patterns (162).

[0064] Afterward, a second spacer film may be formed on the exposed first spacer film surface and the lower insulating patterns (162) formed within the first opening (126), and then anisotropically etched to form a second spacer (160b) covering the sidewall of the bit line structure (150) on the first spacer film surface and the lower insulating patterns (162). The second spacer film may include, for example, an oxide such as silicon oxide.

[0065] Afterwards, a dry etching process using the second capping film pattern (140a) and the second spacer (160b) as an etching mask can be performed to expose the upper surface of the active pattern (106). At this time, the upper surface of the device isolation pattern (104) and the upper surface of the first capping film pattern (114) can also be exposed.

[0066] By the above dry etching process, the first spacer film portion formed on the upper surface of the second capping film pattern (140a) and the upper surface of the second buffer insulating film (410) can be removed, and accordingly, a first spacer (160a) covering the side wall of the bit line structure (150) can be formed. In addition, in the above dry etching process, the first and second buffer insulating films (120, 122) can also be partially removed and remain as first and second buffer insulating patterns (120a, 122a), respectively, on the lower part of the bit line structure (150).

[0067] Referring to FIGS. 9 and 10, a third spacer film can be formed on the upper surface of the second capping film pattern (140a), the outer wall of the second spacer (160b), a portion of the upper surface of the lower insulation pattern (162), and the upper surface of the exposed active pattern (106), device isolation pattern (104), and the first capping film pattern (114), and then the third spacer film can be anisotropically etched to form a third spacer (160c) that covers the side wall of the bit line structure (150). The third spacer film may include a nitride, for example, silicon nitride.

[0068] Afterward, a second opening (164) is formed that exposes the active pattern (106) on the lower surface by additionally etching the active pattern (106) exposed between the third spacers (160c). That is, the second opening (164) is located between the bit line structures (150) and can expose the active pattern (106) between the bit line structures (150). In the etching process, the upper portion of the device isolation pattern (104) adjacent to the active pattern (106) may also be partially etched. Therefore, a portion of the device isolation pattern (104) may be exposed on the lower surface of the second opening (164).

[0069] The first to third spacers (160a, 160b, 160c) sequentially stacked along a horizontal direction parallel to the upper surface of the substrate (100) on the side wall of the bit line structure (150) may be collectively referred to as a spacer structure (160). Although the spacer structure (160) has been described as including the first to third spacers (160a, 160b, 160c), the number of stacked spacers and the material of the spacers included in the spacer structure (160) may not be limited thereto.

[0070] Referring to FIG. 11, a third conductive film is formed to fill the second opening (164). The upper surface of the third conductive film is flattened until the upper surface of the second capping film pattern (140a) is exposed. Accordingly, a preliminary conductive pattern (170) extending in the first direction can be formed between the bit line structures (150).

[0071] The above preliminary challenge pattern (170) may include, for example, polysilicon doped with impurities.

[0072] Referring to FIGS. 12 and 13, second etching mask patterns (174) are formed on the second capping film pattern (140a), the spacer structure (160), and the preliminary conductive pattern (170), extending in the second direction and spaced apart in the first direction. A trench extending in the second direction may be formed between the second etching mask patterns (174).

[0073] In exemplary embodiments, each trench portion may overlap with the gate structure (116) in a vertical direction. That is, each trench portion may be located on the gate structure (116).

[0074] The preliminary conductive pattern (170) is etched using the second etching mask pattern (174). In the etching process, the second capping film pattern (140a) and the spacer structure (160) may not be etched.

[0075] Accordingly, between the bit line structures (150), a preliminary conductive pattern (170) in the area exposed by the trench can be selectively etched. The preliminary conductive pattern (170) can be separated from each other in the first direction to form preliminary contact plugs (170a). The bottom surface of each of the preliminary contact plugs (170a) can be in contact with the active pattern (106).

[0076] Additionally, a third opening (176) may be formed between each of the above-mentioned preliminary contact plugs (170a). The upper surface of the first capping film pattern (114) of the gate structure (116) may be exposed on the bottom surface of each of the third openings (176).

[0077] Meanwhile, as shown in FIG. 3, the side wall portions of each corner of the third opening (176) formed through the process may have a rounded shape.

[0078] Referring to FIG. 14, a barrier insulating film (180) is formed conformally along the surface of the third opening (176) and the surface of the second etching mask pattern (174). The barrier insulating film (180) can be formed through a deposition process. In an exemplary embodiment, the barrier insulating film (180) can be formed by an atomic layer stacking method or a chemical vapor deposition method.

[0079] Although not illustrated, when viewed in a plan view, if the side wall portions of each corner of the third opening (176) have a rounded shape, the barrier insulating film may be partially folded during deposition and formed relatively thicker at the rounded corner portions.

[0080] The barrier insulating film (180) may comprise a material having a higher bandgap than the fence insulating film formed to completely fill the interior of the third opening (176) in a subsequent process. In an exemplary embodiment, the barrier insulating film (180) may comprise a material having a higher bandgap than silicon nitride. For example, the barrier insulating film (180) may include aluminum nitride, silicon oxide, aluminum oxide, aluminum oxynitride, silicon oxynitride, BN, etc.

[0081] Referring to FIG. 15, a fence insulating film (182) is formed on the barrier insulating film (180) to completely fill the interior of the third opening (176). The fence insulating film (182) can be formed through a deposition process. In an exemplary embodiment, the fence insulating film (182) can be formed by an atomic layer stacking method or a chemical vapor deposition method.

[0082] The fence insulating film (182) may comprise a material having a selectivity with respect to silicon oxide. In an exemplary embodiment, the fence insulating film (182) may comprise silicon nitride. In some exemplary embodiments, the fence insulating film may comprise SiOCN, BN, or SiOC having a lower dielectric constant than silicon nitride.

[0083] In an exemplary embodiment, when the deposition temperature ranges of the barrier insulating film (180) and the fence insulating film (182) are similar or identical, the barrier insulating film (180) and the fence insulating film (182) can be formed in situ. For example, when the barrier insulating film (180) is formed of aluminum nitride and the fence insulating film (182) is formed of silicon nitride, the barrier insulating film (180) and the fence insulating film (182) can be formed in situ.

[0084] Meanwhile, in some exemplary embodiments, when the deposition temperature ranges of the barrier insulating film (180) and the fence insulating film (182) are different, the barrier insulating film (180) and the fence insulating film (182) can be formed by extrusion. For example, when the barrier insulating film (180) is formed of aluminum oxide or BN and the fence insulating film (182) is formed of silicon nitride, the barrier insulating film (180) and the fence insulating film (182) can be formed by extrusion.

[0085] In an exemplary embodiment, a pre-cleaning process may be further performed to control the interface resistance between the barrier insulating film (180) and the fence insulating film (182) before forming the fence insulating film (182).

[0086] In an exemplary embodiment, a heat treatment process may be further included after forming the barrier insulating film (180) and / or after forming the fence insulating film (182). Through the heat treatment process, the etch resistance and insulation properties of the barrier insulating film (180) and the fence insulating film (182) can be controlled.

[0087] Referring to FIGS. 16 and 17, the fence insulating film (182), barrier insulating film (180), and second etching mask pattern (174) are flattened until the upper surface of the second capping film pattern (140a) is exposed. Accordingly, a fence insulating structure (184) including a barrier insulating pattern (180a) and a fence insulating pattern (182a) can be formed inside the third opening (176). The barrier insulating pattern (180a) can completely surround the sidewall of the fence insulating pattern (182a). The barrier insulating pattern (180a) can come into contact with a portion of the outer sidewall of the spare contact plug (170a).

[0088] The spare contact plugs (170a) spaced apart from each other in the first direction can be insulated from each other by the fence insulation structure (184).

[0089] As described with reference to FIGS. 14 to 17, the barrier insulation pattern (180a) can be formed through a deposition process.

[0090] Referring to FIG. 18, the upper portion of the preliminary contact plug (170a) is etched to form a lower contact plug (170b). An opening having a shape isolated by the bit line structure (150) and the fence insulation structure (184) may be formed on the lower contact plug (170b).

[0091] A second upper conductive film is formed on the lower contact plug (170b) to fill the opening. The second upper conductive film may be formed to have an upper surface higher than the upper surface of the bit line structure (150). The second upper conductive film may include a metallic material. For example, the metallic material may include tungsten.

[0092] Afterwards, an upper contact plug (190) is formed on the lower contact plug (170b) by etching a portion of the second upper conductive film. Through the etching process of the second upper conductive film, a fourth opening may be formed between the upper portions of the upper contact plug (190).

[0093] The laminated structure of the lower contact plug (170b) and the upper contact plug (190) can be provided as a contact plug structure (194). It forms an upper insulating pattern (192) that fills the interior of the fourth opening.

[0094] In an exemplary embodiment, the second upper conductive film may include a metal silicide pattern, a barrier metal film, and a metal film. In this case, the upper contact plug (190) may include a metal silicide pattern (190a), a barrier metal pattern (190b), and a metal pattern (190c).

[0095] In some exemplary embodiments, the height of the opening can be formed higher than that of the lower contact plug (170b) by etching most of the preliminary contact plug (170a). In this case, the upper contact plug (190) containing metal can have a higher height than the lower contact plug (170b) containing polysilicon.

[0096] In some exemplary embodiments, the preliminary contact plug (170a) may be completely etched and a second upper conductive film may be formed within the opening. In this case, for example, the contact plug structure may include a metal silicide pattern, a barrier metal pattern, and a metal pattern.

[0097] In some exemplary embodiments, a contact plug structure formed solely of polysilicon may be formed without performing a process of etching the preliminary contact plug (170a).

[0098] Referring to FIG. 19, a capacitor (198) is formed in contact with the upper surface of the upper contact plug (190).

[0099] The capacitor (198) may have a structure in which a lower electrode (198a), a dielectric film (198b), and an upper electrode (198c) are stacked.

[0100] By performing the above process, a DRAM device can be completed.

[0101] FIGS. 20 and 21 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

[0102] The method for manufacturing the above semiconductor device includes substantially identical or similar processes to those described with reference to FIGS. 4 to 19, except for the method of forming a fence insulation structure, so a redundant description thereof is omitted.

[0103] Referring to FIG. 20, processes substantially identical or similar to those described with reference to FIGS. 1 through 13 are performed. Afterward, a pre-barrier insulating film (178) is formed conformally along the surface of the third opening (176) and the surface of the second etching mask pattern (174). The pre-barrier insulating film (178) may be formed through a deposition process. In an exemplary embodiment, the pre-barrier insulating film (178) may be formed by an atomic layer stacking method or a chemical vapor deposition method.

[0104] The above preliminary barrier insulating film (178) may include silicon nitride.

[0105] Referring to FIG. 21, a barrier insulating film (178a) is formed by doping aluminum into the preliminary barrier insulating film (178). In this case, the barrier insulating film (178a) may be aluminum-doped silicon nitride. The doping process may include an ion implantation process.

[0106] In some exemplary embodiments, the preliminary barrier insulating film (178) is oxidized to form a barrier insulating film (178a). In this case, the barrier insulating film (178a) may be silicon oxide or silicon oxynitride. The oxidation process may include a radical oxidation process.

[0107] In some exemplary embodiments, the pre-barrier insulating film (178) is doped with aluminum and then oxidized to form a barrier insulating film (178a). In this case, the barrier insulating film (178a) may be an aluminum-doped silicon oxynitride.

[0108] In this way, to form a barrier insulating film (178a) having a higher bandgap than a fence insulating film, after forming a thin silicon nitride film, impurities can be doped into the silicon nitride film or an oxidation process can be performed.

[0109] Afterwards, the semiconductor device can be manufactured by performing processes that are substantially identical or similar to the processes described with reference to FIGS. 15 to 19.

[0110] FIGS. 22 to 27 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

[0111] The manufacturing method of the above semiconductor device includes substantially identical or similar processes to those described with reference to FIGS. 4 to 19, so a redundant description thereof is omitted. The manufacturing method below first forms a fence insulation structure and then forms a contact plug structure.

[0112] Referring to FIG. 22, processes substantially identical or similar to those described with reference to FIG. 4 through 8 are performed.

[0113] Afterwards, a third spacer film (161) is formed on the upper surface of the second capping film pattern (140a), the outer wall of the second spacer (160b), a part of the upper surface of the lower insulation pattern (162), the exposed active pattern (106), the device isolation pattern (104), and the upper surface of the first capping film pattern (114).

[0114] A buried insulating film (200) is formed on the third spacer film (161) to fill the gap between the third spacer films (161). Afterward, the buried insulating film (200) can be flattened so that the second capping film pattern (140a) is exposed. The buried insulating film (200) may include silicon oxide. As an example, the buried insulating film (200) may include TOSZ (Tonen SilaZene) material.

[0115] Referring to FIG. 23, an etching mask pattern (202) for forming a fence insulation pattern is formed on the buried insulating film (200) and the second capping film pattern (140a). The etching mask pattern (202) may be formed to selectively expose the area where the fence insulation pattern is formed. The process of forming the etching mask pattern (202) may include a photolithography process.

[0116] The etching mask pattern (202) may have a line shape extending in the second direction, and a plurality of etching mask patterns (202) may be arranged in the first direction while being spaced apart from each other at a constant interval. The etching mask pattern (202) may expose a portion facing the gate structure (116).

[0117] A second opening (204) is formed by etching the buried insulating film (200) using the etching mask pattern (202) as an etching mask. In the process of forming the opening (204), the upper portion of the third spacer film (161) and the first capping film pattern (114) may also be partially etched.

[0118] The second opening (204) can be formed to overlap vertically with the gate structure (116). Afterward, the etching mask pattern (202) can be removed.

[0119] Referring to FIG. 24, a barrier insulating film (206) is formed conformally on the buried insulating film (200), the second capping film pattern (140a), and the third spacer film (161). That is, the barrier insulating film (206) can be formed conformally along the surface of the second opening (204). The barrier insulating film (206) can be formed through a deposition process. In an exemplary embodiment, the barrier insulating film (206) can be formed by an atomic layer stacking method or a chemical vapor deposition method.

[0120] The barrier insulating film (206) may include a material having a higher bandgap than the fence insulating film material formed in a subsequent process. For example, the barrier insulating film (206) may include aluminum nitride, silicon oxide, aluminum oxide, aluminum oxynitride, silicon oxynitride, BN, etc.

[0121] Referring to FIG. 25, a fence insulating film is formed on the barrier insulating film (206) to fill the second opening (204). The fence insulating film may include, for example, silicon nitride.

[0122] Afterward, the fence insulation film and barrier insulation film (206) are flattened so that the upper surface of the buried insulation film (200) and the second capping film pattern (140a) is exposed, thereby forming a fence insulation structure (210) including a barrier insulation pattern (206a) and a fence insulation pattern (208) inside the second opening (204). Accordingly, the buried insulation film (200) may have a pattern shape isolated by the bit line structure (150) and the fence insulation structure (210).

[0123] Referring to FIG. 26, the buried insulating film (200) is removed to form a preliminary contact hole. Afterward, the third spacer film (161) exposed by the preliminary contact hole and the active pattern (106) below it are further etched. In the etching process, the upper portion of the device isolation pattern (104) adjacent to the active pattern (106) may also be partially etched. Additionally, a third spacer (160 c) is formed.

[0124] Accordingly, a contact hole (212) isolated by the bit line structure (150) and the fence insulation structure (210) is formed. An active pattern (106) may be exposed on the bottom surface of the contact hole (212). The process of removing the buried insulating film (200) may include a wet etching process.

[0125] Referring to FIG. 27, a contact plug structure (194) is formed within the contact hole (212). The contact plug structure (194) may include metal and / or polysilicon.

[0126] For example, a lower contact plug (170b) is formed by forming a conductive film to fill the contact hole (212) and removing the upper portion of the conductive film. The lower contact plug (170b) may include polysilicon. An upper contact plug (190) including metal is formed on the lower contact plug (170b). For example, the upper contact plug (190) may be formed in the same manner as described with reference to FIG. 18.

[0127] Afterwards, a capacitor (198) is formed in contact with the upper surface of the contact plug structure (194).

[0128] By performing the above processes, the semiconductor device can be manufactured.

[0129] FIGS. 28 to 32 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

[0130] The manufacturing method of the above semiconductor device includes processes that are substantially identical or similar to the processes described with reference to FIGS. 22 to 27, so a redundant description thereof is omitted. The manufacturing method below forms a contact plug structure after first forming a fence insulation structure. In addition, when forming the fence insulation structure, a barrier insulation pattern is formed after first forming a fence insulation pattern.

[0131] Referring to FIG. 28, processes substantially identical or similar to those described with reference to FIGS. 4 through 8 are performed. Afterward, the same process as described with reference to FIGS. 22 and FIG. 23 is performed.

[0132] A fence insulating film is formed on the above-mentioned buried insulating film (200), the second capping film pattern (140a), and the third spacer film (161) to completely fill the second opening (204). The fence insulating film may include, for example, silicon nitride.

[0133] Afterward, the fence insulation film is flattened so that the upper surface of the buried insulation film (200) and the second capping film pattern (140a) is exposed, thereby forming a fence insulation pattern (208) inside the second opening (204). In this way, the fence insulation pattern (208) can be formed first before forming the barrier insulation film.

[0134] The above buried insulating film (200) may have a pattern shape isolated by the bit line structure (150) and the fence insulating pattern (208).

[0135] Referring to FIG. 29, the buried insulating film (200) is removed to form a preliminary contact hole (230) isolated by the bit line structure (150) and the fence insulating pattern (208). The process of removing the buried insulating film (200) may include a wet etching process.

[0136] When the above process is performed, some sidewalls of the fence insulation pattern (208) may be exposed to the outside. That is, the sidewall facing the first direction of the fence insulation pattern (208) may be exposed to the outside. Meanwhile, the sidewall facing the second direction of the fence insulation pattern (208) may come into contact with the bit line structure (150).

[0137] Referring to FIG. 30, a barrier insulating film (220) is formed conformally on the exposed sidewall and top surface of the fence insulating pattern (208), the surface of the preliminary contact hole (230), and the top surface of the bit line structure (150). The barrier insulating film (220) can be formed through a deposition process. In an exemplary embodiment, the barrier insulating film (220) can be formed by an atomic layer stacking method or a chemical vapor deposition method.

[0138] For example, the barrier insulating film (220) may be aluminum nitride, silicon oxide, aluminum oxide, aluminum oxynitride, silicon oxynitride, BN, etc.

[0139] Referring to FIG. 31, a barrier insulating film (220) located on the bottom surface of the preliminary contact hole (230) is removed through anisotropic etching. In the etching process, the barrier insulating film (220) on the upper surface of the fence insulating pattern (208) and the upper surface of the bit line structure (150) can also be removed together.

[0140] Accordingly, a barrier insulation pattern (220a) is formed to cover a portion of the sidewall of the fence insulation pattern (208). That is, the barrier insulation pattern (220a) may be formed to cover the sidewall facing the first direction of the fence insulation pattern (208). Meanwhile, the barrier insulation pattern (220a) may be formed to surround the sidewall of the preliminary contact hole (230).

[0141] Afterward, the third spacer film (161) on the bottom surface of the preliminary contact hole (230) and the active pattern (106) below it are additionally etched. In the etching process, the upper portion of the device isolation pattern (104) adjacent to the active pattern (106) may also be partially etched. Thus, a contact hole (230a) isolated by the bit line structure (150) and the fence insulation pattern (208) is formed.

[0142] Referring to FIG. 32, a contact plug structure (194) is formed within the contact hole (230a). The contact plug structure (194) may include metal and / or polysilicon. For example, the contact plug structure (194) can be formed by performing the same process as described with reference to FIG. 27.

[0143] Afterwards, a capacitor (198) is formed in contact with the upper surface of the contact plug structure (194).

[0144] By performing the above processes, the semiconductor device can be manufactured. The semiconductor device manufactured through the process described with reference to FIGS. 28 to 32 may have a structure somewhat different from the semiconductor device illustrated in FIGS. 1 to 3. The fence insulation pattern of the semiconductor device may have a structure different from the fence insulation pattern of the semiconductor device illustrated in FIGS. 1 to 3. The structural features of the semiconductor device will be briefly described below.

[0145] FIG. 33 is a plan view of the semiconductor device. FIG. 34 is an enlarged plan view of a portion of the semiconductor device.

[0146] Specifically, FIG. 34 shows only the contact plug structure, fence insulation pattern, and barrier insulation pattern.

[0147] Referring to FIGS. 32 to 34, in the semiconductor device, the barrier insulation pattern (220a) may not cover the entire sidewall of the fence insulation pattern (208). The barrier insulation pattern (220a) may cover the sidewall facing the first direction of the fence insulation pattern (208). Additionally, the barrier insulation pattern (220a) may not be formed on the lower surface of the fence insulation pattern (208).

[0148] A barrier insulation pattern (220a) is provided on the side wall of the contact hole (230a) for forming the contact plug structure (194). Therefore, the barrier insulation pattern (220a) may have a shape that surrounds the contact plug structure (194).

[0149] FIGS. 35 and 36 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

[0150] The manufacturing method of the semiconductor device described above includes processes that are substantially identical or similar to those described with reference to FIGS. 28 to 32, so a redundant description thereof is omitted. The manufacturing method below forms a contact plug structure after first forming a fence insulation structure. In addition, when forming the fence insulation structure, a barrier insulation pattern is formed after first forming a fence insulation pattern.

[0151] Referring to FIG. 35, substantially identical or similar processes are performed to those described with reference to FIG. 28 and FIG. 29.

[0152] Afterward, aluminum is doped onto the exposed sidewalls and top surface of the fence insulation pattern (208). Thus, a barrier insulation film (222) is formed on at least some of the sidewalls and top surface of the fence insulation pattern (208). In this case, the barrier insulation film (222) may be aluminum-doped silicon nitride.

[0153] Meanwhile, since the aluminum is also doped into the inner surface of the preliminary contact hole (230), the barrier insulating film (222) can also be formed on the surface of the preliminary contact hole (230). That is, the barrier insulating film (222) can also be formed on the surface of the third spacer film (161) exposed by the preliminary contact hole (230). However, depending on the material of the third spacer film (161), the barrier insulating film (222) may not be formed on the surface of the third spacer film (161).

[0154] In some exemplary embodiments, the exposed sidewalls and top surfaces of the fence insulation pattern (208) are oxidized to form a barrier insulation film (222). In this case, the barrier insulation film (222) may be silicon oxide. Meanwhile, in the oxidation process, the surface of the third spacer film (161) exposed by the preliminary contact hole (230) may also be partially oxidized, and in this case, the barrier insulation film may also be formed on the surface of the third spacer film (161).

[0155] In some exemplary embodiments, aluminum is doped into the exposed sidewalls and top surfaces of the fence insulation pattern (208) and then oxidized to form a barrier insulation film (222). In this case, the barrier insulation film (222) may be aluminum-doped silicon oxynitride.

[0156] In this way, after first forming the fence insulation pattern (208), the barrier insulation film (222) can be formed by doping impurities into the exposed surface of the fence insulation pattern (208) or by performing an oxidation process.

[0157] Referring to FIG. 36, a barrier insulating film (222) located on the bottom surface of the preliminary contact hole (230) is removed through anisotropic etching. In the etching process, the barrier insulating film (222) on the upper surface of the fence insulating pattern (208) and the upper surface of the bit line structure (150) can also be removed together.

[0158] Accordingly, a barrier insulation pattern (220a) is formed to cover a portion of the sidewall of the fence insulation pattern (208). That is, the barrier insulation pattern (220a) may be formed to cover the sidewall facing the first direction of the fence insulation pattern (208). In an exemplary embodiment, the barrier insulation pattern (220a) may be formed to surround the sidewall of the preliminary contact hole (230).

[0159] Afterwards, the third spacer film (161) within the preliminary contact hole (230) and the upper portion of the device isolation pattern (104) adjacent to the active pattern (106) may also be partially etched. Thus, a contact hole (230a) isolated by the bit line structure (150) and the fence insulation pattern (208) is formed.

[0160] In the case of a semiconductor device formed through the above process, the barrier insulation pattern included in the fence insulation structure may cover the side wall facing the first direction of the fence insulation pattern. The barrier insulation pattern may not be formed on the lower surface of the fence insulation pattern.

[0161] Afterwards, the semiconductor device can be formed by performing the same process described with reference to FIG. 32.

[0162] The fence insulation structure included in the above semiconductor device may have various stacked structures including a barrier insulation pattern and a fence insulation pattern. An example of the structure of the fence insulation structure is described below.

[0163] FIG. 37 is an enlarged plan view of a portion of a semiconductor device according to an exemplary embodiment. FIG. 38 is a cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0164] Referring to FIGS. 37 and 38, the fence insulation structure (300) may include a first barrier insulation pattern (302a), a fence insulation pattern (304), and a second barrier insulation pattern (302b). The first barrier insulation pattern (302a) and the fence insulation pattern (304) may be conformally formed along the surface of the opening between the bit line structures (150) and the contact plug structures (194), and the second barrier insulation pattern (302b) may fill the inside of the opening.

[0165] FIG. 39 is an enlarged plan view of a portion of a semiconductor device according to an exemplary embodiment. FIG. 40 is a cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0166] Referring to FIGS. 39 and 40, the fence insulation structure (300a) may include a first fence insulation pattern (304a), a barrier insulation pattern (302), and a second fence insulation pattern (304b). The first fence insulation pattern (304a) and the barrier insulation pattern (302) may be conformally formed along the surface of the opening between the bit line structures (150) and the contact plug structures (194), and the second fence insulation pattern (304b) may fill the inside of the opening.

[0167] FIG. 41 shows the energy levels of the contact plug structure and the fence insulation structure in a semiconductor device according to an exemplary embodiment.

[0168] In FIG. 41, reference numeral 10 is the energy level of an electron, and reference numeral 12 is the energy level of a hole.

[0169] In FIG. 41, different voltages may be applied to each contact structure adjacent to each other. For example, when different data is written to each DRAM cell including the contact structure, different voltages may be applied to each contact structure.

[0170] In FIG. 41, the contact plug structure (194) / fence insulation structure (184) / contact plug structure (194) is arranged in a first direction, and when viewed in a cross-sectional view cut in the first direction, the contact plug structure (194), barrier insulation pattern (180a), fence insulation pattern (182a), barrier insulation pattern (180a), and contact plug structure (194) may have an arranged structure.

[0171] Referring to FIG. 41, the band gap of the energy level of the hole is greatly increased in the barrier insulation pattern (180a). In addition, the band gap of the energy level of the electron is also increased in the barrier insulation pattern (180a).

[0172] With the above barrier insulation pattern (180a) provided, the tunneling of electrons and holes can be reduced. In particular, the tunneling of holes can be reduced. Accordingly, the failure of leakage current occurring between contact plug structures (194) due to the tunneling of electrons and holes in the fence insulation structure (184) can be reduced.

[0173] As explained, the semiconductor device can reduce leakage current between contact plug structures, and accordingly, the semiconductor device can have excellent electrical characteristics. Explanation of the symbols

[0174] 100 : Substrate 106 : Active pattern 116 : Gate structure 150 : Bit line structure 160: Spacer structure 194: Contact plug structure 180a: Barrier insulation pattern 182a: Fence insulation pattern 184 : Fence insulation structure 198 : Capacitor

Claims

Claim 1 A semiconductor device comprising: contact plug structures spaced apart from each other in a first direction on a substrate; and a fence insulation structure disposed to fill the space between the first directions of the contact plug structures and insulates the contact plug structures from each other, and comprising a barrier insulation pattern and a fence insulation pattern, wherein the fence insulation structure comprises an insulating material having an etch selectivity ratio with silicon oxide, and the barrier insulation pattern comprises a material having a bandgap higher than that of the fence insulation pattern, and in contact with at least a sidewall facing the first direction of the fence insulation pattern and a part of the sidewall of the contact plug structure. Claim 2 In claim 1, the barrier insulation pattern comprises a semiconductor device having a material with a higher bandgap than silicon nitride. Claim 3 In claim 1, the barrier insulation pattern comprises a semiconductor device including aluminum nitride, silicon oxide, aluminum oxide, aluminum oxynitride, silicon oxynitride, or BN. Claim 4 In claim 1, the barrier insulation pattern comprises a semiconductor device including aluminum-doped silicon nitride or aluminum-doped silicon oxynitride. Claim 5 In claim 1, the fence insulation pattern is a semiconductor device comprising silicon nitride, SiOCN, BN, or SiOC. Claim 6 In claim 1, the fence insulation structure is provided inside the opening between the contact plug structures, the barrier insulation pattern is provided along the sidewall and bottom surface of the opening, and the fence insulation pattern fills the opening on the barrier insulation pattern. Claim 7 In claim 1, the semiconductor device having a shape in which the barrier insulation pattern surrounds the sidewalls and bottom surfaces of the fence insulation pattern. Claim 8 delete Claim 9 In claim 1, the barrier insulation pattern is a semiconductor device surrounding the sidewall of the contact plug structure. Claim 10 A semiconductor device according to claim 1, wherein bit line structures are further provided on the substrate, extending in the first direction and spaced apart in the second direction perpendicular to the first direction, and the contact plug structures and fence insulation structures are disposed between the bit line structures.

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