Display device

Abstract

A display device comprises a first substrate, a circuit element layer including insulating layers and a transistor, a pixel defining film having an opening, a first electrode exposed by the opening, a second electrode and a light-emitting layer disposed between the first and second electrodes, a display element layer including a partition portion disposed on the circuit element layer and overlapping with the surrounding area, a second substrate disposed on the display element layer, a sealing material overlapping with the surrounding area, and a filling material disposed in the internal space, wherein a recess overlapping with the surrounding area is defined on the back surface of the second substrate facing the display element layer, and a portion of the filling material is disposed in the recess.

Description

Technology Field

[0001] The present invention relates to a display device, and more specifically, aims to provide a display device in which the bonding force between a sensing panel and a display panel is improved and the display quality is improved. Background Technology

[0002] Electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions that provide images to users include a display device for displaying images. The display device generates images and provides images to users through a display screen. The display device may be provided in a state where an upper substrate and a lower substrate are bonded together by a seal. The problem to be solved

[0003] The object of the present invention is to provide a display device with improved adhesion between substrates. Accordingly, the invention provides a display device with improved durability. means of solving the problem

[0004] A display device according to one embodiment comprises: a first substrate including an active area and a peripheral area adjacent to the active area; a circuit element layer including a plurality of insulating layers and at least one transistor; a pixel defining film having an opening defined therein and disposed on the circuit element layer and overlapping with the active area; a light-emitting element including a first electrode, a second electrode, and a light-emitting layer disposed between the first and second electrodes, at least a portion of which is exposed by the opening; a display element layer including a partition portion disposed on the circuit element layer and overlapping with the peripheral area; a second substrate disposed on the display element layer; a sealing material disposed between the circuit element layer and the second substrate to define an internal space and overlapping with the peripheral area; and a filling material disposed in the internal space. A recessed portion overlapping with the peripheral area is defined on the back surface of the second substrate facing the display element layer, and a portion of the filling material is disposed in the recessed portion.

[0005] It may be characterized by being adjacent to the active area in the order of the recess, the partition, and the sealing material on a plane.

[0006] The second electrode may be characterized by overlapping with the active region and the surrounding region, and covering the partition portion.

[0007] It may further include an upper organic layer disposed on the second electrode and overlapping with the active region and the surrounding region, wherein the upper organic layer is in contact with the filler.

[0008] The upper organic layer overlapping with the above partition may be characterized by being in contact with the above back surface.

[0009] The above-mentioned depressions may be provided in multiple numbers and may be characterized by being spaced apart and arranged in a direction away from the active area.

[0010] The above-mentioned recess may be defined as a first inner surface parallel to the above-mentioned back surface and a second inner surface connecting the first inner surface and the above-mentioned back surface, and the angle between the first inner surface and the second inner surface may be greater than a right angle.

[0011] The above bulkheads may be provided in multiple numbers and may be characterized by being spaced apart and arranged in a direction away from the active area.

[0012] Among the above insulating layers, the insulating layer overlapping the partition portion may be characterized by having a portion removed from the front surface facing the second substrate and a pattern portion defined overlapping the recessed portion.

[0013] It may further include a sub-wall portion disposed between the pixel definition film and the partition portion and overlapping with the surrounding area, and the valley area between the partition portion and the sub-wall portion may overlap with the depression portion.

[0014] In a planar view, the depression may be characterized as having a closed-line shape surrounding the active region.

[0015] In a planar view, the recessed portion may include short side patterns, each extending in a first direction and spaced apart from a second direction intersecting the first direction with the active area in between, and long side patterns, each extending in the second direction and spaced apart from the first direction with the active area in between, wherein the short side patterns and the long side patterns are spaced apart from each other at the corners of the active area.

[0016] The above-mentioned depression may include a plurality of patterns, and the patterns may be characterized by surrounding the active area and being spaced apart from each other.

[0017] The thickness of the above-mentioned depression may be characterized as being 5 µm or more to 20 µm or less.

[0018] The thickness of the above partition is 3 µm or more to 5 µm or less, the width of the above partition in one direction is 10 µm or more to 50 µm or less, and the width of the above recess in one direction is greater than the width of the above partition.

[0019] The sealing material may be characterized by comprising any one of silicone, epoxy, and acrylic-based thermosetting materials, and having a viscosity of 3,000 cps or more to 40,000 cps or less.

[0020] It may further include a floating pattern disposed on the same layer as any one of the electrodes included in the transistor and overlapping with the surrounding region, and the floating pattern may be characterized by contacting the sealing material.

[0021] A display device according to one embodiment of the present invention comprises: a first substrate including an active area and a peripheral area adjacent to the active area; a plurality of insulating layers disposed on the first substrate; a pixel defining film having an opening defined therein and overlapping with the active area; a first electrode disposed on the same layer as the pixel defining film and overlapping with the peripheral area and a partition portion, at least a portion of which is exposed by the opening; a second electrode and a light-emitting layer disposed between the first and second electrodes and a light-emitting element disposed on the first substrate; a second substrate having a recess defined therein and overlapping with the peripheral area and disposed on the light-emitting element; a sealing material disposed between one of the insulating layers and the second substrate and overlapping with the peripheral area to define an internal space; and a filling material disposed in the internal space, wherein, in a planar view, the recess, the partition portion, and the sealing material are adjacent to the active area in that order.

[0022] A display device in which the recess on a plane is a closed-line shape surrounding the active area.

[0023] The above-mentioned depression may be characterized by having a trapezoidal shape in cross-section. Effects of the invention

[0024] According to an embodiment of the present invention, by including a structure capable of delaying the time for the filler to move, time can be secured until the sealing material is completely cured, and accordingly, the bonding force between the substrates can be increased. Thus, a display device with improved durability can be provided. Brief explanation of the drawing

[0025] FIG. 1a is a combined perspective view of a display device according to one embodiment of the present invention. FIG. 1b is an exploded perspective view of a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of the active area of ​​a display panel according to one embodiment of the present invention. FIG. 4 is a plan view of a display panel according to one embodiment of the present invention. FIG. 5 is a plan view of a sensing panel according to one embodiment of the present invention. Figure 6 is a cross-sectional view taken along I-I' of Figure 1b. FIG. 7 is a plan view illustrating the arrangement relationship of a recess, a partition, and a sealing material according to one embodiment of the present invention. FIG. 8 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 9 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 10 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 11 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 12 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 13 is a plan view illustrating the arrangement relationship of a recess, a partition, and a sealing material according to one embodiment of the present invention. FIG. 14 is a plan view illustrating the arrangement relationship of a recess, a partition, and a sealing material according to one embodiment of the present invention. Specific details for implementing the invention

[0026] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0027] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And / or” includes all one or more combinations that the associated components may define.

[0028] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0029] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0030] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0032] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0034] FIG. 1a is an assembled perspective view of a display device according to an embodiment of the present invention. FIG. 1b is an exploded perspective view of a display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a display device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an active area of ​​a display panel according to an embodiment of the present invention. FIG. 4 is a plan view of a display panel according to an embodiment of the present invention. FIG. 5 is a plan view of a sensing panel according to an embodiment of the present invention.

[0035] Referring to FIGS. 1a and 1b, the display device (EA) may be a device that is activated according to an electrical signal. The display device (EA) may include various embodiments. For example, the display device (EA) may include a tablet, a laptop, a computer, a smart television, etc. In this embodiment, the display device (EA) is illustrated as a smartphone.

[0036] A display device (EA) can display an image (IM) through a display surface (FS). The display surface (FS) is parallel to the plane defined by the first direction (DR1) and the second direction (DR2). The normal direction of the display surface (FS), i.e., the thickness direction of the display device (EA), is indicated by the third direction (DR3). The front (or top) and back (or bottom) surfaces of each member or unit described below are distinguished by the third direction (DR3).

[0037] The display surface (FS) on which the image (IM) is displayed may correspond to the front surface of the display device (EA), and substantially the display surface (FS) of the display device (EA) may correspond to the front surface of the window member (100). Hereinafter, the display surface, the front surface of the display device (EA), and the front surface (FS) of the window member (100) will use the same reference numeral. In FIG. 1a, a clock and a plurality of icons are shown as examples of the image (IM).

[0038] The display device (EA) includes a window member (100) and an electronic panel (200). Although not separately illustrated, the display device (EA) may further include an optical member disposed between the window member (100) and the electronic panel (200). The optical member may include a polarizer. The optical member may include a color filter member that reduces external light reflectivity.

[0039] The window member (100) includes a base panel. For example, the base panel may be composed of glass, plastic, or a combination thereof. The front surface (FS) of the window member (100) includes a transparent area (TA) and a bezel area (BZA). The transparent area (TA) may be an optically transparent area. For example, the transparent area (TA) may be an area with a visible light transmittance of about 90% or more.

[0040] The bezel area (BZA) may be an area with a relatively lower light transmittance compared to the transmission area (TA). The bezel area (BZA) defines the shape of the transmission area (TA). The bezel area (BZA) is adjacent to the transmission area (TA) and may surround the transmission area (TA). The window member (100) may further include a colored light-blocking pattern that is placed on the base panel and defines the bezel area (BZA).

[0041] The bezel area (BZA) may have a predetermined color. The bezel area (BZA) may cover the surrounding area (NAA) of the electronic panel (200) to block the surrounding area (NAA) from being visible from the outside. Meanwhile, this is illustrated as an example, and in the window member (100) according to one embodiment of the present invention, the bezel area (BZA) may be omitted.

[0042] The electronic panel (200) can display an image (IM) and detect an external input (TT). The image (IM) can be displayed on the front (FS) of the electronic panel (200). The front (FS) of the electronic panel (200) includes an active area (AA) and a peripheral area (NAA). The active area (AA) may be an area that is activated according to an electrical signal.

[0043] In the present embodiment, the active area (AA) is an area where an image (IM) is displayed and may simultaneously be an area where an external input (TT) is detected. The active area (AA) corresponds to the transmission area (TA), and the peripheral area (NAA) corresponds to the bezel area (BZA). In this specification, "area / part corresponds to area / part" means "overlaps with each other" and is not limited to having the same area and / or the same shape.

[0044] The electronic panel (200) includes a display panel (210), a sensing panel (220), a driving circuit (DIC), and a circuit module (FTC).

[0045] The display panel (210) substantially generates an image (IM). The display panel (210) may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The panels are distinguished according to the constituent material of the light-emitting element. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods, etc. Hereinafter, the display panel (210) is described as an organic light-emitting display panel.

[0046] The sensing panel (220) detects an external input (e.g., a touch event) applied from the outside. In this embodiment, the sensing panel (220) may be capacitive and is not particularly limited.

[0047] The driving circuit (DIC) is placed on the display panel (210). The driving circuit (DIC) may be mounted on the display panel (210). The driving circuit (DIC) is electrically connected to the display panel (210) and provides an electrical signal to the display panel (210) to drive the display panel (210).

[0048] The circuit module (FTC) is electrically connected to the sensing panel (220). In this embodiment, the circuit module (FTC) may include a flexible circuit board (CF) and a sensing driving circuit (TIC). The flexible circuit board (CF) includes wiring not illustrated. The wiring electrically connects the sensing panel (220) and the sensing driving circuit (TIC). The sensing driving circuit (TIC) may be provided mounted on the flexible circuit board (CF) in the form of a chip-on-film.

[0049] The circuit module (FTC) can connect the sensing panel (220) and the display panel (210). The sensing driving circuit (TIC) may be omitted. The sensing driving circuit (TIC) and the driving circuit (DIC) may be integrated.

[0050] Referring to FIG. 2, the display panel (210) may include a first substrate (SUB1), a circuit element layer (DP-CL), a display element layer (DP-OL), a second substrate (SUB2), a sealing material (SAL), and a filler material (FL). The sensing panel (220) may be placed on the second substrate (SUB2).

[0051] The first substrate (SUB1) may include an active region (AA) and a peripheral region (NAA) adjacent to the active region (AA). The display element layer (DP-OL) may overlap with the active region (AA). In this embodiment, the first substrate (SUB1) may be of a rigid type. For example, the first substrate (SUB1) may include a glass substrate, a metal substrate, a polymer substrate, or an organic / inorganic composite material substrate.

[0052] A circuit element layer (DP-CL) is disposed on a first substrate (SUB1). The circuit element layer (DP-CL) includes at least one insulating layer and a circuit element. The insulating layer includes at least one inorganic film and at least one organic film. The circuit element includes a signal line, a pixel driving circuit, etc. The circuit element layer (DP-CL) can be formed through a process of forming an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc., and a patterning process of an insulating layer, a semiconductor layer, and a conductive layer by photolithography.

[0053] Referring to FIG. 3, a pixel according to the present invention may be defined as including a transistor (TR) and a light-emitting element (OLED). The light-emitting element (OLED) may include a first electrode (AE) (or anode), a second electrode (CE) (or cathode), and a light-emitting layer (EL). A light-emitting element (OLED) according to one embodiment may further include a hole control layer disposed between the first electrode (AE) and the light-emitting layer (EL), and an electronic control layer disposed between the light-emitting layer (EL) and the second electrode (CE).

[0054] A transistor (TR) and a light-emitting element (OLED) may be disposed on a first substrate (SUB1). Although one transistor (TR) is illustrated as an example, substantially, the pixel (PX) may include a plurality of transistors and at least one capacitor for driving the light-emitting element (OLED).

[0055] The active area (AA) may include a light-emitting area (LA) corresponding to each pixel and a non-light-emitting area (NLA) surrounding the light-emitting area (LA).

[0056] A buffer layer (BFL) is disposed on a first substrate (SUB1), and the buffer layer (BFL) may be an inorganic layer. A semiconductor pattern may be disposed on the buffer layer (BFL). The semiconductor pattern may include polysilicon, amorphous silicon, or a metal oxide.

[0057] The semiconductor pattern can be doped with an N-type dopant or a P-type dopant. The semiconductor pattern may include a high-doping region and a low-doping region. The conductivity of the high-doping region is greater than that of the low-doping region and can substantially serve as the source and drain electrodes of the transistor (TR). The low-doping region can substantially correspond to the active (or channel) of the transistor.

[0058] The source (S), active (A), and drain (D) of the transistor (TR) can be formed from a semiconductor pattern. A first insulating layer (INS1) can be disposed on the semiconductor pattern. The gate (G) of the transistor (TR) can be disposed on the first insulating layer (INS1). A second insulating layer (INS2) can be disposed on the gate (G). A third insulating layer (INS3) can be disposed on the second insulating layer (INS2).

[0059] The connecting electrode (CNE) may include a first connecting electrode (CNE1) and a second connecting electrode (CNE2) for connecting a transistor (TR) and a light-emitting element (OLED). However, either the first connecting electrode (CNE1) or the second connecting electrode (CNE2) may be omitted. The first connecting electrode (CNE1) is disposed on a third insulating layer (INS3) and may be connected to a drain (D) through a first contact hole defined in the first to third insulating layers (INS1~INS3).

[0060] A fourth insulating layer (INS4) may be disposed on a first connecting electrode (CNE1). A fifth insulating layer (INS5) may be disposed on the fourth insulating layer (INS4). A second connecting electrode (CNE2) may be disposed on the fifth insulating layer (INS5). The second connecting electrode (CNE2) may be connected to the first connecting electrode (CNE1) through a second contact hole defined in the fourth and fifth insulating layers (INS4, INS5).

[0061] A sixth insulating layer (INS6) may be disposed on the second connecting electrode (CNE2). The layers from the buffer layer (BFL) to the sixth insulating layer (INS6) may be defined as circuit element layers (DP-CL). The first insulating layer to the sixth insulating layer (INS1 to INS6) may be inorganic layers or organic layers.

[0062] The display element layer (DP-OL) may include a light-emitting element (OLED), a pixel defining layer (PDL), and a partition portion (SPC, see FIG. 6) described later.

[0063] A light-emitting element (OLED) may include a first electrode (AE), a second electrode (CE), and a light-emitting layer (EL). The first electrode (AE) may be disposed on a sixth insulating layer (INS6). The first electrode (AE) may be connected to a second connecting electrode (CNE2) through a third contact hole defined in the sixth insulating layer (INS6). A pixel defining film (PDL) may be disposed on the first electrode (AE) and the sixth insulating layer (INS6), having an opening (OP) defined to expose a predetermined portion of the first electrode (AE). In this embodiment, the light-emitting region (LA) may correspond to the area of ​​the first electrode (AE) exposed by the opening (OP), and the non-light-emitting region (NLA) may correspond to the area overlapping with the pixel defining film (PDL).

[0064] The light-emitting layer (EL) may be disposed on the first electrode (AE). The light-emitting layer (EL) may be disposed in an area corresponding to the opening (OP). The light-emitting layer (EL) may include organic and / or inorganic materials. The light-emitting layer (EL) may generate any one of red, green, and blue light.

[0065] The second electrode (CE) can be placed on the light-emitting layer (EL). The second electrode (CE) can be placed in common across the pixels. Thus, the second electrode (CE) can be placed across the entire surface of the light-emitting region (LA) and the non-light-emitting region (NLA). In this embodiment, the layer on which the light-emitting element (OLED) is placed can be defined as the display element layer (DP-OL).

[0066] A first voltage can be applied to a first electrode (AE) through a transistor (TR), and a second voltage can be applied to a second electrode (CE). Holes and electrons injected into the light-emitting layer (EL) combine to form excitons, and as the excitons transition to a ground state, the light-emitting element (OLED) can emit light.

[0067] A display element layer (DP-OL) according to one embodiment of the present invention may further include an upper organic layer (CPL). The upper organic layer (CPL) covers a second electrode (CE) and may be disposed across the entire surface of the light-emitting region (LA) and the non-light-emitting region (NLA) together with the second electrode (CE). The upper organic layer (CPL) may include an organic material and may have a thickness greater than the thickness of the second electrode (CE).

[0068] The filler material (FL) can be disposed on the display element layer (DP-OL) to cover the pixel. The filler material (FL) can be in contact with the upper organic layer (CPL) and the back surface of the second substrate (SUB2). In this specification, "the back surface of the second substrate (SUB2)" may be defined as the surface of the second substrate (SUB2) facing the display element layer (DP-OL). The second substrate (SUB2) may be disposed on the filler material (FL).

[0069] The second substrate (SUB2) is positioned opposite the first substrate (SUB1) to cover the display element layer (DP-OL). According to one embodiment, the second substrate (SUB2) may be an encapsulation substrate. The second substrate (SUB2) may include a glass substrate, a metal substrate, a polymer substrate, or an organic / inorganic composite material substrate.

[0070] Referring again to FIG. 2, a sealing material (SAL) is disposed between the second substrate (SUB2) and the first substrate (SUB1). The sealing material (SAL) is disposed on the circuit element layer (DP-CL) and may overlap with the surrounding region (NAA). The sealing material (SAL) may have a closed-loop shape that surrounds the active region (AA) in a planar shape. The first substrate (SUB1) and the second substrate (SUB2) can be bonded together using the sealing material (SAL). The sealing material (SAL) may include a thermosetting material or a photosetting material. However, the material of the sealing material (SAL) is not limited to the above examples.

[0071] The filler (FL) may be filled into the internal space defined by the first substrate (SUB1), the second substrate (SUB2), and the sealing material (SAL). The filler (FL) may include a silicone, epoxy, or acrylic-based thermosetting material. In this embodiment, the viscosity of the filler (FL) may be 3,000 cps or more and 40,000 cps or less.

[0072] After forming a circuit element layer (DP-CL) and a display element layer (DP-OL) on the first substrate (SUB1), a process is performed to bond the sealing material (SAL) and the filler material (FL) attached to the second substrate (SBU2) to the first substrate (SUB1). At this time, the sealing material (SAL) can be cured by irradiating it with a laser beam. During the process of curing the sealing material (SAL), the filler material (FL) can be filled into the internal space by moving from the active region (AA) toward the peripheral region (NAA) between the display element layer (DP-OL) and the second substrate (SUB2). If the filler material (FL) comes into contact with the sealing material (SAL) before the sealing material (SAL) is cured, a problem of the sealing material (SAL) peeling off occurs. Consequently, the bonding strength between the display element layer (DP-OL) and the second substrate (SUB2) may be reduced.

[0073] Referring to FIG. 4, the display panel (210) may include a driving circuit (GDC), a plurality of signal lines (SGL), and a plurality of pixels (PX).

[0074] The driving circuit (GDC) may include a scanning driving circuit. The scanning driving circuit generates multiple scanning signals and sequentially outputs the scanning signals to multiple scanning lines (GL) described below. The scanning driving circuit may further output another control signal to the driving circuit of the pixels (PX).

[0075] The scanning driving circuit may include a plurality of transistors formed through the same process as the driving circuit of the pixels (PX), such as the LTPS (Low Temperature Polycrystalline Silicon) process or the LTPO (Low Temperature Polycrystalline Oxide) process.

[0076] The signal lines (SGL) include scan lines (GL), data lines (DL), power lines (PL), and control signal lines (CSL). Each of the scan lines (GL) is connected to a corresponding pixel (PX) among the pixels (PX), and each of the data lines (DL) is connected to a corresponding pixel (PX) among the pixels (PX). The power line (PL) is connected to the pixels (PX). The control signal line (CSL) can provide control signals to the scan driving circuit.

[0077] Data lines (DL), power lines (PL), and control signal lines (CSL) can be connected to corresponding pads among the display pads (D-PD) placed in the peripheral area (NAA). The display pads (D-PD) can be connected to a driving circuit (DIC, see FIG. 1b).

[0078] Referring to FIG. 5, a sensing panel (220) is placed on a second substrate (SUB2). The sensing panel (220) may include a plurality of sensing electrodes (SE1, SE2) and a plurality of signal lines (SL1, SL2, SL3) connected to the plurality of sensing electrodes (SE1, SE2).

[0079] Sensing electrodes (SE1, SE2) are placed in an active area (AA). The sensing electrodes (SE1, SE2) may include a plurality of first sensing electrodes (SE1) and a plurality of second sensing electrodes (SE2) that intersect each other. Each of the first sensing electrodes (SE1) may extend along a first direction (DR1) and be arranged along a second direction (DR2). Each of the first sensing electrodes (SE1) may include a plurality of first sensing portions (SP1) and a plurality of intermediate portions (BP1) arranged along the first direction (DR1). At least one intermediate portion may be placed between adjacent first sensing portions.

[0080] Each of the second sensing electrodes (SE2) extends along the second direction (DR2) and may be arranged along the first direction (DR1). Each of the second sensing electrodes (SE2) may include a plurality of second sensing portions (SP2) and a plurality of bridges (BP2) arranged along the second direction (DR2). The bridges (BP2) may be disposed on a different layer from the second sensing portions (SP2).

[0081] Signal lines (SL1, SL2, SL3) are placed in the surrounding area (NAA). The signal lines (SL1, SL2, SL3) include a plurality of first signal lines (SL1), a plurality of second signal lines (SL2), and a plurality of third signal lines (SL3).

[0082] The first signal lines (SL1) are each connected to one end of the two ends of the first sensing electrodes (SE1). The second signal lines (SL2) are each connected to one end of the two ends of the second sensing electrodes (SE2). The third signal lines (SL3) are each connected to the other end of the two ends of the second sensing electrodes (SE2). The connection relationship between the sensing electrodes (SE1, SE2) and the signal lines (SL1, SL2, SL3) is not limited thereto.

[0083] The signal lines (SL1, SL2, SL3) can be connected to corresponding pads among the sensing pads (T-PDs) placed in the surrounding area (NAA). A circuit module (FTC, see FIG. 1b) can be connected to the sensing pads (T-PDs).

[0084] FIG. 6 is a cross-sectional view taken along I-I' of FIG. 1b. FIG. 7 is a plan view illustrating the arrangement relationship of a depression, a partition, and a sealing material according to an embodiment of the present invention.

[0085] The circuit element layer (DP-CL) of the display panel (210) according to the present embodiment may further include a floating pattern (FE). The floating pattern (FE) is placed on the third insulating layer (INS3) and may overlap with the surrounding area (NAA). A portion of the floating pattern (FE) may be in contact with the sealing material (SAL).

[0086] The floating pattern (FE) may be placed on the same layer as any one of the electrodes of the transistor (TR, see FIG. 4). The floating pattern (FE) may comprise a metal or an alloy. FIG. 6 illustrates an exemplary floating pattern (FE) placed on a third insulating layer (INS3), but the location of the floating pattern (FE) is not limited thereto. The floating pattern (FE) may be in a floating state with respect to the transistor (TR, see FIG. 4).

[0087] As the floating pattern (FE) includes a metal or alloy, it can increase the heat transfer efficiency applied to the sealing material (SAL) during the process of curing by irradiating the sealing material (SAL) with a laser beam. Therefore, the curing speed of the sealing material (SAL) can be improved.

[0088] A display element layer (DP-OL) according to one embodiment may include a barrier portion (SPC) and a sub-barrier portion (SPC-S). The barrier portion (SPC) and the sub-barrier portion (SPC-S) are disposed on the sixth insulating layer (INS6) and are disposed on the same layer as the pixel defining film (PDL), and may include the same material as the pixel defining film (PDL). Accordingly, the barrier portion (SPC) and the sub-barrier portion (SPC-S) may include an organic material. The barrier portion (SPC), the sub-barrier portion (SPC-S), and the pixel defining film (PDL) may be structures patterned in the same process.

[0089] According to the present embodiment, the pixel defining layer (PDL) is positioned within the active area (AA), and the barrier portion (SPC) and sub-barrier portion (SPC-S) may be positioned in the surrounding area (NAA). The sub-barrier portion (SPC-S) may be positioned relatively adjacent to the active area (AA) than the barrier portion (SPC). The area between the barrier portion (SPC) and the sub-barrier portion (SPC-S) may be defined as a valley area (VA).

[0090] The partition section (SPC), the sub-partition section (SPC-S), and the pixel definition film (PDL) can be covered by the second electrode (CE). The second electrode (CE) can be covered by the upper organic layer (CPL).

[0091] The filler (FL) can be placed in the internal space defined by the back surface (SB) of the second substrate (SUB2), the sealing material (SAL), and the display element layer (DP-OL).

[0092] In this embodiment, a recess (TC) may be defined on the back surface (SB) of the second substrate (SUB2). The recess (TC) may be defined by removing a portion of the second substrate (SUB2) in a direction from the back surface (SB) toward the upper surface facing the back surface (SB).

[0093] The depression (TC) may overlap with the surrounding region (NAA). The depression (TC) may overlap with the valley region (VA) between the partition (SPC) and the sub-partition (SPC-S). As a portion of the second substrate (SUB2) is removed, the space in the third direction (DR3) between the depression (TC) and the valley region (VA) can be secured to be wider than that of adjacent regions. In this embodiment, the cross-sectional shape of the depression (TC) may be rectangular. However, the cross-sectional shape of the depression (TC) is not limited thereto.

[0094] According to the present embodiment, the width (WD) in the first direction (DR1) of the partition (SPC) may be 10 µm or more and 50 µm or less, and the first thickness (TH1) in the third direction (DR3) of the partition (SPC) may be 3 µm or more and 5 µm or less. The width (WD) and the first thickness (TH1) of the partition (SPC) may be greater than the width and thickness of the sub-partition (SPC-S).

[0095] The second thickness (TH2) in the third direction (DR3) of the depression (TC) may be 5 µm or more and 20 µm or less. The width in the first direction (DR1) of the depression (TC) may be greater than the width (WD) of the partition (SPC).

[0096] Referring to FIG. 7, the recess (TC), the partition (SPC), and the sealing material (SAL) may be adjacent to the active area (AA) in that order on a plane. Although not shown, the sub-partition (SPC-S) may be positioned closer to the active area (AA) than the recess (TC). In this embodiment, the recess (TC), the partition (SPC), and the sealing material (SAL) may have a closed-line shape.

[0097] According to the present invention, by including a depression (TC) that overlaps with a peripheral area (NAA) in the second substrate (SUB2), the time for the filler (FL) to move from the active area (AA) to the peripheral area (NAA) during the process of curing the sealing material (SAL) can be delayed. For example, during the process of bonding the first substrate (SUB1) and the second substrate (SUB2), the filler (FL) can move in a direction toward the sealing material (SAL) after being filled in the depression (TC) and the valley area (VA) by passing through the area between the second substrate (SUB2) and the pixel definition film (PDL) and the area between the second substrate (SUB2) and the sub-partition (SPC-S). The direction of movement of the filler (FL) is illustrated by an arrow in FIG. 6.

[0098] At this time, as a wider space is formed between the depression (TC) and the valley region (VA) than between adjacent regions, the time for the filler (FL) to move and the time for filling the space may be delayed. Therefore, time can be secured until the sealing material (SAL) is completely cured, and accordingly, the bonding strength of the first substrate (SUB1), the circuit element layer (DP-CL), and the second substrate (SUB2) can be increased. Thus, a display device (EA, see FIG. 1a) with improved durability can be provided.

[0099] Again, referring to FIG. 6, a sensing panel (220) may be disposed on a second substrate (SUB2). The sensing panel may include a plurality of insulating layers (IOL, TC-IL1, TC-IL2) and conductive layers (MTL1, MTL2).

[0100] An insulating layer (IOL) may be disposed on the second substrate (SUB2). The insulating layer (IOL) may include an inorganic insulating layer. At least one insulating layer (IOL) may be provided on the second substrate (SUB2). For example, two inorganic insulating layers (IOL) may be sequentially stacked on the second substrate (SUB2).

[0101] A first conductive layer (MTL1) may be disposed on an insulating layer (IOL). A first insulating layer (TC-IL1) may be disposed on the first conductive layer (MTL1). The first insulating layer (TC-IL1) may be disposed on the insulating layer (IOL) to cover the first conductive layer (MTL1). The first insulating layer (TC-IL1) may include an inorganic insulating layer or an organic insulating layer. A second conductive layer (MTL2) may be disposed on the first insulating layer (TC-IL1). A second insulating layer (TC-IL2) may be disposed on the second conductive layer (MTL2) and the first insulating layer (TC-IL1). The second insulating layer (TC-IL2) may be disposed on the first insulating layer (TC-IL1) to cover the second conductive layer (MTL2). The second insulating layer (TC-IL2) may include an organic insulating layer.

[0102] The first conductive layer (MTL1) includes bridges (BP2) described in FIG. 5, and the bridges (BP2) can be connected to corresponding second sensing portions (SP2) through contact holes defined in the insulating layer (IOL). The second conductive layer (MTL2) may include first sensing portions (SP1), intermediate portions (BP1), and second sensing portions (SP2). The second conductive layer (MTL2) may include a plurality of mesh lines extending diagonally in each of the first direction (DR1) and the second direction (DR2), and the mesh lines may overlap with the pixel defining film (PDL) and be spaced apart from the opening (OP).

[0104] FIG. 8 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 9 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 11 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 12 is a cross-sectional view of a display panel according to an embodiment of the present invention. Identical or similar reference numerals are used for configurations identical or similar to those described in FIG. 1a to 7, and redundant descriptions are omitted. FIG. 8 to 12 may correspond to a cross-sectional view cut along I-I' in FIG. 1b.

[0105] Referring to FIG. 8, a display panel (210-A) according to one embodiment may include a first substrate (SUB1), a circuit element layer (DP-CL), a display element layer (DP-OL), and a second substrate (SUB2). A sensing panel (220) may be disposed on the second substrate (SUB2).

[0106] The portion of the upper organic layer (CPL) according to the present embodiment that overlaps with the partition portion (SPC) may come into contact with the back surface (SB) of the second substrate (SUB2). Accordingly, an empty space (SP) may be formed between the sealing material (SAL) and the partition portion (SPC).

[0107] According to the present embodiment, even if the curing of the sealing material (SAL) proceeds, the filler (FL) is filled only up to the space between the depression (TC) and the valley region (VA), and contact between the filler (FL) and the sealing material (SAL) can be prevented.

[0109] Referring to FIG. 9, a display panel (210-B) according to one embodiment may include a first substrate (SUB1), a circuit element layer (DP-CL), a display element layer (DP-OL), and a second substrate (SUB2). A sensing panel (220) may be disposed on the second substrate (SUB2).

[0110] A plurality of first to third recesses (TC1, TC2, TC3) may be defined in the second substrate (SUB2) according to the present embodiment. The first to third recesses (TC1, TC2, TC3) may be arranged far from the active region (AA) in that order. Each of the first to third recesses (TC1, TC2, TC3) may be spaced apart from one another.

[0111] Each of the first to third recesses (TC1, TC2, TC3) may be defined by removing a portion of the second substrate (SUB2) in a direction from the back surface (SB) of the second substrate (SUB2) toward the upper surface facing the back surface (SB). Each of the first to third recesses (TC1, TC2, TC3) may have a closed-line shape that surrounds the active region (AA) in a planar shape. The first recess (TC1) may surround the second recess (TC2), the second recess (TC2) may surround the third recess (TC3), and the third recess (TC3) may surround the active region (AA).

[0112] The number of depressions is not limited thereto and may be two or four or more, and is not limited to any one embodiment.

[0114] Referring to FIG. 10, a display panel (210-C) according to one embodiment may include a first substrate (SUB1), a circuit element layer (DP-CL), a display element layer (DP-OL), and a second substrate (SUB2). A sensing panel (220) may be disposed on the second substrate (SUB2).

[0115] A recess (TC-L) may be defined in the second substrate (SUB2) according to the present embodiment. The recess (TC-L) may be defined by removing a portion of the second substrate (SUB2) in a direction from the back surface (SB) of the second substrate (SUB2) toward the upper surface facing the back surface (SB).

[0116] The depression (TC-L) can be defined as a first inner surface (TU) parallel to the back surface (SB) and a second inner surface (TS) connecting the first inner surface (TU) and the back surface (SB). The depression (TC-L) may have a trapezoidal shape in cross-section. Accordingly, the angle (Θ) between the first inner surface (TU) and the second inner surface (TS) may be greater than a right angle.

[0118] Referring to FIG. 11, a display panel (210-D) according to one embodiment may include a first substrate (SUB1), a circuit element layer (DP-CL), a display element layer (DP-OL), and a second substrate (SUB2). A sensing panel (220) may be disposed on the second substrate (SUB2).

[0119] In this embodiment, the display element layer (DP-OL) may include a plurality of first to third partition portions (SPC1, SPC2, SPC3). The first to third partition portions (SPC1, SPC2, SPC3) may be arranged in order close to the active area (AA). The first to third partition portions (SPC1, SPC2, SPC3) are disposed on the sixth insulating layer (INS6) and may include the same material as the pixel defining film (PDL). Each of the first to third partition portions (SPC1, SPC2, SPC3) may be covered by a second electrode (CE).

[0121] Referring to FIG. 12, a display panel (210-E) according to one embodiment may include a first substrate (SUB1), a circuit element layer (DP-CL), a display element layer (DP-OL), and a second substrate (SUB2). A sensing panel (220) may be disposed on the second substrate (SUB2).

[0122] In this embodiment, a pattern portion (IC) may be defined in the sixth insulating layer (INS6) of the display element layer (DP-OL). The pattern portion (IC) may be formed by removing a portion of the sixth insulating layer (INS6) in the thickness direction. The pattern portion (IC) is positioned between the partition portion (SPC) and the sub-partition portion (SPC-S) and may overlap with the recess (TC). Accordingly, the space in the third direction (DR3) between the recess (TC) and the pattern portion (IC) can be secured to be wider than that of adjacent regions.

[0124] FIG. 13 is a plan view illustrating the arrangement relationship of a recess, a partition, and a sealing material according to an embodiment of the present invention. FIG. 14 is a plan view illustrating the arrangement relationship of a recess, a partition, and a sealing material according to an embodiment of the present invention. Identical or similar reference numerals are used for configurations identical or similar to those described in FIG. 1a to 7, and redundant descriptions are omitted.

[0125] Referring to FIG. 13, the active area (AA) can be adjacent to the recess (TC-1), the bulkhead (SPC), and the sealing material (SAL) in the order of planar.

[0126] In this embodiment, the recess (TC-1) may include a plurality of first to fourth patterns (T1, T2, T3, T4). The first pattern (T1) and the second pattern (T2) each extend in a second direction (DR2) and may be spaced apart from each other along the first direction (DR1) with an active region (AA) in between. The first pattern (T1) and the second pattern (T2) may be defined as "long side patterns".

[0127] The third pattern (T3) and the fourth pattern (T4) are each extended in the first direction (DR1) and can be spaced apart from each other along the second direction (DR2) with the active area (AA) in between. The third pattern (T3) and the fourth pattern (T4) can be defined as "short side patterns".

[0128] In this embodiment, each of the first to fourth patterns (T1, T2, T3, T4) may be spaced apart from each other. For example, each of the first to fourth patterns (T1, T2, T3, T4) extends along the long and short sides of the corresponding active area (AA), and each of the first to fourth patterns (T1, T2, T3, T4) may be spaced apart from each other at the corners of the active area (AA).

[0130] Referring to FIG. 14, the active area (AA) can be adjacent to the recesses (TC-2), bulkheads (SPC), and sealing material (SAL) in the order of planar.

[0131] In this embodiment, the depressions (TC-2) may be spaced apart along the first direction (DR1) and the second direction (DR2). The depressions (TC-2) may surround the active region (AA) and be spaced apart from each other.

[0133] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0134] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0135] EA: Display device 100: Window missing 210: Display panel 220: Detection panel DIC: Driving circuit FTC: Circuit module SUB1: First substrate SUB2: Second substrate SAL: Sealing material FL: Filler material FE: Floating Pattern SPC: Bulkhead SPC-S: Sub-bulkhead

Claims

Claim 1 A first substrate comprising an active region and a peripheral region adjacent to the active region; a circuit element layer comprising a plurality of insulating layers and at least one transistor; a light-emitting element comprising a pixel defining film having an opening defined therein and disposed on the circuit element layer and overlapping with the active region, a first electrode having at least a portion exposed by the opening, a second electrode, and a light-emitting layer disposed between the first and second electrodes, a partition portion disposed on the circuit element layer and overlapping with the peripheral region, and a sub-partition portion disposed between the pixel defining film and the partition portion and overlapping with the peripheral region; a second substrate disposed on the display element layer; and a sealing material disposed between the circuit element layer and the second substrate, defining an internal space and overlapping with the peripheral region. A display device comprising a filler material disposed in the internal space, wherein a recess is defined on the back surface of the second substrate facing the display element layer and the recess overlaps with the surrounding area, a valley area is defined between the partition wall and the sub-partition wall, a portion of the filler material is disposed in the recess, and the valley area overlaps with the recess. Claim 2 In claim 1, a display device adjacent to the active area in the order of the recess, the partition, and the sealing material on a plane. Claim 3 A display device according to claim 1, wherein the second electrode overlaps the active area and the surrounding area and covers the partition portion. Claim 4 A display device according to claim 3, further comprising an upper organic layer disposed on the second electrode and overlapping with the active region and the surrounding region, wherein the upper organic layer is in contact with the filler. Claim 5 In claim 4, the upper organic layer overlapping with the partition wall portion is a display device in contact with the back surface. Claim 6 A display device according to claim 1, wherein the recesses are provided in plurality and the recesses are spaced apart and arranged in a direction away from the active area. Claim 7 A display device according to claim 1, wherein the recess is defined as a first inner surface parallel to the back surface and a second inner surface connecting the first inner surface and the back surface, and the angle between the first inner surface and the second inner surface is greater than a right angle. Claim 8 A display device according to claim 1, wherein the partition members are provided in plurality and the partition members are spaced apart and arranged in a direction away from the active area. Claim 9 A display device according to claim 1, wherein among the insulating layers, the insulating layer overlapping the partition portion has a portion removed from the front surface facing the second substrate and a pattern portion overlapping the recessed portion is defined. Claim 10 delete Claim 11 In claim 1, the display device wherein the recess on the plane is a closed-line shape surrounding the active area. Claim 12 In claim 1, the recessed portion on a plane comprises short side patterns, each extending in a first direction and spaced apart from a second direction intersecting the first direction with the active area in between, and long side patterns, each extending in the second direction and spaced apart from the first direction with the active area in between, and the short side patterns and the long side patterns are spaced apart from each other at the corners of the active area. Claim 13 In claim 1, the recessed portion comprises a plurality of patterns, and the patterns surround the active area and are spaced apart from each other in a display device. Claim 14 A display device according to claim 1, wherein the thickness of the recess is 5 µm or more to 20 µm or less. Claim 15 A display device according to claim 1, wherein the thickness of the partition portion is 3 µm or more to 5 µm or less, the width of the partition portion in one direction is 10 µm or more to 50 µm or less, and the width of the recessed portion in one direction is greater than the width of the partition portion. Claim 16 A display device according to claim 1, wherein the sealing material comprises any one of silicone, epoxy, and acrylic-based thermosetting materials, and the viscosity of the sealing material is 3,000 cps or more to 40,000 cps or less. Claim 17 A display device according to claim 1, further comprising a floating pattern disposed on the same layer as any one of the electrodes included in the transistor and overlapping with the surrounding area, wherein the floating pattern is in contact with the sealing material. Claim 18 A first substrate comprising an active region and a peripheral region adjacent to the active region; a plurality of insulating layers disposed on the first substrate; a pixel defining film having an opening defined and overlapping with the active region; a partition portion disposed on the same layer as the pixel defining film and overlapping with the peripheral region; a sub-partition portion disposed between the pixel defining film and the partition portion and overlapping with the peripheral region; a light-emitting element disposed on the first substrate comprising a first electrode, a second electrode, and a light-emitting layer disposed between the first and second electrodes, at least a portion of which is exposed by the opening; a second substrate disposed on the light-emitting element having a recess defined and overlapping with the peripheral region; and a sealing material disposed between one of the insulating layers and the second substrate, which overlaps with the peripheral region and defines an internal space. A display device comprising a filling material disposed in the internal space, wherein a belly area is defined between the partition section and the sub-partition section, and, in a planar view, the active area is adjacent to the recessed section, the partition section, and the sealing material in that order, and the belly area overlaps with the recessed section. Claim 19 In claim 18, the display device wherein the recess on the plane is a closed-line shape surrounding the active area. Claim 20 In claim 18, the above-mentioned recess is a display device having a trapezoidal shape in cross-section.

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