Semiconductor device

Abstract

The present invention provides a semiconductor device capable of suppressing the degradation of electrical characteristics that becomes more pronounced as the semiconductor device is miniaturized. The semiconductor device comprises a first oxide film, an oxide semiconductor film on the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film on the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film on the second oxide film, and a gate electrode in contact with the gate insulating film. The upper portion of the oxide semiconductor film is curved when viewed in the channel width direction.

Description

Technology Field

[0001] The present invention relates to a semiconductor device.

[0002] In this specification, the term "semiconductor device" refers to a device capable of functioning by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all included in the category of semiconductor devices. Background Technology

[0003] A technology for forming transistors using semiconductor thin films formed on a substrate having an insulating surface is attracting attention. Such transistors are used in a wide range of electronic devices, such as integrated circuits (ICs) and image display devices. Silicon-based semiconductor materials are widely known as materials for semiconductor thin films applicable to transistors. As another example, oxide semiconductors are drawing attention.

[0004] For example, Patent Document 1 discloses a transistor in which an amorphous oxide semiconductor comprising indium (In), gallium (Ga), and zinc (Zn) is included in the active layer.

[0005] Patent documents 2 and 3 disclose a technique for improving carrier mobility by stacking oxide semiconductor films. Prior art literature

[0006] Japanese Patent Publication No. 2006-165528, Japanese Patent Publication No. 2011-124360, Japanese Patent Publication No. 2011-138934 The problem to be solved

[0007] Generally, high integration of circuits requires the miniaturization of transistors. However, it is known that the miniaturization of transistors degrades their electrical characteristics, such as on-state current, threshold voltage, and subthreshold value.

[0008] For example, it is known that shortening the channel length in silicon transistors causes short-channel effects, such as an increase in the subthreshold swing (S value) or a shift of the threshold voltage toward the negative side.

[0009] Meanwhile, transistors using oxide semiconductors are accumulation-type transistors (transistors in which a channel is formed in the accumulation layer) where electrons are the majority carriers, and Drain-Induced Barrier Lowering (DIBL) is less likely to occur in single-channel transistors using oxide semiconductors than in single-channel inversion-type transistors using silicon (transistors in which a channel is formed in the inversion layer). In other words, transistors using oxide semiconductors have resistance to the single-channel effect.

[0010] There is concern that the reduction in the transistor channel width leads to a decrease in the on-state current. As a technique to improve the on-state current, a known method involves forming a thick active layer so that the channel is formed on the sides of the active layer as well. However, when the surface area where the channel is formed increases, carrier scattering increases at the interface between the channel formation region and the gate insulating film, making it difficult to obtain a sufficiently high on-state current.

[0011] One objective of one embodiment of the present invention is to provide a semiconductor device capable of suppressing the degradation of electrical characteristics that becomes more pronounced as the semiconductor device is miniaturized. Another objective is to provide a semiconductor device with high integration density. Another objective is to provide a semiconductor device in which the degradation of on-state current characteristics is reduced. Another objective is to provide a semiconductor device with low power consumption. Another objective is to provide a semiconductor device with high reliability. Another objective is to provide a semiconductor device in which data can be retained even when the power is stopped. Another objective is to provide a novel semiconductor device.

[0012] Furthermore, the description of these purposes does not preclude the existence of other purposes. Also, in one embodiment of the present invention, it is not necessary to achieve all purposes. Other purposes become apparent from the description in the specification, drawings, claims, etc., and can be obtained from the description in the specification, drawings, claims, etc. means of solving the problem

[0013] One embodiment of the present invention relates to a semiconductor device comprising a stacked oxide semiconductor film.

[0014] One embodiment of the present invention is a semiconductor device comprising a first oxide film, an oxide semiconductor film on the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film on the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film on the second oxide film, and a gate electrode in contact with the gate insulating film. The upper portion of the oxide semiconductor film is curved when viewed in the channel width direction.

[0015] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion between components and do not numerically limit the components.

[0016] In the structure described above, the upper surface of the oxide semiconductor film may have a flat portion.

[0017] In the structure described above, the radius of curvature of the end of the oxide semiconductor film when viewed in the channel width direction ( r )(In the case of two ends, each radius of curvature r 1 and r 2) is greater than 0 and channel width( W Less than half of ) (0< r (or r 1 or r 2)≤W / 2).

[0018] In the structure described above, the upper portion of the second oxide film may be aligned with the lower portion of the gate insulating film, and the upper portion of the gate insulating film may be aligned with the lower portion of the gate electrode.

[0019] In the structure described above, it is preferable that the lowest conduction band of each of the first oxide film and the second oxide film be closer to the vacuum level by at least 0.05 eV and at least 2 eV than the lowest conduction band of the oxide semiconductor film.

[0020] The above-described structure may include a first oxide film, an oxide semiconductor film, a source electrode, a drain electrode, a second oxide film, a gate insulating film, and a barrier film that contacts and covers the gate electrode.

[0021] The above-described structure may include a first sidewall insulating film on the side of the first oxide film, the oxide semiconductor film, the source electrode, and the drain electrode, with a barrier film interposed between them.

[0022] The above-described structure may include a second oxide film, a gate insulating film, and a second sidewall insulating film on the side of the gate electrode with a barrier film interposed between them. Effects of the invention

[0023] According to one embodiment of the present invention, any of the following semiconductor devices may be provided: a semiconductor device capable of suppressing the degradation of electrical characteristics that becomes more pronounced as the semiconductor device is miniaturized; a semiconductor device with high integration density; a semiconductor device in which the degradation of on-state current characteristics is reduced; a semiconductor device with low power consumption; a semiconductor device with high reliability; a semiconductor device in which data can be retained even when the power is stopped; and a novel semiconductor device. Furthermore, the description of these effects does not interfere with the existence of other effects. In one embodiment of the present invention, it is not necessary to obtain all effects. Other effects become clear from the descriptions in the specification, drawings, claims, etc., and can be obtained from the descriptions in the specification, drawings, claims, etc. Brief explanation of the drawing

[0024] Figures 1 (A) to (C) are top and cross-sectional views illustrating a transistor. Figures 2 (A) and (B) show the band structure of a multilayer film. Figure 3 is an enlarged cross-sectional view of a transistor. Figures 4 (A) and (B) are cross-sectional views of a transistor in the channel width direction, respectively. Figures 5 (A) and (B) are cross-sectional views of a transistor in the channel width direction, respectively. Figures 6 (A) to (C) are top and cross-sectional views illustrating a transistor. Figure 7 is a cross-sectional view of a transistor. Figures 8 (A) to (C) are cross-sectional views illustrating a method for fabricating a transistor. Figures 9 (A) to (C) are cross-sectional views illustrating a method for fabricating a transistor. Figures 10 (A) and (B) are cross-sectional STEM images of a transistor fabricated in an example. Figure 11 shows the measurement results of the electrical characteristics of the transistor fabricated in the embodiment. Figure 12 shows the measurement results of the electrical characteristics of the transistor fabricated in the embodiment. Figures 13 (A) to (C) each show the measurement results of the electrical characteristics of the transistors fabricated in the examples. Figures 14 (A) to (C) are top and cross-sectional views illustrating a transistor. Figures 15 (A) to (C) illustrate a method for fabricating a transistor. Figures 16 (A) to (C) illustrate a method for fabricating a transistor. Figures 17 (A) to (C) illustrate a method for fabricating a transistor. Figures 18 (A) to (C) each illustrate a method for fabricating a transistor. Each of (A) to (D) of FIG. 19 illustrates an inverter including a semiconductor device of one form of the present invention. FIG. 20 is a circuit diagram of a semiconductor device of one embodiment of the present invention. FIG. 21 is a block diagram of a semiconductor device of one embodiment of the present invention. FIG. 22 is a circuit diagram illustrating a memory device of one form of the present invention. Each of (A) to (C) in FIG. 23 illustrates an electronic device of one form of the present invention. FIG. 24 is an equivalent circuit diagram illustrating an example of a semiconductor device. Figures 25 (A) and (B) are cross-sectional views of a transistor in the channel width direction, respectively. FIG. 26 is a cross-sectional view of a transistor in the channel length direction. Figure 27 shows the I of the transistor d -V g Something that represents the characteristics. Figure 28 shows the I of the transistor d -V g Something that represents the characteristics. Figure 29 shows the I of the transistor d -V g Something that represents the characteristics. Figure 30 shows the temperature dependence of the transistor. Figure 31 shows the temperature dependence of the transistor. Figure 32 (A) and (B) respectively show the reliability of the transistor. Figure 33 shows the reliability of the transistor. Figures (A) to (D) of Figure 34 each show the electrical characteristics of a transistor. Figure 35 (A) and (B) each show the electrical characteristics of the transistor. Figure 36 is a schematic diagram of the structure of a transistor. Figures 37 (A) and (B) each show the nanobeam electron diffraction patterns of an oxide semiconductor film. Figures 38 (A) and (B) illustrate examples of transmission electron diffraction measuring devices. Figure 39 illustrates an example of structural analysis by transmission electron diffraction measurement. Figures (A) to (C) of Figure 40 each show the temperature dependence of the transistor. Specific details for implementing the invention

[0025] Embodiments are described in detail with reference to the drawings. However, it is readily understood by those skilled in the art that the present invention is not limited to the description below, and that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be limited to the description of the embodiments below. Furthermore, in the structure of the present invention described below, the same parts or parts having similar functions are indicated by the same reference numerals in different drawings, and their descriptions may be omitted.

[0026] (Embodiment 1)

[0027] In this embodiment, a semiconductor device of one form of the present invention is described with reference to the drawings.

[0028] FIGS. 1 (A) to (C) are top and cross-sectional views illustrating a transistor of one embodiment of the present invention. FIGS. 1 (A) is a top view. FIGS. 1 (B) is a cross-sectional view along the dotted line AB in FIGS. 1 (A). FIGS. 1 (C) is a cross-sectional view along the dotted line CD in FIGS. 1 (A). Additionally, to simplify the drawings, several components are not shown in the top view of FIGS. 1 (A). The direction of the dotted line AB may be referred to as the channel length direction, and the direction of the dotted line CD may be referred to as the channel width direction. Furthermore, the channel length is the length of the channel forming region in the direction in which carriers flow. The channel width is the length of the channel forming region perpendicular to the channel length direction.

[0029] The transistor (450) illustrated in (A) to (C) of FIG. 1 comprises: a base insulating film (402) on a substrate (400); a first oxide film (404a) and an oxide semiconductor film (404b) on the base insulating film (402); a source electrode (406a) and a drain electrode (406b) on the first oxide film (404a) and the oxide semiconductor film (404b); a second oxide film (404c) on the oxide semiconductor film (404b), the source electrode (406a), and the drain electrode (406b); a gate insulating film (408) on the second oxide film (404c); a gate electrode (410) on the gate insulating film (408); and an oxide insulating film (412) on the source electrode (406a), the drain electrode (406b), and the gate electrode (410). The first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) are collectively referred to as a multilayer film (404).

[0030] When the channel length and channel width of the transistor are reduced, electrodes, semiconductor films, etc. processed using a resist mask may have rounded ends (curved surfaces). When viewed from a cross-section, the upper portion of the oxide semiconductor film (404b) in this embodiment has a rounded, semi-circular shape. Due to this structure, the coverage rate of the gate insulating film (408), gate electrode (410), and oxide insulating film (412) formed on the oxide semiconductor film (404b) can be improved. In addition, electric field concentration that may occur at the ends of the source electrode (406a) and drain electrode (406b) can be reduced, thereby suppressing the degradation of the transistor.

[0031] The oxide semiconductor film (404b) has a radius of curvature r It has the curvature of an osculating circle. Also, the radius of curvature is equal to the radius of the curved osculating circle. The oxide semiconductor film (404b) may have two or more parts having different osculating circle curvatures.

[0032] Specifically, in the oxide semiconductor film (404b) illustrated in (A) to (C) of FIG. 1, the radius of curvature of the upper portion viewed in the channel width direction ( r 1) is greater than 0 and channel width( W It is preferable that it be less than half of ), and likewise the radius of curvature of the upper part viewed in the channel width direction ( r 2)(Radius of curvature( r The upper part having 2) has a radius of curvature ( r From the upper part having 1) channel width ( W (deviated by ) is greater than 0 and channel width( W Less than half of ) (0< r 1, r 2≤W / 2) is preferable. As shown in (C) of FIG. 6, when the upper surface of the oxide semiconductor film (404b) does not have a flat portion when viewed in the channel width direction, the radius of curvature of the upper portion ( r 3) is greater than 0 and channel width( W Less than half of ) (0< r 3≤W / 2) is desirable.

[0033] In addition, for example, the functions of the "source" and "drain" of a transistor may be reversed when transistors of opposite polarity are used or when the direction of current flow changes during circuit operation. Accordingly, in this specification, the term "source" may be used to refer to the drain, and the term "drain" may be used to refer to the source.

[0034] The substrate (400) is not limited to a simple support substrate and may be a substrate on which another device, such as a transistor, is formed. In this case, at least one of the gate electrode (410), source electrode (406a), and drain electrode (406b) of the transistor (450) may be electrically connected to the device described above.

[0035] The lower insulating film (402) may have the function of supplying oxygen to the multilayer film (404) in addition to the function of preventing the diffusion of impurities from the substrate (400). For this reason, it is preferable that the lower insulating film (402) be an insulating film containing oxygen, and it is even more preferable that it be an insulating film containing oxygen with an oxygen content greater than the stoichiometric composition. As described above, when another device is provided on the substrate (400), the lower insulating film (402) also functions as an interlayer insulating film. In this case, since the lower insulating film (402) has a non-flat surface, it is preferable to perform a flattening treatment, such as CMP (Chemical Mechanical Polishing), on the lower insulating film (402) to have a flat surface.

[0036] It is preferable that an aluminum oxide film capable of supplying oxygen be used in the lower insulating film (402). The aluminum oxide film has the function of supplying oxygen as well as the function of blocking hydrogen, water, and oxygen. An aluminum oxide film containing silicon oxide, formed using a target mixed with aluminum oxide and silicon oxide, may be used. In this case, it is preferable that the silicon oxide content be 0.1 wt% or more and 30 wt% or less.

[0037] The multilayer film (404) in the channel forming region of the transistor (450) has a structure in which a first oxide film (404a), an oxide semiconductor film (404b), and a second oxide film (404c) are stacked in sequence from the substrate (400) side. The oxide semiconductor film (404b) is surrounded by the first oxide film (404a) and the second oxide film (404c). As shown in (C) of FIG. 1, when viewed in the channel width direction, the gate electrode (410) electrically covers the oxide semiconductor film (404b).

[0038] Here, for example, an oxide semiconductor with a higher electron affinity (energy difference between the vacuum level and the lowest conduction band) than the first oxide film (404a) and the second oxide film (404c) is used in the oxide semiconductor film (404b). The electron affinity can be obtained by subtracting the energy difference between the lowest conduction band and the highest valence band (so-called energy gap) from the energy difference between the vacuum level and the highest valence band (so-called ionization potential).

[0039] The first oxide film (404a) and the second oxide film (404c) each contain one or more types of metal elements that form the oxide semiconductor film (404b). For example, it is preferable that the first oxide film (404a) and the second oxide film (404c) be formed using an oxide semiconductor in which the lowest conduction band is closer to the vacuum level than that of the oxide semiconductor film (404b). Additionally, it is preferable that the energy difference in the lowest conduction band between the oxide semiconductor film (404b) and the first oxide film (404a) and the energy difference in the lowest conduction band between the oxide semiconductor film (404b) and the second oxide film (404c) be 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more, and 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less, respectively.

[0040] In this structure, when an electric field is applied to the gate electrode (410), a channel is formed in the oxide semiconductor film (404b) in the multilayer film (404) where the lowest conduction band is the lowest. In other words, a second oxide film (404c) is formed between the oxide semiconductor film (404b) and the gate insulating film (408), thereby obtaining a structure in which the channel of the transistor does not come into contact with the gate insulating film (408).

[0041] In addition, since the first oxide film (404a) contains one or more types of metal elements included in the oxide semiconductor film (404b), assuming that the oxide semiconductor film (404b) is in contact with the lower insulating film (402), the oxide semiconductor film (404b) is more difficult to form an interface state at the interface with the first oxide film (404a) than at the interface with the lower insulating film (402). This interface state may form a channel, thereby changing the threshold voltage of the transistor. Therefore, the first oxide film (404a) can reduce fluctuations in the electrical characteristics of the transistor, such as the threshold voltage. In addition, the reliability of the transistor can be improved.

[0042] Additionally, since the second oxide film (404c) contains one or more types of metal elements included in the oxide semiconductor film (404b), assuming that the oxide semiconductor film (404b) is in contact with the gate insulating film (408), the oxide semiconductor film (404b) is less likely to cause carrier scattering at the interface with the second oxide film (404c) than at the interface with the gate insulating film (408). Therefore, the field-effect mobility of the transistor can be increased by the second oxide film (404c).

[0043] For the first oxide film (404a) and the second oxide film (404c), a material containing, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf in a higher atomic ratio than the material used in the oxide semiconductor film (404b) may be used. Specifically, the atomic ratio of any of the aforementioned metal elements in the first oxide film (404a) and the second oxide film (404c) is at least 1.5 times, preferably at least 2 times, and more preferably at least 3 times that of the oxide semiconductor film (404b). Any of the aforementioned metal elements is strongly bound to oxygen and has the function of suppressing the occurrence of oxygen vacancies in the first oxide film (404a) and the second oxide film (404c). That is, it is more difficult for oxygen vacancies to occur in the first oxide film (404a) and the second oxide film (404c) than in the oxide semiconductor film (404b).

[0044] In addition, the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) each comprise indium, zinc, and M ( M In- (metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) comprising at least M - It is Zn oxide, and the first oxide film (404a) is M The atomic ratio of In to Zn is x1:y1:z1, and the oxide semiconductor film (404b) is M and the atomic ratio of In to Zn is x2:y2:z2, and the second oxide film (404c) is MWhen the atomic ratio of In to Zn is x3:y3:z3, it is preferable that y1 / x1 and y3 / x3 are each greater than y2 / x2. Each of y1 / x1 and y3 / x3 is at least 1.5 times, preferably at least 2 times, and more preferably at least 3 times greater than y2 / x2. At this time, in the oxide semiconductor film (404b), if y2 is greater than or equal to x2, the transistor can have stable electrical characteristics. However, since the field-effect mobility of the transistor decreases if y2 is at least 3 times greater than x2, it is preferable that y2 be less than 3 times x2.

[0045] When Zn and O are not considered, the ratio of In to M in the first oxide film (404a) and the second oxide film (404c) is preferably less than 50 atomic% for In and more than 50 atomic% for M, and more preferably more than 34 atomic% for In and less than 66 atomic% for M.

[0046] The thickness of the first oxide film (404a) and the second oxide film (404c) is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. The thickness of the oxide semiconductor film (404b) is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50 nm or less.

[0047] For the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c), oxide semiconductors including, for example, indium, zinc, and gallium may be used. Additionally, it is preferable that the oxide semiconductor film (404b) include indium because it can improve carrier mobility.

[0048] In addition, by reducing the impurity concentration in the oxide semiconductor film to make the oxide semiconductor film intrinsic or substantially intrinsic, stable electrical characteristics can be effectively imparted to a transistor using the oxide semiconductor film as a channel. The term "substantially intrinsic" refers to an oxide semiconductor film having 1×1017 / cm 3 Less than, preferably 1×10 15 / cm 3 Less than, more preferably 1×10 13 / cm 3 It refers to a state having a carrier density of less than

[0049] Some of the hydrogen atoms contained in the oxide semiconductor film are captured in oxygen vacancies, causing the oxide semiconductor film to have an n-type conductivity. Therefore, the Fermi level (E in a high-purity intrinsic oxide semiconductor film) f The Fermi level (E) in an oxide semiconductor film containing more hydrogen than ) f ) is a preaching team (E c Since it is close to the bottom, an improvement in the field-effect mobility of the transistor is expected. When the oxide semiconductor film becomes intrinsic or substantially intrinsic, the Fermi energy of the oxide semiconductor film becomes equal to or substantially equal to the mid gap (the intermediate energy of the oxide semiconductor film's energy gap). In this case, there is concern that the field-effect mobility will decrease due to a reduction in the number of carriers in the oxide semiconductor film.

[0050] However, in a transistor of one embodiment of the present invention, the gate electric field is applied to the oxide semiconductor film not only in the vertical direction but also in the lateral direction. That is, the gate electric field is applied to the entire oxide semiconductor film, and current flows throughout the entire oxide semiconductor film. Therefore, fluctuations in electrical characteristics caused by the high-purity intrinsic oxide semiconductor film can be suppressed, and the field-effect mobility of the transistor can be increased.

[0051] In an oxide semiconductor film, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components of the oxide semiconductor film are impurities. For example, hydrogen and nitrogen form donor levels, which increase carrier density. Additionally, silicon in the oxide semiconductor film forms impurity levels. These impurity levels can become traps, which degrade the electrical characteristics of the transistor. Therefore, it is desirable to reduce the impurity concentration in the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c), and at the interface between these films.

[0052] In order to make the oxide semiconductor film intrinsic or substantially intrinsic, in Secondary Ion Mass Spectrometry (SIMS), for example, the silicon concentration at a defined depth of the oxide semiconductor film or in a region of the oxide semiconductor film is preferably 1×10⁻⁶ 19 atoms / cm 3 Less than, more preferably 5×10 18 atoms / cm 3 Less than, more preferably 1×10 18 atoms / cm 3 It is preferable that it be less than. In addition, the hydrogen concentration at a defined depth of the oxide semiconductor film or in a region of the oxide semiconductor film is preferably 2×10⁻⁶. 20 atoms / cm 3 Below, more preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 It is preferable that it be less than or equal to. In addition, the nitrogen concentration at a defined depth of the oxide semiconductor film or in a region of the oxide semiconductor film is preferably 5×10⁻⁶. 19 atoms / cm 3 Less than, more preferably 5×10 18 atoms / cm 3Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 It is better to be less than this.

[0053] When an oxide semiconductor film contains crystals, high concentrations of silicon or carbon may reduce the crystallinity of the oxide semiconductor film. To avoid lowering the crystallinity of the oxide semiconductor film, for example, the silicon concentration at a defined depth or region of the oxide semiconductor film is set to 1×10⁻⁶ 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than, more preferably 1×10 18 atoms / cm 3 It may be less than. In addition, the carbon concentration at a defined depth of the oxide semiconductor film or in a region of the oxide semiconductor film may be, for example, 1×10⁻⁶ 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than, more preferably 1×10 18 atoms / cm 3 It may be less than that.

[0054] A transistor in which the above-described high-purity oxide semiconductor film is used in the channel formation region has a very low off-state current. For example, when the voltage between the source and drain is set to about 0.1V, 5V, or 10V, the off-state current standardized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm.

[0055] In addition, since silicon-containing insulating films are often used as the gate insulating film of a transistor, for the reasons mentioned above, it is preferable that the region of the multilayer film functioning as a channel does not come into contact with the gate insulating film, as in the case of a transistor of one embodiment of the present invention. If a channel is formed at the interface between the gate insulating film and the multilayer film, carrier scattering may occur at this interface, which may reduce the field-effect mobility of the transistor. For the reasons mentioned above, it is also preferable that the region of the multilayer film functioning as a channel be separated from the gate insulating film.

[0056] Accordingly, by means of a multilayer film (404) having a stacked structure including a first oxide film (404a), an oxide semiconductor film (404b), and a second oxide film (404c) in sequence, a channel can be formed in the oxide semiconductor film (404b), so that the transistor can have high field-effect mobility and stable electrical characteristics.

[0057] Next, the band structure of the multilayer film (404) is described. To analyze the band structure, a stacked film corresponding to the multilayer film (404) is formed. In the stacked film, an In-Ga-Zn oxide with an energy gap of 3.5 eV is used in the layer corresponding to the first oxide film (404a) and the second oxide film (404c), and an In-Ga-Zn oxide with an energy gap of 3.15 eV is used in the layer corresponding to the oxide semiconductor film (404b).

[0058] The thickness of each of the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) was 10 nm. The energy gap was measured using a spectroscopic ellipsometer (HORIBA Jobin Yvon, UT-300). Additionally, the energy difference between the vacuum level and the top of the valence band was measured using an ultraviolet photoelectron spectroscopy (UPS) device (ULVAC-PHI, Inc., VersaProbe).

[0059] FIG. 2 (A) is part of a band structure schematically showing the energy difference (electron affinity) between the vacuum level and the lowest conduction band of each layer, calculated by subtracting the energy gap from the energy difference between the vacuum level and the highest valence band. FIG. 2 (A) is a band diagram showing the case where a silicon oxide film is provided in contact with a first oxide film (404a) and a second oxide film (404c). Here, Ev represents the energy of the vacuum level, EcI1 and EcI2 each represent the lowest conduction band of the silicon oxide film, EcS1 represents the lowest conduction band of the first oxide film (404a), EcS2 represents the lowest conduction band of the oxide semiconductor film (404b), and EcS3 represents the lowest conduction band of the second oxide film (404c).

[0060] As shown in (A) of FIG. 2, the lowest conduction band of the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) varies continuously. This can also be understood in that the components of the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) are similar to each other, making it easy for oxygen to diffuse between the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c). Thus, the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) have different components and form a stack, but have continuous physical properties. In the drawing, the interface between the oxide semiconductor layers of the stack is indicated by a dotted line.

[0061] A multilayer film (404) in which layers containing the same main component are stacked is formed to have not only a simple stacked structure of layers but also a continuous energy band (in particular, a U-shaped well structure in which the lowest conduction band varies continuously between layers). In other words, the stacked structure is formed so that there are no impurities forming defect levels, such as trap centers or recombination centers, at each interface. If impurities are present between the stacked layers in the multilayer film, the continuity of the energy band is lost and carriers are extinguished by capture or recombination.

[0062] Additionally, Figure 2 (A) shows the case where EcS1 and EcS3 are similar to each other, but EcS1 and EcS3 may be different from each other. For example, a part of the band structure in the case where EcS1 is higher than EcS3 is shown in Figure 2 (B).

[0063] For example, when EcS1 is equivalent to EcS3, an In-Ga-Zn oxide having an atomic ratio of In to Ga and Zn of 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6 can be used for the first oxide film (404a) and the second oxide film (404c), and an In-Ga-Zn oxide having an atomic ratio of In to Ga and Zn of 1:1:1 or 3:1:2 can be used for the oxide semiconductor film (404b). Additionally, for example, when EcS1 is higher than EcS3, an In-Ga-Zn oxide with an atomic ratio of In to Ga and Zn of 1:6:4 or 1:9:6 can be used in the first oxide film (404a), an In-Ga-Zn oxide with an atomic ratio of In to Ga and Zn of 1:1:1, 1:1:1.2, 1:1:1.5, or 3:1:2 can be used in the oxide semiconductor film (404b), and an In-Ga-Zn oxide with an atomic ratio of In to Ga and Zn of 1:3:2, 1:3:3, or 1:3:4 can be used in the second oxide film (404c).

[0064] According to (A) and (B) of FIG. 2, the oxide semiconductor film (404b) of the multilayer film (404) functions as a well, and a channel is formed in the oxide semiconductor film (404b) of the transistor containing the multilayer film (404). Additionally, since the lowest conduction band is continuously varied, the multilayer film (404) may be described as a U-shaped well. Furthermore, a channel formed to have such a structure may be described as a buried channel.

[0065] Additionally, a trap level due to impurities or defects may be formed near the interface between each of the first oxide film (404a) and the second oxide film (404c) and an insulating film such as a silicon oxide film. The presence of the first oxide film (404a) and the second oxide film (404c) can keep the oxide semiconductor film (404b) away from the trap level. However, when the energy difference between EcS2 and EcS1 and between EcS2 and EcS3 is small, there are cases where electrons in the oxide semiconductor film (404b) exceed this energy difference and reach the trap level. When electrons are trapped at the trap level, a negative fixed charge is created at the insulating film interface, and the threshold voltage of the transistor shifts in both directions.

[0066] Accordingly, in order to reduce fluctuations in the threshold voltage of the transistor, an energy difference of at least a defined value is required between EcS2 and EcS1 and between EcS2 and EcS3. In each case, the energy difference is preferably 0.1 eV or more, more preferably 0.15 eV or more.

[0067] It is preferable that the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) include a crystal portion. In particular, if a crystal with a c-axis aligned is used, the transistor can have stable electrical characteristics.

[0068] When In-Ga-Zn oxide is used in the multilayer film (404), it is preferable that the second oxide film (404c) contains less In than the oxide semiconductor film (404b) to prevent the diffusion of In into the gate insulating film.

[0069] It is preferable to use a conductive material that readily combines with oxygen for the source electrode (406a) and the drain electrode (406b). For example, Al, Cr, Cu, Ta, Ti, Mo, or W may be used. Among the above materials, it is particularly preferable to use Ti, which readily combines with oxygen, or W, which has a high melting point and can raise the subsequent process temperature relatively high. However, conductive materials that readily combine with oxygen also include materials in which oxygen is easily diffused.

[0070] When a conductive material that readily combines with oxygen comes into contact with a multilayer film, oxygen from the multilayer film diffuses into the conductive material. This phenomenon occurs significantly at high temperatures. Since the transistor fabrication process includes several heat treatment steps, the aforementioned phenomenon creates oxygen vacancies in the multilayer film near the region in contact with the source or drain electrode. These oxygen vacancies combine with hydrogen present in small amounts within the film, causing this region to transform into an n-type region. Consequently, the n-type region can function as the source or drain of the transistor.

[0071] The above n-type region is illustrated in FIG. 3 in an enlarged cross-sectional view (cross-section in the channel length direction) of the transistor. The boundary (435) indicated by the dotted line in the oxide semiconductor film (404b) is the boundary between the intrinsic semiconductor region and the n-type semiconductor region. In the oxide semiconductor film (404b), the region close to the source electrode (406a) or the drain electrode (406b) becomes the n-type region. Here, the boundary (435) is schematically illustrated, but in reality, the boundary may not be clear. FIG. 3 shows the boundary (435) extending in the transverse direction in the oxide semiconductor film (404b), but there are cases where the region in the first oxide film (404a) and the oxide semiconductor film (404b) sandwiched between the source electrode (406a) or the drain electrode (406b) and the first oxide film (404a) becomes n-type overall in the thickness direction. In addition, although not shown, an n-type region may also be formed in the first oxide film or the second oxide film.

[0072] When forming a transistor with a very short channel length, the n-type region formed by the occurrence of oxygen vacancies may extend along the channel length of the transistor. In this case, the electrical characteristics of the transistor, for example, result in a shift in the threshold voltage or make it impossible to control the transistor's on and off states with the gate voltage (in this case, the transistor turns on). Therefore, when forming a transistor with a very short channel length, it is not necessarily desirable to use conductive materials that readily combine with oxygen at the source and drain electrodes.

[0073] In this case, it is preferable to use a conductive material that is less resistant to combining with oxygen than the material described above for the source electrode (406a) and the drain electrode (406b). As the conductive material that is less resistant to combining with oxygen, for example, a material containing tantalum nitride, titanium nitride, or ruthenium may be used. Additionally, when the conductive material comes into contact with the oxide semiconductor film (404b), the source electrode (406a) and the drain electrode (406b) may each have a stacked structure in which the conductive material that is less resistant to combining with oxygen and the conductive material described above that is easy to combine with oxygen are stacked.

[0074] The gate insulating film (408) may be formed using an insulating film comprising one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The gate insulating film (408) may be a laminate comprising any of the materials described above.

[0075] A conductive film formed using Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, etc., may be used for the gate electrode (410). The gate electrode may be a laminate containing any of the materials described above. Alternatively, a conductive film containing nitrogen may be used for the gate electrode (410).

[0076] An oxide insulating film (412) may be formed on the gate insulating film (408) and the gate electrode (410). The oxide insulating film (412) may be formed using an insulating film comprising one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The oxide insulating film (412) may be a laminate comprising any of the materials described above.

[0077] Here, it is preferable that the oxide insulating film (412) contains excess oxygen. An oxide insulating film containing excess oxygen refers to an oxide insulating film capable of releasing oxygen through heat treatment, etc. An oxide insulating film containing excess oxygen has an oxygen release amount of 1.0 × 10⁻⁶ when converted to oxygen atoms in thermal desorption spectroscopic analysis. 19 atoms / cm 3 An ideal film is preferred. Oxygen released from the oxide insulating film can diffuse through the gate insulating film (408) into the channel formation region of the multilayer film (404), thereby filling the oxygen vacancies formed in the channel formation region with oxygen. In this way, the electrical characteristics of the transistor can be stabilized.

[0078] It is preferable that an aluminum oxide film be used in the oxide insulating film (412). The aluminum oxide film has the function of supplying oxygen as well as the function of blocking hydrogen, water, and oxygen. Alternatively, an aluminum oxide film containing silicon oxide may be used, formed using a target in which aluminum oxide and silicon oxide are mixed. In this case, it is preferable that the silicon oxide content be 0.1 wt% or more and 30 wt% or less.

[0079] High integration of semiconductor devices requires the miniaturization of transistors. However, it is known that transistor miniaturization leads to the degradation of their electrical characteristics. In particular, the on-state current, which is directly caused by the reduction in channel width, is significantly reduced.

[0080] Figures 4 (A) and (B) are cross-sectional views in the channel width direction of a conventional transistor including an oxide semiconductor film. Each transistor includes a lower insulating film (220) on a substrate (210), an oxide semiconductor film (230) formed on the lower insulating film, a gate insulating film (260) formed on the oxide semiconductor film, and a gate electrode (270).

[0081] In the transistor in (A) of FIG. 4, the length of the upper surface of the oxide semiconductor film in the channel width direction (W T ) is significantly larger than the thickness of the oxide semiconductor film (230). In this case, the channel width is W T It can be defined as.

[0082] Since the electric field applied from the gate electrode (270) to the side of the oxide semiconductor film (230) is not applied to the entire oxide semiconductor film (230), the channel is not sufficiently formed on the side of the oxide semiconductor film (230). In addition, the length of the upper surface (W T A lateral length (W) corresponding to the thickness of the oxide semiconductor film (230) for ) S1 , W S2 Since the ratio of ) is small, it is estimated that the channel's contribution is small even if a channel is formed. Therefore, W T It can be said that the on-state current decreases as the length becomes shorter, or in other words, as the transistor becomes smaller.

[0083] As shown in (B) of FIG. 4, W is equal to the thickness of the oxide semiconductor film (230). TIn the case of a short transistor, the electric field applied from the gate electrode (270) to the side of the oxide semiconductor film (230) is applied to the entire oxide semiconductor film (230), so a channel is formed on the side of the oxide semiconductor film (230). Therefore, it is expected that the on-state current will increase, for example, by making the oxide semiconductor film (230) thicker. However, in a conventional transistor, the on-state current is not sufficiently increased because carriers are scattered at the interface between the channel forming layer (oxide semiconductor film (230)) and the gate insulating film (260).

[0084] In addition, depending on the deposition method, the thickness (T) of the gate insulating film (260) covering the side of the oxide semiconductor film (230) GI2 The thickness (T) of the gate insulating film covering the upper surface of the oxide semiconductor film GI1 It is easy to make it thinner than ). Therefore, a portion having a low withstand voltage is formed on the gate insulating film (260), which can reduce the reliability of the transistor.

[0085] Also, T GI1 and T GI2 Because they are different from each other, the electric field applied from the gate electrode (270) to the oxide semiconductor film (230) varies. Therefore, the on-state current may vary.

[0086] Meanwhile, in a transistor of one embodiment of the present invention, as described above, a second oxide film (404c) is formed between the gate insulating film (408) and the oxide semiconductor film (404b) in which the channel is formed. Accordingly, scattering of carriers at the interface between the channel forming layer and the gate insulating film can be reduced, and the field-effect mobility of the transistor can be increased.

[0087] In addition, in a transistor of one embodiment of the present invention, a second oxide film (404c) is formed to cover an oxide semiconductor film (404b) in which a channel is formed, so that carrier scattering on the side of the oxide semiconductor film (404b) can be reduced as on the top surface. This means that the on-state current of the transistor of one embodiment of the present invention is higher than that of a conventional transistor.

[0088] Accordingly, a transistor of one embodiment of the present invention is W shown in (A) or (B) of FIG. 5. T It exhibits particularly excellent effects when having a structure that is substantially equal to or smaller than the thickness of the oxide semiconductor film (404b).

[0089] In the case of the transistor shown in (A) or (B) of FIG. 5, since the electric field applied from the gate electrode (170) to the side of the oxide semiconductor film (404b) is applied to the entire oxide semiconductor film (404b), a channel is formed equally on the side and top surface of the oxide semiconductor film (404b).

[0090] When a channel region (137) as in (A) of FIG. 5 is formed in the transistor, the channel width is W T , W S1 , and W S2 It can be defined as the sum of, and an on-state current flows in the transistor according to the channel width.

[0091] A very small W as shown in (B) of Fig. 5 T In the case of a transistor having, the channel region (138) is W T There are cases where it is formed over the entire oxide semiconductor film (404b) in a direction. In this case, current flows over the entire oxide semiconductor film (404b), and a very high on-state current flows in the transistor. W of the transistor shown in (A) of FIG. 5. T W S1 When this is sufficiently small, current flows through the entire oxide semiconductor film (404b).

[0092] One feature of a transistor of one embodiment of the present invention is that the gate insulating film (160) T GI1 and T GI2 is substantially equivalent. In this case, the electric field applied from the gate electrode (170) to the oxide semiconductor film (404b) does not fluctuate, and channels are uniformly formed on the upper and side surfaces of the oxide semiconductor film (404b). Therefore, W S1 and W S2 Ga W T In the equivalent case, the on-state current can be increased by about three times compared to the case where a channel is formed only on the upper surface. W S1 and W S2 Each W T In the case where it is twice the size, the on-state current can be increased by about five times compared to the case where a channel is formed only on the upper surface.

[0093] T of the gate insulating film (160) of a transistor of one form of the present invention GI1 and T GI2 In the case where they are substantially equivalent, a portion having a low withstand voltage is not formed on the gate insulating film (260), and a highly reliable transistor can be formed.

[0094] To efficiently improve the on-state current of a transistor, W T / W S1 (W T / W S2 ) is 3 or less, preferably W T / W S1 (W T / W S2 It is good if ) is nearly 1. Specifically, W T / W S1 (W T / W S2 ) is 0.7~1.3. W T / W S1 (W T / W S2 If ) is greater than 3, the S value and off-state current may increase.

[0095] As described above, with a transistor of one form of the present invention, a sufficiently high on-state current can be obtained even when the transistor is miniaturized. A transistor structure in which the gate electrode electrically covers an oxide semiconductor film and the on-state current is increased is also called an s-channel (surrounded channel) structure.

[0096] In a transistor of one embodiment of the present invention, the oxide semiconductor film (404b) is formed on the first oxide film (404a), making it difficult to form an interface state. Additionally, since the oxide semiconductor film (404b) is an intermediate layer of a three-layer structure, impurities do not enter the oxide semiconductor film (404b) from above and below. Due to the structure in which the oxide semiconductor film (404b) is surrounded by the first oxide film (404a) and the second oxide film (404c), the on-state current of the transistor is increased as described above, and the threshold voltage is stabilized so that the S value can be reduced. Accordingly, the Icut (current when the gate voltage VG is 0V) can be reduced, and power consumption can be reduced. Furthermore, the threshold voltage of the transistor is stabilized, so the long-term reliability of the semiconductor device can be improved.

[0097] A transistor of one embodiment of the present invention may include a conductive film between an insulating film (120) and a substrate (110). When the conductive film is used as a second gate electrode, the on-state current can be further increased and the threshold voltage can be controlled. To increase the on-state current, for example, the gate electrode (170) and the conductive film are set to have the same potential, and the transistor is driven as a dual-gate transistor. Additionally, to control the threshold voltage, a fixed potential different from the potential of the gate electrode (170) is supplied to the conductive film.

[0098] The transistor (460) illustrated in FIGS. 6 (A) to (C) may be used. FIGS. 6 (A) to (C) are top and cross-sectional views illustrating the transistor (460). FIGS. 6 (A) is a top view. FIGS. 6 (B) is a cross-sectional view along the dotted line AB in FIGS. 6 (A). FIGS. 6 (C) is a cross-sectional view along the dotted line CD in FIGS. 6 (A). Additionally, to simplify the drawings, several components are not shown in the top view of FIGS. 6 (A).

[0099] The difference between the transistors in (A) to (C) of FIG. 6 and (A) to (C) of FIG. 1 is that, as shown in (C) of FIG. 6, the upper surface of the oxide semiconductor film (404b) does not have a flat portion when viewed in the channel width direction.

[0100] In the transistor (450) in (A) to (C) of FIG. 1 and the transistor (460) in (A) to (C) of FIG. 6, the multilayer film (404) has a structure in which an oxide semiconductor film (404b) is sandwiched between a first oxide film (404a) and a second oxide film (404c). The structure of the multilayer film (404) is not limited to this structure, and the structure of the transistor (470) in FIG. 7, in which the first oxide film (404a) and the second oxide film (404c) are not provided and only the oxide semiconductor film (404b) is provided, is also acceptable.

[0101] This embodiment may be appropriately combined with any of the other embodiments in this specification.

[0102] (Embodiment 2)

[0103] In this embodiment, a method for forming the transistor (450) described in Embodiment 1 with reference to (A) to (C) of FIG. 1 is explained with reference to (A) to (C) of FIG. 8 and (A) to (C) of FIG. 9.

[0104] First, an insulating film (402) is formed on a substrate (400) (see (A) in FIG. 8).

[0105] For the substrate (400), a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc., may be used. Alternatively, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, etc., a compound semiconductor substrate made of silicon germanium, etc., or an SOI (Silicon-On-Insulator) substrate, etc., may be used. Alternatively, any of these substrates may be used in which a semiconductor device is further provided.

[0106] The lower insulating film (402) can be formed by a plasma CVD method, sputtering method, etc. using an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide; a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide; or a film mixed with any of the above-described materials. Alternatively, a laminate containing any of the above-described materials may be used, and at least the upper layer of the lower insulating film (402) that is in contact with the multilayer film (404) is preferably formed using a material containing excess oxygen that can function as a source of oxygen for the multilayer film (404).

[0107] Oxygen may be added to the lower insulating film (402) using methods such as ion implantation, ion doping, or plasma-infiltrated ion implantation. By adding oxygen, the lower insulating film (402) can more easily supply oxygen to the multilayer film (404).

[0108] If the surface of the substrate (400) is made of an insulator and there is no influence of impurity diffusion into the multilayer film (404) formed later, it is not necessary to provide an insulating film (402).

[0109] Next, a first oxide film (404a) and an oxide semiconductor film (404b) are formed on the lower insulating film (402) by sputtering, CVD, MBE, ALD, or PLD (see (B) in FIG. 8). At this time, as shown in (B) in FIG. 8, the lower insulating film (402) is slightly over-etched. By over-etching the lower insulating film (402), the gate electrode (410) formed later can easily cover the second oxide film (404c).

[0110] In order to process the first oxide film (404a) and the oxide semiconductor film (404b) into an island shape, first, a film that serves as a hard mask (e.g., a tungsten film) and a resist mask are provided on the oxide semiconductor film (404b), and the film that serves as a hard mask is etched to become a hard mask. Afterward, the resist mask is removed, and the first oxide film (404a) and the oxide semiconductor film (404b) are etched using the hard mask. Afterward, the hard mask is removed. In this step, the hard mask is reduced stepwise according to the etching process, and as a result, the edges of the hard mask become rounded and the surface of the hard mask becomes curved. With this structure, the coverage rate of the second oxide film (404c), the gate insulating film (408), the gate electrode (410), and the oxide insulating film (412) formed on the oxide semiconductor film (404b) can be improved, thereby suppressing the occurrence of shape defects such as disconnection. In addition, the electric field concentration that may occur at the ends of the source electrode (406a) and drain electrode (406b) can be reduced, thereby suppressing the degradation of the transistor.

[0111] In order to form a continuous energy band in a stack comprising a first oxide film (404a) and an oxide semiconductor film (404b), or in a stack comprising a first oxide film (404a), an oxide semiconductor film (404b), and a second oxide film (404c) formed in a later step, these layers need to be formed continuously without exposure to the atmosphere using a multi-chamber film deposition apparatus (e.g., a sputtering apparatus) comprising a load lock chamber. Each chamber of the sputtering apparatus is subjected to a high vacuum (5×10⁻¹⁰) by an adsorption vacuum exhaust pump, such as a cryopump, to remove as much as possible water and the like, which act as impurities in the oxide semiconductor. -7 Pa or more than 1×10 -4 A chamber capable of exhausting to a temperature of Pa or less and heating the substrate to be filmed to 100°C or higher, preferably 500°C or higher is preferred. Alternatively, a combination of a turbo molecular pump and a cold trap is preferably used to prevent backflow of gas containing carbon components or moisture, etc., from the exhaust system into the chamber.

[0112] To obtain a high-purity intrinsic oxide semiconductor, it is necessary not only to evacuate the chamber to a high vacuum but also to purify the sputtering gas. The oxygen or argon gas used as the sputtering gas is purified to have a dew point of -40°C or lower, preferably -80°C or lower, and more preferably -100°C or lower, thereby preventing moisture and the like from entering the oxide semiconductor film as much as possible.

[0113] For the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) formed in a later step, the materials described in Embodiment 1 may be used. For example, an In-Ga-Zn oxide having an atomic ratio of In to Ga and Zn of 1:3:4 or 1:3:2 may be used for the first oxide film (404a), an In-Ga-Zn oxide having an atomic ratio of In to Ga and Zn of 1:1:1 may be used for the oxide semiconductor film (404b), and an In-Ga-Zn oxide having an atomic ratio of In to Ga and Zn of 1:3:4 or 1:3:2 may be used for the second oxide film (404c).

[0114] The oxide semiconductor that can be used for each of the first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) preferably comprises at least indium (In) or zinc (Zn). Alternatively, the oxide semiconductor preferably comprises both In and Zn. In order to reduce fluctuations in the electrical characteristics of a transistor comprising the oxide semiconductor, the oxide semiconductor preferably comprises a stabilizer in addition to In and / or Zn.

[0115] Examples of stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). Other examples of stabilizers are lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0116] As an oxide semiconductor, for example, any of the following may be used: indium oxide, tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide These are oxides, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide.

[0117] In addition, for example, "In-Ga-Zn oxide" here refers to an oxide containing In, Ga, and Zn as main components. The In-Ga-Zn oxide may also contain metal elements other than In, Ga, and Zn. Furthermore, in this specification, a film formed using In-Ga-Zn oxide is also referred to as an IGZO film.

[0118] Or, In M O3(ZnO) m ( m >0, m You may use materials indicated as (not an integer). Also, M represents one or more metallic elements selected from Ga, Fe, Mn, and Co. Or, In2SnO5(ZnO) n ( n >0, n You may use materials represented as an integer.

[0119] In addition, as described in detail in Embodiment 1, the materials are selected so that the first oxide film (404a) and the second oxide film (404c) each have a lower electron affinity than the oxide semiconductor film (404b).

[0120] It is preferable that the oxide film and the oxide semiconductor film be formed by the sputtering method, respectively. As the sputtering method, RF sputtering, DC sputtering, AC sputtering, etc., may be used. In particular, it is preferable to use the DC sputtering method because it can reduce dust generated during film deposition and ensure uniform film thickness.

[0121] When using In-Ga-Zn oxide, the first oxide film (404a), the oxide semiconductor film (404b), and / or the second oxide film (404c) use a material in which the atomic ratio of In to Ga and Zn is any one of 1:1:1, 1:1:1.2, 1:1:1.5, 2:2:1, 3:1:2, 1:3:2, 1:3:4, 1:4:3, 1:5:4, 1:6:6, 2:1:3, 1:6:4, 1:9:6, 1:1:4, and 1:1:2, so that the first oxide film (404a) and the second oxide film (404c) each have a lower electron affinity than the oxide semiconductor film (404b).

[0122] Also, for example, the atomic ratio In:Ga:Zn= a : b : c ( a + b + c The composition of an oxide containing In, Ga, and Zn, where =1) is such that the atomic ratio is In:Ga:Zn= A : B : C ( A + B + C In the case of a vicinity of the composition of oxides containing In, Ga, and Zn where =1), for example a , b , and cgo ( a - A ) 2 +( b - B ) 2 +( c - C ) 2 ≤ r 2 Satisfying the relationship of, r For example, 0.05 is good. The same applies to other oxides.

[0123] It is preferable that the indium content of the oxide semiconductor film (404b) be greater than the indium content of the first oxide film (404a) and the indium content of the second oxide film (404c). In oxide semiconductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and as the proportion of In in the oxide semiconductor increases, the overlap of s-orbitals is likely to increase. Therefore, an oxide having a configuration in which the proportion of In is higher than that of Ga has higher mobility than an oxide having a configuration in which the proportion of In is equal to or lower than that of Ga. For this reason, by using an oxide with a high indium content in the oxide semiconductor film (404b), a transistor with high mobility can be obtained.

[0124] The structure of the oxide semiconductor film is explained below.

[0125] In addition, in this specification, the term "parallel" refers to an angle formed between two straight lines that is -10° or greater and 10° or less, and thus includes cases where the angle is -5° or greater and 5° or less. In addition, the term "perpendicular" refers to an angle formed between two straight lines that is 80° or greater and 100° or less, and thus includes cases where the angle is 85° or greater and 95° or less.

[0126] In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

[0127] Oxide semiconductor films are broadly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. Non-single-crystal oxide semiconductor films include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) films, polycrystalline oxide semiconductor films, microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, etc.

[0128] First, I will explain the CAAC-OS membrane.

[0129] The CAAC-OS film is one of the oxide semiconductor films containing multiple crystalline regions.

[0130] In transmission electron microscope (TEM) images of CAAC-OS films, the boundaries between crystal regions, i.e., grain boundaries, are not clearly observed. Therefore, in CAAC-OS films, a decrease in electron mobility due to grain boundaries is unlikely to occur.

[0131] According to the TEM image (cross-sectional TEM image) of the CAAC-OS film observed in a direction substantially parallel to the sample surface, metal atoms in the crystal portion are arranged in layers. Each layer of metal atoms has a shape that reflects the surface on which the CAAC-OS film is formed (hereinafter, the surface on which the CAAC-OS film is formed is referred to as the formation surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formation surface or the upper surface of the CAAC-OS film.

[0132] Meanwhile, according to TEM images of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (planar TEM images), metal atoms are arranged in triangles or hexagons in the crystal regions. However, there is no regularity in the arrangement of metal atoms between different crystal regions.

[0133] In addition, oriented spots (bright spots) are visible in the electron diffraction pattern of the CAAC-OS film. For example, when electron diffraction by an electron beam with a diameter of 1 nm or more and 30 nm or less (such electron diffraction is also called nanobeam electron diffraction) is performed on the upper surface of the CAAC-OS film, spots are observed (see (A) in Fig. 37).

[0134] From the results of cross-sectional TEM images and planar TEM images, the orientation of the crystal portion in the CAAC-OS film was found.

[0135] The structure of the CAAC-OS film is analyzed by an X-ray diffraction (XRD) device. For example, when a CAAC-OS film containing an InGaZnO4 crystal is analyzed by the out-of-plane method, a peak often appears when the diffraction angle (2θ) is around 31°. This peak originates from the (009) plane of the InGaZnO4 crystal, which indicates that the crystal in the CAAC-OS film has a c-axis orientation and is aligned in a direction in which the c-axis is substantially perpendicular to the formation plane or upper plane of the CAAC-OS film.

[0136] Meanwhile, when a CAAC-OS film is analyzed by the in-plane method in which X-rays enter the sample in a direction substantially perpendicular to the c-axis, a peak often appears when 2θ is around 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. Here, analysis (φ scan) is performed under the condition that the sample is rotated with the normal vector of the sample plane as the axis (φ axis) by fixing 2θ around 56°. When the sample is a single-crystal oxide semiconductor film of InGaZnO4, six peaks appear. These six peaks originate from crystal planes equivalent to the (110) plane. On the other hand, in the case of a CAAC-OS film, even if a φ scan is performed with 2θ fixed around 56°, the peaks are not clearly observed.

[0137] According to the results described above, in a CAAC-OS film having a c-axis orientation, the directions of the a-axis and b-axis between the crystal portions are different, and the c-axis is aligned in a direction parallel to the normal vector of the formation plane or the normal vector of the top plane. Accordingly, each layer of the layered metal atoms observed in the cross-sectional TEM image corresponds to a plane parallel to the ab plane of the crystal.

[0138] In addition, the crystal portion is formed simultaneously with the formation of the CAAC-OS film or through crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned in a direction parallel to the normal vector of the formation plane or the normal vector of the top plane. Therefore, for example, when the shape of the CAAC-OS film is changed by etching, the c-axis does not necessarily have to be parallel to the normal vector of the formation plane or the normal vector of the top plane of the CAAC-OS film.

[0139] Furthermore, the degree of crystallization in the CAAC-OS film does not necessarily have to be uniform. For example, if crystal growth forming the CAAC-OS film occurs near the upper surface of the film, the degree of crystallization near the upper surface may be higher than near the formation surface. Additionally, if impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities were added changes, and the degree of crystallization in the CAAC-OS film varies depending on the region.

[0140] In addition, when a CAAC-OS film having an InGaZnO4 crystal is analyzed by the out-of-plane method, a 2θ peak may be observed near 36° in addition to the 2θ peak near 31°. The 2θ peak near 36° indicates that a portion of the CAAC-OS film contains crystals that do not have a c-axis orientation. In the CAAC-OS film, it is preferable that the 2θ peak appears near 31° and that the 2θ peak does not appear near 36°.

[0141] CAAC-OS films are oxide semiconductor films with low impurity concentrations. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, or transition metal elements. In particular, elements such as silicon, which have a stronger affinity for oxygen than the metal elements contained in the oxide semiconductor film, disrupt the atomic arrangement of the film by depriving it of oxygen, thereby causing a decrease in crystallinity. Furthermore, heavy metals such as iron or nickel, as well as argon and carbon dioxide, have large atomic radii (or molecular radii); when included in the oxide semiconductor film, they disrupt the atomic arrangement and reduce crystallinity. Additionally, impurities contained in the oxide semiconductor film can function as carrier traps or carrier generators.

[0142] Furthermore, the CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film function as carrier traps, or as carrier sources when hydrogen is captured.

[0143] A state characterized by low impurity concentration and low defect state density (a small number of oxygen vacancies) is referred to as a high-purity intrinsic state or substantially high-purity intrinsic state. Oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic can have a low carrier density because they have almost no carrier sources. Consequently, transistors containing such oxide semiconductor films have almost no negative threshold voltage (nearly normalization). Oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have almost no carrier traps. Therefore, transistors containing such oxide semiconductor films exhibit small fluctuations in electrical characteristics and high reliability. Charges trapped by carrier traps in oxide semiconductor films take a long time to be released and can behave like fixed charges. Consequently, transistors containing oxide semiconductor films with high impurity concentrations and high defect state densities may exhibit unstable electrical characteristics.

[0144] By using a CAAC-OS film in the transistor, fluctuations in the transistor's electrical characteristics caused by irradiation with visible or ultraviolet light are small.

[0145] Next, polycrystalline oxide semiconductor films are explained.

[0146] In images obtained by TEM, crystal grain boundaries can be found, for example, in a polycrystalline oxide semiconductor film. In images obtained by TEM, the size of the crystal grain boundaries in the polycrystalline oxide semiconductor film is often, for example, 2 nm or more and 300 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less. In addition, in images obtained by TEM, boundaries between crystals can be found in the polycrystalline oxide semiconductor film.

[0147] The polycrystalline oxide semiconductor film may include multiple crystal grain boundaries, and the orientation of the crystals may differ from the multiple crystal grain boundaries. The structure of the polycrystalline oxide semiconductor film is analyzed using an XRD device. For example, when a polycrystalline oxide semiconductor film containing InGaZnO4 crystals is analyzed by the out-of-plane method, a 2θ peak may appear near 31°, 36°, etc.

[0148] Polycrystalline oxide semiconductor films may possess high electron mobility due to their high crystallinity. Consequently, transistors containing polycrystalline oxide semiconductor films exhibit high field-effect mobility. Furthermore, impurities may segregate at the grain boundaries between crystals in the polycrystalline oxide semiconductor film. Additionally, the grain boundaries of the polycrystalline oxide semiconductor film can become defective. Since the grain boundaries of the polycrystalline oxide semiconductor film can function as carrier traps or carrier sources, transistors containing polycrystalline oxide semiconductor films may exhibit greater variation in electrical characteristics and lower reliability compared to transistors containing CAAC-OS films.

[0149] Next, microcrystalline oxide semiconductor films are described.

[0150] In images obtained by TEM, there are cases where crystal regions cannot be clearly identified in microcrystalline oxide semiconductor films. The size of the crystal regions in microcrystalline oxide semiconductor films is often between 1 nm and 100 nm, or between 1 nm and 10 nm. An oxide semiconductor film containing nanocrystals (nc) that are microcrystalline and have a size between 1 nm and 10 nm, or between 1 nm and 3 nm, is specifically called an nc-OS (nanocrystalline Oxide Semiconductor) film. In images of an nc-OS film obtained by TEM, crystal grain boundaries, for instance, cannot be clearly observed.

[0151] In nc-OS films, minute regions (e.g., regions with a size of 1 nm or more and 10 nm or less, particularly regions with a size of 1 nm or more and 3 nm or less) exhibit periodicity in their atomic arrangement. Furthermore, because there is no regularity in crystal orientation between different crystal regions in nc-OS films, orientation across the entire film is not observed. Consequently, nc-OS films may not be distinguishable from amorphous oxide semiconductor films depending on the analysis method. For example, when structural analysis is performed on an nc-OS film using the out-of-plane method with an XRD device that uses X-rays with a diameter larger than that of the crystal region, peaks indicating crystal planes do not appear. Additionally, a halo pattern is observed in the electron diffraction pattern of the nc-OS film (also called the selected region electron diffraction pattern) obtained using an electron beam with a probe diameter larger than that of the crystal region (e.g., 50 nm or more). Meanwhile, spots are observed in the nanobeam electron diffraction pattern of the nc-OS film obtained by using an electron beam having a probe diameter that is approximately equal to or less than the diameter of the crystal region. Additionally, in the nanobeam electron diffraction pattern of the nc-OS film, a region of high brightness in a circular (ring) pattern may be observed. Furthermore, in the nanobeam electron diffraction pattern of the nc-OS film, multiple spots may be seen within the ring-shaped region (see Fig. 37 (B)).

[0152] Since nc-OS films are oxide semiconductor films with higher regularity than amorphous oxide semiconductor films, nc-OS films have a lower defect state density than amorphous oxide semiconductor films. However, because there is no regularity of crystal orientation between different crystal regions in nc-OS films, nc-OS films have a higher defect state density than CAAC-OS films.

[0153] Therefore, nc-OS films may have a higher carrier density than CAAC-OS films. Oxide semiconductor films with high carrier density may possess high electron mobility. Consequently, transistors containing nc-OS films may have high field-effect mobility. Since nc-OS films have a higher defect state density than CAAC-OS films, they may contain many carrier traps. Consequently, transistors containing nc-OS films exhibit greater variation in electrical characteristics and lower reliability compared to transistors containing CAAC-OS films. Because nc-OS films can be formed even with a relatively large amount of impurities, they are easier to form than CAAC-OS films, making them suitable for specific purposes. Therefore, semiconductor devices containing transistors with nc-OS films can be manufactured with high productivity.

[0154] Next, an amorphous oxide semiconductor film is described.

[0155] Amorphous oxide semiconductor films have an irregular atomic arrangement and do not possess crystalline regions. For example, amorphous oxide semiconductor films do not have specific states like quartz.

[0156] In the image obtained by TEM, crystalline regions cannot be found in the amorphous oxide semiconductor film.

[0157] When structural analysis of an amorphous oxide semiconductor film is performed using the out-of-plane method with an XRD device, peaks indicating crystal planes do not appear. Halo patterns are visible in the electron diffraction pattern of the amorphous oxide semiconductor film. Furthermore, halo patterns, rather than spots, are visible in the nanobeam electron diffraction pattern of the amorphous oxide semiconductor film.

[0158] Amorphous oxide semiconductor films contain high concentrations of impurities such as hydrogen. In addition, amorphous oxide semiconductor films have high-density defect states.

[0159] Oxide semiconductor films with high impurity concentrations and high-density defect states have many carrier traps or many carrier sources.

[0160] Therefore, amorphous oxide semiconductor films have a higher carrier density than nc-OS films. Consequently, transistors containing amorphous oxide semiconductor films are prone to becoming normal ions. Thus, such amorphous oxide semiconductor layers may be applied to transistors that require normal ion formation. Since amorphous oxide semiconductor films have a high density of defect states, carrier traps may increase. Consequently, transistors containing amorphous oxide semiconductor films exhibit greater variation in electrical characteristics and lower reliability compared to transistors containing CAAC-OS or nc-OS films.

[0161] Next, a single-crystal oxide semiconductor film is described.

[0162] Single-crystal oxide semiconductor films possess low impurity concentrations and low defect state densities (a small amount of oxygen vacancies). Consequently, carrier density can be reduced. Therefore, transistors containing single-crystal oxide semiconductor films are less likely to become normal ions. Furthermore, carrier trapping can be reduced because single-crystal oxide semiconductor films have low impurity concentrations and low defect state densities. Consequently, transistors containing single-crystal oxide semiconductor films exhibit low variation in electrical characteristics, resulting in high reliability.

[0163] Furthermore, the density of oxide semiconductor films increases if they are almost defect-free. The density of oxide semiconductor films increases if they have high crystallinity. The density of oxide semiconductor films increases if the concentration of impurities, such as hydrogen, is low. Single-crystal oxide semiconductor films have a higher density than CAAC-OS films. CAAC-OS films have a higher density than microcrystalline oxide semiconductor films. Polycrystalline oxide semiconductor films have a higher density than microcrystalline oxide semiconductor films. Microcrystalline oxide semiconductor films have a higher density than amorphous oxide semiconductor films.

[0164] In addition, the oxide semiconductor film may be a stacked film comprising two or more films, such as an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[0165] When an oxide semiconductor film has multiple structures, the structures can sometimes be analyzed using nanobeam electron diffraction.

[0166] FIG. 38 (A) illustrates a transmission electron diffraction measuring device comprising an electron gun chamber (10), an optical system (12) below the electron gun chamber (10), a sample chamber (14) below the optical system (12), an optical system (16) below the sample chamber (14), an observation chamber (20) below the optical system (16), a camera (18) installed in the observation chamber (20), and a film chamber (22) below the observation chamber (20). The camera (18) is provided facing the interior of the observation chamber (20). Additionally, the film chamber (22) does not necessarily need to be provided.

[0167] Fig. 38 (B) illustrates the internal structure of the transmission electron diffraction measuring device shown in Fig. 38 (A). In the transmission electron diffraction measuring device, a material (28) located in the sample chamber (14) is irradiated with electrons emitted from an electron gun installed in the electron gun chamber (10) through an optical system (12). The electrons passing through the material (28) enter a fluorescent plate (32) provided in the observation chamber (20) through an optical system (16). On the fluorescent plate (32), a transmission electron diffraction pattern is measured by the appearance of a pattern corresponding to the intensity of the incoming electrons.

[0168] A camera (18) is installed facing the fluorescent plate (32) and can take a picture of the pattern appearing on the fluorescent plate (32). The angle formed by the straight line passing through the center of the lens of the camera (18) and the center of the fluorescent plate (32) and the upper surface of the fluorescent plate (32) is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70° or less. As the angle decreases, the distortion of the transmission electron diffraction pattern captured by the camera (18) increases. In addition, if the angle is obtained in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. In addition, the camera (18) may be provided in the film chamber (22). For example, the camera (18) may be provided in the film chamber (22) so as to face the incident direction of the electron (24). In this case, a transmission electron diffraction pattern with less distortion can be captured from the back surface of the fluorescent plate (32).

[0169] A holder for fixing a sample material (28) is provided in the sample chamber (14). The holder transmits electrons passing through the material (28). The holder may have the function of moving the material (28) in, for example, X-axis, Y-axis, and Z-axis directions. The movement function of the holder may have the precision to move the material in, for example, ranges of 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, and 100 nm to 1 μm. It is desirable that this range be determined as an optimal range for the structure of the material (28).

[0170] Next, a method for measuring the transmission electron diffraction pattern of a material using the transmission electron diffraction measuring device described above will be explained.

[0171] For example, as shown in (B) of FIG. 38, a change in the structure of the material can be observed by changing (scanning) the portion of the irradiation of the nanobeam electron (24) in the material. At this time, if the material (28) is a CAAC-OS film, a diffraction pattern as shown in (A) of FIG. 37 is observed. If the material (28) is an nc-OS film, a diffraction pattern as shown in (B) of FIG. 37 is observed.

[0172] Even if the material (28) is a CAAC-OS film, there are cases where a diffraction pattern similar to that of an nc-OS film is partially observed. Therefore, whether the CAAC-OS film is of good quality can be determined by the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a given area (also called the CAAC ratio). For a high-quality CAAC-OS film, for example, the CAAC ratio is 60% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. In addition, the ratio of the area where a diffraction pattern different from that of the CAAC-OS film is observed is called the non-CAAC ratio.

[0173] For example, transmission electron diffraction patterns were obtained by scanning the upper surface of a sample containing a CAAC-OS film obtained immediately after deposition (indicated as "as-depo"), and the upper surface of a sample containing a CAAC-OS that had been heat-treated at 350°C or 450°C. Here, the diffraction pattern was observed by scanning at a speed of 5 nm / sec for 60 seconds, and the CAAC ratio was obtained by converting the obtained diffraction pattern into a still image every 0.5 seconds. In addition, a nanobeam with a probe diameter of 1 nm was used as the electron beam.

[0174] The CAAC ratio for each sample is shown in Fig. 39. This result indicates that the CAAC ratio obtained after heat treatment at 450°C is higher than the CAAC ratio obtained immediately after film formation or after heat treatment at 350°C. In other words, heat treatment at a temperature higher than 350°C (e.g., 400°C or higher) reduces the non-CAAC ratio (increases the CAAC ratio). Here, most of the diffraction patterns different from the CAAC-OS film are diffraction patterns similar to the nc-OS film. Therefore, the above results suggest that, due to the influence of the structure of adjacent regions, regions having a structure similar to the nc-OS film are rearranged by heat treatment, and these regions become CAAC.

[0175] In some cases, the structure of an oxide semiconductor film having multiple structures can be analyzed using this measurement method.

[0176] A CAAC-OS film can be formed by a sputtering method using, for example, a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, a crystalline region included in the sputtering target may be peeled off from the target along the ab plane; in other words, sputtering particles having a plane parallel to the ab plane (plate-shaped sputtering particles or pellet-shaped sputtering particles) may be peeled off from the target. In this case, the plate-shaped sputtering particles or the pellet-shaped sputtering particles become charged and reach the substrate while maintaining this crystalline state without aggregating into the plasma, thereby forming a CAAC-OS film.

[0177] After the oxide semiconductor film (404b) is formed, a first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. Alternatively, the first heat treatment may be performed by performing another heat treatment in an atmosphere containing 10 ppm or more of an oxidizing gas to replenish the oxygen lost after the heat treatment is performed in an inert gas atmosphere. Through the first heat treatment, the crystallinity of the oxide semiconductor film (404b) may be improved, and impurities such as hydrogen and water may be removed from the underlying insulating film (402) and the first oxide film (404a). The first heat treatment may be performed before etching to form the oxide semiconductor film (404b).

[0178] A first conductive film, which serves as a source electrode (406a) and a drain electrode (406b), is formed on the first oxide film (404a) and the oxide semiconductor film (404b). For the first conductive film, an alloy material containing Al, Cr, Cu, Ta, Ti, Mo, W, or any of these as a main component may be used. For example, a titanium film with a thickness of 100 nm is formed by a sputtering method, etc. Alternatively, a tungsten film may be formed by a CVD method.

[0179] Afterwards, the first conductive film is etched so as to be divided on the oxide semiconductor film (404b) to form a source electrode (406a) and a drain electrode (406b) (see (C) in FIG. 8). At this time, the first conductive film may be over-etched so that the lower insulating film (402) is partially etched.

[0180] Next, a second oxide film (403c) is formed on the first oxide film (404a), the oxide semiconductor film (404b), the source electrode (406a), and the drain electrode (406b).

[0181] Additionally, a second heat treatment may be performed after the second oxide film (403c) is formed. The second heat treatment may be performed under conditions similar to those of the first heat treatment. The second heat treatment can remove impurities such as hydrogen and water from the second oxide film (403c). Additionally, impurities such as hydrogen and water can be further removed from the first oxide film (404a) and the oxide semiconductor film (404b).

[0182] Next, an insulating film (407) that becomes the gate insulating film (408) is formed on the second oxide film (403c) (see (A) in FIG. 9). The insulating film (407) may be formed using aluminum oxide, magnesium oxide, silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. The insulating film (407) may be a laminate comprising any of the materials described above. The insulating film (407) may be formed by sputtering, CVD, MBE, ALD, PLD, etc. The coverage rate can be improved and as shown in (A) in FIG. 5, T GI1 and T GI2 It is preferable to form a gate insulating film (408) by selecting raw materials, temperature, pressure, distance between electrodes, applied power, etc., so that they are substantially equivalent to each other. For example, the coverage rate can be improved by forming the film under high temperature and high pressure conditions within a range where the film quality as a gate insulating film can be maintained.

[0183] Next, a second conductive film (409) that serves as a gate electrode (410) is formed on the insulating film (407) (see (B) in FIG. 9). For the second conductive film (409), an alloy material containing Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Ta, W, or any of these as a main component may be used. The second conductive film (409) may be formed by a sputtering method, a CVD method, etc. A stack including a conductive film containing any of the above-described materials and a conductive film containing nitrogen, or a conductive film containing nitrogen may be used for the second conductive film (409).

[0184] Afterwards, the second conductive film (409) is selectively etched using a resist mask to form a gate electrode (410) (see (C) in FIG. 9).

[0185] Next, the insulating film (407) is selectively etched using the resist mask or the gate electrode (410) as a mask to form the gate insulating film (408).

[0186] Next, the second oxide film (403c) is etched using the resist mask or gate electrode (410) as a mask to form the second oxide film (404c).

[0187] The upper portion of the second oxide film (404c) is aligned with the lower portion of the gate insulating film (408). The upper portion of the gate insulating film (408) is aligned with the lower portion of the gate electrode (410). Although the gate insulating film (408) and the second oxide film (404c) are formed using the gate electrode (410) as a mask, the gate insulating film (408) and the second oxide film (404c) may be formed before the second conductive film (409) is formed.

[0188] Next, an oxide insulating film (412) is formed on the source electrode (406a), drain electrode (406b), and gate electrode (410) (see (B) in FIG. 1). The material and method for the oxide insulating film (412) may be similar to that of the underlying insulating film (402). The oxide insulating film (412) may be formed using an oxide insulating film comprising aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, silicon nitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, or nitrogen. The oxide insulating film (412) may be formed by sputtering, CVD, MBE, ALD, or PLD, and it is preferable that it be formed containing excess oxygen so as to supply oxygen to the multilayer film (404).

[0189] Oxygen may be added to the oxide insulating film (412) using methods such as ion implantation, ion doping, or plasma-infiltrated ion implantation. By adding oxygen, the oxide insulating film (412) can more easily supply oxygen to the multilayer film (404).

[0190] Next, a third heat treatment may be performed. The third heat treatment may be performed under conditions similar to those of the first heat treatment. By the third heat treatment, excess oxygen can be easily released from the non-insulating film (402), the gate insulating film (408), and the oxide insulating film (412), thereby reducing oxygen vacancies in the multilayer film (404).

[0191] Through the process described above, the transistor (450) illustrated in (A) to (C) of FIG. 1 can be manufactured.

[0192] This embodiment may be appropriately combined with any of the other embodiments in this specification.

[0193] (Embodiment 3)

[0194] In this embodiment, a transistor having a structure different from the transistor described in Si-form 1 is described.

[0195] FIGS. 14 (A) to (C) are top and cross-sectional views of a transistor of one embodiment of the present invention. FIGS. 14 (A) is a top view, FIGS. 14 (B) is a cross-section along the dotted line AB in FIGS. 14 (A), and FIGS. 14 (C) is a cross-section along the dotted line CD in FIGS. 14 (A). Additionally, to simplify the drawings, several components are not shown in the top view of FIGS. 14 (A). The direction of the dotted line AB is referred to as the channel length direction, and the direction of the dotted line CD is referred to as the channel width direction.

[0196] The transistor (550) illustrated in (A) to (C) of FIG. 14 comprises: a lower insulating film (402) on a substrate (400); a first oxide film (404a) and an oxide semiconductor film (404b) on the lower insulating film (402); a source electrode (406a) and a drain electrode (406b) on the first oxide film (404a) and the oxide semiconductor film (404b); a second oxide film (404c) on the oxide semiconductor film (404b), the source electrode (406a), and the drain electrode (406b); a gate insulating film (408) on the second oxide film (404c); a gate electrode (410) on the gate insulating film (408); and a barrier film (414) on the source electrode (406a), the drain electrode (406b), the second oxide film (404c), and the gate electrode (410). A sidewall insulating film (416) covering the sides of a first oxide film (404a), an oxide semiconductor film (404b), a source electrode (406a), and a drain electrode (406b) via a barrier film (414); a sidewall insulating film (418) covering the sides of a second oxide film (404c), a gate insulating film (408), and a gate electrode (410) via a barrier film (414); an oxide insulating film (412) on the source electrode (406a), the drain electrode (406b), the gate electrode (410), the sidewall insulating film (416), and the sidewall insulating film (418); an electrode (419a) and an electrode (419b) embedded in an opening formed in the oxide insulating film (412) and electrically connected to the source electrode (406a) and the drain electrode (406b), respectively, through the opening; It includes wiring (420a) and wiring (420b) electrically connected to electrodes (419a) and (419b), respectively. The first oxide film (404a), the oxide semiconductor film (404b), and the second oxide film (404c) are collectively referred to as a multilayer film (404).

[0197] The oxide semiconductor film (404b) has rounded ends and a semicircular shape. This structure can improve the coverage rate between the gate insulating film (408) and the gate electrode (410) formed on the oxide semiconductor film (404b).

[0198] The barrier film (414) is preferably formed as an insulating film having a blocking effect against hydrogen, water, and oxygen. Typically, an aluminum oxide film is used. The aluminum oxide film is an insulating film that has a blocking effect as well as a function to supply oxygen. An aluminum oxide film containing silicon oxide, formed using a target mixed with aluminum oxide and silicon oxide, may be used. In this case, the silicon oxide content is preferably 0.1 wt% or more and 30 wt% or less.

[0199] Although the barrier film (414) in contact with the side of the multilayer film (404) and the gate electrode (410) may have a low coverage rate, hydrogen, water, and oxygen can be blocked by covering the portion with a low coverage rate with a sidewall insulating film (416) and a sidewall insulating film (418). For the sidewall insulating film (416) and the sidewall insulating film (418), materials similar to those of the lower insulating film (402) and the gate insulating film (408) may be used.

[0200] Electrodes (419a) and (419b) are electrically connected to the source electrode (406a) and drain electrode (406b), respectively. Wiring (420a) and (420b) are electrically connected to the electrodes (419a) and (419b), respectively. In microfabrication, an opening is formed in the oxide insulating film (412) and the wiring (420a) and (420b) are formed to be electrically connected to the source electrode (406a) and drain electrode (406b) through the opening. However, the wiring (420a) and (420b) do not reach the bottom of the opening, so the wiring (420a) and (420b) cannot be electrically connected to the source electrode (406a) and drain electrode (406b), respectively. For this reason, after the opening is filled with electrodes (419a) and (419b), wiring (420a) and wiring (420b) need to be formed. Additionally, if a material is used that allows wiring (420a) and wiring (420b) to be connected to source electrode (406a) and drain electrode (406b), respectively, electrodes (419a) and (419a) are not required.

[0201] For the electrode (419a), electrode (419b), wiring (420a), and wiring (420b), a material similar to that of the source electrode (406a), drain electrode (406b), and gate electrode (410) may be used.

[0202] The structure of a transistor (560) in which the sidewall insulating film (416) is not provided, as shown in (A) of FIG. 18, may be adopted. Alternatively, the structure of a transistor (570) in which the sidewall insulating film (416) and the sidewall insulating film (418) are not provided, as shown in (B) of FIG. 18, may be adopted.

[0203] Alternatively, the structure of a transistor (580) in which electrodes (419a) and (419b) extend to source electrode (406a) and drain electrode (406b), as shown in (C) of FIG. 18, may be adopted.

[0204] This embodiment may be appropriately combined with any of the other embodiments in this specification.

[0205] (Embodiment 4)

[0206] In this embodiment, a method for forming a transistor (550) as described in Embodiment 3 with reference to FIG. 14 (A) to (C) is explained with reference to FIG. 15 (A) to (C), FIG. 16 (A) to (C), and FIG. 17 (A) to (C).

[0207] First, an under-insulating film (402), a first oxide film (403a), and an oxide semiconductor film (403b) are formed on a substrate (400) (see (A) in FIG. 15). For the method and materials for forming the substrate (400), the under-insulating film (402), the first oxide film (403a), and the oxide semiconductor film (403b), the above-described embodiment may be referenced.

[0208] A conductive film that serves as the source electrode (406a) and drain electrode (406b) is formed on the oxide semiconductor film (403b). A conductive film (405a) and a conductive film (405b) are formed by etching the conductive film in the region overlapping with the region where the channel is formed (see (B) in FIG. 15). For the method and material for forming the conductive film that serves as the source electrode (406a) and drain electrode (406b), the above-described embodiment may be referenced.

[0209] Next, a resist mask is formed on the conductive film (405a) and the conductive film (405b), and the first oxide film (403a), the oxide semiconductor film (403b), the conductive film (405a), and the conductive film (405b) are selectively etched to form the first oxide film (404a), the oxide semiconductor film (404b), the source electrode (406a), and the drain electrode (406b) (see (C) of FIG. 15). At this time, the resist formed thinly and finely gradually shrinks in size as it is etched, and as a result, the ends of the source electrode (406a) and the drain electrode (406b) may become rounded and curved. With this structure, the coverage rate of the second oxide film (404c), gate insulating film (408), gate electrode (410), and oxide insulating film (412) formed on the source electrode (406a) and drain electrode (406b) can be improved, thereby suppressing the occurrence of shape defects such as disconnection.

[0210] Next, a second oxide film (403c) and an insulating film (407) are formed on the first oxide film (404a), the oxide semiconductor film (404b), the source electrode (406a), and the drain electrode (406b) (see (A) in FIG. 16). For the method and materials for forming the second oxide film (403c) and the insulating film (407), reference may be made to embodiments 1 to 3.

[0211] Additionally, a second heat treatment may be performed after the second oxide film (403c) is formed. The second heat treatment may be performed under conditions similar to those of the first heat treatment. The second heat treatment can remove impurities such as hydrogen and water from the second oxide film (404c). Additionally, impurities such as hydrogen and water can be further removed from the first oxide film (404a) and the oxide semiconductor film (404b).

[0212] A second conductive film that becomes a gate electrode (410) is formed on an insulating film (407), and the gate electrode (410) is formed by selectively etching it using a resist mask (see (B) in FIG. 16). For the method and material of forming the gate electrode (410), reference can be made to embodiments 1 to 3.

[0213] Next, the insulating film (407) is selectively etched using the resist mask or the gate electrode (410) as a mask to form the gate insulating film (408).

[0214] Next, the second oxide film (403c) is etched using the resist mask or gate electrode (410) as a mask to form the second oxide film (404c).

[0215] Next, a barrier film (414) is formed on the insulating film (402), source electrode (406a), drain electrode (406b), and gate electrode (410) (see (C) of FIG. 16).

[0216] Since the barrier film (414) is an insulating film having a blocking effect against hydrogen, water, and oxygen, it can prevent oxygen contained in the multilayer film (404), the lower insulating film (402), and the gate insulating film (408) from diffusing to the outside, so that oxygen is effectively supplied to the oxide semiconductor film and oxygen vacancies can be reduced, resulting in excellent electrical characteristics. Therefore, a highly reliable semiconductor device can be provided.

[0217] Next, by providing insulating films that become sidewall insulating films (416) and sidewall insulating films (418) and performing a highly anisotropic etching process, sidewall insulating films (416) and sidewall insulating films (418) can be formed on the sides of a multilayer film (404), source electrode (406a), drain electrode (406b), gate insulating film (408), and gate electrode (410) with the barrier film (414) interposed (see (A) of FIG. 17).

[0218] Next, an oxide insulating film (412) is formed on the barrier film (414) (see (B) in FIG. 17). For the method and material for forming the oxide insulating film (412), refer to embodiments 1 to 3.

[0219] Next, a third heat treatment may be performed. The third heat treatment may be performed under conditions similar to those of the first heat treatment. By the third heat treatment, excess oxygen can be easily released from the non-insulating film (402), the gate insulating film (408), and the oxide insulating film (412), thereby reducing oxygen vacancies in the multilayer film (404).

[0220] Next, an opening is formed in the oxide insulating film (412) and the barrier film (414), and electrodes (419a) and (419b), which are electrically connected to the source electrode (406a) and the drain electrode (406b) respectively through the opening, are formed on the oxide insulating film (412) and within the opening.

[0221] By forming a conductive film that serves as an electrode (419a) and an electrode (419b) on the oxide insulating film (412) and within the opening, the electrode (419a) and the electrode (419b) are embedded in the opening, and a removal (friction) treatment is performed on the conductive film to remove a portion of the conductive film and expose the oxide insulating film (412) (see (C) in FIG. 17).

[0222] For the removal process, it is preferable to use Chemical Mechanical Polishing (CMP).

[0223] In addition, in the present embodiment, CMP treatment is performed to remove a portion of the conductive film, but another removal treatment may be employed. Alternatively, friction treatment such as CMP treatment may be combined with etching (dry etching or wet etching) treatment or plasma treatment. For example, after CMP treatment, dry etching treatment or plasma treatment (e.g., reverse sputtering) may be performed to improve the flatness of the processed surface. When removal treatment, etching treatment, plasma treatment, etc. are combined with CMP treatment, the process notation is not particularly limited and may be appropriately set according to the material, film thickness, and surface roughness of the conductive film. Alternatively, most of the conductive film may be removed by CMP treatment and the remaining portion of the conductive film may be removed by dry etching treatment.

[0224] Additionally, the CMP treatment may be performed only once or multiple times. If the CMP treatment is performed multiple times, it is preferable that the first friction be performed at a high friction rate and the last friction be performed at a low friction rate. By performing friction steps with a combination of different friction rates, the surface of the conductive film (electrode (419a) and electrode (419b)) can be further improved.

[0225] Next, wiring (420a) and wiring (420b) electrically connected to electrode (419a) and electrode (419b), respectively, are formed on the oxide insulating film (412), electrode (419a), and electrode (419b) (see (B) of FIG. 14).

[0226] Through the process described above, the transistor (550) illustrated in (A) to (C) of FIG. 14 can be manufactured.

[0227] This embodiment may be appropriately combined with any of the other embodiments in this specification.

[0228] (Embodiment 5)

[0229] In this embodiment, an example of a circuit including a transistor of one form of the present invention is described with reference to the drawings.

[0230] FIG. 19 (A) is a circuit diagram of a semiconductor device, and FIG. 19 (C) and (D) are cross-sectional views of the semiconductor device, respectively. FIG. 19 (C) and (D) respectively show a cross-sectional view of a transistor (450) in the channel length direction on the left and a cross-sectional view of a transistor (450) in the channel width direction on the right. In the circuit diagram, "OS" is written next to the transistor to clearly show that the transistor contains an oxide semiconductor.

[0231] The semiconductor devices illustrated in (C) and (D) of FIG. 19 each include a transistor (2200) comprising a first semiconductor material at the bottom and a transistor comprising a second semiconductor material at the top. Here, an example is described in which the transistor (450) described as an example in Embodiment 1 is used as the transistor comprising the second semiconductor material.

[0232] Here, it is preferable that the first semiconductor material and the second semiconductor material have different energy gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (e.g., silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide), and the second semiconductor material may be an oxide semiconductor as described in Embodiment 1. A transistor including single-crystal silicon, etc., as a material other than an oxide semiconductor can easily operate at high speed. Meanwhile, a transistor including an oxide semiconductor has a low off-state current.

[0233] Here, the transistor (2200) is a p-channel transistor, but it goes without saying that an n-channel transistor can be used to form a circuit with a different configuration. The specific structure of the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, is not limited to that described herein, except for the use of the transistor described in Embodiment 1, which is formed using an oxide semiconductor.

[0234] Figures 19 (A), (C), and (D) each illustrate examples of configurations of so-called CMOS circuits in which a p-channel transistor and an n-channel transistor are connected in series and the gates of the transistors are connected.

[0235] A transistor using an oxide semiconductor of one embodiment of the present invention has a high on-state current capable of achieving high-speed operation of the circuit.

[0236] In the structure illustrated in (C) of FIG. 19, a transistor (450) is provided over a transistor (2200) via an insulating film (2201). Wiring (2202) is provided between the transistor (2200) and the transistor (450). Wiring and electrodes above and below the insulating film are electrically connected through plugs (2203) embedded in the insulating films. An insulating film (2204) covering the transistor (450), wiring (2205) over the insulating film (2204), and wiring (2206) formed by processing a conductive film such as a pair of electrodes of the transistor (450) are provided.

[0237] By stacking two transistors using the method described above, the area occupied by the circuit can be reduced, allowing multiple circuits to be arranged at a high density.

[0238] In (C) of FIG. 19, one of the source and drain of the transistor (450) is electrically connected to one of the source and drain of the transistor (2200) through the wiring (2202) and plug (2203). The gate of the transistor (450) is electrically connected to the gate of the transistor (2200) through the wiring (2205), wiring (2206), plug (2203), wiring (2202), etc.

[0239] In the configuration shown in (D) of FIG. 19, the opening in which the plug (2203) is embedded is provided in the gate insulating layer of the transistor (450), and the gate of the transistor (450) comes into contact with the plug (2203). With this configuration, circuit integration can be easily achieved, and the length and number of wiring and plugs can be reduced compared to the configuration shown in (C) of FIG. 19, so that the circuit can operate at high speed.

[0240] Additionally, various circuits can be formed when the connection between the electrodes of the transistor (450) and the transistor (2200) changes from the configuration shown in (C) or (D) of FIG. 19. For example, a circuit having a configuration in which the source and drain of a transistor are connected to the source and drain of another transistor, as shown in (B) of FIG. 19, can operate as a so-called analog switch.

[0241] A semiconductor device having an image sensor function for reading information about an object can be manufactured using a transistor described in any of the embodiments described above.

[0242] FIG. 24 illustrates an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0243] In the photodiode (602), one electrode is electrically connected to the photodiode reset signal line (658), and the other electrode is electrically connected to the gate of the transistor (640). One of the source and drain of the transistor (640) is electrically connected to the photosensor reference signal line (672), and the other of the source and drain of the transistor (640) is electrically connected to one of the source and drain of the transistor (656). The gate of the transistor (656) is electrically connected to the gate signal line (659), and the other of the source and drain of the transistor (656) is electrically connected to the photosensor output signal line (671).

[0244] As a photodiode (602), for example, a pin photodiode can be used in which a semiconductor layer having p-type conductivity, a high-resistance semiconductor layer (a semiconductor layer having i-type conductivity), and a semiconductor layer having n-type conductivity are stacked.

[0245] Information about an object can be read by detecting light entering the photodiode (602). Additionally, a light source such as a backlight can be used when reading information about an object.

[0246] As each of the transistors (640) and (656), a transistor in which the channel is formed in an oxide semiconductor, as described in any of the embodiments above, may be used. In FIG. 24, "OS" is written next to transistors (640) and (656) so that transistors (640) and (656) can be identified as transistors containing an oxide semiconductor.

[0247] It is preferable that each of the transistors (640) and (656) is one of the transistors described in the above-described embodiment, in which an oxide semiconductor film is electrically covered by the gate electrode. Since the oxide semiconductor film has a rounded top portion and a curved surface, the coverage rate with the film formed on the oxide semiconductor film can be improved. In addition, electric field concentration that may occur at the ends of the source electrode and drain electrode can be reduced, thereby suppressing the degradation of the transistor. Therefore, fluctuations in the electrical characteristics of the transistors (640) and (656) are suppressed, and the transistors (640) and (656) become electrically stable. The semiconductor device having an image sensor function shown in FIG. 24 can have high reliability by including the transistors.

[0248] This embodiment may be appropriately combined with any of the other embodiments in this specification.

[0249] (Embodiment 6)

[0250] In this embodiment, a semiconductor device (memory device) including a transistor of one form of the present invention, capable of maintaining stored data even without power, and having an unlimited number of write cycles is described with reference to the drawings.

[0251] Figure 20 is a circuit diagram of a semiconductor device.

[0252] The semiconductor device illustrated in FIG. 20 includes a transistor (3200) comprising a first semiconductor material, a transistor (3300) comprising a second semiconductor material, and a capacitor (3400). Additionally, the transistor described in Embodiment 1 can be used as the transistor (3300).

[0253] The transistor (3300) is a top-gate transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. Because the off-state current of the transistor (3300) is low, data stored by such a transistor can be maintained for a long period of time. In other words, a refresh operation is not required in the semiconductor memory, or the frequency of the refresh operation can be made very low, leading to a sufficient reduction in power consumption.

[0254] In FIG. 20, the first wire (3001) is electrically connected to the source electrode of the transistor (3200). The second wire (3002) is electrically connected to the drain electrode of the transistor (3200). The third wire (3003) is electrically connected to one of the source electrode and drain electrode of the transistor (3300). The fourth wire (3004) is electrically connected to the gate electrode of the transistor (3300). The gate electrode of the transistor (3200) and the other of the source electrode and drain electrode of the transistor (3300) are electrically connected to one electrode of the capacitor (3400). The fifth wire (3005) is electrically connected to the other electrode of the capacitor (3400).

[0255] By utilizing the feature that the semiconductor device in FIG. 20 can maintain the potential of the gate electrode of the transistor (3200), data can be recorded, maintained, and read as follows.

[0256] The recording and maintenance of data is described. First, the potential of the fourth wire (3004) is set to a potential at which the transistor (3300) turns on, thereby turning on the transistor (3300). Accordingly, the potential of the third wire (3003) is supplied to the gate electrode of the transistor (3200) and the capacitor (3400). That is, a predetermined charge is supplied (recorded) to the gate electrode of the transistor (3200). Here, one of two types of charges (hereinafter referred to as Low level charge and High level charge) providing different potential levels is supplied. After that, the potential of the fourth wire (3004) is set to a potential at which the transistor (3300) turns off, thereby turning off the transistor (3300). After that, the charge supplied to the gate electrode of the transistor (3200) is maintained (maintained).

[0257] Because the off-state current of the transistor (3300) is very low, the charge on the gate electrode of the transistor (3200) is maintained for a long time.

[0258] Next, the reading of data is explained. As a predetermined potential (positive potential) is supplied to the first wiring (3001) and an appropriate potential (read potential) is supplied to the fifth wiring (3005), the potential of the second wiring (3002) changes according to the amount of charge maintained at the gate electrode of the transistor (3200). Generally, when an n-channel transistor is used as the transistor (3200), this is the apparent threshold voltage (V) when a high-level charge is applied to the gate electrode of the transistor (3200). th_H ) is the apparent threshold voltage (V) when a low-level charge is applied to the gate electrode of the transistor (3200). th_L This is because it becomes lower than ). Here, the apparent threshold voltage refers to the potential of the fifth wire (3005) required to turn on the transistor (3200). Therefore, the potential of the fifth wire (3005) is V th_H and V th_LBy setting the potential (V0) to be between V0 and V0, the charge supplied to the gate electrode of the transistor (3200) can be determined. For example, in the recording, a high-level charge is supplied and the potential of the fifth wire (3005) is V0 (>V th_H ) In the case where ), the transistor (3200) is turned on. In the recording, when a low level charge is supplied, the potential of the fifth wire (3005) is V0 ( <V th_L Even if it becomes ), the transistor (3200) remains off. Therefore, by determining the potential of the second wiring (3002), the data maintained at the gate electrode can be read.

[0259] In addition, when memory cells are arranged in an array, it is necessary to be able to read only the data of the desired memory cell. In the fifth wiring (3005) when data is not read, a potential at which the transistor (3200) is turned off regardless of the state of the gate electrode, i.e., V th_H A lower potential may be supplied. Or, a potential at which the transistor (3200) turns on regardless of the state of the gate electrode, i.e., V th_L A higher potential may be supplied to the 5th wiring (3005).

[0260] The semiconductor device described in this embodiment can maintain stored data for a very long time by including a transistor having a channel forming region formed using an oxide semiconductor and having a very low off-state current. In other words, refresh operations become unnecessary or the frequency of refresh operations can be reduced significantly, leading to a sufficient reduction in power consumption. In addition, stored data can be maintained for a long time even when power is not supplied (however, it is preferable that the potential be fixed).

[0261] Furthermore, in the semiconductor device described in this embodiment, high voltage is not required to record data, so there is no problem with device degradation. For example, unlike conventional non-volatile memory, since there is no need for electron injection into the floating gate or electron extraction from the floating gate, problems such as degradation of the gate insulation layer do not occur. In other words, the semiconductor device of the disclosed invention has no limitation on the number of times data can be rewritten, which is a problem of conventional non-volatile memory, and thus reliability is dramatically improved. In addition, since data is recorded according to the state (on or off) of the transistor, high-speed operation can be easily achieved.

[0262] As described above, it is possible to provide a miniaturized and highly integrated semiconductor device having high electrical characteristics.

[0263] (Embodiment 7)

[0264] In this embodiment, a CPU including a memory device described in any of the above embodiments can be used.

[0265] FIG. 21 is a block diagram illustrating an example of a CPU configuration that includes at least a portion of the transistors described in Embodiment 1.

[0266] The CPU illustrated in FIG. 21 includes an ALU (1191) (Arithmetic Logic Unit), an ALU controller (1192), an instruction decoder (1193), an interrupt controller (1194), a timing controller (1195), a register (1196), a register controller (1197), a bus interface (1198), a rewritable ROM (1199), and a ROM interface (1189) on a substrate (1190). A semiconductor substrate, an SOI substrate, a glass substrate, etc., are used as the substrate (1190). The rewritable ROM (1199) and the ROM interface (1189) may be provided on separate chips. It goes without saying that the CPU in FIG. 21 is merely a simplified example of the configuration, and actual CPUs may have various configurations depending on the application. For example, the CPU may be considered as a single core, including a structure comprising the CPU or arithmetic circuit shown in FIG. 21, and may have a configuration in which multiple cores are included and the cores operate in parallel. The number of bits that the CPU can process in the internal arithmetic circuit or data bus may be, for example, 8, 16, 32, or 64.

[0267] Instructions input to the CPU through the bus interface (1198) are input to the instruction decoder (1193), and after being decoded, are input to the ALU controller (1192), interrupt controller (1194), register controller (1197), and timing controller (1195).

[0268] The ALU controller (1192), interrupt controller (1194), register controller (1197), and timing controller (1195) perform various controls according to the decoded instruction. Specifically, the ALU controller (1192) generates a signal to control the operation of the ALU (1191). While the CPU is executing a program, the interrupt controller (1194) determines an interrupt request from an external I / O device or peripheral circuit based on priority or mask status and processes the request. The register controller (1197) generates an address of the register (1196) and performs data reading from the register (1196) or data writing to the register (1196) depending on the state of the CPU.

[0269] The timing controller (1195) generates signals to control the operation timing of the ALU (1191), ALU controller (1192), instruction decoder (1193), interrupt controller (1194), and register controller (1197). For example, the timing controller (1195) includes an internal clock generator that generates an internal clock signal (CLK2) based on a reference clock signal (CLK1), and supplies the internal clock signal (CLK2) to the circuit described above.

[0270] In the CPU illustrated in FIG. 21, a memory cell is provided to a register (1196). As the memory cell of the register (1196), a transistor described in the above-described embodiment may be used.

[0271] In the CPU illustrated in FIG. 21, the register controller (1197) selects a data retention operation in the register (1196) according to a command from the ALU (1191). That is, it selects whether to retain data in the memory cell included in the register (1196) by a flip-flop or by a capacitor. If data retention by a flip-flop is selected, power voltage is supplied to the memory cell in the register (1196). If data retention by a capacitor is selected, the data is rewritten from the capacitor, and the supply of power voltage to the memory cell in the register (1196) can be stopped.

[0272] FIG. 22 is an example of a circuit diagram of a memory element that can be used as a register (1196). The memory element (700) includes a circuit (701) in which stored data is volatile when the power is stopped, a circuit (702) in which stored data is not volatile when the power is stopped, a switch (703), a switch (704), a logic element (706), a capacitor (707), and a circuit (720) having a selection function. The circuit (702) includes a capacitor (708), a transistor (709), and a transistor (710). Additionally, the memory element (700) may further include other elements such as diodes, registers, or inductors as needed.

[0273] Here, the memory device described in the above-described embodiment may be used as the circuit (702). When the supply of power voltage to the memory element (700) is stopped, a ground potential (0V) or a potential at which the transistor (709) in the circuit (702) is turned off is continuously input to the first gate of the transistor (709). For example, the first gate of the transistor (709) is grounded through a load such as a register.

[0274] An example is described in which the switch (703) is a transistor (713) having one type of conductivity (e.g., an n-channel transistor) and the switch (704) is a transistor (714) having a conductivity opposite to that of the one type of conductivity (e.g., a p-channel transistor). Here, the first terminal of the switch (703) corresponds to one of the source and drain of the transistor (713), and the second terminal of the switch (703) corresponds to the other of the source and drain of the transistor (713), and the conduction or non-conduction between the first terminal and the second terminal of the switch (703) (i.e., the ON state or OFF state of the transistor (713)) is selected by a control signal (RD) input to the gate of the transistor (713). The first terminal of the switch (704) corresponds to one of the source and drain of the transistor (714), and the second terminal of the switch (704) corresponds to the other of the source and drain of the transistor (714), and conduction or non-conduction between the first terminal and the second terminal of the switch (704) (i.e., the ON state or OFF state of the transistor (714)) is selected by a control signal (RD) input to the gate of the transistor (714).

[0275] One of the source and drain of the transistor (709) is electrically connected to one of the pair of electrodes of the capacitor (708) and to the gate of the transistor (710). Here, the connection part is designated as a node (M2). One of the source and drain of the transistor (710) is electrically connected to a line capable of supplying a low power potential (e.g., a GND line), and the other of these is electrically connected to the first terminal of the switch (703) (one of the source and drain of the transistor (713)). The second terminal of the switch (703) (the other of the source and drain of the transistor (713)) is electrically connected to the first terminal of the switch (704) (one of the source and drain of the transistor (714)). The second terminal of the switch (704) (the other side of the source and drain of the transistor (714)) is electrically connected to a line capable of supplying a power potential (VDD). The second terminal of the switch (703) (the other side of the source and drain of the transistor (713)), the first terminal of the switch (704) (one side of the source and drain of the transistor (714)), the input terminal of the logic element (706), and one side of a pair of electrodes of the capacitor (707) are electrically connected to each other. Here, the connection part is designated as a node (M1). A constant potential may be supplied to the other side of the pair of electrodes of the capacitor (707). For example, a low power potential (e.g., GND) or a high power potential (e.g., VDD) may be supplied to the other side of the pair of electrodes of the capacitor (707). The other end of the pair of electrodes of the capacitor (707) is electrically connected to a line capable of supplying a low power potential (e.g., a GND line). A constant potential may be supplied to the other end of the pair of electrodes of the capacitor (708). For example, a low power potential (e.g., GND) or a high power potential (e.g., VDD) may be supplied to the other end of the pair of electrodes of the capacitor (708). The other end of the pair of electrodes of the capacitor (708) is electrically connected to a line capable of supplying a low power potential (e.g., a GND line).

[0276] If parasitic capacitance such as that of transistors and wiring is actively utilized, there is no need to supply capacitors (707) and capacitors (708).

[0277] A control signal (WE) is input to the first gate (first gate electrode) of the transistor (709). For each of the switches (703) and (704), a conducting state or a non-conducting state between the first terminal and the second terminal is selected by a control signal (RD) that is different from the control signal (WE). When the first terminal and the second terminal of one of the switches are in a conducting state, the first terminal and the second terminal of the other of the switches are in a non-conducting state.

[0278] A signal corresponding to the data maintained in the circuit (701) is input to the other side of the source and drain of the transistor (709). FIG. 22 illustrates an example in which a signal output from the circuit (701) is input to the other side of the source and drain of the transistor (709). The logic value of the signal output from the second terminal of the switch (703) (the other side of the source and drain of the transistor (713)) is inverted by a logic element (706), and the inverted signal is input to the circuit (701) through the circuit (720).

[0279] In the example of FIG. 22, the signal output from the second terminal of the switch (703) (the other side of the source and drain of the transistor (713)) is input to the circuit (701) through the logic element (706) and the circuit (720), but the present embodiment is not limited thereto. The signal output from the second terminal of the switch (703) (the other side of the source and drain of the transistor (713)) may be input to the circuit (701) without the logic value being inverted. For example, when a node is provided in the circuit (701) in which a signal obtained by inverting the logic value of a signal input from an input terminal is maintained, the signal output from the second terminal of the switch (703) (the other side of the source and drain of the transistor (713)) may be input to the node.

[0280] As the transistor (709) in FIG. 22, the transistor described in Embodiment 1 may be used. As described in Embodiment 3, it is preferable that the transistor (709) includes a second gate (second gate electrode). A control signal (WE) may be input to the first gate, and a control signal (WE2) may be input to the second gate. The control signal (WE2) is a signal having a constant potential. As the constant potential, for example, a ground potential (GND) or a potential lower than the source potential of the transistor (709) is selected. The control signal (WE2) is a potential signal for controlling the threshold voltage of the transistor (709) and can further reduce the Icut of the transistor (709). Additionally, as the transistor (709), a transistor without a second gate may be used.

[0281] Additionally, in FIG. 22, each transistor included in the memory element (700), excluding the transistor (709), may be a transistor in which a channel is formed in a layer or substrate (1190) formed using a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon layer or a silicon substrate may be used. Alternatively, for all transistors used in the memory element (700), a transistor in which a channel is formed in an oxide semiconductor film may be used. Alternatively, in addition to the transistor (709) in the memory element (700), a transistor in which a channel is formed in an oxide semiconductor film may be included, and for the remaining transistors, a transistor in which a channel is formed in a layer or substrate (1190) containing a semiconductor other than an oxide semiconductor may be used.

[0282] As the circuit (701) in FIG. 22, for example, a flip-flop circuit can be used. As the logic element (706), for example, an inverter, a clocked inverter, etc. can be used.

[0283] A semiconductor device of one form of the present invention can maintain data stored in a circuit (701) by a capacitor (708) provided to a circuit (702) during a period when power voltage is not supplied to a memory element (700).

[0284] The off-state current of a transistor in which a channel is formed in an oxide semiconductor film is very low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor film is significantly lower than that of a transistor in which a channel is formed in crystalline silicon. Therefore, if a transistor containing such an oxide semiconductor is used in the transistor (709), the signal maintained in the capacitor (708) is maintained for a long time even during periods when the power supply voltage is not supplied to the memory element (700). Thus, the memory element (700) can maintain the stored content (data) even during periods when the supply of power supply voltage is stopped.

[0285] Since switches (703) and (704) are provided, the memory element performs a precharge operation, so that the time required for the circuit (701) to retain the original data again after the supply of power voltage is resumed can be shortened.

[0286] In circuit (702), the signal maintained by the capacitor (708) is input to the gate of the transistor (710). Therefore, after the supply of power voltage to the memory element (700) is resumed, the signal maintained by the capacitor (708) can be converted to a state (on or off state) of the transistor (710) and read from circuit (702). Thus, even if the potential corresponding to the signal maintained by the capacitor (708) fluctuates slightly, the original signal can be accurately read.

[0287] By applying the memory element (700) described above to a memory device, such as a register or cache memory included in a processor, it is possible to prevent data loss within the memory device due to the interruption of the power supply voltage. Additionally, after the power supply voltage is resumed, the memory device can return to the same state as before the power was interrupted shortly thereafter. Therefore, power can be interrupted for even a short time in the processor, or in one or more logic circuits included in the processor. Thus, power consumption can be suppressed.

[0288] In this embodiment, an example of using the memory element (700) in a CPU has been described, but the memory element (700) can also be used in LSIs such as DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device), and RF-ID (Radio Frequency Identification).

[0289] This embodiment may be appropriately combined with any of the other embodiments in this specification.

[0290] (Embodiment 8)

[0291] In this embodiment, examples of electronic devices that may include the transistor described in Embodiment 1, the memory device described in Embodiment 5 or 6, or the CPU described in Embodiment 7 (including a DSP, custom LSI, PLD, and RF-ID) are described.

[0292] The transistor described in Embodiment 1, the memory device described in Embodiment 5 or 6, and the CPU described in Embodiment 7, etc., may be applied to various electronic devices (including game consoles). Examples of electronic devices include display devices such as televisions and monitors, lighting devices, personal computers, word processors, image playback devices, portable audio players, radios, tape recorders, stereos, telephones, cordless telephones, mobile phones, car phones, transceivers, wireless devices, game consoles, calculators, portable information terminals, electronic notebooks, electronic book readers, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, IC chips, high-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioning systems such as air conditioners, dishwashers, dish dryers, clothes dryers, duvet dryers, electric refrigerators, electric freezers, electric freezers, freezers for DNA preservation, radiation counters, and medical devices such as dialysis machines or X-ray diagnostic devices. In addition, examples of electronic devices include alarm devices such as smoke detectors, heat detectors, gas alarm devices, and security alarm devices. In addition, examples of electronic devices may include industrial equipment such as guide lights, signal lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems. Furthermore, moving objects driven by fuel engines or electric motors using power from non-aqueous secondary batteries are also included in the category of electronic devices. Examples of the moving objects include electric vehicles (EVs), hybrid vehicles (HEVs) including internal combustion engines and electric motors, plug-in hybrid vehicles (PHEVs), tracked vehicles in which the wheels of these vehicles are replaced by caterpillar tracks, motorized two-wheeled vehicles including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, boats or vessels, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spacecraft.Several specific examples of these electronic devices are shown in (A) to (C) of Fig. 23.

[0293] In the television set (8000) illustrated in (A) of FIG. 23, the display unit (8002) is included in the housing (8001). The display unit (8002) can display images, and the speaker unit (8003) can output sound. Any of the transistors described in the above-described embodiment can be used in a driving circuit or pixel for operating the display unit (8002) included in the housing (8001).

[0294] A semiconductor display device such as a liquid crystal display device, an organic EL element, a light-emitting device provided in each pixel, an electrophoretic display device, a DMD (Digital Micromirror Device), or a PDP (Plasma Display Panel) can be used in the display unit (8002).

[0295] The television set (8000) may be provided with a receiver, a modem, etc. By means of the receiver, general television broadcasts can be received. Additionally, when the television set (8000) is connected to a communication network via a wired or wireless connection through a modem, data communication can be performed in one direction (from the transmitter to the receiver) or in two directions (between the transmitter and the receiver, or between receivers, etc.).

[0296] Additionally, the television set (8000) may include a CPU (8004) or memory for performing information communication. Power consumption can be reduced by using any of the transistor, memory device, and CPU described in the above-described embodiment in the CPU (8004) or memory.

[0297] The alarm device (8100) illustrated in (A) of FIG. 23 is a residential fire alarm and is an example of an electronic device comprising a sensor unit (8102) for smoke or heat and a microcomputer (8101). The microcomputer (8101) includes a transistor, memory device, or CPU as described in any of the embodiments described above.

[0298] An air conditioner including an indoor unit (8200) and an outdoor unit (8204) as illustrated in FIG. 23 (A) is an example of an electronic device including a transistor, memory device, CPU, etc., as described in any of the embodiments described above. Specifically, the indoor unit (8200) includes a housing (8201), an air outlet (8202), a CPU (8203), etc. In FIG. 23 (A), the CPU (8203) is provided in the indoor unit (8200), but the CPU (8203) may be provided in the outdoor unit (8204). Alternatively, the CPU (8203) may be provided in both the indoor unit (8200) and the outdoor unit (8204). By using any of the transistors described in the embodiments described above for the CPU of the air conditioner, a reduction in the power consumption of the air conditioner can be achieved.

[0299] The electronic freezer refrigerator (8300) illustrated in FIG. 23 (A) is an example of an electronic device including a transistor, memory device, CPU, etc., as described in any of the embodiments described above. Specifically, the electric freezer refrigerator (8300) includes a housing (8301), a refrigerator door (8302), a freezer door (8303), a CPU (8304), etc. In FIG. 23 (A), the CPU (8304) is provided in the housing (8301). If any of the transistors described in the embodiments described above are used as the CPU (8304) of the electric freezer refrigerator (8300), a reduction in power consumption of the electric freezer refrigerator (8300) can be achieved.

[0300] Figures 23 (B) and (C) illustrate examples of electronic vehicles, which are examples of electronic devices. An electric vehicle (9700) is equipped with a secondary battery (9701). The output of power from the secondary battery (9701) is regulated by a circuit (9702), and power is supplied to a driving device (9703). The circuit (9702) is controlled by a processing device (9704), which includes a ROM, RAM, CPU, etc., not shown. If any of the transistors described in the above-described embodiment are used as the CPU of the electric vehicle (9700), a reduction in power consumption of the electric vehicle (9700) can be achieved.

[0301] The drive unit (9703) includes a DC motor or an AC motor alone or in combination with an internal combustion engine. The processing unit (9704) outputs a control signal to the circuit (9702) based on input information such as operation information (e.g., acceleration, deceleration, or stopping) by the driver of the electric vehicle (9700) or information during operation (e.g., information on uphill or downhill roads, or information on the load on the drive wheels). The circuit (9702) controls the output of the drive unit (9703) by adjusting the electrical energy supplied from the secondary battery (9701) according to the control signal of the processing unit (9704). When an AC motor is installed, an inverter that converts direct current to alternating current is also built in, although not shown.

[0302] This embodiment may be appropriately combined with any of the other embodiments in this specification.

[0303] (Example 1)

[0304] In this embodiment, a transistor having the same structure as the transistor (460) shown in (A) of FIG. 6 was fabricated as an example sample, and the cross-section of the transistor was examined. The electrical characteristics of the fabricated transistor were evaluated.

[0305] First, the method for preparing the sample for the example is explained.

[0306] First, a silicon nitride (SiON) film serving as an insulating film was formed on a silicon substrate with a thickness of 300 nm. The silicon nitride film was formed by sputtering under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 25 sccm:25 sccm); a pressure of 0.4 Pa; a power supply of 5.0 kW (power output); a distance of 60 mm between the silicon substrate and the target; and a substrate temperature of 100°C.

[0307] Friction treatment was performed on the surface of the silicon oxide film, and a first oxide film with a thickness of 10 nm and an oxide semiconductor film with a thickness of 40 nm were deposited. The first oxide film was formed by sputtering using an oxide target (IGZO (132)) of In:Ga:Zn = 1:3:2 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm); a pressure of 0.4 Pa; a power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 200°C. The oxide semiconductor film was formed by sputtering using an oxide target (IGZO (111)) of In:Ga:Zn = 1:1:1 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm); a pressure of 0.4 Pa; A power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 300°C. In addition, the first oxide film and the oxide semiconductor film were formed continuously without being exposed to the atmosphere.

[0308] Next, heat treatment was performed. The heat treatment was performed at 450°C for 1 hour under a nitrogen atmosphere, and then at 450°C for 1 hour under an oxygen atmosphere.

[0309] A tungsten film with a thickness of 5 nm was formed on an oxide semiconductor film and etched to form a hard mask. An inductively coupled plasma (ICP) etching method was employed for etching. The etching conditions were as follows: a carbon tetrafluoride (CF4 = 100 sccm) atmosphere; a power supply of 2000 W; a bias power of 50 W; and a pressure of 0.67 Pa. Subsequently, the etching conditions were changed as follows: a mixed atmosphere of carbon tetrafluoride and oxygen (CF4:O2 = 60 sccm:40 sccm); a power supply of 1000 W; a bias power of 25 W; and a pressure of 2.0 Pa.

[0310] The first oxide film and the oxide semiconductor film were processed into an island shape by ICP etching under the following conditions: a mixed atmosphere of methane and argon (CH4:Ar=16sccm:32sccm); a power supply of 600W; a bias power of 100W; a pressure of 1.0Pa; and a substrate temperature of 70℃.

[0311] Next, a tungsten (W) film serving as the source electrode and drain electrode was formed on the first oxide film and oxide semiconductor film to a thickness of 10 nm. The film was formed by sputtering using a tungsten target under the following conditions: an argon (80 sccm) atmosphere; a pressure of 0.8 Pa; a power supply of 1.0 kW (power output); a distance of 60 mm between the silicon substrate and the target; and a substrate temperature of 230°C.

[0312] Next, a resist mask was formed on the tungsten film, and etching was performed using the ICP etching method. As for the etching, a first etching and a second etching were performed. The conditions for the first etching were as follows: a carbon tetrafluoride (CF4=100 sccm) atmosphere; a power supply of 2000 W; a bias power of 50 W; and a pressure of 0.67 Pa. Next, the conditions for the second etching were changed as follows: a carbon tetrafluoride and oxygen (CF4:O2=60 sccm:40 sccm) atmosphere; a power supply of 1000 W; a bias power of 25 W; and a pressure of 2.0 Pa. Thus, a source electrode and a drain electrode were formed.

[0313] Next, a second oxide film was formed with a thickness of 5 nm on the oxide semiconductor film, source electrode, and drain electrode. The film was formed by sputtering using an oxide target (IGZO (132)) of In:Ga:Zn = 1:3:2 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm); a pressure of 0.4 Pa; a power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 200°C.

[0314] Next, a silicon oxynitride film, which serves as the gate insulating film, was formed with a thickness of 10 nm by the CVD method.

[0315] A titanium nitride film was formed to a thickness of 10 nm on a silicon oxynitride film by sputtering under the following conditions: a nitrogen (N2=50 sccm) atmosphere; a pressure of 0.2 Pa; a power supply of 12 kW; and a distance between the substrate and the target of 400 mm. The substrate temperature was set to room temperature. A tungsten film was formed to a thickness of 10 nm on the titanium nitride film under the following conditions: an argon (Ar=100 sccm) atmosphere; a pressure of 2.0 Pa; a power supply of 4 kW; a distance between the substrate and the target of 60 mm; and a substrate temperature of 230°C.

[0316] A stack of a titanium nitride film with a thickness of 10 nm and a tungsten film with a thickness of 10 nm was etched by ICP etching. As for the etching, a first etching and a second etching were performed. The conditions for the first etching were as follows: a mixed atmosphere of chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm); a power supply of 3000 W; a bias power of 110 W; and a pressure of 0.67 Pa. The second etching was performed after the first etching under the following conditions: a mixed atmosphere of boron trichloride and chlorine (BCl3:Cl2 = 150 sccm:50 sccm); a power supply of 1000 W; a bias power of 50 W; and a pressure of 0.67 Pa. Thus, a gate electrode was formed.

[0317] A stack comprising a gate insulating film and a second oxide film was etched by ICP etching using a gate electrode as a mask. The etching conditions are as follows: a mixed atmosphere of methane and argon (CH4:Ar=16 sccm:32 sccm); a power supply of 600 W; a bias power of 100 W; a pressure of 1.0 Pa; and a substrate temperature of 70°C.

[0318] Next, an aluminum oxide film with a thickness of 20 nm was formed on the gate electrode by sputtering, and a silicon nitride film with a thickness of 150 nm was formed on it by CVD.

[0319] Figures 10 (A) and (B) are cross-sectional STEM images of an example sample prepared by the method described above. Figure 10 (A) is a cross-sectional view in the channel length direction. Figure 10 (B) is a cross-sectional view in the channel width direction.

[0320] As shown in (B) of FIG. 10, when viewed in cross-section in the channel width direction, the oxide semiconductor film IGZO (111) has rounded ends and a semicircular shape. It was found that this structure improves the coverage rate between the second oxide film, the gate insulating film, and the gate electrode formed on the oxide semiconductor film and prevents the occurrence of shape defects such as disconnection.

[0321] The channel length of the fabricated transistor was 68 nm, and the channel width was 34 nm.

[0322] The drain current (I of the transistor fabricated next) d :[A]) was measured. Drain voltage (V d :[V]) was set to 0.1V or 1V, and the gate voltage (V g :[V]) was swept from -3V to 3V. FIG. 29 shows the measurement results of the transistor. In FIG. 29, the solid line represents the drain voltage of 1V (V d This shows the measurement results at :[V]), and the dotted line is the drain voltage of 0.1V (V d This represents the measurement results at :[V]), and the horizontal axis is the gate voltage (V g :[V]) represents, and the vertical axis is the drain current (I d :[A]) represents. Also, "drain voltage (V d "" [V] refers to the potential difference between the drain and the source when the source potential is used as the reference potential, and "gate voltage (V g "[V]" refers to the potential difference between the gate and the source when the source potential is used as the reference potential.

[0323] FIG. 29 shows the drain voltage (V) of the transistor fabricated in this embodiment. d :[V]) represents the case where it is 1V, and the on-state current is 5.31μA; the shift value is 0.13A; the threshold voltage is 0.65V; and the off-state current is below the lower measurement limit. In addition, the shift value is the drain current is 1×10-12 This is the value of the gate voltage when A. When the drain voltage is 0.1V, the field-effect mobility is 20.0cm. 2 / Vs and the S value is 113.1mV / dec.

[0324] The above-described results indicate that the transistor of the present embodiment has excellent electrical characteristics.

[0325] (Example 2)

[0326] In this embodiment, the temperature dependence of the transistor fabricated in Example 1 was investigated.

[0327] In the evaluation, the drain current (I d :[A]) and field-effect mobility (μFE) were measured at -25℃, 50℃, and 150℃. Drain voltage (V d :[V]) was set to 1V, and the gate voltage (V g :[V]) was swept from -3V to 3V. FIG. 30 shows the measurement results of the transistor. In FIG. 30, the horizontal axis is the gate voltage (V g :[V]) represents, and the vertical axis on the left is the drain current (I d :[A]) represents, and the vertical axis on the right is the field-effect mobility (μFE:cm² 2 / Vs) represents.

[0328] As shown in FIG. 30, in the transistor fabricated in Example 1, the on-state current and field-effect mobility hardly change with temperature change.

[0329] Figure 31 shows the temperature dependence of the threshold voltage.

[0330] It was found that the threshold voltage hardly changes with temperature changes.

[0331] The above-described result indicates that the transistor of the present embodiment has temperature resistance.

[0332] (Example 3)

[0333] In this embodiment, the reliability of the transistor fabricated in Example 1 was evaluated.

[0334] For evaluation, the source voltage (V s :[V]) and drain voltage (V d :[V]) was set to 0V, and under stress test conditions where a gate voltage of -1.8V was applied at 150℃ for 1 hour, the drain current (I d :[A]) was measured. Figure 32 (A) shows the measurement results of the transistor. In Figure 32 (A), the solid line represents the drain voltage of 1V (V d This shows the results at :[V]), the dotted line represents the results at a drain voltage of 0.1V, and the horizontal axis is the gate voltage (V g :[V]) represents, and the vertical axis is the drain current (I d :[A]) represents.

[0335] Also, the source voltage (V s :[V]) and gate voltage (V d :[V]) was set to 0V, and under stress test conditions where a drain voltage of 1.8V was applied at 150℃ for 1 hour, the drain current (I d :[A]) was measured. Figure 32 (B) shows the measurement results of the transistor. In Figure 32 (B), the solid line represents the drain voltage of 1V (V d This shows the results at :[V]), the dotted line represents the results at a drain voltage of 0.1V, and the horizontal axis is the gate voltage (V g :[V]) represents, and the vertical axis is the drain current (I d :[A]) represents.

[0336] In addition, in the graph, the solid line represents the results before the stress test, and the dotted line represents the results after the stress test. As shown in Figures 32 (A) and (B), the transistor fabricated in Example 1 has a drain voltage (V) of 1 V. dWhen :[V]) has, the change in threshold voltage (ΔV th ) is small, 0.03V in (A) of Fig. 32 and 0.11V in (B) of Fig. 32.

[0337] The rectangle in Fig. 33 represents the source voltage (V s :[V]) and gate voltage (V g :[V]) was set to 0V, and the drain voltage (V) of 1.8V d This shows the change in threshold voltage when :[V]) is applied at 125℃ for 87.6 hours (equivalent to 0.01 years).

[0338] The diamond shape in Fig. 33 represents the source voltage (V s :[V]) and drain voltage (V d :[V]) was set to 0V, and the gate voltage (V) of -1.8V was set. g This shows the change in threshold voltage when :[V]) is applied at 125℃ for 87.6 hours (equivalent to 0.01 years).

[0339] Figure 33 shows that the change in threshold voltage of the transistor fabricated in Example 1 is small even after 0.01 years.

[0340] The above-described results indicate that the transistor of the present embodiment has high electrical stability.

[0341] (Example 4)

[0342] In this embodiment, the electrical characteristics according to the channel width of the transistor fabricated in Example 1 were evaluated.

[0343] First, the on-state current (I of a transistor having a different channel width) on :[A]) at a drain voltage of 1V (V d It was measured as :[V]). Figure 34 (A) shows the measurement results of the transistor. In Figure 34 (A), the horizontal axis represents the channel length (nm), and the vertical axis represents the on-state current (I on:[A]) represents. Also, the diamond shape in the graph represents the result for a channel width of 40 nm; the triangle represents a channel width of 100 nm, and the square represents a channel width of 500 nm.

[0344] (A) of FIG. 34 shows the on-state current (I) even if the channel width is small. on ) indicates that it is high.

[0345] Next, the field-effect mobility of transistors with different channel widths at a drain voltage (V) of 0.1V d It was measured as :[V]). Fig. 34 (B) shows the measurement results of the transistor. In Fig. 34 (B), the horizontal axis represents the channel length [nm], and the vertical axis represents the field-effect mobility (μFE:cm²). 2 It represents / Vs). Also, the diamond shape in the graph represents the result for a channel width of 40 nm; the triangle represents a channel width of 100 nm, and the square represents a channel width of 500 nm.

[0346] Figure 34 (B) shows a transistor that has higher mobility as the channel width decreases.

[0347] Next, the threshold voltage of a transistor with a different channel width is 1V, and the drain voltage (V d It was measured as :[V]). Figure 34 (C) shows the measurement results of the transistor. In Figure 34 (C), the horizontal axis represents the channel length [nm], and the vertical axis represents the threshold voltage (V th :[V]) represents. Also, the diamond shape in the graph represents the result for a channel width of 40 nm; the triangle represents a channel width of 100 nm, and the square represents a channel width of 500 nm.

[0348] It can be seen from (C) of Fig. 34 that the threshold voltage hardly changes.

[0349] Next, the shift value of a transistor with a different channel width is set to a drain voltage of 1V (Vd It was measured as :[V]). Here, the shift value represents the rising edge and 1 E -12A drain current (I d [A]) gate voltage (V g [V] is defined. Fig. 34 (D) shows the measurement results of the transistor. In Fig. 34 (D), the horizontal axis represents the channel length [nm], and the vertical axis represents the shift value [V]. Also, the diamond shape in the graph represents the result for a channel width of 40 nm; the triangle represents a channel width of 100 nm, and the square represents a channel width of 500 nm.

[0350] (D) of Fig. 34 indicates a transistor in which the change in shift value is smaller as the channel width is smaller.

[0351] Next, the S value of a transistor with a different channel width is at a drain voltage (V) of 0.1V. d It was measured as :[V]). Figure 35 (A) shows the measurement results of the transistor. In Figure 35 (A), the horizontal axis represents the channel length [nm], and the vertical axis represents the S value [mV / dec.]. Also, the diamond shape in the graph represents the result for a channel width of 40 nm; the triangle represents a channel width of 100 nm, and the square represents a channel width of 500 nm.

[0352] Figure 35 (A) indicates a transistor in which the decrease in S value is greater as the channel width decreases.

[0353] Next, DIBL was measured according to the channel width. DIBL is the drain voltage of 1V (V d The threshold voltage at :[V]) is the drain voltage (V) of 0.1V. dIt was obtained by subtracting from the threshold voltage at :[V] and dividing the obtained value by 0.9. Fig. 35 (B) shows the measurement results of the transistor. In Fig. 35 (B), the horizontal axis represents the channel length [nm], and the vertical axis represents the DIBL value [V / V.]. Also, the diamond shape in the graph represents the result for a channel width of 40 nm; the triangle represents a channel width of 100 nm, and the square represents a channel width of 500 nm.

[0354] Figure 35 (B) shows a transistor in which the DIBL decreases as the channel width decreases.

[0355] The above results indicate that the electrical characteristics of the transistor in this embodiment improve as the channel width decreases.

[0356] (Example 5)

[0357] In this embodiment, a transistor having the same structure as the transistor (460) shown in (A) of FIG. 6 was fabricated as an example sample, and the electrical characteristics of the transistor were evaluated.

[0358] First, the method for preparing the sample for the example is explained.

[0359] For the method of preparing the sample of the example, refer to Example 1. The only difference between the transistor of Example 1 and the transistor of the present example is the first oxide film; the thickness of the first oxide film of the transistor of the present example is 10 nm. The above film was formed by sputtering using an oxide target (IGZO (134)) of In:Ga:Zn = 1:3:4 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm); a pressure of 0.4 Pa; a power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 200°C.

[0360] In the transistor fabricated in this embodiment, the channel length was set to 70 nm and the channel width was set to 40 nm.

[0361] Next, the drain current (I d :[A]) drain voltage (V d :[V]) was set to 1V, and the gate voltage (V g :[V]) was measured under conditions where it was swept from -3V to 3V. In addition, the drain voltage (V) of 0.1V was d The field-effect mobility (μFE) at :[V] was measured. Figure 11 shows the drain voltage (V) at 1V. d This shows the measurement results of the transistor at :[V]). In Fig. 11, the horizontal axis is the gate voltage (V g :[V]) represents, and the vertical axis on the left is the drain current (I d :[A]) represents, and the vertical axis on the right is the field-effect mobility (μFE:cm² 2 / Vs) represents.

[0362] As shown in FIG. 11, the drain voltage (V) of the transistor fabricated in this embodiment d When V is 1V, the on-state current is 5.08μA. Also, when the drain voltage is 0.1V, the field-effect mobility is 17.0cm. 2 / Vs.

[0363] The above-described results indicate that the transistor of the present embodiment has excellent electrical characteristics.

[0364] (Example 6)

[0365] In this embodiment, a transistor having the same structure as the transistor (460) shown in (A) of FIG. 6 was fabricated as an example sample, and electrical characteristics according to channel width were evaluated.

[0366] First, the method for preparing the sample for the example is explained.

[0367] For the method of preparing the sample of the example, refer to Example 1. Sample A is the transistor used in Example 1 (the first oxide film is IGZO (132) with a film thickness of 10 nm, and the oxide semiconductor film is IGZO (111) with a film thickness of 40 nm). Sample B is the transistor used in Example 5 (the first oxide film is IGZO (134) with a film thickness of 10 nm, and the oxide semiconductor film is IGZO (111) with a film thickness of 40 nm). Sample C is fabricated such that the first oxide film is IGZO (132) with a film thickness of 20 nm, the oxide semiconductor film is IGZO (111) with a film thickness of 15 nm, and other components are fabricated in the same way as Sample A. The formation conditions of Sample C are as follows. A first oxide film was formed by sputtering using an oxide target (IGZO (132)) of In:Ga:Zn = 1:3:2 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm); a pressure of 0.4 Pa; a power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 200°C. An oxide semiconductor film was formed by sputtering using an oxide target (IGZO (111)) of In:Ga:Zn = 1:1:1 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm); a pressure of 0.4 Pa; a power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 300°C.

[0368] In the transistor fabricated in this embodiment, the channel length was set to 40 nm.

[0369] In a transistor, the channel width ( W On-state current (I) according to ) on :[A]) at a drain voltage of 1V (V dIt was measured as :[V]). In addition, in this embodiment, the on-state current is the current measured at a voltage of (threshold voltage + 1V). Figures (A) to (C) of FIGS. 12 and 13 show the measurement results of the transistor. In Figures (A) to (C) of FIGS. 12 and 13, the horizontal axis represents the channel width (W: [nm]), and the vertical axis on the left represents the on-state current (I on :[A]) represents.

[0370] According to FIG. 12, in sample C comprising an oxide semiconductor film with a thickness of 15 nm, the on-state current (I on ) is the channel width ( W It decreases as ) becomes smaller. Meanwhile, in samples A and B, each containing an oxide semiconductor film with a thickness of 40 nm, the on-state current (I on ) is the channel width ( W It does not decrease as ) becomes smaller.

[0371] This increases the electric field of the gate electrode in the transverse direction when the thick oxide semiconductor film has a small channel width, thereby increasing the on-state current (I on It is likely because ) improves.

[0372] Figure 13 (A) shows the characteristics of sample A. Figure 13 (B) shows the characteristics of sample B. Figure 13 (C) shows the characteristics of sample C. Figures 13 (A) to (C) show the channel width ( W As ) increases, the on-state current (I) of any of samples A, B, and C on It indicates that ) is increasing.

[0373] (Example 7)

[0374] In this embodiment, a transistor having the same structure as the transistor (460) shown in (A) of FIG. 6 was fabricated as an example sample, and the electrical characteristics of the fabricated transistor were evaluated.

[0375] First, the method for preparing the sample for the example is explained.

[0376] First, a silicon nitride (SiON) film serving as an insulating film was formed on a silicon substrate with a thickness of 300 nm. The silicon nitride film was formed by sputtering under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 25 sccm:25 sccm); a pressure of 0.4 Pa; a power supply of 5.0 kW (power output); a distance of 60 mm between the silicon substrate and the target; and a substrate temperature of 100°C.

[0377] Friction treatment was performed on the surface of the silicon oxide film, and a first oxide film with a thickness of 20 nm and an oxide semiconductor film with a thickness of 20 nm were deposited. The first oxide film was formed by sputtering using an oxide target (IGZO (134)) with an In:Ga:Zn ratio of 1:3:4 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 40 sccm:5 sccm); a pressure of 0.4 Pa; a power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 200°C. The oxide semiconductor film was formed by sputtering using an oxide target (IGZO (111)) with an In:Ga:Zn ratio of 1:1:1 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm); a pressure of 0.4 Pa; A power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 300°C. In addition, the first oxide film and the oxide semiconductor film were formed continuously without being exposed to the atmosphere.

[0378] Next, heat treatment was performed. The heat treatment was performed at 450°C for 1 hour under a nitrogen atmosphere, and then at 450°C for 1 hour under an oxygen atmosphere.

[0379] Next, a tungsten film serving as the source electrode and drain electrode was formed on the oxide semiconductor film to a thickness of 150 nm. The film was formed by sputtering using a tungsten target under the following conditions: an argon (80 sccm) atmosphere; a pressure of 0.8 Pa; a power supply of 1.0 kW (power output); a distance of 60 mm between the silicon substrate and the target; and a substrate temperature of 230°C.

[0380] Next, a resist mask was formed on the tungsten film, and etching was performed using the ICP etching method. As for the etching, the first etching, the second etching, and the third etching were performed. The conditions for the first etching are as follows: a mixed atmosphere of chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm); a power supply of 3000 W; a bias power of 110 W; and a pressure of 0.67 Pa. Next, the conditions for the second etching are as follows: an atmosphere of oxygen (O2 = 100 sccm); a power supply of 2000 W; a bias power of 0 W; and a pressure of 3.0 Pa. The conditions for the third etching are as follows: a mixed atmosphere of chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm); The power supply is 3000W; the bias power is 110W; and the pressure is 0.67Pa. Thus, the source electrode and drain electrode were formed.

[0381] Next, a resist mask was formed on the oxide semiconductor film, and the first oxide film and the oxide semiconductor film were processed into an island shape by ICP etching under the following conditions: boron trichloride (BCl3 = 80 sccm) atmosphere; 450 W power supply; 100 W bias power; 1.2 Pa pressure; and a substrate temperature of 70°C.

[0382] Next, a second oxide film was formed with a thickness of 5 nm on the oxide semiconductor film, source electrode, and drain electrode. The film was formed by sputtering using an oxide target of In:Ga:Zn = 1:3:2 (atomic ratio) under the following conditions: a mixed atmosphere of argon and oxygen (argon:oxygen = 30 sccm:15 sccm); a pressure of 0.4 Pa; a power supply of 0.5 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 200°C.

[0383] Next, a silicon oxynitride film, which serves as the gate insulating film, was formed with a thickness of 20 nm by the CVD method.

[0384] A tantalum nitride film was formed to a thickness of 30 nm on a silicon oxynitride film by sputtering under the following conditions: a mixed atmosphere of tantalum nitride and argon (TaN=50 sccm:10 sccm); a pressure of 0.6 Pa; a power supply of 1 kW; and a distance of 60 mm between the substrate and the target. The substrate temperature was set to room temperature. A tungsten film was formed to a thickness of 135 nm on a titanium nitride film under the following conditions: an argon (Ar=100 sccm) atmosphere; a pressure of 2.0 Pa; a power supply of 4 kW; a distance of 60 mm between the substrate and the target; and a substrate temperature of 230°C.

[0385] A stack of a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 135 nm was etched by ICP etching. As for the etching, a first etching and a second etching were performed. The conditions for the first etching were as follows: a mixed atmosphere of chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm); a power supply of 3000 W; a bias power of 110 W; and a pressure of 0.67 Pa. The second etching was performed after the first etching under the following conditions: a chlorine (Cl2 = 100 sccm) atmosphere; a power supply of 1000 W; a bias power of 50 W; and a pressure of 0.67 Pa. Thus, a gate electrode was formed.

[0386] A stack including a gate insulating film and a second oxide film was etched by ICP etching. The etching conditions are as follows: boron trichloride (BCl3 = 80 sccm) atmosphere; a power supply of 450 W; a bias power of 100 W; a pressure of 1.2 Pa; and a substrate temperature of 70°C.

[0387] Next, an aluminum oxide film with a thickness of 140 nm was formed on the gate electrode by sputtering, and a silicon nitride film with a thickness of 300 nm was formed on it by CVD.

[0388] The channel length was 0.48 μm, and the channel width was 0.5 μm.

[0389] Next, the temperature dependence of the fabricated transistor was investigated.

[0390] For the evaluation, the drain current per channel width of 1 μm (I d :[A]) was measured at 25℃, 50℃, 100℃, 150℃, 200℃, and 250℃. Drain voltage (V d :[V]) was set to 1V, and the gate voltage (V g :[V]) was swept from -3V to 3V. Fig. 40 (A) shows the measurement results of the transistor. In Fig. 40 (A), the horizontal axis is the gate voltage (V g :[V]) represents, and the vertical axis is the drain current (I d :[A]) indicates. Also, the arrow in (A) of Fig. 40 indicates the rise in temperature.

[0391] As shown in (A) of FIG. 40, in the transistor fabricated in this embodiment, the on-state current hardly changes with temperature change.

[0392] Figures 40 (B) and (C) show the temperature dependence of the threshold voltage and S value.

[0393] It was found that the threshold voltage and S value hardly change with temperature changes.

[0394] The above-described result indicates that the transistor of the present embodiment has temperature resistance.

[0395] (Example 8)

[0396] In this embodiment, differences in electrical characteristics according to the shape of the oxide semiconductor film were investigated.

[0397] First, I will explain the structure of the transistor.

[0398] Figure 25 (A) is a cross-sectional view in the channel width direction of a transistor in which the top portion of the oxide semiconductor film is angular (hereinafter, such a transistor is also referred to as a transistor having a square structure). In Figure 25 (A), W represents the channel width, and the oxide semiconductor film has a thickness of W / 2.

[0399] FIG. 25 (B) is a cross-sectional view in the channel width direction of a transistor having a rounded top portion of an oxide semiconductor film, which is one embodiment of the present invention (hereinafter, such a transistor is also referred to as a transistor having a semicircular structure). In FIG. 25 (B), r represents the radius of curvature and r =W / 2.

[0400] The effective channel width of a transistor with a rectangular structure is 2W (sum of the side and top surfaces). The effective channel width of a transistor with a semicircular structure is 1.57 W (Circumference of a semicircle, πr=π W / 2=1.57 W ) is. The effective channel width of a transistor having a semicircular structure for a transistor having a square structure ( W The ratio of ) is 0.785.

[0401] FIG. 26 is a cross-sectional view in the channel length direction of the transistors shown in (A) and (B) of FIG. 25. In FIG. 26, L represents the channel length.

[0402] The calculation conditions are explained next.

[0403] The calculation was performed using a Sentaurus device (manufactured by Synopsys, Inc.) under the conditions shown in Table 1.

[0404]

[0405] FIG. 27 shows a drain voltage (V) of 0.1V. d I in :[V]) d -V g This shows the characteristics and mobility. Figure 28 shows the drain voltage (V) of 1V. d I in :[V]) d -V g This represents the characteristics and mobility.

[0406] In FIGS. 27 and 28, the rise voltage (I) of a transistor having a semicircular structure d -V g One of the characteristics) is steeper than that of a transistor with a square structure. Also, the effective channel width ( W The mobility of a transistor with a semicircular structure calculated using ) is higher than that of a transistor with a square structure.

[0407] Table 2 compares the values ​​of the characteristics obtained from Figures 27 and 28.

[0408]

[0409] Excluding the on-state current, it was found from Table 2 that the transistor with a semicircular structure outperforms the transistor with a square structure in terms of characteristics. The on-state current ratio of the transistor with a semicircular structure to the transistor with a square structure is 0.892, so the effective channel width ( W It is higher than 0.785. In other words, electrons are more easily induced in the channel portion of a transistor with a semicircular structure than in the channel portion of a transistor with a square structure.

[0410] Effective channel width ( WThe relationship between the on-state current and the gate insulating film (hereinafter also referred to as GI capacitance) may be one of the reasons why electrons are more easily induced in the channel portion of a transistor with a semicircular structure than in the channel portion of a transistor with a square structure. Although it was thought that the on-state current is proportional to the capacitance of the gate insulating film (hereinafter also referred to as GI capacitance), the GI capacitance of a transistor with a semicircular structure is not represented by a parallel plate capacitor and is approximately represented by the following equation.

[0411] [Equation 1]

[0412]

[0413] In Equation 1, C r represents the GI capacitance per unit channel length of a transistor having a semicircular structure, and ε represents the dielectric constant of the gate insulating film, and t GI represents the thickness of the gate insulating film, and t OS represents the thickness of the oxide semiconductor film.

[0414] In a transistor with a semicircular structure, the GI capacitance is the effective channel width ( W ( π t OS The on-state current is not proportional to the effective channel width ( W It cannot be obtained using the ratio of ).

[0415] Meanwhile, the GI capacitance per unit channel length of a transistor having a square structure is approximately expressed by the following formula.

[0416] [Equation 2]

[0417]

[0418] The ratio of GI capacitance must be used to obtain the on-state current. C is the ratio of the GI capacitance of a transistor having a semicircular structure (obtained from Equation 1) to a transistor having a square structure (obtained from Equation 2). r / C s is approximately 0.968, and the effective channel width is 0.785 (W This estimate is an approximate value and does not match the ratio obtained by calculation, but from the estimate, it can be said that electrons are more easily induced in the channel portion of a transistor with a semicircular structure than in the channel portion of a transistor with a square structure.

[0419] <Reference Example>

[0420] In this reference example, it is explained that a transistor using a CAAC-OS film has sufficient resistance to short-channel effects.

[0421] Characteristic length is widely used as an indicator of resistance to short-channel effects. Characteristic length is an indicator of the potential curve in the channel region. As the characteristic length decreases, the potential rises more steeply, which means higher resistance to short-channel effects.

[0422] Transistors using CAAC-OS films are accumulation transistors. The reason transistors using CAAC-OS films are resistant to short-channel effects is likely because the characteristic length of an accumulation transistor is shorter than that of a transistor formed in an inversion transistor.

[0423] The structure of the transistor is explained in detail using the schematic diagram in Fig. 36. In addition, ε S represents the permittivity of the semiconductor film, and ε OX represents the permittivity of the gate insulating film, and t S represents the thickness of the semiconductor film, and t OX represents the thickness of the gate insulating film.

[0424] First, the potential in the channel region of an n-channel inverting transistor is obtained by solving Poisson's equation. In Fig. 36, Gauss's law applies to the narrow region darkened by the diagonal line (x~( x + dx It was applied to )) and the following equation was obtained.

[0425] [Equation 3]

[0426]

[0427] In Equation 3, φ ( x ) represents the potential (surface potential) at position (x), and φ ( x + dx ) is the location( x + dx Represents the potential (surface potential) at ), V G Is Indicates the gate voltage, V FB represents the flatband voltage, e represents the elementary charge, and N A represents the acceptor density.

[0428] By rearranging Equation 3, we obtain the following equation.

[0429] [Equation 4]

[0430]

[0431] Equation 6 was obtained by substituting Equation 5 into Equation 4.

[0432] [Equation 5]

[0433]

[0434] [Equation 6]

[0435]

[0436] The general solution of Equation 6 is obtained using Equation 7, and Equation 8 is obtained.

[0437] [Equation 7]

[0438]

[0439] [Equation 8]

[0440]

[0441] Potential φ ( x )) satisfies the following boundary conditions.

[0442] [Equation 9]

[0443]

[0444] Coefficients A and B satisfying the aforementioned boundary conditions are obtained, and by rearranging, the particular solution of the differential equation is derived. Potential( φ ( x )) is as follows.

[0445] [Equation 10]

[0446]

[0447] In the above formula x =0 or x = L By substituting It is easily confirmed that Equation 10 satisfies the boundary conditions in Equation 9.

[0448] In Equation 10, l represents the characteristic length, which is an indicator of the potential curve. As the characteristic length decreases, the potential of the channel portion in the FET changes more steeply.

[0449] Therefore, the characteristic length of the inverting transistor is as follows.

[0450] [Equation 11]

[0451]

[0452] Next, accumulation transistors (including transistors using CAAC-OS films in this category) are examined in a similar manner, and the characteristic lengths of accumulation and inversion transistors are compared. As described above, Gauss's law applies to the narrow region (x~( x + dx It was applied to )) and the following equation was obtained.

[0453] [Equation 12]

[0454]

[0455] In Equation 12, n i represents the intrinsic carrier density, and kB represents the Boltzmann constant, and φ F represents the Fermi potential.

[0456] By rearranging Equation 12, the following equation is obtained.

[0457] [Equation 13]

[0458]

[0459] also, l It is equivalent to the characteristic length of an inverting transistor.

[0460] The right side of Equation 13 is expanded using the approximation formula (Equation 14) given below to yield Equation 15.

[0461] [Equation 14]

[0462]

[0463] [Equation 15]

[0464]

[0465] In Equation 15, n 1 is the position ( x This represents the carrier density in 1). By substituting Equations 16 and 17 into Equation 15, Equation 18 is derived.

[0466] [Equation 16]

[0467]

[0468] [Equation 17]

[0469]

[0470] [Equation 18]

[0471]

[0472] Equation 18 is rearranged using Equation 19 to yield Equation 20.

[0473] [Equation 19]

[0474]

[0475] [Equation 20]

[0476]

[0477] Equation 20 is point ( x It is effective only in the vicinity of 1).

[0478] Consequently, the point ( x The characteristic length of the accumulation type transistor in the vicinity of 1) is as follows.

[0479] [Equation 21]

[0480]

[0481] To compare the inverting transistor and the accumulation transistor, the characteristic length of the inverting transistor ( l )cast l Indicated by (inv), the characteristic length of the accumulation transistor ( l' )cast l Indicated as (acc). Compare characteristic lengths.

[0482] [Equation 22]

[0483]

[0484] According to Equation 22 l (inv)> l (acc) can be known.

[0485] Characteristic length of an accumulation transistor ( l The obtained value of (acc) varies depending on the point (x1), but the characteristic length of the accumulator transistor is shorter than that of the inversion transistor in all cases. Additionally, the potential rises more steeply because the electron density increases near the source and drain.

[0486] As mentioned above, it was found that the characteristic length of the accumulation type transistor is shorter than that of the inversion type transistor. Explanation of the symbols

[0487] 110: Substrate, 120: Under-layer insulating film, 137: Channel region, 138: Channel region, 160: Gate insulating film, 170: Gate electrode, 210: Substrate, 220: Under-layer insulating film, 230: Oxide semiconductor film, 260: Gate insulating film, 270: Gate electrode, 400: Substrate, 402: Under-layer insulating film, 403a: First oxide film, 403b: Oxide semiconductor film, 403c: Second oxide film, 404: Multilayer film, 404a: First oxide film, 404b: Oxide semiconductor film, 404c: Second oxide film, 405a: Conductive film, 405b: Conductive film, 406a: Source electrode, 406b: Drain electrode, 407: Insulating film, 408: Gate insulating film, 409: Conductive film, 410: Gate electrode, 412: Oxide insulating film, 414: Barrier film, 416: Sidewall insulating film, 418: Sidewall insulating film, 419a: Electrode, 419b: Electrode, 420a: Wiring, 420b: Wiring, 435: Boundary, 450: Transistor, 460: Transistor, 470: Transistor, 550: Transistor, 560: Transistor, 570: Transistor, 580: Transistor, 602: Photodiode, 640: Transistor, 656: Transistor, 658: Photodiode reset signal, 659: Gate signal line, 672: Photosensor reference signal line, 700: Memory element, 701: Circuit, 702: Circuit, 703: Switch, 704: Switch, 706: Logic element, 707: Capacitor, 708: Capacitor, 709: Transistor, 710: Transistor, 713: Transistor, 714: Transistor, 720: Circuit, 1189: ROM Interface, 1190: Board, 1191: ALU, 1192: ALU Controller, 1193: Instruction Decoder, 1194: Interrupt Controller, 1195: Timing Controller, 1196: Register, 1197: Register Controller, 1198: Bus Interface, 1199: ROM, 2200: Transistor, 2201: Insulator, 2202: Wiring, 2203: Plug, 2204: Insulator, 2205: Wiring,2206: Wiring, 3001: Wiring, 3002: Wiring, 3003: Wiring, 3004: Wiring, 3005: Wiring, 3200: Transistor, 3300: Transistor, 3400: Capacitor, 8000: Television unit, 8001: Housing, 8002: Display unit, 8003: Speaker unit, 8004: CPU, 8100: Alarm device, 8101: Microcomputer, 8102: Sensor unit, 8200: Indoor unit, 8201: Housing, 8202: Air outlet, 8203: CPU, 8204: Outdoor unit, 8300: Electric freezer / refrigerator, 8301: Housing, 8302: Refrigerator door, 8303: Freezer door, 8304: CPU, 9700: Electric vehicle, 9701: Secondary battery, 9702: Circuit, 9703: Driving unit, 9704: Processing unit, The present application is based on Japanese patent application No. 2013-106284 filed with the Japan Patent Office on May 20, 2013; Japanese patent application No. 2013-147191 filed with the Japan Patent Office on July 16, 2013; Japanese patent application No. 2013-196300 filed with the Japan Patent Office on September 23, 2013; and Japanese patent application No. 2014-087067 filed with the Japan Patent Office on April 21, 2014, the full text of which is incorporated by reference into the present specification.

Claims

Claim 1 A semiconductor device comprises: a first transistor comprising silicon in a first channel forming region; and a second transistor comprising an oxide semiconductor in a second channel forming region, wherein the semiconductor device comprises: a first insulating film on the first channel forming region; a first conductive film on the first insulating film functioning as a first gate electrode of the first transistor; a second insulating film on the first conductive film; a second conductive film on the second insulating film; a third insulating film on the second conductive film; the oxide semiconductor on the third insulating film; a third conductive film on the oxide semiconductor and electrically connected to the oxide semiconductor, functioning as one of the source electrode and the drain electrode of the second transistor; a fourth conductive film formed of a conductive film such as the third conductive film; and a fourth insulating film on the third conductive film and the fourth conductive film. A semiconductor device further comprising a fifth conductive film on the fourth insulating film, wherein the third conductive film is electrically connected to one of the source electrode and drain electrode of the first transistor, and the fourth conductive film is not in contact with the oxide semiconductor. Claim 2 A semiconductor device comprises: a first transistor comprising silicon in a first channel forming region; and a second transistor comprising an oxide semiconductor in a second channel forming region, wherein the semiconductor device comprises: a first insulating film on the first channel forming region; a first conductive film on the first insulating film functioning as a first gate electrode of the first transistor; a second insulating film on the first conductive film; a second conductive film on the second insulating film; a third insulating film on the second conductive film; the oxide semiconductor on the third insulating film; a third conductive film on the oxide semiconductor and electrically connected to the oxide semiconductor, functioning as one of the source electrode and the drain electrode of the second transistor; a fourth conductive film formed of a conductive film such as the third conductive film; and a fourth insulating film on the third conductive film and the fourth conductive film. A semiconductor device further comprising a fifth conductive film on the fourth insulating film, wherein the fifth conductive film is electrically connected to the second conductive film through the fourth conductive film, the fourth conductive film does not function as one of the source electrode and drain electrode of a transistor comprising an oxide semiconductor in a channel forming region, and the fourth conductive film does not come into contact with the oxide semiconductor. Claim 3 A semiconductor device comprises: a first transistor comprising silicon in a first channel forming region; and a second transistor comprising an oxide semiconductor in a second channel forming region, wherein the semiconductor device comprises: a first insulating film on the first channel forming region; a first conductive film on the first insulating film functioning as a first gate electrode of the first transistor; a second insulating film on the first conductive film; a second conductive film on the second insulating film; a third insulating film on the second conductive film; the oxide semiconductor on the third insulating film; a third conductive film on the oxide semiconductor and electrically connected to the oxide semiconductor, functioning as one of the source electrode and the drain electrode of the second transistor; a fourth conductive film formed of a conductive film such as the third conductive film; and a fourth insulating film on the third conductive film and the fourth conductive film. A semiconductor device further comprising a fifth conductive film on the fourth insulating film, wherein the third conductive film is electrically connected to one of the source electrode and the drain electrode of the first transistor, the fifth conductive film is electrically connected to the second conductive film through the fourth conductive film, and the fourth conductive film is not in contact with the oxide semiconductor. Claim 4 delete Claim 5 delete Claim 6 A semiconductor device comprises: a first insulating film; an oxide film on the first insulating film; an oxide semiconductor film on the oxide film, the oxide semiconductor film comprising a channel forming region of the first transistor; a source electrode and a drain electrode of the first transistor electrically connected to the oxide semiconductor film; a gate insulating film of the first transistor on the oxide semiconductor film; a gate electrode of the first transistor on the gate insulating film; a second insulating film on the gate electrode of the first transistor; a first wiring on the second insulating film; and a gate electrode of the second transistor below the first insulating film. and includes a channel forming region of the second transistor below the gate electrode of the second transistor, and when nanobeam electron diffraction is performed on the oxide semiconductor film, a plurality of spots are observed within a ring-shaped pattern, the channel forming region of the second transistor comprises silicon, the lower surface of the gate electrode of the first transistor is provided below the lower surface of the oxide semiconductor film, the first insulating film includes a first region that does not overlap with the oxide film and a second region that overlaps with the oxide film, the thickness of the first region is thinner than the thickness of the second region, one of the source electrode and the drain electrode of the first transistor is electrically connected to one of the source electrode and the drain electrode of the second transistor through a first contact hole penetrating the first region of the first insulating film, the gate electrode of the first transistor is electrically connected to the first wiring, and the first wiring is connected through a second contact hole penetrating the first region of the first insulating film A semiconductor device electrically connected to the gate electrode of the second transistor. Claim 7 A semiconductor device comprises: a first insulating film; an oxide film on the first insulating film; an oxide semiconductor film on the oxide film, the oxide semiconductor film comprising a channel forming region of the first transistor; a source electrode and a drain electrode of the first transistor electrically connected to the oxide semiconductor film; a gate insulating film of the first transistor on the oxide semiconductor film; a gate electrode of the first transistor on the gate insulating film; a second insulating film on the gate electrode of the first transistor; a first wiring on the second insulating film; and a gate electrode of the second transistor below the first insulating film. and includes a channel forming region of the second transistor below the gate electrode of the second transistor, and when nanobeam electron diffraction is performed on the oxide semiconductor film, a plurality of spots are observed within a ring-shaped pattern, the channel forming region of the second transistor comprises silicon, the lower surface of the gate electrode of the first transistor is provided below the lower surface of the oxide semiconductor film, the first insulating film includes a first region that does not overlap with the oxide film and a second region that overlaps with the oxide film, the thickness of the first region is thinner than the thickness of the second region, one of the source electrode and the drain electrode of the first transistor is electrically connected to one of the source electrode and the drain electrode of the second transistor through a first contact hole penetrating the first region of the first insulating film, the gate electrode of the first transistor is electrically connected to the first wiring, and the first wiring is connected through a second contact hole penetrating the first region of the first insulating film A semiconductor device electrically connected to the gate electrode of a second transistor, wherein the first transistor is an n-channel type transistor, the second transistor is a p-channel type transistor, and the first transistor and the second transistor form an inverter. Claim 8 delete

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