Charge Trap-Based Selector-Memory Device

Abstract

A charge capture control type selector memory is disclosed. A charge capture control type selector memory according to an embodiment of the present invention may include a selector memory portion, an upper electrode stacked on the upper part of the selector memory portion to which a voltage is applied, a lower electrode stacked on the lower part of the selector memory portion to which it is grounded, and an ultrathin charge capture layer stacked at the interface between the selector memory portion and the upper electrode or the lower electrode to capture electrons or holes as a voltage is applied to the upper electrode.

Description

Technology Field

[0001] The described embodiments relate to artificial intelligence semiconductor technology. Background Technology

[0002] With the current expansion of artificial intelligence semiconductors and the facing of the limits of high-density semiconductor integration, a transition to new technologies is required. Conventional computers have separate processing units and memory; however, processing massive amounts of data results in time delays and high power consumption, necessitating more efficient computational processing.

[0003] To this end, CXL technology is being developed for seamless connectivity, and new memory is being developed that is both fast and non-volatile. To this end, Intel developed X-point memory utilizing phase-change memory; however, due to high leakage current, they commercialized a device in which a selector material was connected in series with the memory material to reduce this. Nevertheless, it failed to achieve efficiency and was eventually withdrawn due to issues such as high aspect ratios and void formation during high-density integration.

[0004] Referring to prior art 1 (publication number 10-2024-0098550, SK Hynix, Korea, published June 28, 2024) and prior art 2 (publication number 10-2022-0021550, Samsung Electronics, Korea, published February 22, 2022), the selector was basically developed by being incorporated into a semiconductor device with a structure connected in series with the memory.

[0005] Subsequently, SK Hynix developed a selector with memory functions and announced a SOM device. This device utilizes a method in which the selector's threshold voltage is modulated using pulses of different polarities to provide memory capabilities. As a highly encouraging result in overcoming aspect ratio issues, it is rapidly emerging as the next-generation memory for CXL.

[0006] However, since these SOM devices use complex compound materials of quaternary or higher, simpler compound materials are required to establish semiconductor processes, including etching, and secure yield.

[0007] In addition, current SOM structures perform memory functions by modulating the threshold voltage by supplying pulses of different polarities, but no clear mechanism has been reported yet, and it is unknown whether uniform operating characteristics can be secured over a large area.

[0008] Therefore, there is a need to discover materials and develop device structures that can perform both selector and memory functions using binary or ternary compounds or lower, while operating with a clearer conductive mechanism. The problem to be solved

[0009] The purpose of the described embodiment is to propose a selector-memory device capable of replacing existing DRAM as a next-generation memory for low power and high speed, in line with the recent increase in demand for artificial intelligence semiconductors.

[0010] The purpose of the described embodiment is to propose a device capable of performing two functions of a selector and a memory using a binary or at most ternary compound while operating as a clear conductive mechanism. means of solving the problem

[0011] A charge capture control type selector memory according to an embodiment may include a selector memory portion, an upper electrode stacked on the upper part of the selector memory portion to which voltage is applied, a lower electrode stacked on the lower part of the selector memory portion to which it is grounded, and an ultrathin charge capture layer stacked at the interface between the selector memory portion and the upper electrode or the lower electrode to capture electrons or holes as voltage is applied to the upper electrode.

[0012] At this time, the selector memory portion is composed of a chalcogenide compound and may include at least one of a binary or ternary material.

[0013] At this time, the selector memory portion can be manufactured by depositing it on the lower electrode using a semiconductor vacuum method including atomic layer deposition (ALD), sputter deposition, and vapor deposition.

[0014] At this time, the selector memory portion may have a thickness of 5 nm to 200 nm.

[0015] At this time, the ultrathin charge capture layer may have a thickness of 0.5 nm to 10 nm.

[0016] At this time, the ultrathin charge capture layer can be composed of one of an oxide and a sulfide.

[0017] At this time, the charge capture control type selector memory according to the embodiment may further include a charge supply layer stacked between the charge capture layer and the lower electrode or upper electrode to supply electrons or holes.

[0018] At this time, the charge supply layer may be composed of one of an oxide and a sulfide.

[0019] At this time, the charge supply layer may have a thickness of 5 nm to 50 nm.

[0020] A charge capture control type selector memory according to an embodiment may include a gate electrode, a gate dielectric film formed in contact with one side of the gate electrode, a charge capture layer formed on top of the gate dielectric film to capture electrons or holes, a selector formed on top of the charge capture layer, a drain electrode connected to one side of the selector on top of the gate dielectric film, and a source electrode connected to the other side of the selector on top of the gate dielectric film.

[0021] At this time, the gate dielectric film can be a general dielectric film or a charge supply dielectric film.

[0022] At this time, the selector may have a thickness of 5 to 50 nm.

[0023] At this time, the charge capture layer captures electrons or holes supplied from the selector or charge supply dielectric film as a voltage pulse or DC voltage is applied to the gate electrode, and the threshold voltage of the selector can be modulated.

[0024] A charge capture control type selector memory according to an embodiment may include a cylindrical first electrode to which voltage is applied, a cylindrical selector memory part inserted inside the first electrode, a cylindrical second electrode inserted inside the selector memory part and grounded, and an ultrathin charge capture layer inserted at the interface between the selector memory part and the second electrode or the first electrode to capture electrons or holes as voltage is applied to the upper electrode.

[0025] At this time, the selector memory portion is composed of a chalcogenide compound and may include at least one of a binary or ternary material.

[0026] At this time, a charge supply layer may be further included that is stacked between the charge capture layer and the lower electrode or the upper electrode to supply electrons or holes. Effects of the invention

[0027] According to the described embodiment, a selector-memory device can be proposed that can replace existing DRAM as a next-generation memory for low power and high speed, in line with the recent increase in demand for artificial intelligence semiconductors.

[0028] According to the described embodiments, a device can be proposed that operates as a clear conductive mechanism and can perform two functions of a selector and a memory using a binary or at most ternary compound. Brief explanation of the drawing

[0029] FIG. 1 is a cross-sectional perspective view of a charge capture control type selector memory with a two-terminal structure according to an embodiment. FIGS. 2 and 3 are diagrams for explaining the threshold voltage control of a selector by charge capture in a charge capture-controlled selector memory according to an embodiment. FIG. 4 is a cross-sectional perspective view of a charge capture control type selector memory with a two-terminal structure according to another embodiment. FIG. 5 is an example of a current-voltage relationship curve showing the change in threshold voltage of a selector and the operation process when electrons are captured by a charge capture layer in a charge capture control type selector memory of a two-terminal structure according to another embodiment. FIG. 6 is a cross-sectional perspective view of a charge capture control type selector memory with a three-terminal structure according to an embodiment. FIG. 7 is an example diagram of memory modulation characteristics using the gate pulse of a 3-terminal transistor element in a charge capture control type selector memory of a 3-terminal structure according to an embodiment. FIG. 8 is an example diagram of memory modulation characteristics using the read voltage of a charge capture control type selector memory 3-terminal transistor device of a 3-terminal structure according to an embodiment. FIG. 9 is a cross-sectional perspective view of a cylindrical two-terminal structure charge capture control type selector memory according to another embodiment. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Throughout the specification, the same reference numerals refer to the same components.

[0031] Although terms such as "first" or "second" are used to describe various components, these components are not limited by such terms. Such terms may be used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0032] The terms used herein are for describing embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used in this specification, "comprises" or "comprising" implies that the mentioned component or step does not exclude the presence or addition of one or more other components or steps.

[0033] Unless otherwise defined, all terms used in this specification may be interpreted in a sense that is commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0034] The present invention proposes a charge capture control type selector memory with a two-terminal or three-terminal structure as a device capable of implementing both selector and memory functions.

[0035] FIG. 1 is a cross-sectional perspective view of a charge capture control type selector memory with a two-terminal structure according to one embodiment.

[0036] Referring to FIG. 1, a charge capture control type selector memory according to one embodiment may include a selector memory portion (110), an upper electrode (120) stacked on the upper part of the selector memory portion (110) to which voltage is applied, a lower electrode (130) stacked on the lower part of the selector memory portion (110) to which it is grounded, and an ultrathin charge capture layer (140) stacked at the interface between the selector memory portion (110) and the upper electrode (120) or the lower electrode (130) to capture electrons or holes as voltage is applied to the upper electrode (120).

[0037] At this time, the selector memory (SM) (110) is composed of a chalcogenide compound and may include at least one of a binary or ternary material. For example, all compounds such as SiTe, SiSeTe, ZnTe, and ZnSeTe may be included.

[0038] Here, the selector memory portion (110) can be manufactured by depositing a thin film on the lower electrode (130) using a semiconductor vacuum method including atomic layer deposition (ALD), sputter deposition, and vapor deposition.

[0039] At this time, the selector memory portion (110) may have a thickness of 5 nm to 200 nm.

[0040] At this time, the ultrathin charge capture layer (140) is a very thin film that captures electrons or holes, and may have a thickness of 0.5 nm to 10 nm.

[0041] At this time, the ultrathin charge capture layer (140) may be composed of one of an oxide and a sulfide. For example, AlO X , SiO X , HfO X , ZrO X , ZnO X , TiO X , InO X , and SnO X The back is possible.

[0042] In the charge capture control type selector memory described above, when a positive voltage or a negative voltage is applied from the upper electrode (120) while the lower electrode (130) is grounded, electrons or holes are captured in the ultrathin charge capture layer (140), causing a change in the threshold voltage of the selector memory unit (110).

[0043] At this time, the charge capture layer (140) may have two types: an electron capture layer that captures electrons and a hole capture layer that captures holes.

[0044] Additionally, the charge capture layer (140) may sometimes be in a form where electrons and holes are competitively captured.

[0045] FIG. 2 is a diagram illustrating the control of the threshold voltage of a selector by electron capture in a charge capture control type selector memory according to one embodiment, and FIG. 3 is a diagram illustrating the control of the threshold voltage of a selector by hole capture in a charge capture control type selector memory according to one embodiment.

[0046] Referring to FIG. 2, a current-voltage relationship curve is shown, illustrating the change in threshold voltage of the selector and the operation process when electrons are trapped by the electron trapping layer (140). The ultrathin charge trapping layer (140) operating as shown in FIG. 2 is called the electron trapping layer.

[0047] V with a larger positive voltage value CT When a voltage pulse of (trap threshold voltage) is applied to the upper electrode (120), electrons are trapped in the electron trapping layer (140). Then, the threshold voltage of the selector moves in the negative direction, changing to state 2 as shown in FIG. 2.

[0048] Conversely, V is a voltage pulse that detraps electrons. CDWhen the voltage required for de-trapping is applied to the upper electrode (120), electrons that were trapped in the electron trapping layer (140) are released.

[0049] At this time, the voltage applied to the upper electrode (120) is typically a negative value, but it may also be a small positive value.

[0050] Then, the threshold voltage of the selector moves in the positive direction, so it changes to state 1 as shown in Fig. 3.

[0051] Meanwhile, referring to FIG. 3, a current-voltage relationship curve is shown that illustrates the change in threshold voltage of the selector and the operation process when a hole is trapped by the charge trapping layer (140). The ultrathin charge trapping layer (140) operating as shown in FIG. 3 is called a hole trapping layer.

[0052] When holes are captured in the hole trap layer, the trap threshold voltage applies a negative voltage pulse, and as shown in Fig. 3, the threshold voltage moves in the negative direction to become state 1.

[0053] Conversely, if a positive voltage pulse or a negative pulse with a small absolute value is applied for de-trapping, de-trapping occurs, the threshold voltage changes to the positive direction, and changes to state 2 in Fig. 3.

[0054] Meanwhile, the aforementioned FIG. 1 illustrates a two-terminal device composed of a selector and an ultra-thin charge capture layer, which can be extended to add a charge supply layer to the charge capture layer (140), and this can be additionally attached to either the upper electrode (120) or the lower electrode (130).

[0055] FIG. 4 is a cross-sectional perspective view of a charge capture control type selector memory with a two-terminal structure according to another embodiment.

[0056] Referring to FIG. 4, the charge capture control type selector memory according to the embodiment may further include a charge supply layer (150) that is stacked between the charge capture layer (140) and the lower electrode (130) or the upper electrode (120) to supply electrons or holes.

[0057] At this time, the charge supply layer (150) may be composed of one of an oxide and a sulfide. For example, AlO X , SiO X , HfO X , ZrO X , InO X , CuO X , and MoO X This may include the back.

[0058] This charge supply layer (150) may have a thickness of 5 nm to 50 nm.

[0059] The charge supply layer (150) serves to supply electrons or holes and is formed from a non-stoichiometric structure.

[0060] And, when an electric field is applied between the upper electrode (120) or the lower electrode (130), electrons or holes move to the charge capture layer (140) and are trapped, thereby changing the threshold voltage of the selector and exhibiting memory characteristics.

[0061] FIG. 5 is an example of a current-voltage relationship curve showing the change in threshold voltage of a selector and the operation process when electrons are captured by a charge capture layer in a charge capture control type selector memory of a two-terminal structure according to another embodiment.

[0062] Referring to FIG. 5, in a charge capture control type selector memory of a two-terminal structure according to another embodiment, a positive voltage pulse is applied to the upper electrode (120). If the charge supply layer (150) is a layer that supplies electrons, the electrons move to the charge capture layer (140) in response to the positive voltage and are trapped, and the threshold voltage moves in the positive direction overall, so that state 1 is achieved as shown in FIG. 5.

[0063] And, if a pulse is applied from the upper electrode (120) in the negative direction, electrons trapped in the charge trapping layer (140) escape, and the threshold voltage moves in the negative direction, moving as shown in FIG. 5, as in state 2.

[0064] Depending on these voltage pulses, different threshold voltages are obtained for state 1 and state 2, and the difference between these threshold voltages becomes a memory window, and a selector that performs memory operations is obtained.

[0065] Meanwhile, selector memory can be manufactured not only as a 2-terminal device but also as a 3-terminal device. When a 3-terminal device is formed, the operational stability of the device improves, and it becomes easier to access semiconductor mass production technology.

[0066] FIG. 6 is a perspective view of a charge capture control type selector memory with a three-terminal structure according to another embodiment.

[0067] Referring to FIG. 6, a charge capture control type selector memory of a three-terminal structure according to another embodiment may include a gate electrode (220), a gate dielectric film (250) formed to be in contact with one side of the gate electrode (220), a charge capture layer (250) formed on the upper side of the gate dielectric film (250) to capture electrons or holes, a selector (210) formed on the upper side of the charge capture layer (240), a drain electrode (232) connected to one side of the selector (210) on the upper side of the gate dielectric film (250), and a source electrode (231) connected to the other side of the selector (210) on the upper side of the gate dielectric film (250).

[0068] Figure 6 illustrates a bottom gate structure as an example, but this is merely an example of the present invention and is not limited thereto. That is, the charge capture control type selector memory of a three-terminal structure according to the embodiment may also be implemented in the form of a top gate structure.

[0069] Meanwhile, the gate dielectric film (250) shown in FIG. 6 may be a general dielectric film or a charge supply dielectric film as shown in FIG. 4.

[0070] Additionally, the charge capture layer (240) may have a thin thickness of 0.5 to 10 nm, as shown in FIG. 4.

[0071] And, the selector (210) may have a thickness of 5 to 50 nm.

[0072] And, the drain electrode (232) and the source electrode (231) can be manufactured using semiconductor pattern forming technology.

[0073] In a charge capture control type selector memory of a three-terminal structure according to another embodiment, the charge capture layer (240) captures electrons or holes supplied from the selector (210) or the charge supply dielectric film (250) as a voltage pulse or DC voltage is applied to the gate electrode (220), thereby allowing the threshold voltage of the selector (210) to be modulated.

[0074] That is, by applying a voltage pulse to the gate electrode (220), electrons or holes supplied from the selector (210) or the charge supply dielectric film (250) can be captured in the charge capture layer (240) or escape from the charge capture layer (240), and thereby, a memory function can be exhibited by changing the threshold voltage of the two-terminal selector element, in which the drain current increases rapidly according to the drain voltage.

[0075] When a positive voltage pulse or a negative voltage pulse is applied to the gate electrode (220), electrons or holes captured in the charge capture layer (240) cause a change in the threshold voltage of the selector in the drain voltage-drain current curve.

[0076] FIG. 7 is an example diagram of memory modulation characteristics using the gate pulse of a three-terminal transistor element in a charge capture control type selector memory of a three-terminal structure according to another embodiment, and FIG. 8 is an example diagram of memory modulation characteristics using the read voltage of a three-terminal transistor element in a charge capture control type selector memory of a three-terminal structure according to another embodiment.

[0077] Referring to FIG. 7, changes in drain voltage and drain current representing the memory characteristics of a three-terminal device using gate pulses are depicted, and selector-memory capability can be demonstrated by controlling different threshold voltages of state 1 and state 2.

[0078] In addition, another method for modulating the threshold voltage of the selector is to modulate the threshold voltage by varying the DC voltage while the DC voltage is applied, without applying pulses to the gate electrode; for convenience, this is referred to as the read voltage (V read It is defined as ).

[0079] If, V read The values ​​of V respectivelyG1 and V G2 If so, the threshold voltage can be controlled by trapping or detrapping electrons or holes in the charge trapping layer under each gate voltage.

[0080] Referring to Fig. 8, such V read The relationship between the drain voltage and drain current of a memory modulation characteristic, which indicates that the threshold voltage is modulated by controlling the value of , is shown.

[0081] In this case, there is an advantage in that the threshold voltage can be controlled simply by setting the DC value of the gate voltage without separately applying a voltage pulse to the gate electrode.

[0082] Meanwhile, as the high integration of semiconductor devices progresses, transistors with a three-dimensional structure are being developed.

[0083] FIG. 9 is a cross-sectional perspective view of a cylindrical two-terminal structure charge capture control type selector memory according to another embodiment.

[0084] Referring to FIG. 9, a charge capture control type selector memory according to another embodiment may include a cylindrical selector memory portion (310), a cylindrical first electrode (320) that accommodates the selector memory (310) inside and to which voltage is applied, a cylindrical second electrode (330) that is inserted into the selector memory portion (310) and grounded, and an ultrathin charge capture layer (340) that is inserted at the interface between the selector memory portion (310) and the first electrode (320) or the second electrode (320) and captures electrons or holes as voltage is applied to the first electrode (310).

[0085] At this time, the selector memory portion (310) is composed of a chalcogenide compound and may include at least one of a binary or ternary material.

[0086] At this time, a charge supply layer (not shown) that supplies electrons or holes may be further included, stacked between the charge capture layer (340) and the lower electrode (330) or the upper electrode (340).

[0087] This is one embodiment, and in the case of a 3-terminal, it can be manufactured in a similar 3-dimensional structure, and the present invention includes such a 3-dimensional selector-memory structure.

[0088] According to the embodiments described above, the structure and material of charge-trapping selector-memory devices with two-terminal and three-terminal forms were presented.

[0089] The described embodiment is a charge-trapping type with high operational stability and durability, high speed, and CMOS compatibility, thus meeting the requirements for a next-generation memory.

[0090] It can be directly utilized as a Selector Only Memory (SOM), and mainly uses micro-semiconductor processes such as atomic layer deposition. Since it is possible to manufacture three-dimensional structures, it can be utilized even when linewidths are reduced in the future, and it can be applied as a next-generation memory device.

[0091] In addition, high compatibility with semiconductor processes, the ability to manufacture large-area products, and high material durability are expected to result in low barriers to mass production.

[0092] If the implementation of such memory devices becomes possible, they will have significant advantages over existing HBM in terms of latency between the computing unit and memory of current AI semiconductors and processing large amounts of data, and it is expected that power consumption can be drastically reduced as integration with the computing unit becomes easier in the future.

[0093] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 A charge capture control type selector memory comprising: a gate electrode; a gate dielectric film formed in contact with one side of the gate electrode; a charge capture layer formed on top of the gate dielectric film; a selector formed on top of the charge capture layer; a drain electrode connected to one side of the selector on top of the gate dielectric film; and a source electrode connected to the other side of the selector on top of the gate dielectric film, wherein the charge capture layer selectively captures electrons or holes supplied from the selector or releases them from the charge capture layer as a voltage pulse or DC voltage is applied to the gate electrode, and the threshold voltage of the selector is modulated according to the capture or release of electrons or holes to form different threshold voltage states. Claim 11 In claim 10, the gate dielectric film is a charge-capturing controlled selector memory, which is a charge-supplying dielectric film. Claim 12 In claim 10, the selector is a charge capture control type selector memory having a thickness of 5 to 50 nm. Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete

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