Display panel

Abstract

The display device includes a first pixel and a second pixel. A light-emitting element and a driving circuit of the second pixel are disposed in a second region. The first pixel includes a silicon transistor and an oxide transistor disposed in the second region. The first pixel includes a connecting wire that electrically connects one of the transistors and a light-emitting element disposed in the first region. The connecting wire is disposed on the same layer as the oxide semiconductor pattern and includes a transparent conductive oxide.

Description

Technology Field

[0001] The present invention relates to a display panel with improved flexibility. Background Technology

[0002] Electronic devices such as smartphones, tablets, laptop computers, car navigation systems, and smart televisions are being developed. These electronic devices are equipped with display devices to provide information.

[0003] Various types of display devices are being developed to satisfy user UX / UI. Among them, the development of flexible display devices has been active. The problem to be solved

[0004] The present invention aims to provide a display panel with improved impact resistance. means of solving the problem

[0005] A display panel according to one embodiment of the present invention comprises a base layer including a boundary region and a pixel region; a plurality of insulating layers disposed on the base layer, wherein an opening corresponding to the boundary region is defined; a first organic layer disposed on the plurality of insulating layers and filling the opening; a pixel circuit superimposed on the pixel region; a light-emitting element superimposed on the pixel region, electrically connected to the pixel circuit, and disposed on the first organic layer; and a first conductive line superimposed on the boundary region, extending in substantially the same direction as the boundary region, disposed on the first organic layer, and electrically connected to the pixel circuit.

[0006] The boundary region may include a first region extended in a first direction and a second region extended in a second direction intersecting the first direction. The opening may include a first opening region extended in the first direction and a second opening region extended from the first opening region in the second direction. The first conductive line may extend in the first direction or extend in the second direction.

[0007] It may further include a second organic layer disposed on the first organic layer and a second conductive line disposed on the second organic layer. The first conductive line may extend in the first direction, and the second conductive line may extend in the second direction.

[0008] It may further include a second organic layer disposed on the first organic layer and a second conductive line disposed on the second organic layer. The first conductive line may overlap the first region and the first opening region, and the second conductive line may overlap the second region and the second opening region.

[0009] The second conductive line can be connected to the first conductive line through a contact hole penetrating the second organic layer.

[0010] It may further include a second organic layer disposed on the first organic layer and a second conductive line disposed on the second organic layer. The first conductive line and the second conductive line may overlap different regions of the first region or overlap different regions of the second region.

[0011] The first conduction line and the second conduction line can receive different signals or different voltages.

[0012] The pixel circuit above may include a silicon transistor or an oxide transistor.

[0013] The first conductive line above can receive a data signal or power voltage.

[0014] It may further include a data driving circuit electrically connected to the first conduction line. The boundary region may include a first region extended in a first direction and a second region extended in a second direction intersecting the first direction.

[0015] The above opening may include a first opening region extended in the first direction and a second opening region extended in the second direction from the first opening region.

[0016] The first conductive line may include a first line overlapping the first region and the first opening region, and a second line overlapping the second region and the second opening region.

[0017] The pixel regions are provided in plurality, and the boundary regions surround each of the plurality of pixel regions on a plane, and one, two, or four light-emitting elements may be arranged in each of the plurality of pixel regions.

[0018] A second conductive line may be further included. The second conductive line may include a first conductive pattern placed below the first organic layer and a boundary area that overlaps the pixel area and intersects the boundary area, and a second conductive pattern placed on the first organic layer and connected to the first conductive pattern.

[0019] The pixel circuit may include a first transistor including a first gate and a silicon semiconductor pattern, and a second transistor including a second gate and an oxide semiconductor pattern.

[0020] The plurality of insulating layers may include a buffer inorganic layer below the silicon semiconductor pattern, a first inorganic layer on the silicon semiconductor pattern, a second inorganic layer on the first inorganic layer and the first gate, a third inorganic layer between the second inorganic layer and the oxide semiconductor pattern, a fourth inorganic layer on the third inorganic layer and the oxide semiconductor pattern, and a fifth inorganic layer on the fourth inorganic layer and the second gate.

[0021] The above-mentioned fourth inorganic layer overlaps the above-mentioned second gate and exposes a non-overlapping region of the above-mentioned oxide semiconductor pattern to the above-mentioned second gate.

[0022] A display panel according to one embodiment of the present invention may include a base layer comprising a boundary region and a pixel region, a plurality of inorganic layers disposed on the base layer having an opening defined in the boundary region, an organic pattern filling the opening, a pixel circuit superimposed on the pixel region, a light-emitting element superimposed on the pixel region and electrically connected to the pixel circuit and disposed on the plurality of inorganic layers, and a conductive line superimposed on the boundary region, extending in substantially the same direction as the boundary region, disposed on the organic pattern, and electrically connected to the pixel circuit.

[0023] It may further include an insulating layer disposed on the plurality of inorganic layers and having a first opening defined therein that exposes the organic pattern. The conductive line may be disposed at least inside the first opening.

[0024] A portion of the above organic pattern may be placed on the uppermost inorganic layer among the plurality of inorganic layers.

[0025] The above-mentioned conductive line can contact the upper surface of the above-mentioned organic pattern.

[0026] The above-mentioned plurality of inorganic layers may further include an insulating layer disposed thereon. The conductive line may include a first conductive line and a second conductive line that intersect each other. The insulating layer may be disposed between the first conductive line and the second conductive line. The organic pattern may include a first organic pattern extending in a first direction and overlapping with the first conductive line, and a second organic pattern extending in a second direction intersecting with the first direction and overlapping with the second conductive line. The first conductive line and the second conductive line may be connected through a contact hole penetrating the insulating layer.

[0027] A display panel according to one embodiment of the present invention may include a base layer comprising a first pixel area, a second pixel area, and a boundary area between the first pixel area and the second pixel area; a first stacked structure corresponding to the first pixel area; a second stacked structure corresponding to the second pixel area and spaced apart from the first stacked structure and the boundary area; an organic material that fills the space between at least the first stacked structure and the second stacked structure and overlaps the boundary area; a transistor and a light-emitting element disposed in the first pixel area; and a conductive line disposed on the organic material, extending in substantially the same direction as the boundary area and electrically connected to the transistor or the light-emitting element. Each of the first stacked structure and the second stacked structure may include a plurality of inorganic layers. Effects of the invention

[0028] As described above, the boundary region can divide the display region into multiple pixel regions. The stacked structure of inorganic layers is divided into island-shaped stacked structures. The island-shaped stacked structures are arranged in each pixel region. The stacked structure of inorganic layers can improve the impact resistance of the display panel compared to the stacked structure of inorganic layers formed commonly in the display region.

[0029] Organic material fills the openings of the inorganic layers formed in the boundary region. The organic material forms an organic pattern or an organic layer. Conductive lines can be placed on the organic pattern or organic layer. The conductive lines can be signal lines or voltage lines. By securing an area outside the pixel region where conductive lines are placed, the design of the pixel circuit within the pixel region becomes more flexible. Brief explanation of the drawing

[0030] FIG. 1 is a plan view of a display panel according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of a pixel according to one embodiment of the present invention. FIG. 4 is an enlarged plan view of a display panel according to one embodiment of the present invention. FIGS. 5A and FIGS. 5B are cross-sectional views of a display panel according to one embodiment of the present invention. FIGS. 6a and FIGS. 6b are plan views illustrating a conductive line according to an embodiment of the present invention. FIGS. 7A and FIGS. 7B are plan views illustrating a conductive line according to an embodiment of the present invention. FIG. 8 is an enlarged plan view of a display panel according to one embodiment of the present invention. FIGS. 9a and FIGS. 9b are enlarged plan views of a display area according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of a display panel according to one embodiment of the present invention. FIGS. 11a and FIGS. 11b are cross-sectional views of a display panel according to an embodiment of the present invention. Specific details for implementing the invention

[0031] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0032] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And / or” includes all one or more combinations that the associated components may define.

[0033] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0034] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0035] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0037] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0039] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0040] FIG. 1 is a plan view of a display panel (100) according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of a display panel (100) according to one embodiment of the present invention.

[0041] Referring to FIG. 1, a display panel (100) may include a display area (100-A) and a peripheral area (100-NA). The peripheral area (100-NA) is adjacent to the display area (100-A) and may surround at least a portion of the display area (100-A). A pixel (PX) is placed in the display area (100-A), and a pixel (PX) is not placed in the peripheral area (100-NA). A data driving circuit (DDC) may be placed on one side of the peripheral area (100-NA).

[0042] The display area (100-A) may include a plane defined by a first direction (DR1) and a second direction (DR2). The thickness direction of the display panel (100) may be a third direction (DR3), which is the normal direction of the display area (100-A). The front (or top) and back (or bottom) surfaces of the members constituting the display panel (100) may be defined based on the third direction (DR3).

[0043] The display panel (100) may be a light-emitting display panel, for example, the display panel (100) may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro LED display panel, or a nano LED display panel.

[0044] As illustrated in FIG. 2, the display panel (100) may include a base layer (110), a circuit layer (120), a light-emitting element layer (130), and an encapsulation layer (140). Another functional layer may be further disposed between two adjacent layers among the base layer (110), the circuit layer (120), the light-emitting element layer (130), and the encapsulation layer (140).

[0045] The base layer (110) may provide a base surface on which the circuit layer (120) is placed. The base layer (110) may be a flexible substrate capable of bending, folding, rolling, etc. The base layer (110) may be a glass substrate, a metal substrate, or a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer (110) may be an inorganic layer, an organic layer, or a composite material layer.

[0046] The base layer (110) may have a multilayer structure. For example, the base layer (110) may include a first synthetic resin layer, a multilayer or single-layer inorganic layer, and a second synthetic resin layer disposed on the multilayer or single-layer inorganic layer. Each of the first and second synthetic resin layers may include a polyimide-based resin, and is not particularly limited.

[0047] A circuit layer (120) may be disposed on a base layer (110). The circuit layer (120) may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line, etc.

[0048] The light-emitting element layer (130) may be disposed on the circuit layer (120). The light-emitting element layer (130) may include a light-emitting element. For example, the light-emitting element may include an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0049] The encapsulation layer (140) may be disposed on the light-emitting element layer (130). The encapsulation layer (140) may protect the light-emitting element layer (130) from foreign substances such as moisture, oxygen, and dust particles. The encapsulation layer (140) may include at least one inorganic layer. The encapsulation layer (140) may include a stacked structure of an inorganic layer / organic layer / inorganic layer.

[0051] FIG. 3 is an equivalent circuit diagram of a pixel (PX) according to one embodiment of the present invention.

[0052] Referring to FIG. 3, a pixel (PX) may include a light-emitting element (LD) and a pixel circuit (PC). The light-emitting element (LD) may be a component included in the light-emitting element layer (130) of FIG. 2, and the pixel circuit (PC) may be a component included in the circuit layer (120) of FIG. 2. The pixel circuit (PC) is connected to a plurality of conductive lines (SL1, SL2, SLp, SLn, EL, DL, VL1, VL2, PL). The plurality of conductive lines (SL1, SL2, SLp, SLn, EL, DL, VL1, VL2, PL) may include scan lines (SL1, SL2, SLp, SLn), light-emitting control lines (EL), data lines (DL), a first initialization voltage line (VL1), a second initialization voltage line (VL2), and a power supply voltage line (PL). Multiple conduction lines (SL1, SL2, SLp, SLn, EL, DL, VL1, VL2, PL) may be a configuration included in the circuit layer (120) of FIG. 2.

[0053] The pixel circuit (PC) may include a plurality of transistors (T1 to T7, or thin-film transistors) and a storage capacitor (Cst). The plurality of transistors (T1 to T7) may include a driving transistor (T1, or the first transistor), a switching transistor (T2, or the second transistor), a compensation transistor (T3, or the third transistor), a first initialization transistor (T4, or the fourth transistor), an operation control transistor (T5, or the fifth transistor), a light emission control transistor (T6, or the sixth transistor), and a second initialization transistor (T7, or the seventh transistor). The light-emitting element (LD) may include a first electrode (e.g., an anode electrode or a pixel electrode) and a second electrode (e.g., a cathode electrode or a common electrode), and the first electrode of the light-emitting element (LD) is connected to the driving transistor (T1) via the light emission control transistor (T6) to provide a driving current (I LD) is provided, and the second electrode may be provided with a low power voltage (ELVSS). The light-emitting element (LD) is provided with a driving current (I LD It can generate light of a luminance corresponding to ).

[0054] Some of the plurality of transistors (T1 to T7) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs). For example, among the plurality of transistors (T1 to T7), the compensation transistor (T3) and the first initialization transistor (T4) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs).

[0055] According to one embodiment of the present invention, among a plurality of transistors (T1 to T7), the compensation transistor (T3), the first initialization transistor (T4), and the second initialization transistor (T7) may be NMOS, and the remainder may be PMOS. According to one embodiment of the present invention, only one of the plurality of transistors (T1 to T7) may be NMOS, and the remainder may be PMOS. According to one embodiment of the present invention, all of the plurality of transistors (T1 to T7) may be NMOS, or all of them may be PMOS.

[0056] The signal line may include a first current scan line (SL1) that transmits a first scan signal (Sn), a second current scan line (SL2) that transmits a second scan signal (Sn'), a prior scan line (SLp) that transmits a previous scan signal (Sn-1) to a first initialization transistor (T4), a light emission control line (EL) that transmits a light emission control signal (En) to an operation control transistor (T5) and a light emission control transistor (T6), a next scan line (SLn) that transmits a subsequent scan signal (Sn+1) to a second initialization transistor (T7), and a data line (DL) that intersects with the first current scan line (SL1) and transmits a data signal (Dm).

[0057] The power supply voltage line (PL) transmits a high power supply voltage (ELVDD) to the driving transistor (T1), and the first initialization voltage line (VL1) can transmit a first initialization voltage (Vint1) that initializes the driving transistor (T1). The gate of the driving transistor (T1) is connected to a storage capacitor (Cst), the source of the driving transistor (T1) is connected to the power supply voltage line (PL) via an operation control transistor (T5), and the drain of the driving transistor (T1) can be electrically connected to the first electrode of the light-emitting element (LD) via a light-emitting control transistor (T6). The driving transistor (T1) receives a data signal (Dm) according to the switching operation of the switching transistor (T2) and transmits a driving current (I) to the light-emitting element (LD). LD Can supply ).

[0058] The gate of the switching transistor (T2) is connected to the first current scan line (SL1) that transmits the first scan signal (Sn), the source of the switching transistor (T2) is connected to the data line (DL), and the drain of the switching transistor (T2) is connected to the source of the driving transistor (T1) and can be connected to the power supply voltage line (PL) via the operation control transistor (T5). The switching transistor (T2) can perform a switching operation in which it is turned on according to the first scan signal (Sn) received through the first current scan line (SL1) and transmits the data signal (Dm) transmitted to the data line (DL) to the source of the driving transistor (T1).

[0059] The gate of the compensation transistor (T3) is connected to the second current scan line (SL2). The drain of the compensation transistor (T3) is connected to the drain of the driving transistor (T1) and can be connected to the first electrode of the light-emitting element (LD) via the light-emitting control transistor (T6). The source of the compensation transistor (T3) can be connected to the first electrode (CE10) of the storage capacitor (Cst) and the gate of the driving transistor (T1). Additionally, the source of the compensation transistor (T3) can be connected to the drain of the first initialization transistor (T4).

[0060] The compensation transistor (T3) is turned on according to the second scan signal (Sn') received through the second current scan line (SL2) to electrically connect the gate and drain of the driving transistor (T1), thereby allowing the driving transistor (T1) to be diode-connected.

[0061] The gate of the first initialization transistor (T4) can be connected to the previous scan line (SLp). The source of the first initialization transistor (T4) can be connected to the source of the second initialization transistor (T7) and the first initialization voltage line (VL1). The drain of the first initialization transistor (T4) can be connected to the first electrode (CE10) of the storage capacitor (Cst), the source of the compensation transistor (T3), and the gate of the driving transistor (T1). The first initialization transistor (T4) can perform an initialization operation by turning on according to the previous scan signal (Sn-1) received through the previous scan line (SLp) to transmit an initialization voltage (Vint1) to the gate of the driving transistor (T1) and initialize the voltage of the gate of the driving transistor (T1).

[0062] The gate of the operation control transistor (T5) is connected to the light emission control line (EL), the operation control source of the operation control transistor (T5) is connected to the power supply voltage line (PL), and the drain of the operation control transistor (T5) can be connected to the source of the driving transistor (T1) and the drain of the switching transistor (T2).

[0063] The gate of the light-emitting control transistor (T6) is connected to the light-emitting control line (EL), and the light-emitting control source of the light-emitting control transistor (T6) is connected to the drain of the driving transistor (T1) and the drain of the compensation transistor (T3), and the drain of the light-emitting control transistor (T6) can be electrically connected to the drain of the second initialization transistor (T7) and the first electrode of the light-emitting element (LD).

[0064] The operation control transistor (T5) and the light emission control transistor (T6) are simultaneously turned on according to the light emission control signal (En) received through the light emission control line (EL), so that the high power supply voltage (ELVDD) is transmitted to the light-emitting element (LD) and the driving current (I) to the light-emitting element (LD) LD Make ) flow.

[0065] The gate of the second initialization transistor (T7) is subsequently connected to the scan line (SLn), the drain of the second initialization transistor (T7) is connected to the drain of the light emission control transistor (T6) and the first electrode of the light-emitting element (LD), and the source of the second initialization transistor (T7) is connected to the second initialization voltage line (VL2) to receive the second initialization voltage (Vint2). The second initialization transistor (T7) is subsequently turned on according to the scan signal (Sn+1) received through the scan line (SLn) to initialize the first electrode of the light-emitting element (LD).

[0066] In another embodiment, the second initialization transistor (T7) can be connected to the light emission control line (EL) and driven according to the light emission control signal (En). Meanwhile, the positions of the source and drain can be swapped depending on the type of transistor (p-type or n-type).

[0067] The storage capacitor (Cst) may include a first electrode (CE10) and a second electrode (CE20). The first electrode (CE10) of the storage capacitor (Cst) is connected to the gate of the driving transistor (T1), and the second electrode (CE20) of the storage capacitor (Cst) is connected to the power supply voltage line (PL). The storage capacitor (Cst) may store a charge corresponding to the difference between the voltage of the gate of the driving transistor (T1) and the high power supply voltage (ELVDD).

[0068] The boosting capacitor (Cbs) may include a first electrode (CE11) and a second electrode (CE21). The first electrode (CE11) of the boosting capacitor (Cbs) is connected to the first electrode (CE11) of the storage capacitor (Cst), and the second electrode (CE21) of the boosting capacitor (Cbs) may receive a first scan signal (Sn). The boosting capacitor (Cbs) can compensate for a voltage drop in the gate by increasing the voltage in the gate of the driving transistor (T1) at the point when the provision of the first scan signal (Sn) is stopped.

[0069] The specific operation of each pixel (PX) according to one embodiment is as follows.

[0070] During the initialization period, when a previous scan signal (Sn-1) is supplied through the previous scan line (SLp), the first initialization transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving transistor (T1) is initialized by the initialization voltage (Vint1) supplied from the first initialization voltage line (VL1).

[0071] During the data programming period, when a first scan signal (Sn) and a second scan signal (Sn') are supplied through the first current scan line (SL1) and the second current scan line (SL2), the switching transistor (T2) and the compensation transistor (T3) are turned on in response to the first scan signal (Sn) and the second scan signal (Sn'). At this time, the driving transistor (T1) is diode-connected by the turned-on compensation transistor (T3) and is forward-biased.

[0072] Then, a compensation voltage (Dm+Vth, where Vth is a negative value) that is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data signal (Dm) supplied from the data line (DL) is applied to the gate of the driving transistor (T1).

[0073] A high power supply voltage (ELVDD) and a compensation voltage (Dm+Vth) are applied across the storage capacitor (Cst), and a charge corresponding to the voltage difference across the storage capacitor (Cst) is stored.

[0074] During the light emission period, the operation control transistor (T5) and the light emission control transistor (T6) are turned on by the light emission control signal (En) supplied from the light emission control line (EL). The driving current (I) depends on the voltage difference between the gate voltage of the driving transistor (T1) and the high power supply voltage (ELVDD). LD ) is generated, and a driving current (I) is produced through the light-emitting control transistor (T6).LD ) is supplied to the light-emitting diode (LD).

[0075] In this embodiment, at least one of the plurality of transistors (T1 to T7) includes a semiconductor layer containing oxide, and the remainder includes a semiconductor layer containing silicon. Specifically, the driving transistor (T1), which directly affects the brightness of the display device, is configured to include a semiconductor layer composed of polycrystalline silicon with high reliability, thereby enabling the realization of a high-resolution display device. Meanwhile, since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even when the driving time is long. That is, since the color change of the image due to voltage drop is not significant even during low-frequency driving, low-frequency driving is possible.

[0076] As such, since oxide semiconductors have the advantage of low leakage current, at least one of the compensation transistor (T3) connected to the gate of the driving transistor (T1), the first initialization transistor (T4), and the second initialization transistor (T7) is adopted as an oxide semiconductor to prevent leakage current from flowing to the gate and at the same time reduce power consumption.

[0078] FIG. 4 is an enlarged plan view of a display panel (100) according to an embodiment of the present invention. FIG. 5a and FIG. 5b are cross-sectional views of a display panel (100) according to an embodiment of the present invention. FIG. 6a and FIG. 6b are plan views illustrating a conductive line (SL) according to an embodiment of the present invention.

[0079] FIG. 4 illustrates an enlarged view of two pixel rows (PXLi, PXLi+1). The i-th pixel row (PXLi) may include a first color pixel (PX1), a second color pixel (PX2), a third color pixel (PX3), and a second color pixel (PX2) arranged in a first direction (DR1). The i+1-th pixel row (PXLi+1) may include a third color pixel (PX3), a second color pixel (PX2), a first color pixel (PX1), and a second color pixel (PX2) arranged in a first direction (DR1). The four color pixels of the pixel rows (PXLi, PXLi+1) shown in FIG. 4 may be repeatedly arranged along the first direction (DR1). The color pixels of the pixel rows (PXLi, PXLi+1) shown in FIG. 4 may be repeatedly arranged along the second direction (DR2).

[0080] The display area (100-A) may include a plurality of pixel areas (PA) and a boundary area (BA) between the plurality of pixel areas (PA). The boundary area (BA) may surround each of the plurality of pixel areas (PA).

[0081] In a plurality of pixel regions (PA), pixel circuits (PC1, PC2, PC3) of a first color pixel (PX1), a second color pixel (PX2), and a third color pixel (PX3) are respectively arranged. Each of the pixel circuits (PC1, PC2, PC3) is the same as the pixel circuit (PC) described with reference to FIG. 3. Although each of the pixel circuits (PC1, PC2, PC3) is depicted as substantially corresponding to the pixel region (PA), it is not limited thereto.

[0082] It is sufficient for the pixel area (PA) to be defined as an area within the display area (100-A) that is not a boundary area (BA). The boundary area (BA) is an area defined by the aperture (BA-OP, see FIG. 5) described later, and the display area (100-A) that does not overlap with the aperture (BA-OP, see FIG. 5) corresponds to the pixel area (PA). In this embodiment, it is shown that one of the first color pixel (PX1), the second color pixel (PX2), and the third color pixel (PX3) is placed in each pixel area (PA), but multiple color pixels may be placed in a single pixel area (PA).

[0083] A first light-emitting element (LD1), a second light-emitting element (LD2), and a third light-emitting element (LD3) are respectively arranged in a plurality of pixel regions (PA). In FIG. 4, a dotted anode is shown representing the first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3), respectively.

[0084] In FIG. 4, the first current scan line (SL1i) of the i-th pixel row (PXLi) and the first current scan line (SL1i+1) of the i+1-th pixel row (PXLi+1) are illustrated to represent the scan lines (SL1, SL2, SLp, SLn, see FIG. 3). In FIG. 4, the light emission control line (EL), data line (DL), first initialization voltage line (VL1), and second initialization voltage line (VL2) illustrated in FIG. 3 are not illustrated.

[0085] A power supply voltage line (PL) is shown in FIG. 4. The power supply voltage line (PL) can receive a high power supply voltage (ELVDD) or a low power supply voltage (ELVSS) as described with reference to FIG. 3.

[0086] The power voltage line (PL) may include a first power line (PL1) extended in a first direction (DR1) and a second power line (PL2) extended in a second direction (DR2). The power voltage line (PL) may include only one component of either the first power line (PL1) or the second power line (PL2).

[0087] The power voltage line (PL) overlaps the boundary region (BA). The power voltage line (PL) extends substantially in the same direction as the boundary region (BA). The boundary region (BA) may include a first region (BA1) extending in a first direction (DR1) and a second region (BA2) extending in a second direction (DR2). The first power line (PL1) extends in the first direction (DR1) and overlaps the first region (BA1). The second power line (PL2) extends in the second direction (DR2) and overlaps the second region (BA2). The intersection region of the first power line (PL1) and the second power line (PL2) overlaps the intersection region of the first region (BA1) and the second region (BA2).

[0088] In FIG. 5a, a silicon transistor (S-TFT) and an oxide transistor (O-TFT) of a second light-emitting element (LD2) and a second pixel circuit (PC2, see FIG. 4) are illustrated. In the equivalent circuit illustrated in FIG. 3, the third and fourth transistors (T3, T4) may be oxide transistors (O-TFTs), and the remaining transistors may be silicon transistors (S-TFTs). In one embodiment of the present invention, the pixel circuit may include only one type of transistor among silicon transistors (S-TFTs) and oxide transistors (O-TFTs).

[0089] A buffer layer (10br) may be disposed on a base layer (110). The buffer layer (10br) can prevent metal atoms or impurities from the base layer (110) from diffusing to the upper first semiconductor pattern (SP1). The first semiconductor pattern (SP1) includes an active region (AC1) of a silicon transistor (S-TFT). The buffer layer (10br) can control the rate of heat supply during the crystallization process for forming the first semiconductor pattern (SP1) so that the first semiconductor pattern (SP1) is formed uniformly. The buffer layer (10br) may include at least one inorganic layer. The buffer layer (10br) of the inorganic layer may be referred to as a buffer inorganic layer. The buffer layer (10br) may include a silicon oxide layer and a silicon nitride layer.

[0090] A first back metal layer (BMLa) may be disposed below a silicon transistor (S-TFT), and a second back metal layer (BMLb) may be disposed below an oxide transistor (O-TFT). The first and second back metal layers (BMLa, BMLb) may overlap with first to third pixel circuits (PC1, PC2, PC3, see FIG. 4). The first and second back metal layers (BMLa, BMLb) may block external light from reaching the first to third pixel circuits (PC1, PC2, PC3).

[0091] The first back metal layer (BMLa) may be positioned to correspond to at least a portion of each of the first to third pixel circuits (PC1, PC2, PC3, see FIG. 4). The first back metal layer (BMLa) may be positioned to overlap with a driving transistor (T1, see FIG. 3) implemented as a silicon transistor (S-TFT).

[0092] A first back metal layer (BMLa) may be disposed between a base layer (110) and a buffer layer (10br). In one embodiment of the present invention, a barrier inorganic layer may be further disposed between the first back metal layer (BMLa) and the buffer layer (10br). The first back metal layer (BMLa) may be connected to an electrode or wiring and may receive a static voltage or signal from them. According to one embodiment of the present invention, the first back metal layer (BMLa) may be a floating electrode in a form isolated from other electrodes or wiring.

[0093] The second back metal layer (BMLb) may be positioned corresponding to the bottom of the oxide transistor (O-TFT). The second back metal layer (BMLb) may be positioned between the second insulating layer (20) and the third insulating layer (30). The second back metal layer (BMLb) may be positioned on the same layer as the second electrode (CE20) of the storage capacitor (Cst). The second back metal layer (BMLb) may be connected to the contact electrode (BML2-C) to receive a constant voltage or signal. The contact electrode (BML2-C) may be positioned on the same layer as the gate (GT2) of the oxide transistor (O-TFT).

[0094] Each of the first back metal layer (BMLa) and the second back metal layer (BMLb) may include a reflective metal. For example, each of the first back metal layer (BMLa) and the second back metal layer (BMLb) may include silver (Ag), an alloy containing silver (Ag), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), and p+-doped amorphous silicon. The first back metal layer (BMLa) and the second back metal layer (BMLb) may include the same material or different materials.

[0095] Although not separately described, according to one embodiment of the present invention, the second back metal layer (BMLb) may be omitted. The first back metal layer (BMLa) may extend to the bottom of the oxide transistor (O-TFT) so that the first back metal layer (BMLa) can block light incident on the bottom of the oxide transistor (O-TFT).

[0096] The first semiconductor pattern (SP1) may be disposed on the buffer layer (10br). The first semiconductor pattern (SP1) may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern (SP1) may include low-temperature polysilicon.

[0097] FIG. 5a illustrates only a portion of the first semiconductor pattern (SP1) disposed on the buffer layer (10br), and additional first semiconductor patterns (SP1) may be disposed in other areas. The first semiconductor pattern (SP1) may be arranged according to a specific rule across the pixel area (PA, see FIG. 4). The electrical properties of the first semiconductor pattern (SP1) may differ depending on whether it is doped. The first semiconductor pattern (SP1) may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or a region doped at a lower concentration compared to the first region.

[0098] The conductivity of the first region is greater than the conductivity of the second region, and the first region can substantially function as an electrode or a signal line. The second region can substantially correspond to the active region (or channel) of the transistor. In other words, a part of the first semiconductor pattern (SP1) may be the active region of the transistor, another part may be the source or drain of the transistor, and yet another part may be a connecting electrode or a connecting signal line.

[0099] The source region (SE1, or source), active region (AC1, or channel), and drain region (DE1, or drain) of the silicon transistor (S-TFT) can be formed from the first semiconductor pattern (SP1). The source region (SE1) and the drain region (DE1) can extend in opposite directions from the active region (AC1) on a cross-section.

[0100] The first insulating layer (10) may be disposed on a buffer layer (10br). The first insulating layer (10) overlaps in common with a plurality of pixels (PX1, PX2, PX3, see FIG. 4) and may cover a first semiconductor pattern (SP1). The first insulating layer (10) may be an inorganic layer and may have a single-layer or multi-layer structure. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer (10) may be a single-layer silicon oxide layer. The inorganic layer of the circuit layer (120) described below, as well as the first insulating layer (10), may have a single-layer or multi-layer structure and may include at least one of the materials described above, but is not limited thereto.

[0101] The gate (GT1) of the silicon transistor (S-TFT) is placed on the first insulating layer (10). The gate (GT1) may be part of a metal pattern. The gate (GT1) overlaps the active region (AC1). In the process of doping the first semiconductor pattern (SP1), the gate (GT1) may function as a mask. The gate (GT1) may include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0102] A second insulating layer (20) is disposed on the first insulating layer (10) and can cover the gate (GT1). A third insulating layer (30) can be disposed on the second insulating layer (20). A second electrode (CE20) of a storage capacitor (Cst) can be disposed between the second insulating layer (20) and the third insulating layer (30). Additionally, a first electrode (CE10) of a storage capacitor (Cst) can be disposed between the first insulating layer (10) and the second insulating layer (20). The second insulating layer (20) and the third insulating layer (30) may be inorganic layers.

[0103] The second semiconductor pattern (SP2) may be disposed on the third insulating layer (30). The second semiconductor pattern (SP2) may include an active region (AC2) of an oxide transistor (O-TFT). The second semiconductor pattern (SP2) may include an oxide semiconductor. The second semiconductor pattern (SP2) may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0104] The oxide semiconductor may include multiple regions distinguished by whether the transparent conductive oxide is reduced. The region where the transparent conductive oxide is reduced (hereinafter, the reduced region) has greater conductivity than the region where it is not reduced (hereinafter, the non-reduced region). The reduced region substantially serves as the source / drain or signal line of the transistor. The non-reduced region substantially corresponds to the semiconductor region (or active region or channel) of the transistor. In other words, some regions of the second semiconductor pattern (SP2) may be the semiconductor region of the transistor, some regions may be the source / drain region of the transistor, and other regions may be the signal transmission region.

[0105] The source region (SE2, or source), active region (AC2, or channel), and drain region (DE2, or drain) of the oxide transistor (O-TFT) can be formed from a second semiconductor pattern (SP2). The source region (SE2) and the drain region (DE2) can extend in opposite directions from the active region (AC2) on a cross-section.

[0106] The fourth insulating layer (40) may be placed on the third insulating layer (30). The fourth insulating layer (40) may cover the second semiconductor pattern (SP2). As shown in FIG. 5a, the gate (GT2) of the oxide transistor (O-TFT) is placed on the fourth insulating layer (40). The gate (GT2) of the oxide transistor (O-TFT) may be part of the metal pattern. The gate (GT2) of the oxide transistor (O-TFT) overlaps the active region (AC2).

[0107] The fifth insulating layer (50) is disposed on the fourth insulating layer (40) and can cover the gate (GT2). The first connecting electrode (CNE1) can be disposed on the fifth insulating layer (50). The fourth insulating layer (40) and the fifth insulating layer (50) may be inorganic layers. The first connecting electrode (CNE1) can be connected to the drain region (DE1) of the silicon transistor (S-TFT) through a contact hole penetrating the first to fifth insulating layers (10, 20, 30, 40, 50).

[0108] The buffer layer (10br) and the first to fifth insulating layers (10, 20, 30, 40, 50) can define a stacked structure of insulating layers. In this embodiment, the stacked structure of insulating layers is described as a stacked structure of inorganic layers, but some of the insulating layers of the stacked structure may be organic layers.

[0109] In the stacked structure of the inorganic layers, an opening (BA-OP) corresponding to the boundary region (BA) described with reference to FIG. 4 is defined. Although not separately illustrated, the opening (BA-OP) may include a first opening region corresponding to the first region (BA1) and a second opening region corresponding to the second region (BA2).

[0110] The stacked structure of inorganic layers is divided into multiple islands corresponding to multiple pixels (PX1, PX2, PX3) shown in FIG. 4. This prevents the formation of cracks in the stacked structure of inorganic layers due to external impact. This is because the multiple island structures can disperse external impact.

[0111] A sixth insulating layer (60) may be disposed on the fifth insulating layer (50). The sixth insulating layer (60) fills the opening (BA-OP). The sixth insulating layer (60) can remove the step formed in the inorganic layers on the lower side and provide a flat upper surface.

[0112] A second connecting electrode (CNE2) may be disposed on the sixth insulating layer (60). The second connecting electrode (CNE2) may be connected to the first connecting electrode (CNE1) through a contact hole penetrating the sixth insulating layer (60). A first power line (PL1) is disposed on the sixth insulating layer (60) overlapping the opening (BA-OP).

[0113] The seventh insulating layer (70) is disposed on the sixth insulating layer (60) and can cover the second connecting electrode (CNE2). The third connecting electrode (CNE3) can be disposed on the seventh insulating layer (70). The third connecting electrode (CNE3) can be connected to the second connecting electrode (CNE2) through a contact hole penetrating the seventh insulating layer (70). A second power line (PL2) is disposed on the seventh insulating layer (70) overlapping the opening (BA-OP). The second power line (PL2) can be connected to the first power line (PL1) through a contact hole penetrating the seventh insulating layer (70). The eighth insulating layer (80) can be disposed on the seventh insulating layer (70).

[0114] In this embodiment, the sixth insulating layer (60), the seventh insulating layer (70), and the eighth insulating layer (80) may each be an organic layer. The sixth insulating layer (60) may be defined as the first organic layer, and the seventh insulating layer (70) and the eighth insulating layer (80) may be defined as the second organic layer and the third organic layer, respectively.

[0115] Each of the 6th insulating layer (60), the 7th insulating layer (70), and the 8th insulating layer (80) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0116] The second light-emitting element (LD2) may include a first electrode (AE2, or pixel electrode), a light-emitting layer (EL2), and a second electrode (CE, or common electrode). The second electrode of the first light-emitting element (LD1) and the third light-emitting element (LD3) described with reference to FIG. 4 may have an integral shape with the second electrode (CE) of the second light-emitting element (LD2). That is, the second electrode (CE) may be provided in common to the first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3).

[0117] The first electrode (AE2) may be disposed on the eighth insulating layer (80). The first electrode (AE2) may be a transparent electrode, a translucent electrode, or a reflective electrode. According to one embodiment of the present invention, the first electrode (AE2) may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO) or indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode (AE2) may include a stacked structure of ITO / Ag / ITO.

[0118] A pixel defining film (PDL) may be disposed on the eighth insulating layer (80). The pixel defining film (PDL) may have transparent properties or light-absorbing properties. For example, a light-absorbing pixel defining film (PDL) may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining film (PDL) may correspond to a light-blocking pattern having light-blocking properties.

[0119] The pixel defining layer (PDL) can cover a portion of the first electrode (AE2). For example, an opening (PDL-O2) that exposes a portion of the first electrode (AE2) can be defined in the pixel defining layer (PDL). The pixel defining layer (PDL) can increase the distance between the edge of the first electrode (AE2) and the second electrode (CE). Therefore, the pixel defining layer (PDL) can serve to prevent the occurrence of arcs, etc., at the edge of the first electrodes (AE2).

[0120] Although not shown, a hole control layer may be disposed between the first electrode (AE2) and the light-emitting layer (EL2). The hole control layer includes a hole transport layer and may further include a hole injection layer. An electronic control layer may be disposed between the light-emitting layers (EL2) and the second electrode (CE). The electronic control layer includes an electron transport layer and may further include an electron injection layer. The hole control layer and the electronic control layer may be formed in common on a plurality of pixels (PX1, PX2, PX3, see FIG. 4) using an open mask.

[0121] The encapsulation layer (140) may be disposed on the light-emitting element layer (130). The encapsulation layer (140) may include sequentially stacked inorganic layers (141), organic layers (142), and inorganic layers (143), but the layers constituting the encapsulation layer (140) are not limited thereto.

[0122] Inorganic layers (141, 143) can protect the light-emitting element layer (130) from moisture and oxygen, and organic layer (142) can protect the light-emitting element layer (130) from foreign substances such as dust particles. The inorganic layers (141, 143) may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. The organic layer (142) may include an acrylic-based organic layer, but is not limited thereto.

[0123] In FIG. 5b, a silicon transistor (S-TFT) and an oxide transistor (O-TFT) are shown that are distinct from the silicon transistor (S-TFT) and oxide transistor (O-TFT) shown in FIG. 5a of the second pixel circuit (PC2, see FIG. 4). Additionally, a first current scanline (SL1i) shown in FIG. 4 is shown. The first current scanline (SL1i) may include a first conductive pattern (SL-C1) placed on the fifth insulating layer (50) and overlapping the pixel area (PA), and a second conductive pattern (SL-C2) placed on the sixth insulating layer (60) and intersecting the boundary area (BA).

[0124] The second conductive pattern (SL-C2) is placed on a different layer from the second power line (PL2) so that no interference occurs with the second power line (PL2). In one embodiment of the present invention, the first conductive pattern (SL-C1) may be placed on the seventh insulating layer (70).

[0126] Referring to FIG. 6a, the conductive line (SL) may include a plurality of first lines (SL10) extended in a first direction (DR1) and a plurality of second lines (SL20) extended in a second direction (DR2). The first lines (SL10) and second lines (SL20) may correspond to the first power line (PL1) and second power line (PL2) shown in FIG. 4 to 5b, respectively, but are not limited thereto. The first line (SL10) overlaps the first region (BA1) shown in FIG. 4, and the second line (SL20) overlaps the second region (BA2) shown in FIG. 4. When either of the first line (SL10) and the second line (SL20) is placed on the same layer as any one of the first connecting electrode (CNE1) to the third connecting electrode (CNE3) shown in FIG. 5a, the other of the first line (SL10) and the second line (SL20) may be placed on the same layer as the other of the first connecting electrode (CNE1) to the third connecting electrode (CNE3) shown in FIG. 5a.

[0127] The first initialization voltage line (VL1) or the second initialization voltage line (VL2) can be implemented in the same form as the conduction line (SL) shown in FIG. 6a. The voltage line providing the low power supply voltage (ELVSS) to the light-emitting element (LD) shown in FIG. 3 can also be implemented in the same form as the conduction line (SL) shown in FIG. 6a.

[0128] As illustrated in FIG. 6b, the data line (DL) may include only the second line (SL20) component. The data line (DL) may be placed in each pixel column. The data line (DL) overlaps the second region (BA2) illustrated in FIG. 4.

[0130] FIGS. 7a and 7b are plan views illustrating conductive lines (SL-1, SL-2, SL-3) according to an embodiment of the present invention. Detailed descriptions of configurations identical to those described with reference to FIGS. 1 to 6b are omitted.

[0131] The display panel (100) may include two types of conductive lines (SL-1, SL-2) as shown in FIG. 7a, or three types of conductive lines (SL-1, SL-2, SL-3) as shown in FIG. 7b.

[0132] A first line (SL11) of a first type of conductive line (SL-1) may be placed in a part of the first area (BA1, see FIG. 4) of the entire display panel (100), and a first line (SL12) of a second type of conductive line (SL-2) may be placed in another part of the first area (BA1). A second line (SL21) of a first type of conductive line (SL-1) may be placed in a part of the second area (BA2, see FIG. 4) of the entire display panel (100), and a second line (SL22) of a second type of conductive line (SL-2) may be placed in another part of the second area (BA2).

[0133] When the first type of conductive line (SL-1) is any one of the power line receiving the high power supply voltage (ELVDD) or the low power supply voltage (ELVSS), the first initialization voltage line (VL1), and the second initialization voltage line (VL1), the second type of conductive line (SL-2) may be the other one.

[0134] In one embodiment of the present invention, the first line (SL11) of the first type of conductive line (SL-1) or the first line (SL12) of the second type of conductive line (SL-2) may include a first conductive pattern (SL-C1) and a second conductive pattern (SL-C2), such as the first current scan line (SL1i) shown in FIG. 5b.

[0135] As shown in FIG. 7b, if the first region (BA1, see FIG. 4) and the second region (BA2, see FIG. 4) are spatially divided, three types of conductive lines (SL-1, SL-2, SL-3) may be arranged so as not to interfere with each other.

[0137] FIG. 8 is an enlarged plan view of a display panel (100) according to one embodiment of the present invention.

[0138] Referring to FIG. 8, the conduction line (SL) may correspond to a bypass line and may constitute part of the data line. The bypass line (SL) may replace the signal line placed in the surrounding area (100-NA). Accordingly, the area of ​​the surrounding area (100-NA) may be reduced.

[0139] FIG. 8 illustrates two groups of data lines (DL1-1, DL1-2, DL2-1, DL2-2) connected to a data driving circuit (DDC, see FIG. 1). The first group of data lines (DL1-1, DL1-2) has a single shape, and the second group of data lines (DL2-1, DL2-2) includes a bypass line (SL) and may include a plurality of parts.

[0140] The bypass line (SL) may include a horizontal line (SL11, or the first line) extended in a first direction (DR1) and a first vertical line (SL21, or one second line) and a second vertical line (SL22, or another second line) extended in a second direction (DR2). The horizontal line (SL11) corresponds to the first power line (PL1) shown in FIG. 4 or the first line (SL10) of FIG. 6a, and the first vertical line (SL21) and the second vertical line (SL22) each correspond to the second power line (PL2) shown in FIG. 4 or the second line (SL20) of FIG. 6a. The horizontal line (SL11) may be placed on a different layer from the first and second vertical lines (SL21, SL22).

[0141] The bypass line (SL) can be connected to the third line (SL-NA) placed in the surrounding area (100-NA) and to the fourth line (SL-A) placed in the display area (100-A), respectively. The horizontal line (SL11) is connected to the first vertical line (SL21) and the second vertical line (SL22), respectively, through the first contact hole (CH1). The first vertical line (SL21) is connected to the third line (SL-NA) through the second contact hole (CH2). The second vertical line (SL22) is connected to the fourth line (SL-A) through the second contact hole (CH2).

[0142] The horizontal line (SL11), the first and second vertical lines (SL21, SL22), and the third and fourth lines (SL-NA, SL-A) may be placed on different layers. When any one of the horizontal line (SL11), the first and second vertical lines (SL21, SL22), and the third and fourth lines (SL-NA, SL-A) is placed on the same layer as the first connecting electrode (CNE1) shown in FIG. 5a, the other of the horizontal line (SL11), the first and second vertical lines (SL21, SL22), and the third and fourth lines (SL-NA, SL-A) may be placed on the same layer as the second connecting electrode (CNE2) shown in FIG. 5a. The remaining one of the horizontal line (SL11), the first and second vertical lines (SL21, SL22), and the third and fourth lines (SL-NA, SL-A) may be placed on the same layer as the third connecting electrode (CNE3).

[0144] FIGS. 9a and 9b are enlarged plan views of a display area (100-A) according to an embodiment of the present invention. Hereinafter, detailed descriptions of configurations identical to those described with reference to FIGS. 1 to 6b are omitted.

[0145] Each of the pixel regions (PA) may include a plurality of pixels (PX1, PX2, PX3). As illustrated in FIG. 9a, first and second color pixels (PX1, PX2) may be placed in one pixel region (PA), and second and third color pixels (PX2, PX3) may be placed in another pixel region (PA). As illustrated in FIG. 9b, one first color pixel (PX1), one third color pixel (PX3), and two second color pixels (PX2) may be placed in one pixel region (PA).

[0147] FIG. 10 is a cross-sectional view of a display panel (100) according to an embodiment of the present invention. Hereinafter, a detailed description of a configuration identical to the configuration described with reference to FIG. 5a and FIG. 5b is omitted.

[0148] A fourth insulating layer (40) may be placed on the third insulating layer (30). As shown in FIG. 5a, the fourth insulating layer (40) may overlap the gate (GT2) of the oxide transistor (O-TFT) and expose a non-overlapping region of the gate (GT2) of the oxide transistor (O-TFT). The source region (SE2) and drain region (DE2) of the oxide transistor (O-TFT) may be exposed from the insulating pattern of the fourth insulating layer (40).

[0150] FIGS. 11a and FIGS. 11b are cross-sectional views of a display panel (100) according to an embodiment of the present invention. Hereinafter, a detailed description of a configuration identical to the configuration described with reference to FIGS. 5a and FIGS. 5b is omitted.

[0151] As illustrated in FIGS. 11a and 11b, the display panel (100) may include an organic pattern (ORP) that fills an opening (BA-OP). The organic pattern (ORP) may have the same shape as the shape of the opening (BA-OP) on the plane. The organic pattern (ORP) may have a grid shape on the plane.

[0152] As illustrated in FIG. 11a, a sixth insulating layer (60) covering an organic pattern (ORP) is disposed on the fifth insulating layer (50). An opening (60-OP) exposing the organic pattern (ORP) is defined in the sixth insulating layer (60). The sixth insulating layer (60) may be an organic layer or an inorganic layer. If the sixth insulating layer (60) is an inorganic layer, the size of a contact hole disposed within a pixel area (PA), such as a contact hole disposed between the second connecting electrode (CNE2) and the first connecting electrode (CNE1), can be reduced.

[0153] A first power line (PL1) is disposed on the sixth insulating layer (60). The first power line (PL1) is disposed inside the opening (60-OP) of the sixth insulating layer (60) and can come into contact with the organic pattern (ORP). A second power line (PL2) can be connected to the first power line (PL1) through a contact hole penetrating the seventh insulating layer (70).

[0154] As illustrated in FIG. 11b, a sixth insulating layer (60) is disposed on the fifth insulating layer (50). The sixth insulating layer (60) may be an organic layer or an inorganic layer. An opening (BA-OP) may extend to the sixth insulating layer (60). A portion of the organic pattern (ORP) may be disposed on the upper surface of the sixth insulating layer (60).

[0155] A first power line (PL1) is disposed on an organic pattern (ORP), and the first power line (PL1) may be partially disposed on the upper surface of the sixth insulating layer (60). A second power line (PL2) may be connected to the first power line (PL1) through a contact hole penetrating the seventh insulating layer (70).

[0157] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0158] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0159] Base layer 110 Boundary area BA Pixel area PA Insulating layers 10br, 10-50 1st organic layer 60 Pixel circuit PC Light-emitting diode LD 1st Challenge Line PL, PL1 Area 1, Area 2 BA1, BA2 2nd organic layer 70 2nd Challenge Line PL2 Silicon transistor, oxide transistor S-TFT, O-TFT Data Driving Circuit (DDC) Line 1 and Line 2 of the 1st challenge line PL1, PL2 Challenge Pattern 1, Challenge Pattern 2 SL-C1, SL-C2 Buffer inorganic layer, 1st to 5th inorganic layers 10br, 10-50 Organic Pattern ORP

Claims

Claim 1 A display panel comprising: a base layer including a boundary region and a pixel region; a plurality of insulating layers disposed on the base layer, wherein an opening corresponding to the boundary region is defined; a first organic layer disposed on the plurality of insulating layers and filling the opening; a pixel circuit superimposed on the pixel region; a light-emitting element superimposed on the pixel region, electrically connected to the pixel circuit, and disposed on the first organic layer; and a first conductive line superimposed on the boundary region, extending in substantially the same direction as the boundary region, disposed between the first organic layer and the light-emitting element, and electrically connected to the pixel circuit, wherein, on a plane, the first conductive line is disposed inside the opening. Claim 2 In claim 1, the boundary area includes a first area extended in a first direction and a second area extended in a second direction intersecting the first direction, the opening includes a first opening area extended in the first direction and a second opening area extended from the first opening area in the second direction, and the first conductive line is a display panel extended in the first direction or in the second direction. Claim 3 In claim 2, the display panel further comprises a second organic layer disposed on the first organic layer and a second conductive line disposed on the second organic layer, wherein the first conductive line extends in the first direction and the second conductive line extends in the second direction. Claim 4 A display panel according to claim 2, further comprising a second organic layer disposed on the first organic layer and a second conductive line disposed on the second organic layer, wherein the first conductive line overlaps the first region and the first opening region, and the second conductive line overlaps the second region and the second opening region. Claim 5 In claim 4, the second conductive line is a display panel connected to the first conductive line through a contact hole penetrating the second organic layer. Claim 6 A display panel according to claim 2, further comprising a second organic layer disposed on the first organic layer and a second conductive line disposed on the second organic layer, wherein the first conductive line and the second conductive line overlap different regions of the first region or overlap different regions of the second region. Claim 7 In claim 6, the first conductive line and the second conductive line are a display panel that receives different signals or different voltages. Claim 8 In claim 1, the pixel circuit is a display panel comprising a silicon transistor or an oxide transistor. Claim 9 In claim 1, the first conductive line is a display panel that receives a data signal or power voltage. Claim 10 A display panel according to claim 1, further comprising a data driving circuit electrically connected to the first conductive line, wherein the boundary area comprises a first area extended in a first direction and a second area extended in a second direction intersecting the first direction, and the opening comprises a first opening area extended in the first direction and a second opening area extended from the first opening area in the second direction, and the first conductive line comprises a first line overlapping the first area and the first opening area and a second line overlapping the second area and the second opening area. Claim 11 A display panel according to claim 1, wherein the pixel area is provided in plurality, the boundary area surrounds each of the plurality of pixel areas on a plane, and one, two, or four light-emitting elements are disposed in each of the plurality of pixel areas. Claim 12 A display panel according to claim 1, further comprising a second conductive line, wherein the second conductive line comprises: a first conductive pattern disposed below the first organic layer and overlapping the pixel area; and a second conductive pattern that intersects the boundary area, is disposed on the first organic layer, and is connected to the first conductive pattern. Claim 13 In claim 1, the pixel circuit comprises a first transistor including a first gate and a silicon semiconductor pattern and a second transistor including a second gate and an oxide semiconductor pattern, and the plurality of insulating layers comprises: a buffer inorganic layer below the silicon semiconductor pattern; a first inorganic layer on the silicon semiconductor pattern; a second inorganic layer on the first inorganic layer and the first gate; a third inorganic layer between the second inorganic layer and the oxide semiconductor pattern; a fourth inorganic layer on the third inorganic layer and the oxide semiconductor pattern; and a fifth inorganic layer on the fourth inorganic layer and the second gate. Claim 14 In claim 13, the fourth inorganic layer overlaps the second gate and exposes a non-overlapping region of the oxide semiconductor pattern to the second gate, thereby forming a display panel. Claim 15 A display panel comprising: a base layer including a boundary region and a pixel region; a plurality of inorganic layers disposed on the base layer, wherein an opening corresponding to the boundary region is defined; an organic pattern filling the opening; a pixel circuit superimposed on the pixel region; a light-emitting element superimposed on the pixel region, electrically connected to the pixel circuit, and disposed on the plurality of inorganic layers; and a conductive line superimposed on the boundary region, extending in substantially the same direction as the boundary region, disposed between the organic pattern and the light-emitting element, and electrically connected to the pixel circuit, wherein, on a plane, the conductive line is disposed inside the opening. Claim 16 In claim 15, the display panel further comprises an insulating layer disposed on the plurality of inorganic layers and having a first opening defined therein that exposes the organic pattern, wherein the conductive line is disposed at least inside the first opening. Claim 17 In claim 15, a portion of the organic pattern is a display panel disposed on the uppermost inorganic layer among the plurality of inorganic layers. Claim 18 In claim 17, the conductive line is a display panel in contact with the upper surface of the organic pattern. Claim 19 In claim 15, the display panel further comprises an insulating layer disposed on the plurality of inorganic layers, wherein the conductive line comprises a first conductive line and a second conductive line intersecting each other, the insulating layer is disposed between the first conductive line and the second conductive line, the organic pattern comprises a first organic pattern extending in a first direction and superimposing the first conductive line, and a second organic pattern extending in a second direction intersecting the first direction and superimposing the second conductive line, and the first conductive line and the second conductive line are connected through a contact hole penetrating the insulating layer. Claim 20 A base layer comprising a first pixel area, a second pixel area, and a boundary area between the first pixel area and the second pixel area; a first stacked structure corresponding to the first pixel area; a second stacked structure corresponding to the second pixel area and spaced apart from the first stacked structure and the boundary area; an organic material filling at least the space between the first stacked structure and the second stacked structure and overlapping the boundary area; a transistor and a light-emitting element disposed in the first pixel area; and a conductive line disposed between the organic material and the light-emitting element, extending in substantially the same direction as the boundary area and electrically connected to the transistor or the light-emitting element, wherein each of the first stacked structure and the second stacked structure comprises a plurality of inorganic layers, and wherein, on a plane, the conductive line is disposed inside the space between the first stacked structure and the second stacked structure.

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