A current buffer circuit that converts a single signal to differential signal to minimize current mismatch

Abstract

The present invention provides a current buffer circuit comprising: an input terminal into which an input current is introduced; a first current mirror section having a first current mirror and generating a first mirror current corresponding to a first current which is at least a part of the input current; a second current mirror section having a second current mirror and generating a second mirror current corresponding to a second current which is another at least part of the input current; a third current mirror section having a third current mirror and generating a third mirror current corresponding to a third current which is part of the first mirror current; a first output terminal having a first output signal consisting of a fourth current which is the remainder of the input current and a third mirror current; and a second output terminal having a second output signal consisting of a fifth current which is the remainder of the first mirror current and a second mirror current, and a differential signal of the first output signal.

Description

Technology Field

[0001] The present invention relates to a current buffer circuit that converts a single signal into a differential signal so as to minimize current mismatch. Background Technology

[0002] Optical sensors are devices that measure light intensity or wavelength and convert it into electrical signals, and they are utilized in various industrial fields. These sensors detect light using optoelectronic elements such as photodiodes and convert the resulting minute current into voltage. At this stage, the current generated by the optoelectronic elements is very minute, and a current buffer capable of processing such minute currents is required for high-sensitivity measurements.

[0003] The current buffer serves to transmit the current generated by the optical sensor to other circuits, such as the TIA (Transimpedance Amplifier). Therefore, the current buffer must be implemented to minimize signal distortion or loss during the current transmission process.

[0004] To this end, current buffers process the current generated by the sensor in the form of a differential signal. Here, a differential signal consists of two opposing signals, which is advantageous for suppressing noise caused by common mode voltage and improving the signal-to-noise ratio (SNR). Therefore, differential signals are effective in increasing the accuracy of transmitted signals and minimizing the impact of external noise or various interferences. Accordingly, there is a need for a method to convert the minute currents generated by optical sensors into differential signals. The problem to be solved

[0005] The present invention relates to a current buffer circuit that converts a single signal into a differential signal to minimize current mismatch, which can minimize the mismatch of a differential signal caused by a current error that may occur depending on the process of a transistor used in a current mirror. means of solving the problem

[0006] To solve the problem described above, a current buffer circuit according to the present invention may include: an input terminal into which an input current is introduced; a first current mirror section provided with a first current mirror, wherein a first mirror current corresponding to a first current which is at least a part of the input current is generated; a second current mirror section provided with a second current mirror, wherein a second mirror current corresponding to a second current which is another at least part of the input current is generated; a third current mirror section provided with a third current mirror, wherein a third mirror current corresponding to a third current which is part of the first mirror current is generated; a first output terminal in which a first output signal consisting of a fourth current which is the remainder of the input current and the third mirror current is output; and a second output terminal in which a second output signal consisting of a fifth current which is the remainder of the first mirror current and the second mirror current is output, wherein the second output signal is a differential signal of the first output signal. Effects of the invention

[0007] According to various embodiments of the present invention, a current buffer circuit that converts a single signal into a differential signal to minimize current mismatch can minimize the mismatch of the differential signal caused by current errors that may occur depending on the process of the transistor used in the current mirror by generating a differential signal corresponding to the input signal using multiple designed current mirrors. Brief explanation of the drawing

[0008] Figure 1 illustrates one embodiment of a current buffer circuit. Figure 2 illustrates one embodiment of a bias circuit. FIG. 3 illustrates an example of a common mode feedback circuit. Figure 4 illustrates an example of a common mode voltage. FIG. 5 illustrates a current buffer circuit according to the present invention. FIG. 6 illustrates an embodiment in which the input current is branched from the input terminal. FIG. 7 illustrates one embodiment of a first current mirror. FIG. 8 illustrates an embodiment in which the first mirror current is branched. FIG. 9 illustrates one embodiment of a second current mirror. FIG. 10 illustrates one embodiment of a third current mirror. FIG. 11 illustrates an embodiment in which an output signal is output at the output terminal. Specific details for implementing the invention

[0009] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components are assigned the same reference number regardless of the drawing symbols, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" used for components in the following description are assigned or used interchangeably solely for the ease of drafting the specification and do not have distinct meanings or roles in themselves. Furthermore, in describing the embodiments disclosed in this specification, if it is determined that a detailed description of related prior art could obscure the essence of the embodiments disclosed in this specification, such detailed description will be omitted. Additionally, the attached drawings are intended only to facilitate understanding of the embodiments disclosed in this specification; the technical concept disclosed in this specification is not limited by the attached drawings, and it should be understood that they include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the present invention.

[0010] Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0011] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0012] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0013] In this application, terms such as “comprising” or “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0014] FIG. 1 illustrates an embodiment of a current buffer circuit. FIG. 2 illustrates an embodiment of a bias circuit. FIG. 3 illustrates an embodiment of a common mode feedback circuit. FIG. 4 illustrates an embodiment of a common mode voltage. FIG. 5 illustrates a current buffer circuit according to the present invention. FIG. 6 illustrates an embodiment in which an input current is branched from an input terminal. FIG. 7 illustrates an embodiment of a first current mirror. FIG. 8 illustrates an embodiment in which the first mirror current is branched. FIG. 9 illustrates an embodiment of a second current mirror. FIG. 10 illustrates an embodiment of a third current mirror. FIG. 11 illustrates an embodiment in which an output signal is output from an output terminal.

[0015] Referring to FIG. 1, the current buffer circuit (20) may be configured to generate a differential signal corresponding to the input current when the current generated from a predetermined sensor (10) is input as the input current. Through this, the differential signal generated by the current buffer circuit (20) can be utilized in a TIA (30) (Transimpedance Amplifier), etc., and may be implemented to be used for various purposes depending on the embodiment.

[0016] Here, a predetermined sensor (10) may be implemented to generate a variable current according to an external input, such as an optical sensor. Accordingly, the current generated by the predetermined sensor (10) can be input to a current buffer circuit (20) as an input current.

[0017] Additionally, the differential signal may refer to two output signals in which the input current generated from a predetermined sensor (10) is differentiated by the current buffer circuit (20). That is, the differential signal may include a first output signal and a second output signal output from the current buffer circuit (20).

[0018] At this time, the first output signal and the second output signal may be currents with the same magnitude and opposite phase.

[0019] Meanwhile, the current buffer circuit (20) is provided with multiple current mirrors composed of multiple transistors, and can be implemented to generate a first output signal and a second output signal, respectively, based on the current generated by the multiple current mirrors along with the input current.

[0020] Here, the transistor may include a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and depending on the embodiment, it may be replaced with other transistors such as a BJT. Accordingly, this specification is written based on embodiments using a MOSFET as the transistor to facilitate understanding of the invention, but the invention is not limited thereto and may be understood to include other transistors that can replace the MOSFET depending on the embodiment.

[0021] Meanwhile, a signal based on at least one of a predetermined bias voltage, operating voltage, and adjustment voltage can be input to the gate of each of the plurality of transistors provided in the current buffer circuit (20).

[0022] Here, the operating voltage may be a fixed DC voltage that is predetermined, and may be set to a voltage value sufficiently large to allow multiple transistors used in the current buffer circuit to operate. Additionally, the bias voltage may be a voltage appearing at a specific point in a bias circuit implemented based on the operating voltage, and the adjustment voltage may be a voltage appearing at a specific point in a common mode feedback circuit implemented based on the common mode voltage appearing from the differential signal.

[0023] At this time, referring to FIG. 2, the bias circuit (40) can be implemented to generate a bias voltage (BIAS) corresponding to the operating voltage (VDD) by using an N-channel transistor-based current mirror (43) configured to mirror a predetermined reference current (41) based on the operating voltage (VDD), and a P-channel transistor-based current mirror (45) configured to mirror the mirror current generated through the N-channel transistor-based current mirror (43).

[0024] Additionally, referring to FIG. 3, the common mode feedback circuit (50) can be implemented such that an adjustment voltage (CMFB2) is formed in response to a common mode voltage (CMFB1) appearing from the output terminal of the current buffer circuit (20), based on an operating voltage (VDD) and a predetermined reference voltage (VCM).

[0025] To this end, the common mode feedback circuit (50) may be composed of an N-channel transistor-based current mirror (51) having a voltage (VNBIAS_CMFB) appearing at a specific point of the bias circuit as a gate input, and a P-channel transistor-based current mirror (53) having an operating voltage (VDD) connected to each source, and an adjustment voltage (CMFB2) may be generated according to N-channel transistors (55, 56) respectively provided between the N-channel transistor-based current mirror (51) and the P-channel transistor-based current mirror (53).

[0026] At this time, the common mode feedback circuit (50) can be implemented such that a predetermined reference voltage (VCM) and a common mode voltage (CMFB1) are applied to the gates of N-channel transistors (55, 56) respectively provided between the two current mirrors (51, 53), and the drain voltage of the transistor (55) to which the common mode voltage (CMFB1) is input can be set as the adjustment voltage (CMFB2).

[0027] In this regard, referring to FIG. 4, the common mode voltage (CMFB1) can represent the magnitude of a voltage common to the first output terminal (61) where a first output signal is output and the second output terminal (62) where a second output signal is output in the current buffer circuit (20). To this end, the current buffer circuit (20) is provided with two resistors (R2) having the same magnitude between the first output terminal (61) and the second output terminal (63), and the common mode voltage (CMFB1) can appear at the point where the two resistors (R2) meet.

[0028] Meanwhile, referring to FIG. 5, the current buffer circuit (20) may include an input terminal (70), a first current mirror section (81), a second current mirror section (83), a third current mirror section (85), and output terminals (61, 63). Based on the configuration of the current buffer circuit (20), the configuration and operation of the current buffer circuit (20) will be described in more detail below.

[0029] Referring to FIG. 6, the current buffer circuit (20) according to the present invention includes an input terminal (70) into which an input current (Iin) is introduced, and a first transistor (M1), a second transistor (M2), and a third transistor (M3) can be connected to the input terminal (70) at a single contact. Specifically, the input terminal (70) can be connected to the drain of the first transistor (M1), the source of the second transistor (M2), and the third transistor (M3), respectively, at a single contact.

[0030] Accordingly, the input current (Iin) can be branched to the first transistor (M1), the second transistor (M2), and the third transistor (M3), respectively. At this time, the current branched from the input current (Iin) to the first transistor (M1) may be the first current (I1), the current branched from the input current (Iin) to the second transistor (M2) may be the second current (I2), and the current branched from the input current (Iin) to the third transistor (M3) may be the fourth current (I4).

[0031] Here, the first transistor (M1), the second transistor (M2), and the third transistor (M3) can each be provided as N-channel transistors, and the same bias voltage (BIAS) can be input to the respective gates of the second transistor (M2) and the third transistor (M3) by means of a pre-provided bias circuit. Additionally, the drain and gate of the first transistor (M1) can be short-circuited so that the voltage at the input terminal (70) can be input to the gate.

[0032] Additionally, the current buffer circuit (20) may have the seventh transistor (M7), which will be described later, connected to the second transistor (M2), and the eleventh transistor (M11), which will be described later, connected to the third transistor (M3). Accordingly, the current buffer circuit (20) may have the same magnitude for the second current (I2) branched to the second transistor (M2) and the fourth current (I4) branched to the third transistor (M3). Additionally, the current buffer circuit (20) may have the magnitude of the first current (I1) branched to the first transistor (M1) appear as twice the magnitude of the second current (I1) and the fourth current (I4), respectively. That is, if the first current (I1) is 2i, the second current (I2) and the fourth current (I4) may each be i.

[0033] Furthermore, referring to FIG. 7, the current buffer circuit (20) may include a first current mirror and a first current mirror section (81) in which a first mirror current (IM1) corresponding to a first current (I1) which is at least a part of the input current (Iin) is generated.

[0034] Here, the first current mirror section (81) may include a first transistor (M1) and a fourth transistor (M4) formed by the first transistor (M1) and the current mirror. Accordingly, the first current mirror may refer to a current mirror formed by the first transistor (M1) and the fourth transistor (M4), and the first current mirror section (81) may generate a first mirror current (IM1) by mirroring the first current (I1) introduced into the drain of the first transistor (M1) to the drain of the fourth transistor (M1).

[0035] That is, the first current (I1) and the first mirror current (IM1) may be currents of the same magnitude, and according to the embodiment, the first mirror current (IM1) may include a mirror current mirrored based on the first current (I1) and a current error generated by the process of the first transistor (M1) and the fourth transistor (M4).

[0036] For example, when an input current (Iin) corresponding to 4i is introduced into the first current mirror section (81) through the input terminal (70), 2i can be branched into the first current (I1), and a first mirror current (IM1) corresponding to 2i can be generated by the first current mirror.

[0037] At this time, the first current mirror section (81) may have a current error in the first mirror current (IM1) due to the process of the first transistor (M1) and the fourth transistor (M4), and in this case, the current error included in the first mirror current (IM1) may be 2e. That is, the magnitude of the first mirror current (IM1) may be the sum of 2i and 2e.

[0038] Meanwhile, the first transistor (M1) and the fourth transistor (M4) may be provided as N-channel transistors, and the source of the fourth transistor (M4) may be short-circuited with the source of the first transistor (M1), and the gate of the fourth transistor (M4) may be short-circuited with the gate of the first transistor (M1). At this time, the gate of the first transistor (M1) may be short-circuited with the drain of the first transistor (M1). Accordingly, the voltage at the input terminal (70) is input to the gate of the fourth transistor (M4), and a first mirror current (IM1) may be generated according to the first current (I1) of the first transistor (M1). Here, the source of the fourth transistor (M4) and the source of the first transistor (M1) may be grounded.

[0039] In this regard, referring to FIG. 8, the fourth transistor (M4) can be connected to the fifth transistor (M5) and the sixth transistor (M6), and accordingly, the first current mirror section (81) can branch the first mirror current (IM1) from the fourth transistor (M4) to the fifth transistor (M5) and the sixth transistor (M6), respectively. At this time, the current branched from the first mirror current (IM1) to the fifth transistor (M5) may be the third current (I3), and the current branched from the first mirror current (IM1) to the sixth transistor (M6) may be the fifth current (I5).

[0040] Additionally, the current buffer circuit (20) may have the 10th transistor (M10), which will be described later, connected to the 5th transistor (M5), and the 8th transistor (M8), which will be described later, connected to the 6th transistor (M6). Accordingly, the current buffer circuit (20) may have the same magnitude for the 3rd current (I3) branched to the 5th transistor (M5) and the 5th current (I5) branched to the 6th transistor (M6). That is, when the 1st mirror current (IM1) is 2i, the 3rd current (I3) and the 5th current (I5) may each be i.

[0041] Meanwhile, the fifth transistor (M5) and the sixth transistor (M6) may each be equipped as N-channel transistors, and the drain of the fourth transistor (M4) and the source of the fifth transistor (M5) and the sixth transistor (M6) may be connected at a single contact.

[0042] Additionally, the same bias voltage (BIAS) can be input to the respective gates of the fifth transistor (M5) and the sixth transistor (M6) by means of a pre-equipped bias circuit. At this time, the voltage input to the gates of the fifth transistor (M5) and the sixth transistor (M6) may be the same as the voltage input to the gates of the second transistor (M2) and the third transistor (M3). That is, the bias circuit can be implemented to be connected to the gates of the second transistor (M2), the third transistor (M3), the fifth transistor (M5), and the sixth transistor (M6), respectively, so as to apply the same bias voltage to the gates of the second transistor (M2), the third transistor (M3), the fifth transistor (M5), and the sixth transistor (M6).

[0043] Furthermore, referring to FIG. 9, the current buffer circuit (20) may include a second current mirror and a second current mirror section (83) in which a second mirror current (IM2) corresponding to a second current (I2) which is at least another part of the input current (Iin) is generated.

[0044] Here, the second current mirror section (83) may include a seventh transistor (M7) and an eighth transistor (M8) formed by the seventh transistor (M7) and a current mirror. Accordingly, the second current mirror may refer to a current mirror formed by the seventh transistor (M7) and the eighth transistor (M8), and the second current mirror section (83) may generate a second mirror current (IM2) by mirroring the second current (I2), which is introduced into the drain of the seventh transistor (M7) through the drain of the second transistor (M2), to the drain of the eighth transistor (M8).

[0045] That is, the second current (I2) and the second mirror current (IM2) may be currents of the same magnitude, and according to the embodiment, the second mirror current (IM2) may include a mirror current mirrored based on the second current (I2) and a current error generated by the process of the seventh transistor (M7) and the eighth transistor (M8).

[0046] For example, when an input current (Iin) corresponding to 4i is applied to the second current mirror section (83) through the input terminal (70), a second current (I2) corresponding to i can be branched to the second transistor (M2), the second current (I2) is fed into the seventh transistor (M7), and a second mirror current (IM2) corresponding to i can be generated by the second current mirror.

[0047] At this time, the second current mirror section (83) may have a current error in the second mirror current (IM2) due to the process of the seventh transistor (M7) and the eighth transistor (M8), and in such a case, the current error included in the second mirror current (IM2) may be e. That is, the magnitude of the second mirror current (IM2) may be expressed as the sum of i and e.

[0048] Meanwhile, each of the seventh transistor (M7) and the eighth transistor (M8) may be provided as a P-channel transistor, the drain of the seventh transistor (M7) is connected to the drain of the second transistor (M2), an inverter element is connected to the gate of the seventh transistor (M7), and the drain of the seventh transistor (M7) and the drain of the second transistor (M2) may be connected to the other side of the inverter element.

[0049] Additionally, the source of the seventh transistor (M7) may be short-circuited with the source of the eighth transistor (M8), wherein a predetermined operating voltage (VDD) may be applied to the source of the seventh transistor (M7) and the source of the eighth transistor (M8).

[0050] Additionally, the drain of the eighth transistor (M8) may be connected to the drain of the sixth transistor (M6), and the gate of the eighth transistor (M8) may be connected to an inverter element, and the drain of the seventh transistor (M7) and the drain of the second transistor (M2) may be connected to the other side of the inverter element. Additionally, a pre-prepared resistor element is connected to the other side of the inverter element connected to the gate of the eighth transistor (M8), and the other side of the resistor element may be connected to the drain of the eighth transistor (M8) and the drain of the sixth transistor (M6) at a single contact.

[0051] Meanwhile, the second current mirror section (83) may include a ninth transistor (M9) so that the magnitude of the voltage applied to the gates of the seventh transistor (M7) and the eighth transistor (M8) is adjusted based on a common mode feedback circuit.

[0052] To this end, the ninth transistor (M9) may be provided as a P-channel transistor, and the source of the ninth transistor (M9) may be short-circuited with the source of the seventh transistor (M7) and the eighth transistor (M8), respectively; that is, a predetermined operating voltage (VDD) may be applied to the source of the ninth transistor (M9). Additionally, the drain of the ninth transistor (M9) may be connected to the other side of an inverter element connected to the gate of the seventh transistor (M7) and the eighth transistor (M8), respectively. Furthermore, the gate of the ninth transistor (M9) may be connected to an inverter element, and the output terminal of a common mode feedback circuit may be connected to the other side of the inverter element. Accordingly, an inverted adjustment voltage (CMFB2) output from the common mode feedback circuit may be applied to the gate of the ninth transistor.

[0053] Furthermore, referring to FIG. 10, the current buffer circuit (20) may include a third current mirror and a third current mirror section (85) in which a third mirror current (IM3) corresponding to a third current (I3) which is part of the first mirror current (IM1) is generated.

[0054] Here, the third current mirror section (85) may include a tenth transistor (M10) and an eleventh transistor (M11) formed by the tenth transistor (M10) and the current mirror. Accordingly, the third current mirror may refer to a current mirror formed by the tenth transistor (M10) and the eleventh transistor (M11), and the third current mirror section (85) may generate a third mirror current (IM3) by mirroring the third current (I3), which is introduced into the drain of the tenth transistor (M10) through the drain of the fifth transistor (M5), to the drain of the eleventh transistor (M11).

[0055] That is, the third current (I3) and the third mirror current (IM3) may be currents of the same magnitude, and according to the embodiment, the third mirror current (IM3) may include a mirror current mirrored based on the third current (I3) and a current error generated by the process of the tenth transistor (M10) and the eleventh transistor (M11). In this case, if the first mirror current (IM1) contains a current error due to the process of the first transistor (M1) and the fourth transistor (M4), the current error regarding the current error remaining in the third current (I3) branched from the first mirror current (IM1) may be superimposed on the third mirror current (IM3).

[0056] For example, when an input current (Iin) corresponding to 4i is applied to the first current mirror section (81) through the input terminal (70), 2i can be branched into the first current (I1), and a first mirror current (IM1) corresponding to 2i can be generated by the first current mirror.

[0057] At this time, the first current mirror section (81) may have a current error in the first mirror current (IM1) due to the process of the first transistor (M1) and the fourth transistor (M4), and in this case, the current error included in the first mirror current (IM1) may be 2e. That is, the magnitude of the first mirror current (IM1) may be the sum of 2i and 2e.

[0058] Accordingly, the first mirror current (IM1) can be uniformly branched into the fifth transistor (M5) and the sixth transistor (M6), and the magnitudes of the third current (I3) and the fifth current (I5) supplied to the fifth transistor (M5) and the sixth transistor (M6), respectively, can be represented as the sum of i and e.

[0059] Accordingly, the third current mirror section (85) can generate a third mirror current (IM3) corresponding to the sum of i and e by the third current mirror, and at this time, the third current mirror section (85) may have a current error in the third mirror current (IM3) due to the process of the 10th transistor (M10) and the 11th transistor (M11), and in this case, the current error newly included in the third mirror current (IM3) may be e. That is, the magnitude of the third mirror current (IM3) is a magnitude in which e is added to the sum of i and e, and can be represented as the sum of i and 2e.

[0060] Meanwhile, each of the 10th transistor (M10) and the 11th transistor (M11) may be provided as a P-channel transistor, the drain of the 10th transistor (M10) is connected to the drain of the 5th transistor (M5), an inverter element is connected to the gate of the 10th transistor (M10), and the drain of the 10th transistor (M10) and the drain of the 5th transistor (M5) may be connected to the other side of the inverter element.

[0061] Additionally, the source of the 10th transistor (M10) may be short-circuited with the source of the 11th transistor (M11), wherein a predetermined operating voltage (VDD) may be applied to the source of the 10th transistor (M10) and the source of the 11th transistor (M11). At this time, the operating voltage (VDD) may be the same as the operating voltage (VDD) applied to the source of the 7th transistor (M7) and the source of the 8th transistor (M8), that is, the source of the 7th transistor (M7), the source of the 8th transistor (M8), the source of the 10th transistor (M10), and the source of the 11th transistor (M11) may be short-circuited with each other.

[0062] Additionally, the drain of the eleventh transistor (M11) may be connected to the drain of the third transistor (M3), and the gate of the eleventh transistor (M11) may be connected to an inverter element, and the drain of the tenth transistor (M10) and the drain of the fifth transistor (M5) may be connected to the other side of the inverter element. Additionally, a pre-prepared resistor element is connected to the other side of the inverter element connected to the gate of the eleventh transistor (M11), and the other side of the resistor element may be connected to the drain of the eleventh transistor (M11) and the drain of the third transistor (M3) at a single contact.

[0063] Meanwhile, the third current mirror section (85) may include a 12th transistor (M12) so that the magnitude of the voltage applied to the gates of the 10th transistor (M10) and the 11th transistor (M11) is adjusted based on a common mode feedback circuit.

[0064] To this end, the 12th transistor (M12) may be provided as a P-channel transistor, and the source of the 12th transistor (M12) may be short-circuited with the source of the 10th transistor (M10) and the 11th transistor (M11), respectively; that is, a predetermined operating voltage (VDD) may be applied to the source of the 12th transistor (M12). Additionally, the drain of the 12th transistor (M12) may be connected to the other side of an inverter element connected to the gate of the 10th transistor (M10) and the 11th transistor (M11), respectively. Furthermore, the gate of the 12th transistor (M12) is connected to an inverter element, and the output terminal of a common mode feedback circuit may be connected to the other side of the inverter element. Accordingly, an inverted adjustment voltage (CMFB2) output from the common mode feedback circuit may be applied to the gate of the 12th transistor (M12). At this time, the adjustment voltage (CMFB2) input to the gate of the 12th transistor (M12) may be the same as the adjustment voltage (CMFB2) input to the gate of the 9th transistor (M9).

[0065] Furthermore, referring to FIG. 11, the current buffer circuit (20) may include a first output terminal (61) (Ioutn) where a first output signal (91) consisting of a fourth current (I4) which is the remainder of the input current (Iin) and a third mirror current (IM3) is output, and a second output terminal (63) (Ioutp) where a second output signal (92) consisting of a fifth current (I5) which is the remainder of the first mirror current (IM1) and a second mirror current (IM2) which is the differential signal of the first output signal (91) is output.

[0066] Here, for this purpose, the first output terminal (61) can be connected to the contact between the drain of the fourth transistor (M4) and the drain of the eleventh transistor (M11), and the second output terminal (63) can be connected to the contact between the drain of the sixth transistor (M6) and the drain of the eighth transistor (M8).

[0067] Accordingly, the first output terminal (61) can output a first output signal (91) in which the fifth current (I5) branched from the first mirror current (IM1) and the second mirror current (IM2) are combined, and the second output terminal (63) can output a second output signal (92) in which the fourth current (I4) branched from the input current (Iin) and the third mirror current (IM3) are combined.

[0068] At this time, the first output signal (91) and the second output signal (92) may be currents with the same magnitude and opposite phases, that is, the first output signal (91) and the second output signal (92) may be differential signals. Here, the first output signal (91) and the second output signal (92) may each include a current error due to the process of the transistors provided in the current buffer circuit (20), and at this time, the current error included in the first output signal (91) and the current error included in the second output signal (92) may also be generated as differential signals with the same magnitude and opposite phases.

[0069] For example, when an input current (Iin) corresponding to 4i is introduced through the input terminal of the current buffer circuit (20), a first current (I1) corresponding to 2i is branched to the first transistor (M1), a second current (I2) corresponding to i is branched to the second transistor (M2), and a fourth current (I4) corresponding to i is branched to the third transistor (M3).

[0070] Accordingly, the second current mirror section (83) receives a second current (I2) having a magnitude of i into the seventh transistor (M7), and the second mirror current (IM2) having a magnitude equal to the sum of the current i and the current error e can be generated by the second current mirror.

[0071] Additionally, the first current mirror section (81) can generate a first mirror current (IM1) having a magnitude equal to the sum of 2i and 2e from a first current (I1) having a magnitude equal to 2i by the first current mirror. At this time, the first mirror current (IM1) is uniformly branched into the fifth transistor (M5) and the sixth transistor (M6) so that a third current (I3) and a fifth current (I5) having a magnitude equal to the sum of i and e may appear.

[0072] Additionally, the third mirror current section (85) receives a third current (I3) having a magnitude equal to the sum of i and e through the 10th transistor (M10), and a third mirror current (IM3) having a magnitude equal to the sum of i and 2e can be generated by the third current mirror.

[0073] Accordingly, the first output terminal (61) can output a first output signal (91) having a size equal to the sum of 2i and 2e by combining a fifth current (I5) having a size equal to the sum of i and e and a second mirror current (IM2) having a size equal to the sum of i and e, and the second output terminal (63) can output a second output signal (92) having a size equal to the sum of 2i and 2e by combining a fourth current (I4) having a size equal to i and a third mirror current (IM3) having a size equal to the sum of i and 2e.

[0074] Through the above configurations, the current buffer circuit (20) according to the present invention generates a differential signal corresponding to an input signal using multiple designed current mirrors, thereby minimizing the discrepancy of the differential signal caused by current errors that may occur depending on the process of the transistor used in the current mirror.

[0075] Furthermore, the present invention described above can be implemented as a program that is executed by one or more processes in an electronic device and stored on a computer-readable recording medium.

[0076] Accordingly, the present invention can be implemented as computer-readable code or instructions on a medium on which a program is recorded. That is, various control methods according to the present invention can be provided in the form of integrated or individual programs.

[0077] Meanwhile, computer-readable media include all types of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable media include HDD (Hard Disk Drive), SSD (Solid State Disk), SSD (Silicon Disk Drive), ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

[0078] Furthermore, the computer-readable medium may be a server or cloud storage that includes a storage and is accessible to an electronic device via communication. In this case, the computer may download the program according to the present invention from the server or cloud storage via wired or wireless communication.

[0079] Furthermore, in the present invention, the computer described above is an electronic device equipped with a processor, namely a CPU (Central Processing Unit), and no special limitations are placed on its type.

[0080] Meanwhile, the above detailed description should not be interpreted restrictively in all respects but should be considered exemplary. The scope of the invention shall be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the invention are included within the scope of the invention.

Claims

Claim 1 A current buffer circuit comprising: an input terminal into which an input current is introduced; a first current mirror section provided with a first current mirror, wherein a first mirror current corresponding to a first current which is at least a part of the input current is generated; a second current mirror section provided with a second current mirror, wherein a second mirror current corresponding to a second current which is another at least part of the input current is generated; a third current mirror section provided with a third current mirror, wherein a third mirror current corresponding to a third current which is a part of the first mirror current is generated; a first output terminal in which a first output signal is output, consisting of a fourth current which is the remainder of the input current and the third mirror current; and a second output terminal in which a second output signal is output, consisting of a fifth current which is the remainder of the first mirror current and the second mirror current, wherein the second output signal is a differential signal of the first output signal. Claim 2 In claim 1, the input terminal is a current buffer circuit connected to a first transistor, a second transistor, and a third transistor at a single contact. Claim 3 In claim 2, the first current mirror section comprises the first transistor and a fourth transistor formed of the first transistor and a current mirror, and the first current introduced into the drain of the first transistor is mirrored to the drain of the fourth transistor to generate the first mirror current, a current buffer circuit. Claim 4 In claim 3, the fourth transistor is connected to the fifth transistor and the sixth transistor, and the first mirror current is branched from the fourth transistor to the fifth transistor and the sixth transistor, respectively, in a current buffer circuit. Claim 5 In claim 4, the second current mirror section comprises a seventh transistor and an eighth transistor formed by the seventh transistor and a current mirror, and the second current introduced to the drain of the seventh transistor through the drain of the second transistor is mirrored to the drain of the eighth transistor to generate the second mirror current, a current buffer circuit. Claim 6 In claim 5, the third current mirror section comprises a tenth transistor and a eleventh transistor formed by the tenth transistor and a current mirror, and the third current introduced to the drain of the tenth transistor through the drain of the fifth transistor is mirrored to the drain of the eleventh transistor to generate the third mirror current, in a current buffer circuit. Claim 7 delete Claim 8 In claim 2, the input terminal is a current buffer circuit connected at a single junction to the drain of the first transistor, the source of the second transistor, and the source of the third transistor. Claim 9 A current buffer circuit according to claim 2, wherein the first current is a current branched from the input current to the first transistor, the second current is a current branched from the input current to the second transistor, and the fourth current is a current branched from the input current to the third transistor, wherein the magnitude of the first current is twice the magnitude of each of the second current and the fourth current. Claim 10 In claim 3, the first transistor and the fourth transistor are provided as N-channel transistors, the source of the fourth transistor is short-circuited to the source of the first transistor and grounded, and the gate of the fourth transistor is short-circuited to the gate of the first transistor and the drain of the first transistor, forming a current buffer circuit. Claim 11 A current buffer circuit according to claim 4, wherein the third current is a current branched to the fifth transistor, the fifth current is a current branched to the sixth transistor, and the magnitudes of the third current and the fifth current are the same. Claim 12 In claim 4, the fifth transistor and the sixth transistor are each equipped as N-channel transistors, and the drain of the fourth transistor is connected to the source of the fifth transistor and the source of the sixth transistor at a single contact, forming a current buffer circuit. Claim 13 In claim 5, each of the seventh transistor and the eighth transistor is provided as a P-channel transistor, the drain of the seventh transistor is connected to the drain of the second transistor, the gate of the seventh transistor is connected to one side of an inverter element to which the drain of the seventh transistor and the drain of the second transistor are connected to the other side, the source of the seventh transistor is short-circuited with the source of the eighth transistor and a predetermined operating voltage is applied, the drain of the eighth transistor is connected to the drain of the sixth transistor, the gate of the eighth transistor is connected to one side of an inverter element to which the drain of the seventh transistor and the drain of the second transistor are connected to the other side, a pre-arranged resistor element is connected to the other side of the inverter element connected to the gate of the eighth transistor, and the other side of the resistor element is connected to the drain of the eighth transistor and the drain of the sixth transistor at a single contact, a current buffer circuit. Claim 14 In claim 5, the second current mirror section further includes a ninth transistor to adjust the magnitude of the voltage applied to the gates of the seventh transistor and the eighth transistor, respectively, based on a common mode feedback circuit, wherein the drain of the ninth transistor is connected to the other side of an inverter element connected to the gates of the seventh transistor and the eighth transistor, and the gate of the ninth transistor is connected to an inverter element to which the output terminal of the common mode feedback circuit is connected to the other side, so that the adjustment voltage output from the common mode feedback circuit is inverted and applied, thereby adjusting the magnitude of the voltage applied to the gates of the seventh transistor and the eighth transistor, respectively, in a current buffer circuit. Claim 15 In claim 14, the ninth transistor is provided as a P-channel transistor, the source of the ninth transistor is short-circuited with the source of each of the seventh transistor and the eighth transistor, the drain of the ninth transistor is connected to the other side of an inverter element connected to the gate of each of the seventh transistor and the eighth transistor, and the gate of the ninth transistor is connected to an inverter element to which the output terminal of a common mode feedback circuit is connected to the other side, so that the adjustment voltage output from the common mode feedback circuit is inverted and applied, a current buffer circuit. Claim 16 In claim 6, each of the 10th transistor and the 11th transistor is provided as a P-channel transistor, the drain of the 10th transistor is connected to the drain of the 5th transistor, the gate of the 10th transistor is connected to one side of an inverter element to which the drain of the 10th transistor and the drain of the 5th transistor are connected to the other side, the source of the 10th transistor is short-circuited to the source of the 11th transistor and a predetermined operating voltage is applied, the drain of the 11th transistor is connected to the drain of the 3rd transistor, the gate of the 11th transistor is connected to one side of an inverter element to which the drain of the 10th transistor and the drain of the 5th transistor are connected to the other side, a pre-arranged resistor element is connected to the other side of the inverter element connected to the gate of the 11th transistor, and the other side of the resistor element is connected to the drain of the 11th transistor and the drain of the 3rd transistor at a single contact, a current buffer circuit. Claim 17 In claim 6, the third current mirror section further includes a 12th transistor to adjust the magnitude of the voltage applied to the gates of the 10th transistor and the 11th transistor, respectively, based on a common mode feedback circuit, wherein the drain of the 12th transistor is connected to the other side of an inverter element connected to the gates of the 10th transistor and the 11th transistor, and the gate of the 12th transistor is connected to an inverter element to which the output terminal of the common mode feedback circuit is connected to the other side, so that the adjustment voltage output from the common mode feedback circuit is inverted and applied, thereby adjusting the magnitude of the voltage applied to the gates of the 10th transistor and the 11th transistor, respectively. Claim 18 In claim 17, the 12th transistor is provided as a P-channel transistor, the source of the 12th transistor is short-circuited with the source of each of the 10th transistor and the 11th transistor, the drain of the 12th transistor is connected to the other side of an inverter element connected to the gate of each of the 10th transistor and the 11th transistor, and the gate of the 12th transistor is connected to an inverter element to which the output terminal of a common mode feedback circuit is connected to the other side, so that the adjustment voltage output from the common mode feedback circuit is inverted and applied, a current buffer circuit. Claim 19 In claim 17, the common mode feedback circuit is a current buffer circuit implemented such that an adjustment voltage is formed in response to the common mode voltage appearing from the first output terminal and the second output terminal, based on a predetermined operating voltage and a predetermined reference voltage. Claim 20 In claim 19, the common mode voltage is a current buffer circuit in which two resistors having the same size are provided between the first output terminal and the second output terminal, and the voltage at the point where the two resistors meet.

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