Display apparatus

Abstract

The display device may include a first active pattern disposed on a substrate, a second active pattern comprising a material different from the first active pattern, a voltage line disposed below the second active pattern, a horizontal transmission line disposed above the second active pattern and extending in a first direction, and a connection pattern spaced apart from the horizontal transmission line, disposed on the same layer as the horizontal transmission line, and electrically contacting the second active pattern and the voltage line. The horizontal transmission wiring and the voltage wiring may be separated, and the second active pattern and the voltage wiring may come into contact through a connection pattern. Accordingly, the contact resistance value may be reduced, and the dispersion of the contact resistance values ​​may be reduced.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] A display device may include a display panel and a panel driver (e.g., a data driver, a gate driver, etc.). A plurality of conductive patterns are sequentially formed on the display panel, and the conductive patterns may come into contact through contacts. The panel driver may provide signals and / or voltage to the conductive patterns of the display panel. The conductive patterns are patterned to have repetitive unit structures when viewed in a planar view, and the conductive patterns having one of the unit structures may be defined as pixel structures. Meanwhile, contact resistance may occur between the conductive patterns that come into contact through the contacts. As the dispersion of the contact resistance values ​​increases, the dispersion of the electrical characteristics of the pixel structures may increase. This causes a degradation in the display quality of the display device. The problem to be solved

[0003] One objective of the present invention is to provide a display device with improved display quality by reducing the dispersion of contact resistance values.

[0004] However, the objectives of the present invention are not limited to the objectives described above and may be expanded in various ways without departing from the spirit and scope of the present invention. means of solving the problem

[0005] To achieve one objective of the present invention, a display device according to embodiments may include a first active pattern disposed on a substrate, a second active pattern comprising a material different from that of the first active pattern, a voltage line disposed below the second active pattern, a horizontal transmission line disposed above the second active pattern and extending in a first direction, and a connection pattern spaced apart from the horizontal transmission line, disposed on the same layer as the horizontal transmission line, and electrically contacting the second active pattern and the voltage line.

[0006] In one embodiment, the connection pattern contacts the second active pattern through each of the first contact and the second contact and contacts the voltage wiring through the third contact, and the third contact may be positioned between the first contact and the second contact.

[0007] In one embodiment, the voltage wiring can provide an initialization voltage to the second active pattern through the connection pattern.

[0008] In one embodiment, the display device may further include gate wiring that transmits a gate signal.

[0009] In one embodiment, the connection pattern may be spaced apart from the horizontal transmission wiring and the gate wiring when viewed in a plane, and may be positioned between the horizontal transmission wiring and the gate wiring.

[0010] In one embodiment, the display device may further include a first conductive pattern disposed below the second active pattern, a second conductive pattern disposed below the second active pattern and disposed above the first conductive pattern, and a third conductive pattern disposed above the second active pattern.

[0011] In one embodiment, the third conductive pattern includes a gate electrode that overlaps with the second active pattern, and the second conductive pattern includes a gate wiring, the gate wiring being electrically connected to the gate electrode and may extend in the first direction.

[0012] In one embodiment, the second conductive pattern includes a gate electrode that overlaps with the second active pattern, and the third conductive pattern includes the gate wiring, the gate wiring being electrically connected to the gate electrode and extending in the first direction.

[0013] In one embodiment, the first active pattern may include a silicon semiconductor, and the second active pattern may include an oxide semiconductor.

[0014] In one embodiment, the apparatus may further include a data line disposed on the horizontal transmission line and extending in the second direction to provide a data voltage to the first active pattern, and a vertical transmission line disposed on the same layer as the data line and extending in the second direction to provide a data voltage to the horizontal transmission line.

[0015] In one embodiment, the second active pattern further includes a first extension and a second extension extending in the first direction, and the first extension and the second extension overlap with the voltage wiring and the horizontal transmission wiring, and the display device may further include a first conductive pattern disposed below the second active pattern, a second conductive pattern disposed below the second active pattern and disposed above the first conductive pattern, and a third conductive pattern disposed above the second active pattern.

[0016] In one embodiment, the third conductive pattern includes a gate electrode that overlaps with the second active pattern, and the second conductive pattern includes a gate wiring that transmits a gate signal, the gate wiring being electrically connected to the gate electrode and may extend in the first direction.

[0017] In one embodiment, the second conductive pattern includes a gate electrode that overlaps with the second active pattern, and the third conductive pattern includes a gate wiring that transmits a gate signal, wherein the gate wiring is electrically connected to the gate electrode and can extend in the first direction.

[0018] In one embodiment, the first conductive pattern includes a gate electrode that overlaps with the second active pattern, and the third conductive pattern includes a gate wiring that transmits a gate signal, wherein the gate wiring is electrically connected to the gate electrode and can extend in the first direction.

[0019] A display device according to one embodiment may include a first active pattern disposed on a substrate, a second active pattern comprising a material different from the first active pattern, a voltage line disposed below the second active pattern, a connection pattern disposed above the second active pattern and electrically contacting the second active pattern and the voltage line, and a horizontal transmission line extending in a first direction, disposed on the same layer as the connection pattern, and overlapping with the second active pattern to transmit a data signal.

[0020] In one embodiment, the connection pattern contacts the second active pattern through each of the first contact and the second contact and contacts the voltage wiring through the third contact, and the third contact may be positioned between the first contact and the second contact.

[0021] In one embodiment, the voltage wiring can provide an initialization voltage to the second active pattern through the connection pattern.

[0022] In one embodiment, the display device may further include gate wiring that transmits a gate signal.

[0023] In one embodiment, the connection pattern is spaced apart from the horizontal transfer wiring and the gate wiring when viewed in a planar view, and the horizontal transfer wiring may be positioned between the connection pattern and the gate wiring.

[0024] In one embodiment, the first active pattern may include a silicon semiconductor, and the second active pattern may include an oxide semiconductor. Effects of the invention

[0025] A display device according to embodiments of the present invention may include a plurality of pixel structures, and each of the pixel structures may include a first active pattern, a second active pattern, a voltage line, a horizontal transmission line, and a connection pattern. The horizontal transmission line and the voltage line may be spaced apart. An initialization voltage may be transmitted through the voltage line, the connection pattern, and the second active pattern. The second active pattern and the voltage line may come into contact through the connection pattern. Accordingly, the contact resistance value may be reduced, and the dispersion of the contact resistance values ​​may be reduced.

[0026] The connection pattern may be located between the horizontal transmission wiring and the gate wiring that transmits the gate signal. Accordingly, the connection pattern can prevent coupling phenomena that may occur between the horizontal transmission wiring and the third gate wiring.

[0027] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0028] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Figure 2 is a plan view showing the display device of Figure 1. FIG. 3 is an enlarged view illustrating data transmission wiring included in the display device of FIG. 2. Figure 4 is a circuit diagram showing an example of a pixel circuit and an organic light-emitting diode included in the display device of Figure 1. FIGS. 5 to 15 are layout drawings for explaining pixel structures included in a display device according to one embodiment. Figure 16 is an enlarged view of area A of Figure 13. Figure 17 is a cross-sectional view taken along line II' of Figure 13. FIG. 18 is a cross-sectional view taken along the line II-II' of FIG. 13. FIGS. 19 to 23 are layout drawings for explaining pixel structures included in a display device according to one embodiment. FIG. 23 is a cross-sectional view taken along the line II-II' of FIG. 21. FIG. 24 is a cross-sectional view taken along the line III-III' of FIG. 22. FIG. 25 is a cross-sectional view taken along the line IV-IV' of FIG. 22. FIG. 26 is a cross-sectional view taken along the VV' line of FIG. 22. FIGS. 27 to 34 are layout drawings for explaining pixel structures included in a display device according to one embodiment. FIG. 35 is a cross-sectional view taken along the line VI-VI' of FIG. 33. FIGS. 36 to 41 are layout drawings for explaining pixel structures included in a display device according to one embodiment. FIG. 42 is a cross-sectional view taken along the line VII-VII' of FIG. 40. FIGS. 43 to 51 are layout drawings for explaining pixel structures included in a display device according to one embodiment. FIG. 52 is a cross-sectional view taken along the line VIII-VIII' of FIG. 50. Specific details for implementing the invention

[0029] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0030] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 2 is a plan view showing the display device of FIG. 1. FIG. 3 is an enlarged view for explaining data transmission wiring included in the display device of FIG. 2. FIG. 4 is a circuit diagram showing an example of a pixel circuit and an organic light-emitting diode included in the display device of FIG. 1.

[0031] Referring to FIG. 1, a display device (10) according to one embodiment of the present invention may include a display panel (PNL), a data driving unit (DDV), a gate driving unit (GDV), and a control unit (CON).

[0032] The above display panel (PNL) may include a plurality of pixel structures (e.g., pixel structures (PX) of FIG. 2). For example, the above display panel (PNL) may include a first pixel structure (PX1), a second pixel structure (PX2), a third pixel structure (PX3), and a fourth pixel structure (PX4). Each of the first to fourth pixel structures (PX1, PX2, PX3, PX4) may be provided with a data voltage (DATA), a gate signal (GS), a high power supply voltage (ELVDD), a low power supply voltage (ELVSS), an initialization voltage (VINT), and an anode initialization voltage (AINT).

[0033] The data driver (DDV) can generate the data voltage (DATA) based on output image data (ODAT) and a data control signal (DCTRL). For example, the data driver (DDV) can generate the data voltage (DATA) corresponding to the output image data (ODAT) and output the data voltage (DATA) in response to the data control signal (DCTRL). The data control signal (DCTRL) may include an output data enable signal, a horizontal start signal, and a load signal. In one embodiment, the data driver (DDV) may be electrically connected to the display panel (PNL) by one or more integrated circuits (ICs). In another embodiment, the data driver (DDV) may be mounted on the display panel (PNL) or integrated into the periphery of the display panel (PNL).

[0034] The gate driver (GDV) can generate the gate signal (GS) based on the gate control signal (GCTRL). For example, the gate signal (GS) may include a gate-on voltage that turns on the transistor and a gate-off voltage that turns off the transistor. The gate control signal (GCTRL) may include a vertical start signal, a clock signal, etc. In one embodiment, the gate driver (GDV) may be mounted on the display panel (PNL). In another embodiment, the gate driver (GDV) may be electrically connected to the display panel (PNL) in the form of the COF.

[0035] The above control unit (CON) (e.g., timing controller (T-CON)) may receive input image data (IDAT) and control signals (CTRL) from an external host processor (e.g., GPU). For example, the input image data (IDAT) may be RGB data including red image data, green image data, and blue image data. The control signals (CTRL) may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Based on the input image data (IDAT) and the control signals (CTRL), the control unit (CON) may generate the gate control signal (GCTRL), the data control signal (DCTRL), and the output image data (ODAT).

[0036] Referring to FIGS. 2 and 3, the display device (10) may include a display area (DA), a non-display area (NDA) surrounding the display area (DA), a bendable bending area (BA), a peripheral area (SA) and a pad area (PA) between the display area (DA) and the bending area (BA).

[0037] For example, the pixel structure (PX) may be disposed in the display area (DA), and a driving unit for driving the pixel structure (PX) may be disposed in the non-display area (NDA). For example, a pad unit (PD) and a data driving unit (DDV) may be disposed in the pad area (PA), and the bending area (BA) may be bent based on a virtual bending axis.

[0038] In the above display area (DA), the pixel structure (PX) and data wiring (DL), gate wiring (GL), high power voltage wiring (PL), and data transmission wiring (FL1, FL2) connected to the pixel structure (PX) may be arranged.

[0039] The data wiring (DL) is electrically connected to the data driver (DDV) and can be extended along the second direction (D2). The gate wiring (GL) is connected to the gate driver (GDV) and can be extended along the first direction (D1) that intersects the second direction (D2). The high power voltage wiring (PL) is connected to the pad (PD) and can be extended along the second direction (D2).

[0040] The data transmission wires (FL1, FL2) can be electrically connected to the data driver (DDV) and the data wire (DL). The data transmission wires (FL1, FL2) can connect the data driver (DDV) and the data wire (DL).

[0041] In one embodiment, as illustrated in FIG. 3, the display device (10) may have first to fourth data lines (DL1, DL2, DL3, DL4), a first data transmission line (FL1), and a second data transmission line (FL2). For example, the first and second data transmission lines (FL1, FL2) may be fan-out lines that electrically connect the data driver (DDV) and the data line (DL).

[0042] In one embodiment, the first data transmission line (FL1) may include a first vertical transmission line (VFL1) and a first data transmission horizontal line (HFL1), and the second data transmission line (FL2) may include a second vertical transmission line (VFL2) and a second data transmission horizontal line (HFL2). For example, the first and second vertical transmission lines (VFL1, VFL2) may extend in the second direction (D2), and the first and second data transmission horizontal lines (HFL1, HFL2) may extend in the first direction (D1).

[0043] The first data transmission line (FL1) can electrically connect the data driving unit (DDV) and the first data line (DL1). For example, the first data voltage can be provided to the first pixel structure (PX1) through the first data transmission line (FL1) and the first data line (DL1).

[0044] Specifically, the first vertical transmission line (VFL1) is connected to the first connection line (SCL1), the first connection line (SCL1) is connected to the first bending connection line (BCL1), and the first bending connection line (BCL1) can be connected to the first data connection line (DCL1).

[0045] For example, the first vertical transmission line (VFL1) extends from the surrounding area (SA) to the display area (DA) and may be formed in a first layer (e.g., the layer where the vertical transmission line (SD2b) of FIG. 14 is formed). The first connection line (SCL1) is placed in the surrounding area (SA) and may be formed in a second layer placed below the first layer. The first bending connection line (BCL1) is placed in the bending area (BA) and may be formed in the first layer. The first data connection line (DCL1) is placed in the pad area (PA) and may receive the first data voltage from the data driver (DDV).

[0046] The second data transmission line (FL2) can electrically connect the data driving unit (DDV) and the second data line (DL2). For example, the second data voltage can be provided to the second pixel structure (PX2) through the second data transmission line (FL2) and the second data line (DL2).

[0047] Specifically, the second vertical transmission wire (VFL2) is connected to the second connection wire (SCL2), the second connection wire (SCL2) is connected to the second bending connection wire (BCL2), and the second bending connection wire (BCL2) can be connected to the second data connection wire (DCL2). However, since the structure of the second vertical transmission wire (VFL2), the second connection wire (SCL2), the second bending connection wire (BCL2), and the second data connection wire (DCL2) is substantially the same as the structure of the first vertical transmission wire (VFL1), the first connection wire (SCL1), the first bending connection wire (BCL1), and the first data connection wire (DCL1), a detailed description is omitted.

[0048] The third data wiring (DL3) can be connected to the data driving unit (DDV). For example, the third data voltage can be provided to the third pixel structure (PX3) through the third data wiring (DL3).

[0049] Specifically, the third data wiring (DL3) is connected to the third connection wiring (SCL3), the third connection wiring (SCL3) is connected to the third bending connection wiring (BCL3), and the third bending connection wiring (BCL3) can be connected to the third data connection wiring (DCL3).

[0050] For example, the third data wiring (DL3) may extend from the peripheral area (SA) to the display area (DA) and may be formed on the first layer. The third connection wiring (SCL3) may be placed in the peripheral area (SA) and may be formed on a third layer located below the first layer. The third bending connection wiring (BCL3) may be placed in the bending area (BA) and may be formed on the first layer. The third data connection wiring (DCL3) may be placed in the pad area (PA) and may receive the third data voltage from the data driver (DDV).

[0051] The fourth data wiring (DL4) can be connected to the data driving unit (DDV). For example, the fourth data voltage can be provided to the fourth pixel structure (PX4) through the fourth data wiring (DL4).

[0052] Specifically, the fourth data wire (DL4) is connected to the fourth connection wire (SCL4), the fourth connection wire (SCL4) is connected to the fourth bending connection wire (BCL4), and the fourth bending connection wire (BCL4) can be connected to the fourth data connection wire (DCL4). However, since the structure of the fourth data wire (DL4), the fourth connection wire (SCL4), the fourth bending connection wire (BCL4), and the fourth data connection wire (DCL4) is substantially the same as the structure of the third data wire (DL3), the third connection wire (SCL3), the third bending connection wire (BCL3), and the third data connection wire (DCL3), a detailed description is omitted.

[0053] Figure 4 is a circuit diagram showing an example of a pixel circuit and an organic light-emitting diode included in the display device of Figure 1.

[0054] Referring to FIGS. 1 and 4, the first pixel structure (PX1) can emit light through a pixel circuit (PC) and an organic light-emitting diode (OLED). Additionally, the second pixel structure (PX2) can emit light through a pixel circuit having a circuit structure substantially identical to that of the pixel circuit (PC) and an organic light-emitting diode having a structure substantially identical to that of the organic light-emitting diode (OLED). Hereinafter, the connection structure of the pixel circuit (PC) and the organic light-emitting diode (OLED) of the first pixel structure (PX1) will be described.

[0055] The pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), a storage capacitor (CST), and a boosting capacitor (CBS). The pixel circuit (PC) may be electrically connected to the organic light-emitting diode (OLED) to provide a driving current to the organic light-emitting diode (OLED).

[0056] The above organic light-emitting diode (OLED) may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal), wherein the first terminal of the organic light-emitting diode (OLED) is connected to the first transistor (T1) via the sixth transistor (T6) to receive the driving current, and the second terminal may receive the low power supply voltage (ELVSS). The organic light-emitting diode (OLED) may generate light of brightness corresponding to the driving current.

[0057] The storage capacitor (CST) may include a first terminal and a second terminal. The first terminal of the storage capacitor (CST) is connected to the first transistor (T1), and the second terminal of the storage capacitor (CST) may receive the high power supply voltage (ELVDD).

[0058] The boosting capacitor (CBS) may include a first terminal and a second terminal. The first terminal of the boosting capacitor (CBS) is connected to the first terminal of the storage capacitor (CST), and the second terminal of the boosting capacitor (CBS) may receive the first gate signal (GW). The boosting capacitor (CBS) can compensate for a voltage drop at the gate terminal by increasing the voltage at the gate terminal of the first transistor (T1) at the point when the supply of the first gate signal (GW) is discontinued.

[0059] The first transistor (T1) may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the first transistor (T1) may be connected to the first terminal of the storage capacitor (CST). The first terminal of the first transistor (T1) may be connected to the second transistor (T2) to receive the data voltage (DATA). The second terminal of the first transistor (T1) may provide the driving current to the organic light-emitting diode (OLED). The first transistor (T1) may generate the driving current based on the voltage difference between the gate terminal and the first terminal. For example, the first transistor (T1) may be referred to as a driving transistor. In one embodiment, the first transistor (T1) may further include a back-gate terminal. For example, the back-gate terminal may be sinking with or electrically floating with the gate terminal or the first terminal of the first transistor (T1). The back-gate terminal may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, a doped silicon semiconductor, etc. The back-gate terminal may overlap with the gate terminal and be implemented below the gate terminal.

[0060] The second transistor (T2) may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the second transistor (T2) may receive the first gate signal (GW). The first terminal of the second transistor (T2) may receive the data voltage (DATA). The second terminal of the second transistor (T2) may provide the data voltage (DATA) to the first terminal of the first transistor (T1) during the period when the second transistor (T2) is turned on.

[0061] The second transistor (T2) may be turned on or turned off in response to the first gate signal (GW). For example, if the second transistor (T2) is a PMOS transistor, the second transistor (T2) may be turned off when the first gate signal (GW) has a positive voltage level and turned on when the first gate signal (GW) has a negative voltage level. For example, the second transistor (T2) may be referred to as a switching transistor.

[0062] The third transistor (T3) may include a gate terminal, a back-gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal and the back-gate terminal of the third transistor (T3) may receive a second gate signal (GC). As the third transistor (T3) has a dual-gate structure, the reliability of the third transistor (T3) may be improved. The first terminal of the third transistor (T3) may be connected to the second terminal of the first transistor (T1). The second terminal of the third transistor (T3) may be connected to the gate terminal of the first transistor (T1).

[0063] The third transistor (T3) may be turned on or turned off in response to the second gate signal (GC). For example, if the third transistor (T3) is an NMOS transistor, the third transistor (T3) may be turned on when the second gate signal (GC) has a positive voltage level and turned off when the second gate signal (GC) has a negative voltage level.

[0064] During the period in which the third transistor (T3) is turned on in response to the second gate signal (GC), the third transistor (T3) can diode-connect the first transistor (T1). Since the first transistor (T1) is diode-connected, a voltage difference equal to the threshold voltage of the first transistor (T1) can occur between the gate terminal of the first transistor (T1) and the first terminal of the first transistor (T1). Accordingly, the data voltage (DATA) compensated by the voltage difference can be provided to the gate terminal of the first transistor (T1). Thus, the third transistor (T3) can compensate the threshold voltage of the first transistor (T1). For example, the third transistor (T3) may be referred to as a compensation transistor.

[0065] The fourth transistor (T4) may include a gate terminal, a back-gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal and the back-gate terminal of the fourth transistor (T4) may receive a third gate signal (GI). As the fourth transistor (T4) has a dual-gate structure, the reliability of the fourth transistor (T4) may be improved. The first terminal of the fourth transistor (T4) may receive the initialization voltage (VINT). The second terminal of the fourth transistor (T4) may be connected to the gate terminal of the first transistor (T1).

[0066] The fourth transistor (T4) may be turned on or turned off in response to the third gate signal (GI). For example, if the fourth transistor (T4) is an NMOS transistor, the fourth transistor (T4) may be turned on when the third gate signal (GI) has a positive voltage level and turned off when the third gate signal (GI) has a negative voltage level.

[0067] During the period in which the fourth transistor (T4) is turned on by the third gate signal (GI), the initialization voltage (VINT) may be provided to the gate terminal of the first transistor (T1). Accordingly, the fourth transistor (T4) may initialize the gate terminal of the first transistor (T1) with the initialization voltage (VINT). For example, the fourth transistor (T4) may be referred to as an initialization transistor.

[0068] The fifth transistor (T5) may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fifth transistor (T5) may receive a light emission control signal (EM). The first terminal of the fifth transistor (T5) may receive the high power supply voltage (ELVDD). The second terminal of the fifth transistor (T5) may be connected to the first terminal of the first transistor (T1). When the fifth transistor (T5) is turned on in response to the light emission control signal (EM), the fifth transistor (T5) may provide the high power supply voltage (ELVDD) to the first transistor (T1).

[0069] The sixth transistor (T6) may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the sixth transistor (T6) may receive the light emission control signal (EM). The first terminal of the sixth transistor (T6) may be connected to the second terminal of the first transistor (T1). The second terminal of the sixth transistor (T6) may be connected to the first terminal of the organic light-emitting diode (OLED). When the sixth transistor (T6) is turned on in response to the light emission control signal (EM), the sixth transistor (T6) may provide the driving current generated by the first transistor (T1) to the organic light-emitting diode (OLED).

[0070] The seventh transistor (T7) may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the seventh transistor (T7) may receive a fourth gate signal (GB). The first terminal of the seventh transistor (T7) may receive an anode initialization voltage (AINT). The second terminal of the seventh transistor (T7) may be connected to a first terminal of the organic light-emitting diode (OLED). When the seventh transistor (T7) is turned on in response to the fourth gate signal (GB), the seventh transistor (T7) may provide the anode initialization voltage (AINT) to the organic light-emitting diode (OLED). Accordingly, the seventh transistor (T7) may initialize the first terminal of the organic light-emitting diode (OLED) with the anode initialization voltage (AINT). For example, the seventh transistor (T7) may be referred to as an anode initialization transistor.

[0071] Meanwhile, the connection structure of the pixel circuit (PC) and the organic light-emitting diode (OLED) shown in FIG. 4 is exemplary and can be changed in various ways.

[0072] FIGS. 5 to 15 are layout drawings for explaining pixel structures included in a display device according to one embodiment.

[0073] Referring to FIGS. 1, 4, and 5, the display device (10) may include the first pixel structure (PX1) and the second pixel structure (PX2) adjacent to each other. For example, the second pixel structure (PX2) may have a structure that is symmetrical to the structure of the first pixel structure (PX1) with respect to a virtual symmetry line.

[0074] The substrate (SUB) may include glass, quartz, plastic, etc. In one embodiment, the substrate (SUB) may include plastic, and accordingly, the display device (10) may have flexible characteristics. In this case, the substrate (SUB) may have a structure in which at least one organic film layer and at least one barrier layer are alternately laminated. For example, the organic film layer may be formed using an organic material such as polyimide, and the barrier layer may be formed using an inorganic material.

[0075] A barrier layer (e.g., the barrier layer (BRR) of FIG. 17) may be disposed on the substrate (SUB). The barrier layer may prevent metal atoms or impurities from diffusing from the substrate (SUB) into the first active pattern (AP1). The barrier layer may include silicon oxide, silicon nitride, or silicon oxynitride and may have a single layer or a multilayer structure.

[0076] A buffer layer (e.g., the buffer layer (BFR) of FIG. 17) may be disposed on the substrate (SUB). The buffer layer can prevent metal atoms or impurities from the substrate (SUB) from diffusing into the first active pattern (AP1). Additionally, the buffer layer can control the rate of heat supply during the crystallization process for forming the first active pattern (AP1), and the first active pattern (AP1) can be formed uniformly. The buffer layer may include silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer or multi-layer structure.

[0077] The first active pattern (AP1) may be disposed on the buffer layer. In one embodiment, the first active pattern (AP1) may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first active pattern (AP1) may include polycrystalline silicon formed by crystallizing the amorphous silicon.

[0078] In one embodiment, ions may be implanted into the first active pattern (AP1). For example, if the first, second, fifth, sixth, and seventh transistors (T1, T2, T5, T6, T7) are the PMOS transistors, ions such as boron may be implanted into the first active pattern (AP1).

[0079] The first gate insulating layer covers the first active pattern (AP1) and can be disposed on the substrate (SUB). The first gate insulating layer may include an insulating material. For example, the first gate insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

[0080] Referring to FIGS. 1, 4 and 6, a first conductive pattern may be disposed on the first gate insulating layer. The first conductive pattern may include a first gate wiring (GT1a), a first gate electrode (GT1b), and a second gate wiring (GT1c).

[0081] The first gate wiring (GT1a) may be extended in a first direction (D1). The first gate wiring (GT1a) may form the second transistor (T2) together with the first active pattern (AP1). For example, the first gate signal (GW) may be provided to the first gate wiring (GT1a). Additionally, the first gate wiring (GT1a) may form the seventh transistor (T7) together with the first active pattern (AP1). For example, the fourth gate signal (GB) may be provided to the first gate wiring (GT1a). The first gate signal (GW) and the fourth gate signal (GB) may have substantially the same waveform with a time difference.

[0082] The first gate electrode (GT1b) can be arranged in an island shape. The first gate electrode (GT1b) can form the first transistor (T1) together with the first active pattern (AP1).

[0083] The second gate wiring (GT1c) may extend in the first direction (D1). The second gate wiring (GT1c) may form the fifth and sixth transistors (T5, T6) together with the first active pattern (AP1). For example, the light emission control signal (EM) may be provided to the second gate wiring (GT1c). The second gate wiring (GT1c) may be referred to as the light emission control wiring.

[0084] For example, the first conductive pattern may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. For example, the first conductive pattern may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti). A second gate insulating layer covers the first conductive pattern and may be disposed on the first gate insulating layer. The second gate insulating layer may include an insulating material. Specifically, the second gate insulating layer may include silicon oxide, silicon nitride, or silicon oxynitride, and may have a single layer or a multilayer structure.

[0085] Referring to FIGS. 1, 4 and 7, a second conductive pattern may be disposed on the second gate insulating layer. The second conductive pattern may include a third gate wiring (GT2a), a fourth gate wiring (GT2b), a storage capacitor electrode (GT2c), and a voltage wiring (GT2d).

[0086] The third gate wiring (GT2a) may be extended in the first direction (D1). For example, the third gate wiring (GT2a) may be spaced apart from the first gate wiring (GT1a) when viewed in a plane. The third gate signal (GI) may be provided to the third gate wiring (GT2a).

[0087] The fourth gate wiring (GT2b) may be extended in the first direction (D1). For example, the fourth gate wiring (GT2b) may be spaced apart from the first gate wiring (GT1a) and the third gate wiring (GT2a) when viewed in a plane. The second gate signal (GC) may be provided to the fourth gate wiring (GT2b).

[0088] The storage capacitor electrode (GT2c) overlaps with the first gate electrode (GT1b) and may extend in the first direction (D1). For example, the storage capacitor electrode (GT2c) may form the storage capacitor (CST) together with the first gate electrode (GT1b). The high power supply voltage (ELVDD) may be supplied to the storage capacitor electrode (GT2c). Additionally, a hole penetrating the storage capacitor electrode (GT2c) may be formed in the storage capacitor electrode (GT2c), and the first gate electrode (GT1b) may be exposed through the hole.

[0089] The voltage wiring (GT2d) may be extended in the first direction (D1). In one embodiment, the initial voltage (VINT) may be provided through the voltage wiring (GT2d). The voltage wiring (GT2d) may provide the initial voltage (VINT) to the connection pattern (SD1h) described below.

[0090] For example, the second conductive pattern may include metals, alloys, conductive metal oxides, transparent conductive materials, etc. Specifically, the second conductive pattern may include metals such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti).

[0091] The first interlayer insulating layer covers the second conductive pattern and may be disposed on the second gate insulating layer. The first interlayer insulating layer may include an insulating material. For example, the first interlayer insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

[0092] Referring to FIGS. 1, 4, 8, and 9, a second active pattern (AP2) may be disposed on the first interlayer insulating layer. The second active pattern (AP2) may include an oxide semiconductor. The first active pattern (AP1) and the second active pattern (AP2) may include different materials.

[0093] For example, the second active pattern (AP2) may include a binary compound (ABx), a ternary compound (ABxCy), a quaternary compound (ABxCyDz), etc. containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc.

[0094] In one embodiment, the second active pattern (AP2) may include indium-gallium-zinc oxide.

[0095] In one embodiment, the second active pattern (AP2) may be spaced apart from the first active pattern (AP1) in a plan view so as not to overlap with the first active pattern (AP1).

[0096] In one embodiment, the second active pattern (AP2) may be placed on a different layer from the first active pattern (AP1) and may not overlap with the first active pattern (AP1). In other words, the second active pattern (AP2) may be formed separately from the first active pattern (AP1).

[0097] In one embodiment, the second active pattern (AP2) may have a symmetrical shape with respect to a virtual line extending along a second direction (D2) perpendicular to the first direction (D1). The second active pattern (AP2) may include a portion placed in the first pixel area (PX1) and a portion placed in the second pixel area (PX2).

[0098] In one embodiment, the second active pattern (AP2) may overlap with the first gate wiring (GT1a), the third gate wiring (GT2a), the fourth gate wiring (GT2b), and the voltage wiring (GT2d).

[0099] The third gate insulating layer covers the second active pattern (AP2) and may be disposed on the first interlayer insulating layer. The third gate insulating layer may include an insulating material. The third gate insulating layer may include silicon oxide, silicon nitride, or silicon oxynitride and may be formed as a single layer or a multilayer structure.

[0100] Referring to FIGS. 1, FIGS. 4, FIGS. 10 and FIGS. 11, a third conductive pattern may be disposed on the third gate insulating layer. The third conductive pattern may include a second gate electrode (GT3a), a fifth gate wiring (GT3b), and a first transfer pattern (GT3c).

[0101] The second gate electrode (GT3a) may overlap with the third gate wiring (GT2a) and the second active pattern (AP2). The second gate electrode (GT3a) may be electrically connected to the third gate wiring (GT2a). For example, the second gate electrode (GT3a) may be in contact with the third gate wiring (GT2a) through a contact. The third gate signal (GI) may be provided to the second gate electrode (GT3a). The third gate wiring (GT2a), the second active pattern (AP2), and the second gate electrode (GT3a) may constitute the fourth transistor (T4). For example, the third gate wiring (GT2a) corresponds to the back-gate terminal of the fourth transistor (T4) described with reference to FIG. 4, and the second gate electrode (GT3a) corresponds to the gate terminal of the fourth transistor described with reference to FIG. 4.

[0102] The length of the second gate electrode (GT3a) in the first direction (D1) may be smaller than the length of the third gate wiring (GT2a) in the first direction (D1).

[0103] The fifth gate wiring (GT3b) may extend in the first direction (D1). The fifth gate wiring (GT3b) may overlap with the fourth gate wiring (GT2b) and the second active pattern (AP2). The fifth gate wiring (GT3b) may be electrically connected to the fourth gate wiring (GT2b). For example, the fifth gate wiring (GT3b) may be in contact with the fourth gate wiring (GT2b) through a contact. The second gate signal (GC) may be provided to the fifth gate wiring (GT3b). The fourth gate wiring (GT2b), the second active pattern (AP2), and the fifth gate wiring (GT3b) may constitute the third transistor (T3). For example, the fourth gate wiring (GT2b) corresponds to the back-gate terminal of the third transistor (T3) described with reference to FIG. 4, and the fifth gate wiring (GT3b) corresponds to the gate terminal of the third transistor (T3) described with reference to FIG. 4.

[0104] The first transfer pattern (GT3c) can come into contact with the exposed first gate electrode (GT1b). The first transfer pattern (GT3c) can transfer the initialization voltage (VINT) to the first gate electrode (GT1b).

[0105] For example, the third conductive pattern may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the third conductive pattern may include the same material as the first conductive pattern or the second conductive pattern.

[0106] The second interlayer insulating layer covers the third conductive pattern and may be disposed on the third gate insulating layer. The third interlayer insulating layer may include an insulating material. For example, the third interlayer insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

[0107] Referring to FIGS. 1, 4, 12 and 13, a fourth conductive pattern may be disposed on the second interlayer insulating layer. The fourth conductive pattern may include a horizontal transfer wiring (SD1a), a second transfer pattern (SD1b), an anode initialization voltage wiring (SD1c), a third transfer pattern (SD1d), a fourth transfer pattern (SD1e), a fifth transfer pattern (SD1f), a sixth transfer pattern (SD1g), and a connection pattern (SD1h).

[0108] The horizontal transmission wiring (SD1a) may extend in the first direction (D1). In one area, the horizontal transmission wiring (SD1a) may correspond to a horizontal extension of the connection wiring described in FIG. 1. Thus, the data voltage (DATA) may be provided to the horizontal transmission wiring (SD1a). The data voltage may be transmitted to another data line not shown. In another pixel area, the horizontal transmission wiring (SD1a) may be a dummy wiring to which the data voltage is not applied. In one embodiment, the horizontal transmission wiring (SD1a) may overlap with the voltage wiring (GT2d). For example, the voltage wiring (GT2d) may shield the horizontal transmission wiring (SD1a).

[0109] The second transmission pattern (SD1b) can come into contact with the first active pattern (AP1). The data voltage (DATA) can be transmitted to the first active pattern (AP1) through the second transmission pattern (SD1b).

[0110] The anode initialization voltage wiring (SD1c) may be extended in the first direction (D1). The anode initialization voltage (AINT) may be provided to the anode initialization voltage wiring (SD1c). The anode initialization voltage wiring (SD1c) may be in contact with the first active pattern (AP1) and may transmit the anode initialization voltage (AINT) to the first active pattern (AP1).

[0111] The third transfer pattern (SD1d) can be in contact with the second active pattern (AP2) and the first transfer pattern (GT3c). The initialization voltage (VINT) can be transferred to the first gate electrode (GT1b) through the voltage wiring (GT2d), the connection pattern (SD1h), the second active pattern (AP2), the third transfer pattern (SD1d), and the first transfer pattern (GT3c).

[0112] The fourth transfer pattern (SD1e) can come into contact with the second active pattern (AP2) and the first active pattern (AP1). The fourth transfer pattern (SD1e) can electrically connect the second active pattern (AP2) and the first active pattern (AP1).

[0113] The fifth transfer pattern (SD1f) may be extended in the first direction (D1). The high power supply voltage (ELVDD) may be provided to the fifth transfer pattern (SD1f). The fifth transfer pattern (SD1f) may be in contact with the first active pattern (AP1) and may transfer the high power supply voltage (ELVDD) to the first active pattern (AP1).

[0114] The sixth transfer pattern (SD1g) can come into contact with the first active pattern (AP1). The sixth transfer pattern (SD1g) can transfer the driving current or the anode initialization voltage (AINT) from the first active pattern (AP1) to the organic light-emitting diode (OLED).

[0115] The connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a). Specifically, the connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a) in the second direction (D2) that intersects the first direction (D1). Additionally, the connection pattern (SD1h) may be spaced apart from the third gate wiring (GT2a) and the second gate electrode (GT3a). When viewed in a planar view, the connection pattern (SD1h) may be positioned between the third gate wiring (GT2a) and the horizontal transmission wiring (SD1a). The connection pattern (SD1h) may be electrically in contact with the second active pattern (AP2) and the voltage wiring (GT2d). Specifically, the connection pattern (SD1h) may be in contact with the second active pattern (AP2) and the voltage wiring (GT2d) through a contact (CNT). A detailed description of the above connection pattern (SD1h) and the above contact (CNT) will be provided later.

[0116] The first via insulating layer covers the fourth conductive pattern and may be disposed on the second interlayer insulating layer. The first via insulating layer may include an organic insulating material. For example, the first via insulating layer may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, etc.

[0117] Referring to FIGS. 1, FIGS. 4, FIGS. 14 and FIGS. 15, a fifth conductive pattern may be disposed on the first via insulating layer. The fifth conductive pattern may include a data line (SD2a), a vertical transmission line (SD2b), a high power voltage line (SD2c), and a seventh transmission pattern (SD2d).

[0118] The data wiring (SD2a) may be extended to the second direction (D2). The data voltage (DATA) may be transmitted to the first active pattern (AP1) through the data wiring (SD2a) and the second transmission pattern (SD1b).

[0119] The vertical transfer wiring (SD2b) may extend in the second direction (D2). The vertical transfer wiring (SD2b) may come into contact with the horizontal transfer wiring (SD1a). In one embodiment, the vertical transfer wiring (SD2b) may overlap with the voltage wiring (GT2d), the anode initialization voltage wiring (SD1c), and the fifth transfer pattern (SD1f). The voltage wiring (GT2d), the anode initialization voltage wiring (SD1c), and the fifth transfer pattern (SD1f) may shield the vertical transfer wiring (SD2b).

[0120] In one embodiment, the horizontal transmission wiring (SD1a) corresponds to the first data transmission horizontal wiring (HFL1) described with reference to FIG. 3, the data wiring (SD2a) corresponds to the fourth data wiring (DL4) described with reference to FIG. 3, and the vertical transmission wiring (SD2b) corresponds to the first vertical transmission wiring (VFL1) described with reference to FIG. 3. For example, different data voltages may be provided to the data wiring (SD2a) and the vertical transmission wiring (SD2b). Specifically, the first data voltage may be transmitted to the first active pattern (AP1) through the data wiring (SD2a), and a second data voltage different from the first data voltage may be transmitted to the horizontal transmission wiring (SD1a) through the vertical transmission wiring (SD2b).

[0121] The seventh transfer pattern (SD2d) can come into contact with the sixth transfer pattern (SD1g). The seventh transfer pattern (SD2d) can transfer the driving current or the anode initialization voltage (AINT) from the sixth transfer pattern (SD1g) to the organic light-emitting diode (OLED).

[0122] The second via insulating layer covers the fifth conductive pattern and may be disposed on the first via insulating layer. The second via insulating layer may include an organic insulating material.

[0123] FIG. 16 is an enlarged view of area A of FIG. 13. FIG. 17 is a cross-sectional view cut along line II' of FIG. 13.

[0124] Referring to FIGS. 13 and 16, the connection pattern (SD1h) can overlap with the voltage wiring (GT2d) when viewed in a planar view. Additionally, the connection pattern (SD1h) can overlap with a part of the second active pattern (AP2). Thus, the voltage wiring (GT2d) can overlap with the part of the second active pattern (AP2).

[0125] Referring further to FIG. 17, the second active pattern (AP2) may include a first part (a), a second part (b), and a third part (c). The first part (a) may be a part that overlaps with the connection pattern (SD1h) and the voltage wiring (GT2d). The second part (b) may be a part that does not overlap with both the connection pattern (SD1h) and the second gate electrode (GT3a). The third part (c) may be a part that overlaps with the second gate electrode (GT3a). The third part (c) that overlaps with the second gate electrode (GT3a) may not be doped with ions. The first and second parts (a, b) that do not overlap with the second gate electrode (GT3a) may be doped with ions.

[0126] FIG. 18 is a cross-sectional view taken along the line II-II' of FIG. 13.

[0127] Referring to FIG. 18, in one embodiment, the connection pattern (SD1h) may contact the second active pattern (AP2) through the first contact (CNT1) and the second contact (CNT2), respectively. The first contact (CNT1) may be placed at one end of the connection pattern (SD1h). The second contact (CNT2) may be placed at the other end of the connection pattern (SD1h).

[0128] In one embodiment, the connection pattern (SD1h) may further include a third contact (CNT3). The third contact (CNT3) may be positioned between the first contact (CNT1) and the second contact (CNT2). However, in another embodiment, the first to third contacts (CNT1, CNT2, CNT3) may be positioned differently from each other. Through the third contact (CNT3), the connection pattern (SD1h) may contact the voltage wiring (GT2d).

[0129] In one embodiment, the connection pattern (SD1h) may be electrically connected to the voltage wiring (GT2d) and the second active pattern (AP2). The voltage wiring (GT2d) may provide the initialization voltage (VINT) to the connection pattern (SD1h). Additionally, the connection pattern (SD1h) may provide the initialization voltage (VINT) to the second active pattern (AP2). Thus, the initialization voltage (VINT) may be provided to the first terminal of the fourth transistor through the voltage wiring (GT2d), the connection pattern (SD1h), and the second active pattern (AP2).

[0130] In conventional display devices, voltage wiring and an active pattern may come into contact through a contact. An initial voltage may be provided from the voltage wiring to the active pattern through the contact. However, there was a problem in that the dispersion of contact resistance values ​​increased due to the contact. In one embodiment according to the present invention, the voltage wiring (GT2d) and the second active pattern (AP2) may be electrically connected through a connection pattern (SD1h) instead of the contact. The initial voltage (VINT) may be provided from the voltage wiring (GT2d) to the second active pattern (AP2) through the connection pattern (SD1h). Therefore, the dispersion of the contact resistance values ​​may be reduced.

[0131] Additionally, the connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a) in the second direction (D2). Referring to FIG. 17, the connection pattern (SD1h) may be located between the horizontal transmission wiring (SD1a) and the third gate wiring (GT2a). Additionally, the connection pattern (SD1h) may be located between the horizontal transmission wiring (SD1a) and the second gate electrode (GT3a). Thus, the connection pattern (SD1h) can prevent coupling phenomena that may occur between the horizontal transmission wiring (SD1a), the third gate wiring (GT2a), and the second gate electrode (GT3a). Specifically, a data voltage (DATA) may be provided to the horizontal transmission wiring (SD1a), and a third gate signal (GI) may be provided to the third gate wiring (GT2a). By placing the above-mentioned connection batten (SD1h) between the horizontal transmission wiring (SD1a) and the third gate wiring (GT2a), coupling between the data voltage (DATA) and the third gate signal (GI) can be prevented.

[0132] FIGS. 19 to 23 are layout drawings for explaining pixel structures included in a display device according to one embodiment. Among the pixel structures of the display device (11) described with reference to FIGS. 19 to 23, configurations identical to the pixel structures of the display device (10) described with reference to FIGS. 5 to 15 have been described above and may be omitted below.

[0133] Referring to FIGS. 1, FIGS. 4, FIGS. 19 and FIGS. 20, the display device (10) may include the first pixel structure (PX1) and the second pixel structure (PX2) adjacent to each other. For example, the second pixel structure (PX2) may have a structure that is symmetrical to the structure of the first pixel structure (PX1) with respect to a virtual symmetry line.

[0134] A first active pattern (AP1) may be disposed on a buffer layer disposed on a substrate. In one embodiment, the first active pattern (AP1) may include a silicon semiconductor. A first gate insulating layer covers the first active pattern (AP1) and may be disposed on the substrate (SUB).

[0135] A first conductive pattern may be disposed on the first gate insulating layer. The first conductive pattern may include a first gate wiring (GT1a), a first gate electrode (GT1b), and a second gate wiring (GT1c).

[0136] The second gate insulating layer covers the first conductive pattern and can be disposed on the first gate insulating layer. The second active pattern (AP2) can be disposed on the first interlayer insulating layer.

[0137] A second conductive pattern may be disposed on the second gate insulating layer. The second conductive pattern may include a third gate wiring (GT2a), a fourth gate wiring (GT2b), a storage capacitor electrode (GT2c), and a voltage wiring (GT2d).

[0138] The first interlayer insulating layer covers the second conductive pattern and can be disposed on the second gate insulating layer.

[0139] The second active pattern (AP2) may be continuously extended in the first pixel area (PX1) and the second pixel area (PX2). For example, the second active pattern (AP2) may have a symmetrical shape with respect to a virtual line extending along a second direction (D2) perpendicular to the first direction (D1). The second active pattern (AP2) may include a first extension (EXT1) and a second extension (EXT2) extending in the first direction (D1). The first extension (EXT1) may be placed in the first pixel structure (PX1). The second extension (EXT2) may be placed in the second pixel structure (PX2). In one embodiment, the second active pattern (AP2) may overlap with the first gate wiring (GT1a), the third gate wiring (GT2a), the fourth gate wiring (GT2b), and the voltage wiring (GT2d). Specifically, the first extension part (EXT1) and the second extension part (EXT2) can overlap with the voltage wiring (GT2d).

[0140] The third gate insulating layer covers the second active pattern (AP2) and may be disposed on the first interlayer insulating layer. The third gate insulating layer may include an insulating material.

[0141] Referring to FIGS. 1, FIGS. 4 and FIGS. 21, a third conductive pattern may be disposed on the third gate insulating layer. The third conductive pattern may include a second gate electrode (GT3a), a fifth gate wiring (GT3b), and a first transfer pattern (GT3c).

[0142] The second gate electrode (GT3a) may overlap with the third gate wiring (GT2a) and the second active pattern (AP2). The second gate electrode (GT3a) may be electrically connected to the third gate wiring (GT2a). The third gate signal (GI) may be provided to the second gate electrode (GT3a). The third gate wiring (GT2a), the second active pattern (AP2), and the second gate electrode (GT3a) may constitute the fourth transistor (T4).

[0143] The length of the second gate electrode (GT3a) in the first direction (D1) may be smaller than the length of the third gate wiring (GT2a) in the first direction (D1).

[0144] The second interlayer insulating layer covers the third conductive pattern and can be disposed on the third gate insulating layer.

[0145] Referring to FIGS. 1, FIGS. 4 and FIGS. 22, a fourth conductive pattern may be disposed on the second interlayer insulating layer. The fourth conductive pattern may include a horizontal transfer wiring (SD1a), a second transfer pattern (SD1b), an anode initialization voltage wiring (SD1c), a third transfer pattern (SD1d), a fourth transfer pattern (SD1e), a fifth transfer pattern (SD1f), a sixth transfer pattern (SD1g), and a connection pattern (SD1h).

[0146] The horizontal transmission wiring (SD1a) may be extended in the first direction (D1). In one embodiment, the horizontal transmission wiring (SD1a) may overlap with the voltage wiring (GT2d). For example, the voltage wiring (GT2d) may shield the horizontal transmission wiring (SD1a). The horizontal transmission wiring (SD1a) may overlap with the first extension (EXT1) and the second extension (EXT2) of the second active pattern (AP2).

[0147] The above connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a). Specifically, the above connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a) in the second direction (D2) that intersects the first direction (D1). Additionally, the above connection pattern (SD1h) may be spaced apart from the third gate wiring (GT2a). When viewed in a planar view, the above connection pattern (SD1h) may be positioned between the third gate wiring (GT2a) and the horizontal transmission wiring (SD1a).

[0148] The above connection pattern (SD1h) can be electrically contacted with the second active pattern (AP2) and the voltage wiring (GT2d). Specifically, the above connection pattern (SD1h) can be contacted with the second active pattern (AP2) through a first contact (CNT1) and a second contact (CNT2). Additionally, the above connection pattern (SD1h) can be contacted with the voltage wiring (GT2d) through a third contact (CNT3).

[0149] The first via insulating layer covers the fourth conductive pattern and can be disposed on the second interlayer insulating layer.

[0150] Referring to FIGS. 1, FIGS. 4 and FIGS. 23, a fifth conductive pattern may be disposed on the first via insulating layer. The fifth conductive pattern may include a data line (SD2a), a vertical transmission line (SD2b), a high power supply voltage line (SD2c), and a seventh transmission pattern (SD2d).

[0151] FIG. 24 is a cross-sectional view taken along the line III-III' of FIG. 22. FIG. 25 is a cross-sectional view taken along the line IV-IV' of FIG. 22.

[0152] Referring to FIGS. 22, 24, and 25, the connection pattern (SD1h) can overlap with the voltage wiring (GT2d) when viewed in a planar view. The voltage wiring (GT2d) can overlap with the first extension (EXT1) and the second extension (EXT2) of the second active pattern (AP2).

[0153] FIG. 26 is a cross-sectional view taken along the VV' line of FIG. 22.

[0154] Referring to FIG. 26, in one embodiment, the connection pattern (SD1h) may include a first contact (CNT1) and a second contact (CNT2). The connection pattern (SD1h) may contact the second active pattern (AP2) through each of the first contact (CNT1) and the second contact (CNT2). In one embodiment, the connection pattern (SD1h) may further include a third contact (CNT3). Through the third contact (CNT3), the connection pattern (SD1h) may contact the voltage wiring (GT2d).

[0155] In one embodiment, the connection pattern (SD1h) may be electrically connected to the voltage wiring (GT2d) and the second active pattern (AP2). The initialization voltage (VINT) may be provided sequentially through the voltage wiring (GT2d), the connection pattern (SD1h), and the second active pattern (AP2). Thus, the dispersion of the contact resistance values ​​may be reduced.

[0156] Additionally, the second gate electrode (GT3a) and the third gate wiring (GT2a) may be spaced apart from the horizontal transmission wiring (SD1a). The connection pattern (SD1h) may be located between the horizontal transmission wiring (SD1a) and the third gate wiring (GT2a). Thus, the connection pattern (SD1h) can prevent coupling phenomena that may occur between the horizontal transmission wiring (SD1a) and the third gate wiring (GT2a). Similarly, the first extension () and the second extension () of the second active pattern (AP2) can prevent coupling phenomena that may occur between the horizontal transmission wiring (SD1a) and the third gate wiring (GT2a).

[0157] FIGS. 27 to 34 are layout drawings for explaining pixel structures included in a display device according to one embodiment. Among the pixel structures of the display device (12) described with reference to FIGS. 27 to 34, configurations identical to the pixel structures of the display device (10) described with reference to FIGS. 5 to 15 have been described above and may be omitted below.

[0158] Referring to FIGS. 1, FIGS. 4 and FIGS. 27, a first conductive pattern may be disposed on a first gate insulating layer. The first conductive pattern may include a first gate wiring (GT1a), a first gate electrode (GT1b), a second gate wiring (GT1c), and a second gate electrode (GT1d).

[0159] The second gate electrode (GT1d) may overlap with the second active pattern (AP2) and the fourth gate wiring (GT3a) described later. The second gate electrode (GT1d) may be electrically connected to the fourth gate wiring (GT3a) (see FIG. 33).

[0160] The second gate insulating layer covers the first conductive pattern and may be disposed on the first gate insulating layer. The second gate insulating layer may include an insulating material. Specifically, the second gate insulating layer may include silicon oxide, silicon nitride, or silicon oxynitride, and may have a single layer or a multilayer structure.

[0161] Referring to FIGS. 1, FIGS. 4 and FIGS. 28, a second conductive pattern may be disposed on the second gate insulating layer. The second conductive pattern may include a third gate wiring (GT2b), a storage capacitor electrode (GT2c), and a voltage wiring (GT2d).

[0162] The voltage wiring (GT2d) may be extended in the first direction (D1). In one embodiment, the initial voltage (VINT) may be provided through the voltage wiring (GT2d). The voltage wiring (GT2d) may provide the initial voltage (VINT) to the connection pattern (SD1h) described below.

[0163] The first interlayer insulating layer covers the second conductive pattern and can be disposed on the second gate insulating layer.

[0164] Referring to FIGS. 1, FIGS. 4, and FIGS. 29, a second active pattern (AP2) may be disposed on the first interlayer insulating layer. The second active pattern (AP2) may include an oxide semiconductor. The first active pattern (AP1) and the second active pattern (AP2) may include different materials.

[0165] In one embodiment, the second active pattern (AP2) may be placed on a different layer from the first active pattern (AP1). In other words, the second active pattern (AP2) may be formed separately from the first active pattern (AP1).

[0166] In one embodiment, the second active pattern (AP2) may be continuously extended in the first pixel area (PX1) and the second pixel area (PX2). For example, the second active pattern (AP2) may have a symmetrical shape with respect to a virtual line extending along a second direction (D2) perpendicular to the first direction (D1). The second active pattern (AP2) may include a first extension portion (EXT1) and a second extension portion (EXT2) extending in the first direction (D1). The first extension portion (EXT1) may be placed in the first pixel structure (PX1). The second extension portion (EXT2) may be placed in the second pixel structure (PX2).

[0167] In one embodiment, the second active pattern (AP2) may overlap with the first gate wiring (GT1a), the second gate electrode (GT1d), the third gate wiring (GT2b), and the voltage wiring (GT2d). Specifically, the first extension (EXT1) and the second extension (EXT2) may overlap with the voltage wiring (GT2d).

[0168] The third gate insulating layer covers the second active pattern (AP2) and may be disposed on the first interlayer insulating layer. The third gate insulating layer may include an insulating material.

[0169] Referring to FIGS. 1, FIGS. 4, FIGS. 30 and FIGS. 31, a third conductive pattern may be disposed on the third gate insulating layer. The third conductive pattern may include a fourth gate wiring (GT3a), a fifth gate wiring (GT3b), and a first transfer pattern (GT3c).

[0170] The fourth gate wiring (GT3a) may extend in the first direction (D1). The fourth gate wiring (GT3a) may overlap with the second gate electrode (GT1d) and the second active pattern (AP2). The second gate electrode (GT1d) may be electrically connected to the fourth gate wiring (GT3a). For example, the second gate electrode (GT1d) may be in contact with the fourth gate wiring (GT3a) through a contact. The third gate signal (GI) may be provided to the fourth gate wiring (GT3a). The second gate electrode (GT1d), the second active pattern (AP2), and the fourth gate wiring (GT3a) may form a fourth transistor (T4). For example, the second gate electrode (GT1d) corresponds to the back-gate terminal of the fourth transistor (T4) described with reference to FIG. 4, and the fourth gate wiring (GT3a) corresponds to the gate terminal of the fourth transistor (T4) described with reference to FIG. 4.

[0171] The length of the fourth gate wiring (GT3a) in the first direction (D1) may be greater than the length of the second gate electrode (GT1d) in the first direction (D1).

[0172] The fifth gate wiring (GT3b) may extend in the first direction (D1). The fifth gate wiring (GT3b) may overlap with the third gate wiring (GT2b) and the second active pattern (AP2). The fifth gate wiring (GT3b) may be electrically connected to the third gate wiring (GT2b). For example, the fifth gate wiring (GT3b) may be in contact with the third gate wiring (GT2b) through a contact. The second gate signal (GC) may be provided to the fifth gate wiring (GT3b). The third gate wiring (GT2b), the second active pattern (AP2), and the fifth gate wiring (GT3b) may constitute the third transistor (T3). For example, the third gate wiring (GT2b) corresponds to the back-gate terminal of the third transistor (T3) described with reference to FIG. 4, and the fifth gate wiring (GT3b) corresponds to the gate terminal of the third transistor (T3) described with reference to FIG. 4.

[0173] For example, the third conductive pattern may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the third conductive pattern may include the same material as the first conductive pattern or the second conductive pattern.

[0174] The second interlayer insulating layer covers the third conductive pattern and may be disposed on the third gate insulating layer. The third interlayer insulating layer may include an insulating material. For example, the third interlayer insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

[0175] Referring to FIGS. 1, FIGS. 4, FIGS. 32 and FIGS. 33, a fourth conductive pattern may be disposed on the second interlayer insulating layer. The fourth conductive pattern may include a horizontal transfer wiring (SD1a), a second transfer pattern (SD1b), an anode initialization voltage wiring (SD1c), a third transfer pattern (SD1d), a fourth transfer pattern (SD1e), a fifth transfer pattern (SD1f), a sixth transfer pattern (SD1g), and a connection pattern (SD1h).

[0176] The connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a). Specifically, the connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a) in the second direction (D2) that intersects the first direction (D1). Additionally, the connection pattern (SD1h) may be spaced apart from the fourth gate wiring (GT3a). When viewed in a planar view, the connection pattern (SD1h) may be positioned between the horizontal transmission wiring (SD1a) and the fourth gate wiring (GT3a). The connection pattern (SD1h) may be electrically in contact with the second active pattern (AP2) and the voltage wiring (GT2d). Specifically, the connection pattern (SD1h) may be in contact with the second active pattern (AP2) and the voltage wiring (GT2d) through a contact (CNT).

[0177] Referring to FIGS. 1, FIGS. 4 and FIGS. 34, a fifth conductive pattern may be disposed on a first via insulating layer. The fifth conductive pattern may include a data line (SD2a), a vertical transmission line (SD2b), a high power voltage line (SD2c), and a seventh transmission pattern (SD2d).

[0178] FIG. 35 is a cross-sectional view taken along the line VI-VI' of FIG. 33.

[0179] Referring to FIGS. 33 and 35, in one embodiment, the connection pattern (SD1h) may overlap with the voltage wiring (GT2d) when viewed in a planar view. Additionally, the connection pattern (SD1h) may overlap with a part of the second active pattern (AP2). The voltage wiring (GT2d) may overlap with the first extension (EXT1) and the second extension (EXT2) of the second active pattern (AP2) (see FIG. 29).

[0180] In one embodiment, the connection pattern (SD1h) may include a first contact (CNT1) and a second contact (CNT2). The connection pattern (SD1h) may contact the second active pattern (AP2) through each of the first contact (CNT1) and the second contact (CNT2). In one embodiment, the connection pattern (SD1h) may further include a third contact (CNT3). Through the third contact (CNT3), the connection pattern (SD1h) may contact the voltage wiring (GT2d) (see FIG. 26).

[0181] In one embodiment, the connection pattern (SD1h) may be electrically connected to the voltage wiring (GT2d) and the second active pattern (AP2). The initialization voltage (VINT) may be provided sequentially through the voltage wiring (GT2d), the connection pattern (SD1h), and the second active pattern (AP2). Thus, the dispersion of the contact resistance values ​​may be reduced.

[0182] Additionally, the second gate electrode (GT1d) and the fourth gate wiring (GT3a) may be spaced apart from the horizontal transfer wiring (SD1a). The connection pattern (SD1h) may be located between the horizontal transfer wiring (SD1a) and the fourth gate wiring (GT3a). The connection pattern (SD1h) may be located between the horizontal transfer wiring (SD1a) and the second gate electrode (GT1d). Therefore, the connection pattern (SD1h) can prevent coupling phenomena that may occur between the horizontal transfer wiring (SD1a) and the fourth gate wiring (GT3a).

[0183] FIGS. 36 to 41 are layout drawings for explaining pixel structures included in a display device according to one embodiment. Among the pixel structures of the display device (13) described with reference to FIGS. 36 to 41, configurations identical to the pixel structures of the display device (10) described with reference to FIGS. 5 to 15 have been described above and may be omitted below.

[0184] Referring to FIGS. 1, FIGS. 4 and FIGS. 36, a first conductive pattern may be disposed on a first gate insulating layer. The first conductive pattern may include a first gate wiring (GT1a), a first gate electrode (GT1b), and a second gate wiring (GT1c).

[0185] The second gate insulating layer covers the first conductive pattern and may be disposed on the first gate insulating layer. The second gate insulating layer may include an insulating material.

[0186] Referring to FIGS. 1, FIGS. 4 and FIGS. 37, a second conductive pattern may be disposed on a second gate insulating layer. The second conductive pattern may include a second gate electrode (GT2a), a third gate wiring (GT2b), a storage capacitor electrode (GT2c), and a voltage wiring (GT2d).

[0187] The second gate electrode (GT2a) may overlap with the second active pattern (AP2) and the fourth gate wiring (GT3a) described later. The second gate electrode (GT2a) may be electrically connected to the fourth gate wiring (GT3a).

[0188] The first interlayer insulating layer covers the second conductive pattern and can be disposed on the second gate insulating layer.

[0189] Referring to FIGS. 1, FIGS. 4 and FIGS. 38, a second active pattern (AP2) may be disposed on the first interlayer insulating layer. The second active pattern (AP2) may include an oxide semiconductor. The first active pattern (AP1) may include a silicon semiconductor. The first active pattern (AP1) and the second active pattern (AP2) may include different materials. In one embodiment, the second active pattern (AP2) may be disposed on a different layer from the first active pattern (AP1). In other words, the second active pattern (AP2) may be formed separately from the first active pattern (AP1).

[0190] In one embodiment, the second active pattern (AP2) may have a symmetrical shape with respect to a virtual line extending along a second direction (D2) perpendicular to the first direction (D1). The second active pattern (AP2) may include a first extension (EXT1) and a second extension (EXT2) extending in the first direction (D1). The first extension (EXT1) may be placed in a first pixel structure (PX1). The second extension (EXT2) may be placed in a second pixel structure (PX2).

[0191] In one embodiment, the second active pattern (AP2) may overlap with the first gate wiring (GT1a), the second gate electrode (GT2a), the third gate wiring (GT2b), and the voltage wiring (GT2d). Specifically, the first extension (EXT1) and the second extension (EXT2) may overlap with the voltage wiring (GT2d).

[0192] The third gate insulating layer covers the second active pattern (AP2) and may be disposed on the first interlayer insulating layer. The third gate insulating layer may include an insulating material.

[0193] Referring to FIGS. 1, FIGS. 4 and FIGS. 39, a third conductive pattern may be disposed on the third gate insulating layer. The third conductive pattern may include a fourth gate wiring (GT3a), a fifth gate wiring (GT3b), and a first transfer pattern (GT3c).

[0194] The fourth gate wiring (GT3a) may extend in the first direction (D1). The fourth gate wiring (GT3a) may overlap with the second gate electrode (GT2a) and the second active pattern (AP2). The second gate electrode (GT2a) may be electrically connected to the fourth gate wiring (GT3a). For example, the second gate electrode (GT2a) may be in contact with the fourth gate wiring (GT3a) through a contact. The third gate signal (GI) may be provided to the fourth gate wiring (GT3a). The second gate electrode (GT2a), the second active pattern (AP2), and the fourth gate wiring (GT3a) may form a fourth transistor (T4). For example, the second gate electrode (GT2a) corresponds to the back-gate terminal of the fourth transistor (T4) described with reference to FIG. 4, and the fourth gate wiring (GT3a) corresponds to the gate terminal of the fourth transistor (T4) described with reference to FIG. 4.

[0195] The length of the fourth gate wiring (GT3a) in the first direction (D1) may be greater than the length of the second gate electrode (GT2a) in the first direction (D1).

[0196] The fifth gate wiring (GT3b) may extend in the first direction (D1). The fifth gate wiring (GT3b) may overlap with the third gate wiring (GT2b) and the second active pattern (AP2). The fifth gate wiring (GT3b) may be electrically connected to the third gate wiring (GT2b). For example, the fifth gate wiring (GT3b) may be in contact with the third gate wiring (GT2b) through a contact. The second gate signal (GC) may be provided to the fifth gate wiring (GT3b). The third gate wiring (GT2b), the second active pattern (AP2), and the fifth gate wiring (GT3b) may constitute the third transistor (T3).

[0197] For example, the third conductive pattern may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the third conductive pattern may include the same material as the first conductive pattern or the second conductive pattern.

[0198] The second interlayer insulating layer covers the third conductive pattern and may be disposed on the third gate insulating layer. The third interlayer insulating layer may include an insulating material. For example, the third interlayer insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

[0199] Referring to FIGS. 1, 4 and 40, a fourth conductive pattern may be disposed on the second interlayer insulating layer. The fourth conductive pattern may include a horizontal transfer wiring (SD1a), a second transfer pattern (SD1b), an anode initialization voltage wiring (SD1c), a third transfer pattern (SD1d), a fourth transfer pattern (SD1e), a fifth transfer pattern (SD1f), a sixth transfer pattern (SD1g), and a connection pattern (SD1h).

[0200] The connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a). Additionally, the connection pattern (SD1h) may be spaced apart from the fourth gate wiring (GT3a). When viewed in a planar view, the connection pattern (SD1h) may be positioned between the horizontal transmission wiring (SD1a) and the fourth gate wiring (GT3a). The connection pattern (SD1h) may be electrically in contact with the second active pattern (AP2) and the voltage wiring (GT2d). Specifically, the connection pattern (SD1h) may be in contact with the second active pattern (AP2) and the voltage wiring (GT2d) through a contact (CNT).

[0201] Referring to FIGS. 1, 4 and 41, a fifth conductive pattern may be disposed on a first via insulating layer. The fifth conductive pattern may include a data line (SD2a), a vertical transmission line (SD2b), a high power voltage line (SD2c), and a seventh transmission pattern (SD2d).

[0202] FIG. 42 is a cross-sectional view taken along the line VII-VII' of FIG. 40.

[0203] Referring to FIGS. 40 and 42, in one embodiment, the connection pattern (SD1h) may overlap with the voltage wiring (GT2d) when viewed in a planar view. Additionally, the connection pattern (SD1h) may overlap with a part of the second active pattern (AP2). The voltage wiring (GT2d) may overlap with the first extension (EXT1) and the second extension (EXT2) of the second active pattern (AP2) (see FIG. 38).

[0204] In one embodiment, the connection pattern (SD1h) may include a first contact (CNT1) and a second contact (CNT2). The connection pattern (SD1h) may contact the second active pattern (AP2) through each of the first contact (CNT1) and the second contact (CNT2). In one embodiment, the connection pattern (SD1h) may further include a third contact (CNT3). Through the third contact (CNT3), the connection pattern (SD1h) may contact the voltage wiring (GT2d) (see FIG. 26).

[0205] In one embodiment, the connection pattern (SD1h) may be electrically connected to the voltage wiring (GT2d) and the second active pattern (AP2). The initialization voltage (VINT) may be provided sequentially through the voltage wiring (GT2d), the connection pattern (SD1h), and the second active pattern (AP2). Thus, the dispersion of the contact resistance values ​​may be reduced.

[0206] Additionally, the second gate electrode (GT2d) and the fourth gate wiring (GT3a) may be spaced apart from the horizontal transfer wiring (SD1a). The connection pattern (SD1h) may be located between the horizontal transfer wiring (SD1a) and the fourth gate wiring (GT3a). Thus, the connection pattern (SD1h) can prevent coupling phenomena that may occur between the horizontal transfer wiring (SD1a) and the fourth gate wiring (GT3a).

[0207] FIGS. 43 to 51 are layout drawings for explaining pixel structures included in a display device according to one embodiment. Among the pixel structures of the display device (14) described with reference to FIGS. 43 to 51, configurations identical to the pixel structures of the display device (10) described with reference to FIGS. 5 to 15 have been described above and may be omitted below.

[0208] Referring to FIGS. 1, 4 and 43, a first conductive pattern may be disposed on the first gate insulating layer. The first conductive pattern may include a first gate wiring (GT1a), a first gate electrode (GT1b), and a second gate wiring (GT1c).

[0209] The second gate insulating layer covers the first conductive pattern and can be disposed on the first gate insulating layer.

[0210] Referring to FIGS. 1, 4 and 44, a second conductive pattern may be disposed on the second gate insulating layer. The second conductive pattern may include a third gate wiring (GT2a), a fourth gate wiring (GT2b), a storage capacitor electrode (GT2c), and a voltage wiring (GT2d).

[0211] The voltage wiring (GT2d) may be extended in the first direction (D1). In one embodiment, the initial voltage (VINT) may be provided through the voltage wiring (GT2d). The voltage wiring (GT2d) may provide the initial voltage (VINT) to the connection pattern (SD1h) described below.

[0212] The first interlayer insulating layer covers the second conductive pattern and can be disposed on the second gate insulating layer.

[0213] Referring to FIGS. 1, 4, 45 and 46, a second active pattern (AP2) may be disposed on the first interlayer insulating layer. The second active pattern (AP2) may include an oxide semiconductor. The first active pattern (AP1) may include a silicon semiconductor. The first active pattern (AP1) and the second active pattern (AP2) may include different materials.

[0214] In one embodiment, the second active pattern (AP2) may have a symmetrical shape with respect to a virtual line extending along a second direction (D2) perpendicular to the first direction (D1). The second active pattern (AP2) may include a portion placed in the first pixel area (PX1) and a portion placed in the second pixel area (PX2).

[0215] In one embodiment, the second active pattern (AP2) may overlap with the first gate wiring (GT1a), the third gate wiring (GT2a), the fourth gate wiring (GT2b), and the voltage wiring (GT2d).

[0216] The second active pattern (AP2) of FIG. 8 and the second active pattern (AP2) of FIG. 45 may have different shapes. The length of the second active pattern (AP2) of FIG. 45 in the second direction (D2) may be greater than the length of the second active pattern (AP2) of FIG. 8 in the second direction (D2). Also, the gap between the voltage wiring (GT2d) of FIG. 46 and the third gate wiring (GT2a) may be greater than the gap between the voltage wiring (GT2d) of FIG. 9 and the third gate wiring (GT2a).

[0217] The third gate insulating layer covers the second active pattern (AP2) and may be disposed on the first interlayer insulating layer. The third gate insulating layer may include an insulating material.

[0218] Referring to FIGS. 1, FIGS. 4, FIGS. 47 and FIGS. 48, a third conductive pattern may be disposed on the third gate insulating layer. The third conductive pattern may include a second gate electrode (GT3a), a fifth gate wiring (GT3b), and a first transfer pattern (GT3c).

[0219] The second gate electrode (GT3a) may overlap with the third gate wiring (GT2a) and the second active pattern (AP2). The second gate electrode (GT3a) may be electrically connected to the third gate wiring (GT2a). The third gate signal (GI) may be provided to the second gate electrode (GT3a) through the third gate wiring (GT2a). The third gate wiring (GT2a), the second active pattern (AP2), and the second gate electrode (GT3a) may form the fourth transistor (T4). For example, the third gate wiring (GT2a) may correspond to the back-gate terminal of the fourth transistor (T4) described with reference to FIG. 4, and the second gate electrode (GT3a) may correspond to the gate terminal of the fourth transistor described with reference to FIG. 4.

[0220] The length of the second gate electrode (GT3a) in the first direction (D1) may be smaller than the length of the third gate wiring (GT2a) in the first direction (D1).

[0221] The second interlayer insulating layer covers the third conductive pattern and can be disposed on the third gate insulating layer.

[0222] Referring to FIGS. 1, 4, 49 and 50, a fourth conductive pattern may be disposed on the second interlayer insulating layer. The fourth conductive pattern may include a horizontal transfer wiring (SD1a), a second transfer pattern (SD1b), an anode initialization voltage wiring (SD1c), a third transfer pattern (SD1d), a fourth transfer pattern (SD1e), a fifth transfer pattern (SD1f), a sixth transfer pattern (SD1g), and a connection pattern (SD1h).

[0223] The horizontal transmission wiring (SD1a) may extend in the first direction (D1). In one area, the horizontal transmission wiring (SD1a) may correspond to a horizontal extension of the connection wiring described in FIG. 1. Thus, the data voltage (DATA) may be provided to the horizontal transmission wiring (SD1a). The data voltage may be transmitted to another data line not shown. In another pixel area, the horizontal transmission wiring (SD1a) may be a dummy wiring to which the data voltage is not applied. In one embodiment, the horizontal transmission wiring (SD1a) may overlap with the voltage wiring (1510). For example, the voltage wiring (1510) may shield the horizontal transmission wiring (SD1a).

[0224] Unlike the horizontal transmission wiring (SD1a) of FIG. 13, the above horizontal transmission wiring (SD1a) can overlap with the second active pattern (AP2). Specifically, the horizontal transmission wiring (SD1a) of FIG. 13 can be spaced apart from the second active pattern (AP2). In contrast, the straight section (STR) of the above horizontal transmission wiring (SD1a) of FIG. 52 can overlap with the second active pattern (AP2).

[0225] The above connection pattern (SD1h) may be spaced apart from the horizontal transfer wiring (SD1a) and the third gate wiring (GT2a). The horizontal transfer wiring (SD1a) may be positioned between the connection pattern (SD1h) and the third gate wiring (GT2a) when viewed in a planar view. The connection pattern (SD1h) may be electrically in contact with the second active pattern (AP2) and the voltage wiring (GT2d). Specifically, the connection pattern (SD1h) may be in contact with the second active pattern (AP2) and the voltage wiring (GT2d) through a contact (CNT).

[0226] Unlike the horizontal transmission wiring (SD1a) of FIG. 50, the horizontal transmission wiring (SD1a) of FIG. 12 may include a straight section (STR). By including the straight section (STR) in the horizontal transmission wiring (SD1a) of FIG. 50, the manufacturing process of the display device (14) can be easily carried out. The straight section (STR) of the horizontal transmission wiring (SD1a) may be spaced apart from the connection pattern (SD1h) in the second direction (D2).

[0227] The first via insulating layer covers the fourth conductive pattern and can be disposed on the second interlayer insulating layer.

[0228] Referring to FIGS. 1, FIGS. 4 and FIGS. 51, a fifth conductive pattern may be disposed on the first via insulating layer. The fifth conductive pattern may include a data line (SD2a), a vertical transmission line (SD2b), a high power voltage line (SD2c), and a seventh transmission pattern (SD2d).

[0229] FIG. 52 is a cross-sectional view taken along the line VIII-VIII' of FIG. 50.

[0230] Referring to FIGS. 50 and 52, the connection pattern (SD1h) may overlap with the voltage wiring (GT2d) when viewed in a plane. The connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a) in a third direction (D3) opposite to the second direction (D2).

[0231] In one embodiment, the connection pattern (SD1h) may include a first contact (CNT1) and a second contact (CNT2). The connection pattern (SD1h) may contact the second active pattern (AP2) through each of the first contact (CNT1) and the second contact (CNT2). In one embodiment, the connection pattern (SD1h) may further include a third contact (CNT3). Through the third contact (CNT3), the connection pattern (SD1h) may contact the voltage wiring (GT2d) (see FIG. 18).

[0232] In one embodiment, the connection pattern (SD1h) may be spaced apart from the horizontal transmission wiring (SD1a), and the connection pattern (SD1h) may be electrically connected to the voltage wiring (GT2d) and the second active pattern (AP2). The initialization voltage (VINT) may be provided sequentially through the voltage wiring (GT2d), the connection pattern (SD1h), and the second active pattern (AP2). Thus, the dispersion of the contact resistance values ​​may be reduced.

[0233] In one embodiment, the horizontal transmission wiring (SD1a) includes the straight section (STR), so that no design resolution constraints may occur in the display device (14).

[0234] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Industrial applicability

[0235] A display device according to exemplary embodiments of the present invention can be applied to a display device including a computer, laptop, mobile phone, smartphone, smartpad, PMP, PDA, MP3 player, etc.

[0236] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0237] 10, 11, 12, 13, 14: Display device PNL: Display panel PX1: 1st pixel structure PX2: 2nd pixel structure AP1: 1st active pattern AP2: 2nd active pattern GT1a: 1st gate wiring GT1b: 1st gate electrode GT1c: 2nd gate wiring GT2d: Voltage wiring EXT1: 1st extension part EXT2: 2nd extension part SD1a: Horizontal transmission wiring SD1h: Connection pattern CNT1: First contact CNT2: Second contact CNT3: Third contact SD2a: Data wiring SD2b: Vertical transmission wiring

Claims

Claim 1 A display device comprising: a first active pattern disposed on a substrate; a second active pattern comprising a material different from that of the first active pattern; a voltage line disposed below the second active pattern; a horizontal transmission line disposed above the second active pattern and extending in a first direction; a connection pattern spaced apart from the horizontal transmission line and disposed on the same layer as the horizontal transmission line, and electrically contacting the second active pattern and the voltage line, wherein the connection pattern contacts the second active pattern through a first contact and a second contact, respectively, and contacts the voltage line through a third contact, wherein the third contact is disposed between the first contact and the second contact, and the connection pattern connects the second active pattern and the voltage line to each other through the first contact and the third contact, and connects the second active pattern and the voltage line to each other through the second contact and the third contact. Claim 2 delete Claim 3 A display device according to claim 1, characterized in that the voltage wiring provides an initialization voltage to the second active pattern through the connection pattern. Claim 4 A display device according to claim 1, further comprising gate wiring that transmits a gate signal. Claim 5 A display device according to claim 4, characterized in that the connection pattern is spaced apart from the horizontal transmission wiring and the gate wiring when viewed on a plane, and is positioned between the horizontal transmission wiring and the gate wiring. Claim 6 A display device according to claim 4, further comprising: a first conductive pattern disposed below the second active pattern; a second conductive pattern disposed below the second active pattern and disposed above the first conductive pattern; and a third conductive pattern disposed above the second active pattern. Claim 7 A display device according to claim 6, wherein the third conductive pattern includes a gate electrode that overlaps with the second active pattern, the second conductive pattern includes a gate wiring, the gate wiring is electrically connected to the gate electrode and extends in the first direction. Claim 8 A display device according to claim 6, wherein the second conductive pattern includes a gate electrode that overlaps with the second active pattern, and the third conductive pattern includes the gate wiring, wherein the gate wiring is electrically connected to the gate electrode and extends in the first direction. Claim 9 A display device according to claim 1, wherein the first active pattern comprises a silicon semiconductor and the second active pattern comprises an oxide semiconductor. Claim 10 A display device according to claim 1, further comprising: a data line disposed above the horizontal transmission line and extending in a second direction and providing a data voltage to the first active pattern; and a vertical transmission line disposed in the same layer as the data line and extending in the second direction and providing a data voltage to the horizontal transmission line. Claim 11 A display device according to claim 1, wherein the second active pattern further comprises a first extension portion and a second extension portion extending in the first direction, and the first extension portion and the second extension portion overlap with the voltage wiring and the horizontal transmission wiring and further comprise a first conductive pattern disposed below the second active pattern; a second conductive pattern disposed below the second active pattern and disposed above the first conductive pattern; and a third conductive pattern disposed above the second active pattern. Claim 12 A display device according to claim 11, wherein the third conductive pattern includes a gate electrode that overlaps with the second active pattern, and the second conductive pattern includes a gate wiring that transmits a gate signal, and the gate wiring is electrically connected to the gate electrode and extends in the first direction. Claim 13 A display device according to claim 11, wherein the second conductive pattern includes a gate electrode that overlaps with the second active pattern, and the third conductive pattern includes a gate wiring that transmits a gate signal, wherein the gate wiring is electrically connected to the gate electrode and extends in the first direction. Claim 14 A display device according to claim 11, wherein the first conductive pattern includes a gate electrode that overlaps with the second active pattern, and the third conductive pattern includes a gate wiring that transmits a gate signal, wherein the gate wiring is electrically connected to the gate electrode and extends in the first direction. Claim 15 A display device comprising: a first active pattern disposed on a substrate; a second active pattern comprising a material different from that of the first active pattern; a voltage line disposed below the second active pattern; a connection pattern disposed above the second active pattern and electrically contacting the second active pattern and the voltage line; and a horizontal transmission line extending in a first direction, disposed on the same layer as the connection pattern, overlapping with the second active pattern, and transmitting a data signal, wherein the connection pattern contacts the second active pattern through a first contact and a second contact, respectively, and contacts the voltage line through a third contact, wherein the third contact is disposed between the first contact and the second contact, and the connection pattern connects the second active pattern and the voltage line to each other through the first contact and the third contact, and connects the second active pattern and the voltage line to each other through the second contact and the third contact. Claim 16 delete Claim 17 A display device according to claim 15, characterized in that the voltage wiring provides an initialization voltage to the second active pattern through the connection pattern. Claim 18 A display device according to claim 15, further comprising gate wiring that transmits a gate signal. Claim 19 A display device according to claim 18, characterized in that the connection pattern is spaced apart from the horizontal transmission wiring and the gate wiring when viewed in a planar view, and the horizontal transmission wiring is positioned between the connection pattern and the gate wiring. Claim 20 A display device according to claim 15, wherein the first active pattern comprises a silicon semiconductor and the second active pattern comprises an oxide semiconductor.

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