Display device

Abstract

A display device comprises a substrate including a first display area, a non-display area bent from the first display area, and a second display area adjacent to the non-display area, a first data line disposed on the first display area and connected to a data driver, a second data line disposed on the second display area, and a bypass data line disposed on the non-display area and electrically connecting the data driver and the second data line.

Description

Technology Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a bent display device. Background Technology

[0002] A display device is a device that displays an image using light emitted by pixels. The pixels emit light based on data voltage. Recently, display devices having a bent structure are being developed. In order to display an image even in the bent area, it is necessary to transmit data voltage to the pixels formed in the bent area. The problem to be solved

[0003] The objective of the present invention is to provide a display device.

[0004] However, the purpose of the present invention is not limited to the aforementioned purpose and may be expanded in various ways without departing from the spirit and scope of the present invention. means of solving the problem

[0005] To achieve the aforementioned objective of the present invention, a display device according to one embodiment of the present invention may include a substrate comprising a first display area, a non-display area bent from the first display area, and a second display area adjacent to the non-display area; a first data line disposed on the first display area of ​​the substrate and connected to a data driving unit; a second data line disposed on the second display area of ​​the substrate; and a bypass data line disposed on the non-display area of ​​the substrate and electrically connecting the data driving unit and the second data line.

[0006] According to one embodiment, the second display area is adjacent to the first display area in a first direction, and the bypass data wiring may include a bypass horizontal wiring extending in the first direction.

[0007] According to one embodiment, the bypass data wiring may further include a first bypass vertical wiring that is positioned on the first display area and extends in a second direction intersecting the first direction, and a second bypass vertical wiring that is positioned on the second display area and extends in the second direction.

[0008] According to one embodiment, the first bypass vertical wiring and the bypass horizontal wiring are connected through a first contact hole in the first display area, and the second bypass vertical wiring and the bypass horizontal wiring can be connected through a second contact hole in the second display area.

[0009] According to one embodiment, the display device may further include an active pattern disposed on the first display area of ​​the substrate, a gate electrode disposed on the active pattern, and a connecting electrode disposed between the gate electrode and the first data line and connecting the active pattern and the first data line. The bypass horizontal line is formed together with the connecting electrode, and the first bypass vertical line and the second bypass vertical line may be formed together with the first data line.

[0010] According to one embodiment, the bypass data wiring may include aluminum.

[0011] According to one embodiment, a first pixel electrically connected to the first data wiring may be disposed in the first display area, and a second pixel electrically connected to the second data wiring may be disposed in the second display area.

[0012] According to one embodiment, pixels may not be placed in the non-display area.

[0013] According to one embodiment, the display device may further include a light-blocking layer disposed on the non-display area of ​​the substrate.

[0014] To achieve the aforementioned objective of the present invention, a display device according to another embodiment of the present invention may include a substrate comprising a first display area, a non-display area bent from the first display area, and a second display area adjacent to the non-display area in a first direction, a first gate wiring disposed on the first display area of ​​the substrate and extending in the first direction, a second gate wiring disposed on the second display area of ​​the substrate and extending in the first direction and electrically connected to the first gate wiring, and a vertical wiring disposed on the non-display area of ​​the substrate and extending in a second direction intersecting the first direction.

[0015] According to one embodiment, the vertical wiring may include aluminum.

[0016] According to one embodiment, a power voltage may be applied to the vertical wiring.

[0017] According to one embodiment, the display device may further include a gate bridge wiring that extends in the first direction from the non-display area and connects the first gate wiring and the second gate wiring.

[0018] According to one embodiment, a sensing voltage may be applied to the vertical wiring.

[0019] According to one embodiment, the display device may further include a gate bridge wiring that extends in the second direction from the non-display area and connects the first gate wiring and the second gate wiring, and a shielding pattern disposed between the gate bridge wiring and the vertical wiring.

[0020] According to one embodiment, the display device may further include a driving transistor disposed on the non-display area of ​​the substrate and providing a gate signal to the first gate wiring and the second gate wiring, and a shielding pattern disposed between the driving transistor and the vertical wiring.

[0021] To achieve the aforementioned objective of the present invention, a display device according to another embodiment of the present invention may include a substrate comprising a first display area, a non-display area bent from the first display area, and a second display area adjacent to the non-display area in a first direction, a first gate wiring disposed on the first display area of ​​the substrate and extending in the first direction, a second gate wiring disposed on the second display area of ​​the substrate and extending in the first direction and electrically connected to the first gate wiring, and a driving transistor disposed on the non-display area of ​​the substrate and providing a gate signal to the first gate wiring and the second gate wiring.

[0022] According to one embodiment, the display device may further include power wiring that is disposed on the driving transistor and extends in a second direction intersecting the first direction. Effects of the invention

[0023] A display device according to embodiments of the present invention may include a first display area, a non-display area bent from the first display area, and a second display area adjacent to the non-display area. A data voltage may be transmitted to a pixel formed in the second display area through a bypass data wiring. As the bypass data wiring is formed in the first display area (DA1), the first non-display area (NDA1), and the second display area (DA2), a fan-out wiring may not be formed in the display device. Accordingly, the dead space of the display device may be reduced.

[0024] Additionally, pixels may not be placed in the above-mentioned non-display area. In other words, a layer for forming the pixels (e.g., an inorganic layer, a light-emitting layer, etc.) may not be placed in the above-mentioned non-display area. Accordingly, the above-mentioned non-display area can be bent more smoothly.

[0025] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0026] FIG. 1 is a plan view for illustrating a display device according to embodiments of the present invention. FIG. 2 is a side view illustrating the display device of FIG. 1. Figure 3 is a circuit diagram for explaining a pixel included in the display device of Figure 1. FIG. 4 is an enlarged view for explaining a display device according to one embodiment of the present invention. Figure 5 is a cross-sectional view illustrating the display device of Figure 4. FIG. 6 is a cross-sectional view illustrating the display device of FIG. 4. FIGS. 7 to 11 are cross-sectional views for explaining a method of manufacturing the display device of FIG. 4. FIG. 12 is an enlarged view for illustrating a display device according to another embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating the display device of FIG. 12. FIG. 14 is an enlarged view illustrating a display device according to another embodiment of the present invention. FIG. 15 is a cross-sectional view illustrating the display device of FIG. 14. FIG. 16 is an enlarged view illustrating another embodiment of the present invention. FIG. 17 is a cross-sectional view illustrating the display device of FIG. 16. FIG. 18 is a cross-sectional view illustrating another embodiment of the present invention. Specific details for implementing the invention

[0027] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0028] FIG. 1 is a plan view for illustrating a display device according to embodiments of the present invention.

[0029] Referring to FIG. 1, a display device (1000) according to embodiments of the present invention may include a substrate (SUB), a data driving unit (DDV), and a circuit board (CB).

[0030] The above substrate (SUB) may include a first display area (DA1), a second display area (DA2), a third display area (DA3), a first non-display area (NDA1), and a second non-display area (NDA2).

[0031] Pixels (PX) may be placed in the first display area (DA1), the second display area (DA2), and the third display area (DA3). For example, a first pixel (PX1) may be placed in the first display area (DA1), a second pixel (PX2) may be placed in the second display area (DA2), and a third pixel (PX3) may be placed in the third display area (DA3). Each of the first to third pixels (PX1, PX2, PX3) may have substantially the same structure as each other.

[0032] The user can see the first display area (DA1) through the front of the display device (1000). For example, the first display area (DA1) may be the main display area of ​​the display device (1000).

[0033] The user can see the second display area (DA2) and the third display area (DA3) through the side of the display device (1000). For example, the second display area (DA2) and the third display area (DA3) may be auxiliary display areas of the display device (1000).

[0034] In one embodiment, the planar area of ​​the first display area (DA1) may be larger than the planar area of ​​the second display area (DA2) and may be larger than the planar area of ​​the third display area (DA3). The planar area of ​​the second display area (DA2) may be substantially the same as the planar area of ​​the third display area (DA3). However, the planar areas of each display area are not limited to those described above.

[0035] The first non-display area (NDA1) may be adjacent to the first display area (DA1) in the first direction (D1). The second display area (DA2) may be adjacent to the first non-display area (NDA1) in the first direction (D1). For example, the first non-display area (NDA1) may be located between the first display area (DA1) and the second display area (DA2).

[0036] In one embodiment, pixels may not be placed in the first non-display area (NDA1). In other words, a layer for forming the pixels (e.g., an inorganic layer, a light-emitting layer, etc.) may not be placed in the first non-display area (NDA1). Accordingly, the first non-display area (NDA1) can be bent more smoothly.

[0037] The second non-display area (NDA2) may be adjacent to the first display area (DA1) in a direction opposite to the first direction (D1). For example, the second non-display area (NDA2) may be located between the first display area (DA1) and the second display area (DA2).

[0038] In one embodiment, pixels may not be placed in the second non-display area (NDA2). In other words, a layer for forming the pixels (e.g., an inorganic layer, a light-emitting layer, etc.) may not be placed in the second non-display area (NDA1). Accordingly, the second non-display area (NDA2) can be bent more smoothly.

[0039] The data driving unit (DDV) may be disposed on the circuit board (CB) and may be electrically connected to the substrate (SUB) through the circuit board (CB). In one embodiment, the data driving unit (DDV) may generate a data voltage and provide it to the pixel (PX). For example, the data driving unit (DDV) may provide a first data voltage to the first pixel (PX1), provide a second data voltage to the second pixel (PX2), and provide a third data voltage to the third pixel (PX3).

[0040] FIG. 2 is a side view for explaining the display device of FIG. 1. For example, FIG. 2 is a side view for explaining the structure of the display device of FIG. 1 that is bent.

[0041] Referring to FIG. 2, the display device (1000) may include a protective film (PF), a substrate (SUB), a transistor layer (TL), a light-emitting layer (EL), an encapsulation layer (ENC), a sensing layer (SL), a polarizer (POL), a window (WIN), a protective layer (PL), a bending protective layer (BPL), and a light-blocking layer (BM). The first non-display area (NDA1) may be bent from the first display area (DA1). Accordingly, the first display area (DA1) and the second display area (DA2) may extend in a direction that intersects each other.

[0042] The protective film (PF) may be disposed on the lower part of the substrate (SUB). The protective film (PF) may overlap with the first display area (DA1), the first non-display area (NDA1), and the second display area (DA2). The protective film (PF) may support the substrate (SUB). In one embodiment, the protective film (PF) may be a plastic film. Examples of plastics that can be used in the above protective film (PF) include polyimide (polyimide PI), polyethylene terephthalate (polyethylene terephthalate PET), polyethylene naphthalene (polyethylene naphthalene PEN), polypropylene (polypropylene PP), polycarbonate (polycarbonate PC), polystyrene (polystyrene PS), polysulfone (polysulfone PSul), polyethylene (polyethylene PE), polyphthalamide (polyphthalamide PPA), polyethersulfone (polyethersulfone PES), polyarylate (polyarylate PAR), polycarbonate oxide (polycarbonate oxide PCO), and modified polyphenylene oxide (modified polyphenylene oxide MPPO). These may be used alone or in combination with each other.

[0043] The substrate (SUB) may be placed on a protective film (PF). In one embodiment, the substrate (SUB) may be formed of glass, quartz, plastic, etc. Examples of plastics that may be used for the substrate (SUB) include polyimide (polyimide PI), polyethylene terephthalate (polyethylene terephthalate PET), polyethylene naphthalene (polyethylene naphthalene PEN), polypropylene (polypropylene PP), polycarbonate (polycarbonate PC), polystyrene (polystyrene PS), polysulfone (polysulfone PSul), polyethylene (polyethylene PE), polyphthalamide (polyphthalamide PPA), polyethersulfone (polyethersulfone PES), polyarylate (polyarylate PAR), polycarbonate oxide (polycarbonate oxide PCO), modified polyphenylene oxide (modified polyphenylene oxide MPPO), etc. These may be used alone or in combination with each other.

[0044] The transistor layer (TL) may be disposed on the substrate (SUB). The transistor layer (TL) may overlap with the first display area (DA1), the first non-display area (NDA1), and the second display area (DA2).

[0045] An inorganic layer, an organic layer, and metal patterns may be formed on the transistor layer (TL) that overlaps with the first display area (DA1) and the second display area (DA2). A transistor may be implemented through the inorganic layer, the organic layer, and the metal patterns.

[0046] Organic layers and metal patterns may be formed on the transistor layer (TL) that overlaps with the first non-display area (NDA1). The transistor layer (TL) of the first non-display area (NDA1) may be a layer that electrically connects the first display area (DA1) and the second display area (DA2).

[0047] The light-emitting layer (EL) may be disposed on the transistor layer (TL). The light-emitting layer (EL) may overlap with the first display area (DA1) and the second display area (DA2). The light-emitting layer (EL) may emit light based on the driving current provided from the transistor layer (TL). In one embodiment, the light-emitting layer (EL) may not overlap with the first non-display area (NDA1).

[0048] The above encapsulation layer (ENC) may be disposed on the light-emitting layer (EL). The above encapsulation layer (ENC) may overlap with the first display area (DA1) and the second display area (DA2). The above encapsulation layer (ENC) may have a structure in which an inorganic layer and an organic layer are laminated. The above encapsulation layer (ENC) can prevent moisture, air, etc. from penetrating into the light-emitting layer (EL).

[0049] The sensing layer (SL) may be disposed on the encapsulation layer (ENC). The sensing layer (SL) may include a sensing electrode and may detect a user's touch.

[0050] The above polarization layer (POL) may be disposed on the sensing layer (SL). The polarization layer (POL) can change the direction of light propagation to suppress the reflection of external light.

[0051] The window (WIN) may be disposed on the polarizing layer (POL). The window (WIN) may protect components disposed below the window (WIN). In one embodiment, the window (WIN) may be formed of glass, plastic, etc. Examples of materials that can be used as the window (WIN) include ultra-thin glass (UTG), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalene (PEN), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polysulfone (PSul), polyethylene (PE), polyphthalamide (PPA), polyethersulfone (PES), polyarylate (PAR), and polycarbonate oxide (PCO). These may be used alone or in combination with each other.

[0052] The above protective layer (PL) can be placed on the window (WIN). The protective layer (PL) can protect the window (WIN) from external impact.

[0053] The bending protection layer (BPL) may be disposed on the transistor layer (TL). The bending protection layer (BPL) may overlap with the first non-display area (NDA1). The bending protection layer (BPL) may be formed of polyimide, epoxy resin, acrylic resin, polyester, photoresist, polyacrylic resin, polyimide resin, polyamide resin, silosan resin, silicone, urethane, thermoplastic polyurethane, etc. These may be used alone or in combination with each other.

[0054] The light-blocking layer (BM) may overlap with the first non-display area (NDA1). The light-blocking layer (BM) may block light. Accordingly, the light-blocking layer (BM) may prevent components placed below the light-blocking layer (BM) from being visible to the user.

[0055] In one embodiment, the light-blocking layer (BM) may be disposed on the protective layer (PL). However, the present invention is not limited thereto. In another embodiment, the light-blocking layer (BM) may be disposed below the protective layer (PL). In yet another embodiment, the light-blocking layer (BM) may be disposed below the window (WIN).

[0056] The light-emitting layer (EL) and the encapsulation layer (ENC) may not be formed in the first non-display area (NDA1) of the display device (1000), and at least one inorganic layer may be omitted. Additionally, a flexible bending protection layer (BPL) may be formed in the first non-display area (NDA1). Accordingly, the first non-display area (NDA1) can be bent more smoothly.

[0057] Figure 3 is a circuit diagram for explaining a pixel included in the display device of Figure 1.

[0058] Referring to FIG. 3, the pixel (PX) may include a first transistor (TR1), a second transistor (TR2), a third transistor (TR3), a fourth transistor (TR4), a fifth transistor (TR5), a sixth transistor (TR6), a seventh transistor (TR7), a storage capacitor (CST), and an organic light-emitting diode (OLED).

[0059] The first transistor (TR1) may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be connected to the storage capacitor (CST). The first terminal may be connected to the second transistor (TR2). The second terminal may be connected to the sixth transistor (TR6). The first transistor (TR1) may generate a driving current (ID) based on the voltage difference between the gate terminal and the first terminal.

[0060] The second transistor (TR2) may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a first gate signal (GW). The first terminal may receive a data voltage (DATA). The second terminal may be connected to the first transistor (TR1). The second transistor (TR2) may transmit the data voltage (DATA) to the first transistor (TR1) in response to the first gate signal (GW).

[0061] The third transistor (TR3) may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive the first gate signal (GW). The first terminal may be connected to the gate terminal of the first transistor (TR1). The second terminal may be connected to the second terminal of the first transistor (TR1). The third transistor (TR3) may compensate for the threshold voltage of the first transistor (TR1).

[0062] The fourth transistor (TR4) may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a second gate signal (GI). The first terminal may be connected to the gate terminal of the first transistor (TR1). The second terminal may receive an initialization voltage (VINT). The fourth transistor (TR4) may initialize the gate terminal of the first transistor (TR1).

[0063] The fifth transistor (TR5) may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a light emission control signal (EM). The first terminal may receive a high power supply voltage (ELVDD). The second terminal may be connected to the first transistor (TR1).

[0064] The sixth transistor (TR6) may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a light emission control signal (EM). The first terminal may be connected to the first transistor (TR1). The second terminal may be connected to the organic light-emitting diode (OLED). The sixth transistor (TR6) may transmit the driving current (ID) to the organic light-emitting diode (OLED) in response to the light emission control signal (EM).

[0065] The seventh transistor (TR7) may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a third gate signal (GB). The first terminal may be connected to the organic light-emitting diode (OLED). The second terminal may receive the initialization voltage (VINT). The seventh transistor (TR7) may initialize the organic light-emitting diode (OLED).

[0066] The storage capacitor (CST) may include a first terminal and a second terminal. The first terminal may receive the high power supply voltage (ELVDD). The second terminal may be connected to the gate terminal of the first transistor (TR1).

[0067] The above organic light-emitting diode (OLED) may include a first terminal and a second terminal. The first terminal may be connected to the sixth transistor (TR6). The second terminal may be provided with a low power supply voltage (ELVSS). The organic light-emitting diode (OLED) may emit light based on the driving current (ID).

[0068] FIG. 4 is an enlarged view for explaining a display device according to an embodiment of the present invention, FIG. 5 is a cross-sectional view for explaining the display device of FIG. 4, and FIG. 6 is a cross-sectional view for explaining the display device of FIG. 4. For example, FIG. 4 is an enlarged view of area A of FIG. 1.

[0069] Referring to FIGS. 1 and 4, a display device (1100) according to one embodiment of the present invention may include a data driving unit (DDV), a first data line (DL1), a bypass data line (BL), and a second data line (DL2). The bypass data line (BL) may include a first bypass vertical line (BVL1), a first bypass horizontal line (BHL1), a second bypass vertical line (BVL2), and a second bypass horizontal line (BHL2).

[0070] The first data line (DL1) is placed on the substrate (SUB) and may overlap with the first display area (DA1). The first data line (DL1) may extend in a second direction (D2) that intersects the first direction (D1). The first data line (DL1) may electrically connect the data driver (DDV) and the first pixel (PX1). The first data line (DL1) may transmit a first data voltage to the first pixel (PX1).

[0071] In one embodiment, the first bypass vertical wiring (BVL1) is placed on the substrate (SUB) and may overlap with the first display area (DA1). The first bypass vertical wiring (BVL1) may extend in the second direction (D2). The first bypass vertical wiring (BVL1) may electrically connect the data driver (DDV) and the first bypass horizontal wiring (BHL1). For example, the first bypass vertical wiring (BVL1) may contact the first bypass horizontal wiring (BHL1) through a first contact hole (CNT1).

[0072] In one embodiment, the first bypass horizontal wiring (BHL1) is disposed on the substrate (SUB) and may overlap with the first display area (DA1), the first non-display area (NDA1), and the second display area (DA2). The first bypass horizontal wiring (BHL1) may extend in the first direction (D1). The first bypass horizontal wiring (BHL1) may electrically connect the first bypass vertical wiring (BVL1) and the second bypass vertical wiring (BVL2). For example, the first bypass horizontal wiring (BHL1) may contact the second bypass vertical wiring (BVL2) through a second contact hole (CNT2).

[0073] In one embodiment, the second bypass vertical wiring (BVL2) is disposed on the substrate (SUB) and may overlap with the second display area (DA2). The second bypass vertical wiring (BVL2) may extend in the second direction (D2). The second bypass vertical wiring (BVL2) may electrically connect the first bypass horizontal wiring (BHL1) and the second bypass horizontal wiring (BHL2). For example, the second bypass vertical wiring (BVL2) may contact the first bypass horizontal wiring (BHL1) through the second contact hole (CNT2).

[0074] In one embodiment, the second bypass horizontal wiring (BHL2) is placed on the substrate (SUB) and may overlap with the second display area (DA2). The second bypass horizontal wiring (BHL2) may extend in the first direction (D1). The second bypass horizontal wiring (BHL2) may electrically connect the second bypass vertical wiring (BVL2) and the second data wiring (DL2).

[0075] The second data wiring (DL2) is placed on the substrate (SUB) and can overlap with the second display area (DA2). The second data wiring (DL2) can extend in the second direction (D2).

[0076] The second data line (DL2) can transmit a second data voltage to the second pixel (PX2). In one embodiment, the second data voltage output from the data driver (DDV) can be transmitted to the second data line (DL2) through the bypass data line (BL).

[0077] As the bypass data wiring (BL) is formed in the first display area (DA1), the first non-display area (NDA1), and the second display area (DA2), fan-out wiring may not be formed in the display device (1100). Accordingly, the dead space of the display device (1100) may be reduced.

[0078] In one embodiment, the first data line (DL1), the second data line (DL2), the first bypass vertical line (BVL1), and the second bypass vertical line (BVL2) may be formed together. The first bypass horizontal line (BHL1) and the second bypass horizontal line (BHL2) may be formed together. The first bypass horizontal line (BHL1) and the second bypass horizontal line (BHL2) may be formed below the first bypass vertical line (BVL1) and the second bypass vertical line (BVL2). However, the present invention is not limited thereto. For example, the first bypass horizontal line (BHL1) and the second bypass horizontal line (BHL2) may be formed above the first bypass vertical line (BVL1) and the second bypass vertical line (BVL2).

[0079] In one embodiment, the first contact hole (CNT1) may be formed in the first display area (DA1), and the second contact hole (CNT2) may be formed in the second display area (DA2).

[0080] Referring to FIGS. 4 and 5, the transistor layer (TL) may include a buffer layer (BFR), a first inorganic insulating layer (IL1), a second inorganic insulating layer (IL2), a first organic insulating layer (OL1), a second organic insulating layer (OL2), a transistor (TR), the first bypass horizontal wiring (BHL1), the first bypass vertical wiring (BVL1), and the first data wiring (DL1). The transistor (TR) may include an active pattern (ACT), a gate electrode (GAT), a first connection electrode (CE1), and a second connection electrode (CE2).

[0081] The buffer layer (BFR) may be disposed on the substrate (SUB). In one embodiment, the buffer layer (BFR) may be formed of an insulating material. Examples of materials that may be used for the buffer layer (BFR) include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0082] The above active pattern (ACT) may be disposed on the buffer layer (BFR). In one embodiment, the active pattern (ACT) may be formed of an oxide semiconductor, a silicon semiconductor, etc.

[0083] The first inorganic insulating layer (IL1) is disposed on the buffer layer (BFR) and can cover the active pattern (ACT). In one embodiment, the first inorganic insulating layer (IL1) may be formed of an insulating material. Examples of materials that can be used as the first inorganic insulating layer (IL1) include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0084] The gate electrode (GAT) may be disposed on the first inorganic insulating layer (IL1) and may overlap with the active pattern (ACT). In one embodiment, the gate electrode (GAT) may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used as the gate electrode (GAT) include silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other.

[0085] The second inorganic insulating layer (IL2) is disposed on the first inorganic insulating layer (IL1) and can cover the gate electrode (GAT). In one embodiment, the second inorganic insulating layer (IL2) may be formed of an insulating material. Examples of materials that can be used as the second inorganic insulating layer (IL2) include silicon oxide, silicon nitride, silicon oxynitride, etc. These may be used alone or in combination with each other.

[0086] The first connecting electrode (CE1) and the second connecting electrode (CE2) may be disposed on the second inorganic insulating layer (IL2) and may come into contact with the active pattern (ACT). In one embodiment, the first connecting electrode (CE1) and the second connecting electrode (CE2) may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used as the first connecting electrode (CE1) and the second connecting electrode (CE2) include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. In one embodiment, the first connecting electrode (CE1) and the second connecting electrode (CE2) may have a Ti / Al / Ti structure including aluminum.

[0087] The first bypass horizontal wiring (BHL1) may be disposed on the second inorganic insulating layer (IL2). In one embodiment, the first bypass horizontal wiring (BHL1) may be formed together with the first connecting electrode (CE1) and the second connecting electrode (CE2). Examples of materials that may be used as the first bypass horizontal wiring (BHL1) include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. In one embodiment, the first bypass horizontal wiring (BHL1) may have a Ti / Al / Ti structure including aluminum.

[0088] The first organic insulating layer (OL1) is disposed on the second inorganic insulating layer (IL1) and can cover the first connecting electrode (CE1), the second connecting electrode (CE2), and the first bypass horizontal wiring (BHL1). In one embodiment, the first organic insulating layer (OL1) may be formed of an insulating material. Examples of materials that can be used as the first organic insulating layer (OL1) include photoresist, polyacrylic resin, polyimide resin, acrylic resin, etc. These may be used alone or in combination with each other.

[0089] The first data wiring (DL1) may be disposed on the first organic insulating layer (OL1) and may come into contact with the first connecting electrode (CE1). The first connecting electrode (CE1) may electrically connect the first data wiring (DL1) and the active pattern (ACT). In one embodiment, the first data wiring (DL1) may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used as the first data wiring (DL1) include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. In one embodiment, the first data wiring (DL1) may have a Ti / Al / Ti structure containing aluminum.

[0090] The third connecting electrode (CE3) can be placed on the first organic insulating layer (OL1) and can be in contact with the second connecting electrode (CE2).

[0091] The first bypass vertical wiring (BVL1) may be disposed on the first organic insulating layer (OL1) and may be in contact with the first bypass horizontal wiring (BHL1) through the first contact hole (CNT1). In one embodiment, the first bypass vertical wiring (BVL1) may be formed together with the first data wiring (DL1). Examples of materials that can be used as the first bypass vertical wiring (BVL1) include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other. In one embodiment, the first bypass vertical wiring (BVL1) may have a Ti / Al / Ti structure including aluminum.

[0092] The second organic insulating layer (OL2) is disposed on the first organic insulating layer (OL1) and can cover the first data wiring (DL1) and the first bypass vertical wiring (BVL1). In one embodiment, the second organic insulating layer (OL2) may be formed of an insulating material. Examples of materials that can be used as the second organic insulating layer (OL2) include photoresist, polyacrylic resin, polyimide resin, acrylic resin, etc. These may be used alone or in combination with each other.

[0093] The first electrode (ADE) may be disposed on the second organic insulating layer (OL2) and may be in contact with the third connecting electrode (CE3). The pixel defining film (PDL) may be disposed on the second organic insulating layer (OL2) and may include an opening that exposes the first electrode (ADE). The light-emitting layer (EL) may be disposed on the first electrode (ADE). The second electrode (CTE) may be disposed on the light-emitting layer (EL).

[0094] The above encapsulation layer (ENC) may be disposed on the second electrode (CTE). The encapsulation layer (ENC) can prevent moisture and air from penetrating into the light-emitting layer (EL). In one embodiment, the encapsulation layer (ENC) may have a structure in which an inorganic insulating layer, an organic insulating layer, and an inorganic insulating layer are stacked in sequence.

[0095] The sensing layer (SL) may include a sensing electrode (SE) and a sensing insulating layer (SIL). The sensing electrode (SE) may be disposed on the encapsulation layer (ENC). A sensing voltage may be applied to the sensing electrode (SE). The sensing insulating layer (SIL) may be disposed on the encapsulation layer (ENC) and may cover the sensing electrode (SE).

[0096] The polarization layer (POL) may be disposed on the sensing layer (SL), the window (WIN) may be disposed on the polarization layer (POL), and the protective layer (PL) may be disposed on the window (WIN). However, the polarization layer (POL), the window (WIN), and the protective layer (PL) may be substantially the same as the polarization layer (POL), the window (WIN), and the protective layer (PL) described with reference to FIG. 2. Additionally, the polarization layer (POL) may be omitted.

[0097] Referring to FIGS. 4 and 6, the first bypass vertical wiring (BVL1) may contact the first bypass horizontal wiring (BHL1) through the first contact hole (CNT1), and the second bypass vertical wiring (BVL2) may contact the first bypass horizontal wiring (BHL1) through the second contact hole (CNT2). The bending protection layer (BPL) and the light-blocking layer (BM) may overlap with the first non-display area (NDA1).

[0098] FIGS. 7 to 11 are cross-sectional views for explaining a method of manufacturing the display device of FIG. 4.

[0099] Referring to FIG. 7, contact holes may be formed in the buffer layer (BFR), the first inorganic insulating layer (IL1), and the second inorganic insulating layer (IL2). The buffer layer (BFR), the first inorganic insulating layer (IL1), and the second inorganic insulating layer (IL2) that overlap with the first non-display area (NDA1) may be removed.

[0100] Referring to FIG. 8, the first bypass horizontal wiring (BHL1), the first connecting electrode (CE1), and the second connecting electrode (CE2) may be formed on the second inorganic insulating layer (IL2).

[0101] Referring to FIG. 9, the first organic insulating layer (OL1) is formed, and a contact hole may be formed in the first organic insulating layer (OL1).

[0102] Referring to FIG. 10, the first bypass vertical wiring (BVL1), the second bypass vertical wiring (BVL2), the first data wiring (DL1), and the third connecting electrode (CE3) may be formed on the first organic insulating layer (OL1). The first bypass vertical wiring (BVL1) and the second bypass vertical wiring (BVL2) may be connected to the first bypass horizontal wiring (BHL1).

[0103] Referring to FIG. 11, the bending protection layer (BPL) and the light-blocking layer (BM) may overlap with the first non-display area (NDA1). The first inorganic insulating layer (IL1), the second inorganic insulating layer (IL2), the light-emitting layer (EL), and the encapsulation layer (ENC) may not overlap with the first non-display area (NDA1).

[0104] FIG. 12 is an enlarged view for explaining a display device according to another embodiment of the present invention, and FIG. 13 is a cross-sectional view for explaining the display device of FIG. 12. For example, FIG. 12 is an enlarged view of area B of FIG. 1, and FIG. 13 is a cross-sectional view cut along line II' of FIG. 12.

[0105] Referring to FIGS. 1 and 12, a display device (1200) according to another embodiment of the present invention may include a first high power wiring (VDDL1), a high power bridge wiring (BDDL), a second high power wiring (VDDL2), a first gate wiring (GL1), a gate bridge wiring (BGL), a second gate wiring (GL2), a first light-emitting wiring (EML1), a light-emitting bridge wiring (BEML), a second light-emitting wiring (EML2), a first low power wiring (VSSL1), a low power bridge wiring (BSSL), a second low power wiring (VSSL2), and a vertical wiring (VL). The vertical wiring (VL) may include a first vertical wiring (VL1) and a second vertical wiring (VL2).

[0106] The first high power wiring (VDDL1) is placed on the substrate (SUB) and can overlap with the first display area (DA1). The first high power wiring (VDDL1) can be extended in the first direction (D1). The high power voltage (ELVDD) described with reference to FIG. 3 can be applied to the first high power wiring (VDDL1).

[0107] The high power bridge wiring (BDDL) is placed on the substrate (SUB) and may overlap with the first non-display area (NDA1). The high power bridge wiring (BDDL) may extend in the first direction (D1). The high power bridge wiring (BDDL) may be connected to the first high power wiring (VDDL1) through a contact hole.

[0108] The second high power wiring (VDDL2) is placed on the substrate (SUB) and can overlap with the second display area (DA2). The second high power wiring (VDDL2) can be extended in the first direction (D1). The second high power wiring (VDDL2) can be connected to the high power bridge wiring (BDDL) through a contact hole.

[0109] The first gate wiring (GL1) is placed on the substrate (SUB) and may overlap with the first display area (DA1). The first gate wiring (GL1) may extend in the first direction (D1). The first gate signal (GW) described with reference to FIG. 3 may be applied to the first gate wiring (GL1).

[0110] The gate bridge wiring (BGL) is placed on the substrate (SUB) and may overlap with the first non-display area (NDA1). The gate bridge wiring (BGL) may extend in the first direction (D1). The gate bridge wiring (BGL) may be connected to the first gate wiring (GL1) through a contact hole.

[0111] The second gate wiring (GL2) is placed on the substrate (SUB) and can overlap with the second display area (DA2). The second gate wiring (GL2) can extend in the first direction (D1). The second gate wiring (GL2) can be connected to the gate bridge wiring (BGL) through a contact hole.

[0112] The first light-emitting wire (EML1) is placed on the substrate (SUB) and may overlap with the first display area (DA1). The first light-emitting wire (EML1) may extend in the first direction (D1). The light-emitting control signal (EM) described with reference to FIG. 3 may be applied to the first light-emitting wire (EML1).

[0113] The light-emitting bridge wiring (BEML) is placed on the substrate (SUB) and may overlap with the first non-display area (NDA1). The light-emitting bridge wiring (BEML) may extend in the first direction (D1). The light-emitting bridge wiring (BEML) may be connected to the first light-emitting wiring (EML1) through a contact hole.

[0114] The second light-emitting wiring (EML2) is placed on the substrate (SUB) and can overlap with the second display area (DA2). The second light-emitting wiring (EML2) can extend in the first direction (D1). The second light-emitting wiring (EML2) can be connected to the light-emitting bridge wiring (BEML) through a contact hole.

[0115] The first low power wiring (VSSL1) is placed on the substrate (SUB) and may overlap with the first display area (DA1). The first low power wiring (VSSL1) may extend in the first direction (D1). The low power voltage (ELVSS) described with reference to FIG. 3 may be applied to the first low power wiring (VSSL1).

[0116] The low power bridge wiring (BSSL) is placed on the substrate (SUB) and may overlap with the first non-display area (NDA1). The low power bridge wiring (BSSL) may extend in the first direction (D1). The low power bridge wiring (BSSL) may be connected to the first low power wiring (VSSL1) through a contact hole.

[0117] The second low power wiring (VSSL2) is placed on the substrate (SUB) and can overlap with the second display area (DA2). The second low power wiring (VSSL2) can be extended in the first direction (D1). The second low power wiring (VSSL2) can be connected to the low power bridge wiring (BSSL) through a contact hole.

[0118] The first vertical wiring (VL1) and the second vertical wiring (VL2) are placed on the substrate (SUB) and may overlap with the first non-display area (NDA1). The first vertical wiring (VL1) and the second vertical wiring (VL2) may extend in the second direction (D2). In one embodiment, a power supply voltage may be applied to the vertical wiring (VL). The power supply voltage may include the high power supply voltage (ELVDD) and the low power supply voltage (ELVSS). For example, the high power supply voltage (ELVDD) may be applied to the first vertical wiring (VL1), and the low power supply voltage (ELVSS) may be applied to the second vertical wiring (VL2).

[0119] Referring to FIGS. 12 and 13, the first gate wiring (GL1) and the second gate wiring (GL2) may be disposed on the first inorganic insulating layer (IL1). In one embodiment, the first gate wiring (GL1) and the second gate wiring (GL2) may be formed from a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used for the first gate wiring (GL1) and the second gate wiring (GL2) include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0120] In one embodiment, the buffer layer (BFR), the first inorganic insulating layer (IL1), and the second inorganic insulating layer (IL2) overlapping with the first non-display area (NDA1) are removed, and the gate bridge wiring (BGL) can be disposed on the substrate (SUB). The gate bridge wiring (BGL) can be connected to the first gate wiring (GL1) and the second gate wiring (GL2). In one embodiment, the gate bridge wiring (BGL) can be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used as the gate bridge wiring (BGL) include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. In one embodiment, the gate bridge wiring (BGL) may have a Ti / Al / Ti structure containing aluminum.

[0121] The first vertical wiring (VL1) and the second vertical wiring (VL2) are disposed on the first organic insulating layer (OL1) and may overlap with the first non-display area (NDA1). In one embodiment, the first vertical wiring (VL1) and the second vertical wiring (VL2) may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used for the first vertical wiring (VL1) and the second vertical wiring (VL2) include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. In one embodiment, the first vertical wiring (VL1) and the second vertical wiring (VL2) may have a Ti / Al / Ti structure containing aluminum.

[0122] FIG. 14 is an enlarged view for explaining a display device according to another embodiment of the present invention, and FIG. 15 is a cross-sectional view for explaining the display device of FIG. 14. For example, FIG. 14 is an enlarged view of area B of FIG. 1, and FIG. 15 is a cross-sectional view cut along line II-II' of FIG. 14.

[0123] Referring to FIGS. 1 and 14, a display device (1300) according to another embodiment of the present invention may include the first high power wiring (VDDL1), the high power bridge wiring (BDDL), the second high power wiring (VDDL2), the first gate wiring (GL1), the gate bridge wiring (BGL), the second gate wiring (GL2), the first light-emitting wiring (EML1), the light-emitting bridge wiring (BEML), the second light-emitting wiring (EML2), the first low power wiring (VSSL1), the low power bridge wiring (BSSL), the second low power wiring (VSSL2), a shielding pattern (SDL), and a vertical wiring (VL). The vertical wiring (VL) may include a first vertical wiring (VL1) and a second vertical wiring (VL2).

[0124] However, the display device (1300) may be substantially the same as the display device (1200) described with reference to FIG. 12, except for the shielding pattern (SDL), the first vertical wiring (VL1), and the second vertical wiring (VL2).

[0125] The shielding pattern (SDL) is disposed on the substrate (SUB) and may overlap with the first non-display area (NDA1). The shielding pattern (SDL) may extend in the second direction (D2). In one embodiment, the shielding pattern (SDL) may shield between the first vertical wiring (VL1) and the bridge wiring (e.g., the high power bridge wiring (BDDL), the gate bridge wiring (BGL), the light-emitting bridge wiring (BEML), and / or the low power bridge wiring (BSSL)). Additionally, the shielding pattern (SDL) may shield between the second vertical wiring (VL2) and the bridge wiring. For example, a positive voltage may be applied to the shielding pattern (SDL), or the shielding pattern (SDL) may be electrically floating.

[0126] The first vertical wiring (VL1) and the second vertical wiring (VL2) are disposed on the substrate (SUB) and may overlap with the first non-display area (NDA1). The first vertical wiring (VL1) and the second vertical wiring (VL2) may extend in the second direction (D2). In one embodiment, the sensing voltage may be applied to the first vertical wiring (VL1) and the second vertical wiring (VL2). Additionally, at least one horizontal wiring intersecting the first and second vertical wirings (VL2) may be further formed in the first non-display area (NDA1).

[0127] Referring to FIGS. 14 and 15, the shielding pattern (SDL) may be disposed on the first organic insulating layer (OL1) and may overlap with the first non-display area (NDA1). In one embodiment, the shielding pattern (SDL) may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used as the shielding pattern (SDL) include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. In one embodiment, the shielding pattern (SDL) may have a Ti / Al / Ti structure including aluminum.

[0128] The first vertical wiring (VL1) and the second vertical wiring (VL2) may be disposed on the bending protection layer (BPL) and may overlap with the first non-display area (NDA1). In one embodiment, the first vertical wiring (VL1) and the second vertical wiring (VL2) may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that can be used for the first vertical wiring (VL1) and the second vertical wiring (VL2) include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. In one embodiment, the first vertical wiring (VL1) and the second vertical wiring (VL2) may have a Ti / Al / Ti structure containing aluminum.

[0129] FIG. 16 is an enlarged view for explaining a display device according to another embodiment of the present invention, and FIG. 17 is a cross-sectional view for explaining the display device of FIG. 16. For example, FIG. 16 is an enlarged view of area B of FIG. 1, and FIG. 17 is a cross-sectional view cut along line III-III' of FIG. 16.

[0130] Referring to FIGS. 1 and 16, a display device (1400) according to another embodiment of the present invention may include the first high power wiring (VDDL1), the high power bridge wiring (BDDL), the second high power wiring (VDDL2), the first gate wiring (GL1), the gate bridge wiring (BGL), the second gate wiring (GL2), the first light-emitting wiring (EML1), the light-emitting bridge wiring (BEML), the second light-emitting wiring (EML2), the first low power wiring (VSSL1), the low power bridge wiring (BSSL), the second low power wiring (VSSL2), and a driving unit (DV).

[0131] However, the display device (1400) may be substantially the same as the display device (1300) described with reference to FIG. 14, except for the driving unit (DV).

[0132] The driving unit (DV) is disposed on the substrate (SUB) and may overlap with the first non-display area (NDA1). In one embodiment, the driving unit (DV) may be a gate driving unit that generates gate signals (e.g., the first gate signal (GW), the second gate signal (GI), and the third gate signal (GI)). The driving unit (GV) may generate the gate signals and supply them to the first gate wiring (GL1) and the second gate wiring (GL2).

[0133] As illustrated in FIGS. 16 and 17, the present specification describes the case where the driving unit (GV) is the gate driving unit, but the present invention is not limited thereto. In other embodiments, the driving unit (DV) may be a light-emitting driving unit that generates the light-emitting control signal (EM).

[0134] Referring to FIGS. 16 and 17, the driving unit (DV) may include at least one driving transistor (DTR). The driving transistor (DTR) may overlap with the first non-display area (NDA1). The driving transistor (DTR) may generate the gate signal and supply it to the first gate wiring (GL1) and the second gate wiring (GL2). The driving transistor (DTR) may include a driving active pattern (DACT), a driving gate electrode (DGAT), a first driving connection electrode (DCE1), and a second driving connection electrode (DCE2).

[0135] FIG. 18 is a cross-sectional view illustrating a display device according to another embodiment of the present invention.

[0136] Referring to FIG. 18, a display device (1500) according to another embodiment of the present invention may include the first gate wiring (GL1), the second gate wiring (GL2), the driving transistor (DTR), the shielding pattern (SDL), the first vertical wiring (VL1), and the second vertical wiring (VL2).

[0137] However, the display device (1500) may be substantially the same as the display device (1400) described with reference to FIG. 17, except for the shielding pattern (SDL), the first vertical wiring (VL1), and the second vertical wiring (VL2).

[0138] The shielding pattern (SDL) is placed on the driving transistor (DTR) and may overlap with the first non-display area (NDA1). The shielding pattern (SDL) may shield between the first vertical wiring (VL1) (or the second vertical wiring (VL2)) and the driving transistor (DTR).

[0139] The first vertical wiring (VL1) and the second vertical wiring (VL2) are disposed on the bending protection layer (BPL) and may overlap with the first non-display area (NDA1). The first vertical wiring (VL1) and the second vertical wiring (VL2) may extend in the second direction (D2). In one embodiment, the sensing voltage may be applied to the first vertical wiring (VL1) and the second vertical wiring (VL2). Additionally, at least one horizontal wiring intersecting the first and second vertical wirings (VL2) may be further formed in the first non-display area (NDA1).

[0140] Although the foregoing description refers to exemplary embodiments of the present invention, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as set forth in the following claims. Industrial applicability

[0141] The present invention can be applied to display devices. For example, the present invention can be applied to display devices such as high-resolution smartphones, mobile phones, smartpads, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc.

[0142] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Explanation of the symbols

[0143] 1000, 1100, 1200, 1300, 1400, 1500: Display device SUB: Substrate DA1: First display area NDA1: 1st Non-Display Area DL1: 1st Data Wiring BL: Bypass data wiring BVL1: 1st bypass vertical wiring BHL1: 1st Bypass Horizontal Wiring BGL: Gate Bridge Wiring VL1: 1st vertical wiring SDL: Shielding pattern DTR: Driving transistor

Claims

Claim 1 A display device comprising: a substrate including a first display area, a non-display area bent from the first display area, and a second display area adjacent to the non-display area; a first data line disposed on the first display area of ​​the substrate and connected to a data driving unit; a second data line disposed on the second display area of ​​the substrate; a bypass data line disposed on the non-display area of ​​the substrate and electrically connecting the data driving unit and the second data line; an active pattern disposed on the first display area of ​​the substrate; a gate electrode disposed on the active pattern; and a connecting electrode disposed between the gate electrode and the first data line and connecting the active pattern and the first data line, wherein the bypass data line includes a bypass horizontal line extending in a first direction, and the bypass horizontal line is formed together with the connecting electrode. Claim 2 A display device according to claim 1, wherein the second display area is adjacent to the first display area in the first direction. Claim 3 A display device according to claim 2, further comprising: a first bypass vertical line extending in a second direction intersecting the first direction, which is disposed on the first display area; and a second bypass vertical line extending in the second direction, which is disposed on the second display area. Claim 4 A display device according to claim 3, wherein the first bypass vertical wiring and the bypass horizontal wiring are connected through a first contact hole in the first display area, and the second bypass vertical wiring and the bypass horizontal wiring are connected through a second contact hole in the second display area. Claim 5 A display device according to claim 3, wherein the first bypass vertical wiring and the second bypass vertical wiring are formed together with the first data wiring. Claim 6 A display device according to claim 1, wherein the bypass data wiring comprises aluminum. Claim 7 A display device according to claim 1, characterized in that a first pixel electrically connected to the first data wiring is disposed in the first display area, and a second pixel electrically connected to the second data wiring is disposed in the second display area. Claim 8 A display device according to claim 7, characterized in that pixels are not placed in the non-display area. Claim 9 A display device characterized by further including a light-blocking layer disposed on the non-display area of ​​the substrate in claim 7. Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete

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