Channel-Stacked Gate-All-Around Ferroelectric Transistor and Method of Fabrication Thereof

Abstract

The present invention comprises: a plurality of channel layers vertically stacked on a semiconductor substrate; a gate structure formed to surround all sides of the channel layers; and source lines and drain lines independently connected to each of the channel layers and capable of individual control, wherein an interlayer insulating film for electrical insulation is provided between the channel layers.

Description

Technology Field

[0001] The present invention relates to a channel stacked gate-all-around ferroelectric transistor and a method for manufacturing the same, and in particular to a channel stacked gate-all-around ferroelectric transistor having features such as high integration, high speed, and non-volatility, and a method for manufacturing the same. Background Technology

[0002] The recent rapid advancement of artificial intelligence (AI) technology has increased the need for next-generation memory devices capable of high-speed processing of large volumes of data. Charge trap flash (CTF), a currently commercialized non-volatile memory, uses a method of storing information by injecting charge into the charge trap layer of the gate thin film. However, CTF suffers from high write / erase voltage (±10 V), slow operating speed (~200 μsec), and low cycling endurance (< 10 5 It has limitations such as ), so it has limitations as a next-generation memory device.

[0003] Ferroelectric field-effect transistors (FeFETs) are attracting attention as an alternative to solve these problems. FeFETs are memory devices that utilize the remnant polarization characteristics of ferroelectric thin films, offering lower write voltage (< 5 V), faster operating speed (~10 nsec), and superior endurance characteristics (~10 nsec) compared to CTFs. 7 It has ). In particular, when using HfO2-based ferroelectric thin films, ferroelectricity can be realized even at thicknesses of 10 nm or less, and high compatibility with CMOS processes makes it suitable for next-generation memory applications such as compute express link (CXL) and storage class memory (SCM).

[0004] However, just like CTF, FeFETs also face issues such as leakage current, interference, and disturbance during the miniaturization process. While these problems can be solved through stacked structures such as the 3D NAND array of CTF, existing stacked structures have limitations in that the operating speed is reduced due to the lower charge mobility compared to single-crystal silicon, as polycrystalline silicon is used as the channel material.

[0005] Therefore, to realize next-generation memory capable of high integration, high speed, and low voltage operation, it is necessary to develop a new structure of FeFET that is based on a single-crystal silicon channel and capable of three-dimensional stacking. In particular, a technical solution is required to improve the electric field control of the gate and ensure independent operation of each layer. The problem to be solved

[0006] The present invention aims to provide a channel-stacked gate-all-around ferroelectric transistor capable of high-speed operation and a method for manufacturing the same by providing a gate-all-around structure based on a single-crystal silicon channel and a stacked ferroelectric transistor capable of independent control for each layer, thereby solving leakage current and interference problems associated with high integration. means of solving the problem

[0007] To achieve the above objective, the present invention comprises: a plurality of channel layers vertically stacked on a semiconductor substrate; a gate structure formed to surround all sides of the channel layers; and source lines and drain lines independently connected to each of the channel layers and capable of individual control, wherein an interlayer insulating film for electrical insulation is provided between the channel layers.

[0008] Preferably, the gate structure may include a structure in which an oxide insulating layer, a ferroelectric layer, and a metal gate electrode are sequentially stacked.

[0009] Preferably, the ferroelectric layer may include an HfO2-based ferroelectric material or a ferroelectric material having a perovskite structure.

[0010] Preferably, the channel layer can be formed in the form of a nanowire or a nanosheet.

[0011] Preferably, the channel layer can be formed as a junctionless structure in which the source region and the drain region have the same doping concentration.

[0012] Preferably, the transistor is 8F 2 Three or more channel layers can be stacked per unit area.

[0013] Preferably, the channel layer may be composed of single-crystal silicon or an oxide semiconductor material, and the oxide semiconductor material may be any one of ZnO, In2O3, and IGZO.

[0014] In addition, the present invention is further characterized by comprising the steps of: alternately stacking a silicon layer and a silicon germanium layer on a semiconductor substrate; defining a channel region by patterning the stacked structure; selectively removing the silicon germanium layer to form a plurality of single-crystal silicon channel layers; forming an interlayer insulating film between the channel layers; forming source and drain regions on both sides of the channel layers, respectively, while connecting independent source and drain lines for each channel layer; and sequentially forming a gate insulating layer, a ferroelectric layer, and a metal gate electrode to surround all sides of the channel layers. Effects of the invention

[0015] According to the present invention, based on the high charge mobility of a single-crystal silicon channel and the excellent electric field control characteristics of a gate-all-around structure, 8F 2There is an advantage in that it can realize next-generation memory capable of high integration, high speed, and low power operation by providing a vertical stacking structure capable of integrating three or more elements per area. Brief explanation of the drawing

[0016] FIG. 1 shows a schematic diagram of a channel stacked gate-all-around ferroelectric transistor according to an embodiment of the present invention. FIG. 2 shows a circuit diagram of a channel stacked gate-all-around ferroelectric transistor according to an embodiment of the present invention. FIGS. 3 and 4 show a flowchart of a gate-last process-based manufacturing method according to an embodiment of the present invention. Figure 5 shows a flowchart of a gate-first process and a manufacturing method based on a junctionless structure according to an embodiment of the present invention. Specific details for implementing the invention

[0017] The present invention will be described in detail below with reference to the contents described in the attached drawings. However, the present invention is not limited or restricted by exemplary embodiments. Identical reference numerals in each drawing indicate components that perform substantially the same function.

[0018] The purpose and effects of the present invention may be naturally understood or become clearer through the following description, and the purpose and effects of the present invention are not limited solely to the description below. Furthermore, in describing the present invention, if it is determined that a detailed description of known technology related to the present invention may unnecessarily obscure the essence of the present invention, such detailed description will be omitted.

[0019] The terms used in this invention are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the description of the invention, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0020] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0021] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which this invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this invention.

[0022] In interpreting the components, they are interpreted to include a margin of error even without a separate explicit indication. In the case of descriptions regarding temporal relationships, for example, where the temporal sequence is described using 'after,' 'following,' 'next,' 'before,' etc., cases that are not continuous are included unless 'immediately' or 'directly' is used.

[0023] Hereinafter, the technical configuration of the present invention will be described in detail with reference to the attached drawings.

[0024] FIG. 1 shows a schematic diagram of a channel stacked gate-all-around ferroelectric transistor (100) according to an embodiment of the present invention. Referring to FIG. 1, the channel stacked gate-all-around ferroelectric transistor (100) may include a plurality of channel layers (120), a gate structure (130), a source line (141), and a drain line (142).

[0025] The left side of FIG. 1 shows a three-dimensional perspective view of a channel stacked gate-all-around ferroelectric transistor (100), the center shows a cross-sectional view in the A-A' direction, and the right side shows a cross-sectional view in the B-B' direction.

[0026] As can be seen in the perspective view, the channel stacked gate-all-around ferroelectric transistor (100) has a structure in which multiple channel layers are stacked vertically. Each channel layer is connected to independent source lines (SL1, SL2, SL3) and drain (bit) lines (BL1, BL2, BL3) so that individual control is possible. The central vertical structure represents a gate structure formed in common across all channel layers.

[0027] A cross-sectional view in the AA' direction shows the vertical structure of the gate structure. Multiple channel layers formed of single-crystal silicon (Si) are vertically stacked, and between them, a SiO2 insulating film and a ferroelectric layer are sequentially formed. A metal gate electrode (TiN gate) is located at the top.

[0028] The cross-sectional view in the BB' direction shows the horizontal structure of the device. Each channel layer consists of source, channel, and drain regions, and the channel region is completely surrounded by the gate structure (gate-all-around structure). An interlayer insulating film of SiO2 is formed between the stacked source and drain lines to prevent electrical interference between the layers. The gate structure has a structure in which an oxide insulating layer, a ferroelectric layer, and a metal gate electrode are sequentially stacked.

[0029] FIG. 2 shows a circuit diagram of a channel stacked gate-all-around ferroelectric transistor (100) according to an embodiment of the present invention. The left side of FIG. 2 shows an array structure of a channel stacked gate-all-around ferroelectric transistor (100), and the right side shows a structure of a unit device.

[0030] Looking at the array structure, the word lines (WL1–WL6) are arranged horizontally, while the source lines (SL) and drain lines (BL) are arranged vertically. The source and drain lines are each grouped into sets of three and are numbered sequentially, as indicated by (1-3), (4-6), and (7-9). This structure is 8F 2 It enables the integration of multiple transistors in a unit area.

[0031] On the right side of the drawing, an enlarged view of the area indicated by the dotted line is shown. This illustrates the structure of the unit device and represents a structure in which three ferroelectric transistors (FeFET (1), FeFET (2), FeFET (3)) are stacked vertically. Each transistor is connected to an independent source line and drain line, allowing for individual control.

[0032] The channel stacked gate-all-around ferroelectric transistor (100) is 8F 2Three or more channel layers can be stacked per unit area. Referring to Fig. 2, dimensions representing the cell area are indicated, showing sizes based on the minimum line width (F), as indicated by 4F and 2F. Through this, 8F 2 It can be seen that three transistors can be integrated per unit area. This signifies an integration density improvement of more than three times compared to a planar structure. This array structure enables high integration, and efficient memory operation is possible as transistors in each layer can be controlled independently. In particular, the orthogonal array structure of the word line and drain line provides compatibility with general memory arrays and facilitates connection with peripheral circuits. The layer-by-layer structure of the array is 8F 2 Not limited to, and 6F 2 It may include structures, etc.

[0033] The program (PGM) and erase (ERS) operations of the channel stacked gate-all-around ferroelectric transistor (100) are performed on the device at a gate-to-source voltage (V) greater than a specific value. GS This can be performed by applying ) to change the polarization characteristics of the ferroelectric material configured in the gate thin film. In other words, to implement independent memory operation, independent V for each layer GS Authorization must be possible.

[0034] Therefore, the channel stacked gate-all-around ferroelectric transistor (100) has independent V layers per layer. GS To enable application, a structure can be formed that shares a single metal gate and has independent source and drain lines connected. In this structure, although the same gate voltage is applied, the source / drain voltages applied per layer can be controlled, allowing for different V values ​​for each layer. GS Authorization is possible, enabling the implementation of independent memory operation.

[0035] The channel stacked gate-all-around ferroelectric transistor (100) may be a NOR array structure that shares a common source for each channel layer.

[0036] The channel layer (120) can be stacked vertically on the semiconductor substrate (110). The channel layer (120) may have a structure connected to independent drain lines (142) and source lines (141) for each layer. The substrate (110) may be an SOI substrate or a bulk Si substrate.

[0037] An interlayer insulating film for electrical insulation may be provided between the channel layers (120). An SiO2 insulating film is deposited between the stacking of the source line (141) and the drain line (142), so that independent voltage application and memory operation may be possible for each layer.

[0038] The channel layer (120) can be formed in the form of nanowires or nanosheets. Here, a nanowire refers to a structure in which the cross-section of the channel is cylindrical or elliptical, and a nanosheet refers to a structure in which the cross-section of the channel is rectangular or square. Such nanowire or nanosheet structures can be formed by selectively removing the SiGe layer from a stacked structure formed through a Si / SiGe epitaxy process. In another embodiment, the channel layer (120) can also be fabricated based on various stacked structures, such as polycrystalline silicon / oxide insulating film, rather than a Si / SiGe stacked structure.

[0039] Channel structures in the form of nanowires or nanosheets have the advantage of facilitating electric field control due to an increased surface area affected by the gate electric field. In particular, when combined with a gate-all-around structure, the gate electric field acts uniformly around the entire perimeter of the channel, effectively suppressing the short channel effect. Furthermore, nanowire or nanosheet structures allow for fine control of the channel thickness and width, facilitating the control of the transistor's threshold voltage, which can contribute to improving the reliability of memory devices.

[0040] The channel layer (120) may have a gate-all-around structure in which a gate thin film composed of a ferroelectric or oxide material surrounds four sides of a single-crystal silicon (Si) nanowire or nanosheet channel. The gate-all-around structure has superior gate gripping power compared to a two-dimensional planar structure, so all stacked Si channels can be effectively controlled.

[0041] The channel layer (120) can be formed as a junctionless structure in which the source region and the drain region have the same doping concentration. Unlike a conventional transistor in which the source and drain regions form a junction with different doping types or concentrations from the channel region, in a junctionless structure, the entire source, channel, and drain regions are doped with the same type and concentration.

[0042] Junctionless structures can fundamentally resolve problems caused by abrupt doping concentration gradients that occur in conventional junction structures. In particular, they can avoid issues such as doping non-uniformity, junction leakage current, and junction capacitance that arise as devices become miniaturized. Furthermore, from a manufacturing perspective, they offer the advantage of simplifying the process as complex ion implantation or heat treatment processes are unnecessary.

[0043] The non-bonded structure is particularly useful in the channel stacked structure of the present invention. Unlike conventional bonded structures that require precise control of doping concentration for each layer, all layers can be formed with the same doping concentration, making it easy to fabricate the stacked structure and minimizing variations in interlayer properties.

[0044] The channel layer (120) may be composed of single-crystal silicon or an oxide semiconductor material, and the oxide semiconductor material may be any one of ZnO, In2O3, or IGZO. The channel layer (120) is formed based on single-crystal silicon and has a very fast operating speed.

[0045] The gate structure (130) can be formed to surround all sides of the channel layer (120). The gate structure (130) is formed as a gate-all-around structure that surrounds all four sides of the channel layer (120), thereby effectively controlling leakage current. Accordingly, the transistor (100) according to the present invention can realize a highly integrated, high-speed, non-volatile memory device for the latest AI technology.

[0046] The gate structure (130) may include a structure in which an oxide insulating layer (131), a ferroelectric layer (132), and a metal gate electrode (133) are sequentially stacked.

[0047] The oxide insulating layer (131) may be composed of an antiferroelectric material (ZrO, t-phase HZO, PbZrO, etc.). The oxide insulating layer (131) may be composed of a charge trap layer (Si3N4, HfO2, AlN, etc.) or a phase change material (VO2, GST, etc.).

[0048] The ferroelectric layer (132) may include at least one of an HfO2-based ferroelectric material, a ferroelectric material having a perovskite structure, and a charge trap layer material (Si3N4, HfO2, AlN, etc.).

[0049] The gate structure (130) may have a stacked structure that is not a metal-ferroelectric-oxide-insulating-semiconductor (MFIS) structure but a metal-ferroelectric-metal-oxide-insulating-semiconductor (MFMIS) structure.

[0050] The source line (141) and drain line (142) may be independently connected to each channel layer to enable individual control. The source line (141) and drain line (142) may be injected with different types of dopants.

[0051] FIGS. 3 and 4 show a flowchart of a gate-last process-based manufacturing method according to an embodiment of the present invention. Referring to FIGS. 3 and 4, a method for manufacturing a channel-stacking gate-all-around ferroelectric transistor may include the steps of stacking, defining a channel region, forming a channel layer, forming an interlayer insulating film, connecting source and drain lines, and forming a gate structure.

[0052] As with conventional Charge Trap Flash (CTF) devices, FeFETs may experience issues such as leakage current, interference, and disturbance when undergoing continuous miniaturization for high-density memory. While these problems can be solved by introducing a stacked structure such as the 3D NAND array of CTFs, this requires the use of polycrystalline silicon, which has lower mobility compared to single-crystal silicon, which can lead to a degradation in operating speed.

[0053] The method for fabricating a channel-stacked gate-all-around ferroelectric transistor utilized epitaxy process technology, which involves growing a single-crystal silicon thin film on a silicon substrate, to form all stacked channels from single-crystal silicon. After stacking silicon and silicon germanium using epitaxy technology, the silicon germanium in the channel region was selectively removed to realize a single-crystal silicon-based channel stacking structure. Additionally, the method utilized atomic layer deposition (ALD) technology to form a GAA structure in which the gate thin film covers all four sides of the channel. ALD is a deposition technology with excellent step coverage, and by utilizing this, the gate thin film was evenly deposited on all four sides of the channel to form the GAA structure.

[0054] The method for fabricating channel-stacked gate-all-around ferroelectric transistors was designed based on silicon-on-insulator (SOI) wafers, but it can also be implemented on bulk wafers.

[0055] The stacking step may alternately stack silicon layers and silicon germanium layers on a semiconductor substrate. The step of defining the channel region may define the channel region by patterning the stacked structure.

[0056] The step of forming channel layers may form multiple single-crystal silicon channel layers by selectively removing a silicon germanium layer. The step of forming interlayer insulating films may form interlayer insulating films between channel layers.

[0057] The step of connecting the source and drain lines involves forming source and drain regions on both sides of the channel layer, respectively, and connecting independent source and drain lines for each channel layer.

[0058] FIG. 5 shows a flowchart of a gate-first process and a manufacturing method based on a junctionless structure according to an embodiment of the present invention. Referring to FIG. 5, the gate-first process and the manufacturing method based on a junctionless structure allow for easy fabrication of a transistor according to the present invention with fewer process steps compared to the gate last process of FIG. 3 and FIG. 4.

[0059] Hereinafter, a method for manufacturing a channel-stacking gate-all-around ferroelectric transistor will be described in detail with reference to FIGS. 3 to 5.

[0060] 1) Silicon / silicon germanium thin film stacking

[0061] A silicon / silicon germanium (Si / SiGe) thin film is deposited on a silicon substrate using epitaxy technology. The deposited silicon germanium thin film is used as a sacrificial layer for silicon nanowire or nanosheet structures, while the silicon thin film is used as a channel layer. A nitride thin film is then deposited to serve as a hard mask in the subsequent Chemical Mechanical Polishing (CMP) process. At this time, the deposition method is not limited to epitaxy technology, and various deposition technologies such as CVD and ALD can be used.

[0062] 2) Source line / drain line patterning

[0063] The upper nitride thin film is patterned using photolithography and etching processes, and source / drain regions are formed through an ion implantation process. Oxide sidewall spacers (SiO2 sidewall spacers) are formed based on the nitride pattern and utilized as a hard mask to anisotropically etch the silicon / silicon germanium thin films.

[0064] 3) Separation of source line / drain line

[0065] The silicon germanium thin film located between the source and drain lines is selectively etched using an etching technique with excellent selectivity. To separate the source and drain lines, an oxide insulating film is deposited between them using a deposition technique with excellent step coverage, such as Atomic Layer Deposition (ALD). Subsequently, the remaining area is also filled with an oxide thin film using methods such as High-Density Plasma Chemical Vapor Deposition (HDPCVD), followed by planarization using chemical mechanical polishing.

[0066] 4) Active fin patterning

[0067] The nitride thin film is removed using an etching technique with excellent selectivity. An oxide thin film is present on top of the source line / drain line region, while a silicon / silicon germanium stacked thin film is exposed in the remaining active region. An active pin pattern is formed using a photolithography or electron beam lithography process, followed by anisotropic etching. During the anisotropic etching process, the oxide thin film on top of the source line / drain line is used as a mask, while a photoresist or electron beam resist is used for the active pin region.

[0068] 5) Dummy gate patterning

[0069] To form a dummy gate, oxide, amorphous silicon, and nitride thin films are deposited in that order, followed by patterning. While it is preferable to use the formed dummy gate as a hard mask to dope the source / drain regions to a high concentration via an ion implantation process, selective epitaxy growth techniques may also be used. The silicon germanium thin film is selectively etched using an etching technique with excellent selectivity. Subsequently, an oxide thin film is deposited using a deposition technique with excellent step coverage. Finally, a chemical mechanical polishing process is performed using the nitride thin film formed on top of the dummy gate as a hard mask. As a result, a structure is formed in which all silicon regions, excluding the channel region, are separated layer by layer.

[0070] 6) Ferroelectric and Metal Gate Deposition

[0071] Using an etching technique with excellent selectivity, the dummy gate is removed by etching the nitride, amorphous silicon, and oxide thin films constituting the dummy gate in the described order. Subsequently, the silicon germanium thin film located between the stacked silicon channel layers is removed by isotropic etching to form silicon nanowire or nanosheet structures. A Rapid Thermal Annealing (RTA) process is performed to recover the silicon lattice damaged during the ion activation and ion implantation processes. Atomic Layer Deposition (ALD) technology is used to deposit hafnium oxide (HfO2)-based ferroelectric and metal gates constituting the transistor gate. Finally, additional heat treatment is performed to crystallize the ferroelectric material.

[0072] 7) Word line patterning and wiring process

[0073] Word-line (WL) patterning is performed using photolithography and etching techniques to form a stacked transistor array structure. Finally, the fabrication of a channel-stacked gate-all-around ferroelectric transistor is completed by performing a back-end-of-line (BEOL) process.

[0074] The manufacturing method described above is designed based on a gate-last process, in which a gate pattern is formed after the source and drain are formed. However, if a channel-stacked gate-all-around ferroelectric transistor is fabricated based on a junctionless structure in which the source, channel, and drain regions are all doped to the same high concentration, it can be easily fabricated based on a gate-first process.

[0075] Although the present invention has been described in detail above through representative embodiments, those skilled in the art will understand that various modifications can be made to the above-described embodiments within the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the claims set forth below as well as all modifications or variations derived from the claims and equivalent concepts. Explanation of the symbols

[0076] 100: Channel stacked gate-all-around ferroelectric transistor. 110: Substrate 120: Channel layer 130: Gate structure 131: Oxide insulating layer 132: Ferroelectric layer 133: Metal gate electrode 141: Source line 142: Drain line

Claims

Claim 1 A channel-stacked gate-all-around ferroelectric transistor comprises: a plurality of channel layers vertically stacked on a semiconductor substrate; a gate structure formed to wrap around the entire side extending along the length direction of the channel layers; and source lines and drain lines independently connected to each of the channel layers and capable of individual control; wherein an interlayer insulating film for electrical insulation is provided between the source lines and between the drain lines, respectively; wherein the channel layers are a plurality of single-crystal silicon channel layers formed by alternately stacking a single-crystal silicon layer and a silicon germanium layer through an epitaxy process and selectively removing the silicon germanium layer; wherein the transistor implements independent memory operation through different source / drain voltage control for each layer under the same gate voltage; and wherein the transistor is formed in a structure that shares a common source line between adjacent transistors located at the same layer level when a plurality of transistors form an array, thereby improving the integration density per unit area. Claim 2 A channel stacked gate-all-around ferroelectric transistor according to claim 1, characterized in that the gate structure comprises a structure in which an oxide insulating layer, a ferroelectric layer, and a metal gate electrode are sequentially stacked. Claim 3 A channel stacked gate-all-around ferroelectric transistor according to claim 2, characterized in that the ferroelectric layer comprises an HfO2-based ferroelectric material or a ferroelectric material having a perovskite structure. Claim 4 A channel-stacked gate-all-around ferroelectric transistor according to claim 1, wherein the channel layer is formed in the form of a nanowire or a nanosheet. Claim 5 A channel stacked gate-all-around ferroelectric transistor according to claim 1, characterized in that the channel layer is formed as a junctionless structure in which the source region, channel region, and drain region as a whole have the same doping type and doping concentration. Claim 6 In claim 1, the transistor is 8F 2 Channel stacked gate-all-around ferroelectric transistor characterized by having three or more channel layers stacked per unit area. Claim 7 A channel stacked gate-all-around ferroelectric transistor according to claim 1, wherein the channel layer may be composed of single-crystal silicon or an oxide semiconductor material, and the oxide semiconductor material is any one of ZnO, In2O3, and IGZO. Claim 8 A method for manufacturing a channel-stacking gate-all-around ferroelectric transistor comprising: a step of alternately stacking a single-crystal silicon layer and a silicon germanium layer on a semiconductor substrate through an epitaxy process; a step of defining a channel region by patterning the stacked structure; a step of forming a plurality of single-crystal silicon channel layers by selectively removing the silicon germanium layer; a step of forming source and drain regions on both sides of the channel layer, respectively, and connecting source lines and drain lines corresponding to each of the plurality of channel layers so that voltage control is possible individually for each channel layer; a step of forming an interlayer insulating film between the source lines and between the drain lines, respectively; and a step of forming a gate structure to wrap around the entire side extending along the length direction of the channel layer; wherein an oxide insulating layer, a ferroelectric layer, and a metal gate electrode are sequentially stacked.

Images