Circuit board and semiconductor package having the same

Abstract

A circuit board according to an embodiment comprises an insulating layer; a circuit layer disposed on the insulating layer; and a protective layer disposed on the insulating layer, wherein the circuit layer is disposed on a first region of the insulating layer and includes a first pattern portion comprising a first-1 pad and a first-2 pad, and the protective layer includes a first protective pattern disposed on the first region of the insulating layer, wherein the first protective pattern includes a first portion disposed in an adjacent region of the first pattern portion that includes a region between the first-1 pad and the first-2 pad in the first region, and a second portion disposed in an edge region of the first region excluding the adjacent region, wherein the upper surface of the first portion is positioned lower than the upper surface of the first pattern portion, and the upper surface of the second portion is positioned higher than the upper surface of the first pattern portion, and the width of the first-1 pad and the first-2 pad in each direction is different from each other.

Description

Technology Field

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. In particular, the embodiments relate to a circuit board including a protective layer capable of solving the problem of short circuits between adjacent pads while reducing thickness, and a semiconductor package including the same. Background Technology

[0002] Generally, a printed circuit board (PCB) is a laminated structure in which insulating layers and conductive layers are alternately stacked, and the conductive layers can be formed into circuit patterns by patterning.

[0003] Such a printed circuit board is provided with a solder resist (SR) that protects the circuit formed on the outermost side of the laminate, prevents oxidation of the conductor layer, and acts as an insulator during electrical connection with a chip or other substrate mounted on the printed circuit board.

[0004] In conventional solder resists, opening regions (SRO: Solder Resist Opening) are formed to serve as electrical connection pathways by combining connecting means such as solder or bumps. As printed circuit boards become higher performance and higher density, a larger number of opening regions is required to enhance I / O (Input / Output) performance, thereby necessitating a small bump pitch in these opening regions. In this context, the bump pitch of the opening regions refers to the center distance between adjacent opening regions.

[0005] Meanwhile, the opening region (SRO) of the solder resist includes SMD (Solder Mask Defined type) and NSMD (Non-Solder Mask Defined type) types.

[0006] The above SMD type is characterized in that the width of the opening area (SRO) is smaller than the width of the pad exposed through the opening area (SRO), and accordingly, at least a portion of the upper surface of the pad in the SMD type is covered by the solder resist.

[0007] In addition, the NSMD type is characterized in that the width of the opening area (SRO) is greater than the width of the pad exposed through the opening area (SRO). Accordingly, in the NSMD type, the solder resist is positioned at a certain distance from the pad, and thus has a structure in which both the upper and side surfaces of the pad are exposed.

[0008] However, in the case of the above SMD type, there is a problem in that the solder ball separates from the pad exposed through the opening area (SRO) during the Solder Ball Joint Reliability test regarding the bonding strength of the solder ball after the semiconductor package is bonded to the main board. Additionally, in the case of the NSMD type, there is a problem in that the pad where the solder ball is placed separates from the substrate. Accordingly, conventionally, SMD and NSMD types are applied by appropriately combining them on a single circuit board.

[0009] At this time, conventional circuit boards provide a space for mounting components such as Multi-Layered Ceramic Capacitors (MLCCs). In this case, the solder resist in the space where the MLCCs are placed on the conventional circuit board is of the SMD type. Consequently, there is a problem in that the overall thickness of a semiconductor package with MLCCs mounted on a conventional circuit board increases by the thickness of the solder resist.

[0010] To solve this problem, solder resist is not placed in the space where the conventional multilayer ceramic capacitor is positioned. Additionally, an adhesive member, such as a solder ball, has a structure that extends along the side of the pad. Consequently, in a structure where the solder resist is not placed, there is a short circuit problem where the adhesive members placed on adjacent pads are interconnected.

[0011] (Patent Document 1) KR 10-2013-0046726 A

[0012] (Patent Document 2) KR 10-1877963 B The problem to be solved

[0013] The embodiment aims to provide a circuit board capable of slimming down and a semiconductor package including the same.

[0014] Additionally, the embodiment aims to provide a circuit board capable of reducing the spacing between adjacent pads and a semiconductor package including the same.

[0015] In addition, the embodiment aims to provide a circuit board capable of solving the problem of short circuits between adhesive members disposed on a pad, and a semiconductor package including the same.

[0016] In addition, the embodiment aims to provide a circuit board with improved physical and electrical reliability and a semiconductor package including the same.

[0017] In addition, the embodiment aims to provide a circuit board and a semiconductor package including the same that can solve the problem of an adhesive member penetrating between an insulating layer and a pad.

[0018] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the proposed embodiments belong from the description below. means of solving the problem

[0019] A circuit board according to an embodiment comprises an insulating layer; a circuit layer disposed on the insulating layer; and a protective layer disposed on the insulating layer, wherein the circuit layer is disposed on a first region of the insulating layer and includes a first pattern portion comprising a first-1 pad and a first-2 pad, and the protective layer includes a first protective pattern disposed on the first region of the insulating layer, wherein the first protective pattern includes a first portion disposed in an adjacent region of the first pattern portion that includes a region between the first-1 pad and the first-2 pad in the first region, and a second portion disposed in an edge region of the first region excluding the adjacent region, wherein the upper surface of the first portion is positioned lower than the upper surface of the first pattern portion, and the upper surface of the second portion is positioned higher than the upper surface of the first pattern portion, and the width of the first-1 pad and the first-2 pad in each direction is different from each other.

[0020] In addition, the thickness of the first portion of the first protective pattern satisfies a range of 40% to 90% of the thickness of the first pattern portion.

[0021] In addition, the thickness of the first pattern portion satisfies the range of 10㎛ to 25㎛, and the thickness of the first portion of the first protective pattern satisfies the range of 3㎛ to 21㎛.

[0022] In addition, the difference between the thickness of the first pattern portion and the thickness of the first portion of the first protection pattern satisfies 3㎛ to 10㎛.

[0023] Additionally, the upper surface of the first pattern portion includes a curved surface, and the difference between the thickness of the first pattern portion and the thickness of the first part of the first protective pattern is the vertical distance between the top of the first pattern portion and the top of the first part of the first protective pattern.

[0024] In addition, the thickness of the second portion of the first protective pattern satisfies the range of 17㎛ to 45㎛.

[0025] Additionally, the first-1 pad and the first-2 pad are spaced apart in the second direction perpendicular to the first direction on the first region of the insulating layer, and the width of each of the first-1 pad and the first-2 pad in the first direction has a range of 125% to 220% of the width of each of the first-1 pad and the first-2 pad in the second direction.

[0026] In addition, the width of each of the first-1 pad and the first-2 pad in the first direction exceeds 195 μm, and the width of each of the first-1 pad and the first-2 pad in the second direction exceeds 125 μm.

[0027] In addition, the gap between the first-1 pad and the first-2 pad satisfies a range of 70% to 120% of the width in the second direction of each of the first-1 pad and the first-2 pad.

[0028] In addition, the inner wall of the second part of the first protective pattern is spaced apart from the side of the first pattern part by a distance of 15 μm to 23 μm.

[0029] In addition, the first pattern portion does not overlap with the protective layer in the thickness direction.

[0030] In addition, the second portion of the first protective pattern is in direct contact with at least a portion of the side of the first-1 pad and the side of the first-2 pad.

[0031] Additionally, the first-1 pad includes a first-1 side facing the first-2 pad and a first-2 side excluding the first-1 side, and the first-2 pad includes a second-1 side facing the first-1 side and a second-2 side excluding the second-1 side, and the second portion of the first protective pattern is in direct contact with at least a portion of the first-2 side of the first-1 pad and the second-2 side of the first-2 pad.

[0032] Additionally, the circuit layer is disposed on a second region of the insulating layer and includes a second pattern portion comprising a second pad and a second trace, wherein the second pad has a width in the range of 3 μm to 30 μm, the second trace has a width in the range of 1 μm to 10 μm, and the gap between the second pad and the second trace has a range of 1 μm to 10 μm.

[0033] In addition, the protective layer is not placed on the second region of the insulating layer.

[0034] Additionally, the protective layer includes a second protective pattern disposed on the second region, the second protective pattern does not overlap with the second pattern portion in the thickness direction, and the upper surface of the second protective pattern is positioned lower than the upper surface of the second pattern portion.

[0035] Additionally, the circuit layer is disposed on a third region of the insulating layer and includes a third pattern portion comprising a plurality of third pads and a plurality of third traces, the width of the third pad satisfies a range of 30㎛ to 70㎛, and the spacing between the third pads and the third traces satisfies a range of 10㎛ to 40㎛.

[0036] Additionally, the protective layer comprises a third protective pattern disposed on the third region covering at least a portion of the upper surface of the third pad and including an opening that overlaps in the thickness direction with the remaining portion of the upper surface of the third pad.

[0037] Meanwhile, a semiconductor package according to an embodiment comprises: an insulating layer; a first pattern portion disposed on a first region of the insulating layer and including a first-1 pad and a first-2 pad; a first connection portion including a first-1 connection portion disposed on the first-1 pad and a first-2 connection portion disposed on the first-2 pad; a first chip disposed on the first connection portion; and a protective layer disposed on the insulating layer, wherein the protective layer comprises a first protective pattern disposed on the first region, and the first protective pattern comprises a first portion disposed in an adjacent region of the first pattern portion including an area between the first-1 pad and the first-2 pad in the first region, and a second portion disposed in an edge region of the first region excluding the adjacent region, wherein the second portion of the first protective pattern does not overlap with the first chip in the thickness direction, the upper surface of the first portion is positioned lower than the upper surface of the first pattern portion, and the upper surface of the second portion is positioned higher than the upper surface of the first pattern portion.

[0038] Additionally, the side of the first-1 connection part is adjacent to the first-2 pad more than the side of the first-1 pad, and the side of the first-2 connection part is adjacent to the first-1 pad more than the side of the first-2 pad, and the lower surface of the first-1 connection part is positioned higher than the lower surface of the first-1 pad and the upper surface of the insulating layer and lower than the upper surface of the first-1 pad, and the lower surface of the first-2 connection part is positioned higher than the lower surface of the first-2 pad and the upper surface of the insulating layer and lower than the upper surface of the first-2 pad.

[0039] Additionally, the semiconductor package further comprises a second pattern portion disposed on a second region of the insulating layer; a second connection portion disposed on the second pattern portion; and a second chip disposed on the second connection portion, wherein the second chip comprises a processor chip, and the protective layer is not disposed on the second region of the insulating layer.

[0040] Additionally, the protective layer comprises a third pattern portion disposed on a third region of the insulating layer; and a third connection portion disposed on the third pattern portion, wherein the protective layer comprises a third protective pattern that covers at least a portion of the upper surface of the third pattern portion and includes an opening that overlaps in the thickness direction with the remaining portion of the upper surface of the third pattern portion. Effects of the invention

[0041] The circuit board of the embodiment includes a first region where a first chip is disposed. In the first region of the insulating layer, a first pattern portion and a first protective pattern of the protective layer are disposed. The first protective pattern does not contact the upper surface of the first pattern portion, but contacts at least a portion of the side surface of the first pattern portion. That is, the first protective pattern includes a first portion disposed in a surrounding area adjacent to the first pattern portion and a second portion surrounding the first portion. Furthermore, the first portion of the first protective pattern does not contact the upper surface of the first pattern portion, but contacts at least a portion of the side surface of the first pattern portion. For example, the upper surface of the first portion of the first protective pattern is disposed lower than the upper surface of the first pattern portion. Accordingly, in the embodiment, the thickness and width of the contact member disposed on the first pattern portion can be reduced by utilizing the first portion of the first protective pattern. For example, in the first comparative example, the thickness of the contact member increased due to the placement of the protective layer, and in the second comparative example, the degree of expansion of the contact member increased due to the non-placement of the protective layer, thereby increasing the width of the contact member. In contrast, in the embodiment, the degree of expansion of the contact member can be reduced through the combination of the first and second parts of the first protective pattern, thereby reducing the width of the contact member. Furthermore, in the embodiment, since only the first part of the first protective pattern exists in the area where the first chip is placed, the problem of the thickness of the contact member increasing due to the placement of the protective layer can be resolved.

[0042] Accordingly, in the embodiment, the thickness of the semiconductor package on which the first chip is mounted on the circuit board can be reduced, and thus miniaturization can be achieved. Furthermore, in the embodiment, the degree of expansion of the contact member can be reduced to solve the problem of circuit shorting between adjacent contact members. Accordingly, in the embodiment, the electrical reliability and product reliability of the semiconductor package can be improved. Furthermore, in the embodiment, by solving the circuit shorting problem, it is not necessary to increase the spacing between the first pattern portions, and accordingly, the circuit integration density can be improved.

[0043] In addition, the embodiment can solve the problem of an adhesive member penetrating between the insulating layer and the pad by utilizing the first portion of the first protection pattern, and thereby further improve product reliability. Brief explanation of the drawing

[0044] Figure 1 is a cross-sectional view of a semiconductor package according to the first comparative example. Figure 2 is a cross-sectional view of a semiconductor package according to the second comparative example. FIG. 3 is a cross-sectional view showing the overall layer structure of a circuit board according to one embodiment. FIG. 4 is a diagram showing the structure of a second region of a circuit board according to a first embodiment. FIG. 5 is a diagram showing the structure of a second region of a circuit board according to a second embodiment. FIG. 6 is a diagram showing the structure of a third region of a circuit board according to an embodiment. FIG. 7a is a plan view of a first region of a circuit board according to a first embodiment. Figure 7b is a cross-sectional view taken along the CC' direction of Figure 7a. FIG. 7c is a cross-sectional view taken along the DD' direction of FIG. 7a. FIG. 8 is a perspective view showing a component mounted in a first region of a circuit board according to one embodiment. FIG. 9 is a plan view of a first region of a circuit board according to a second embodiment. FIG. 10a is a plan view of a first region of a circuit board according to a third embodiment. FIG. 10b is a cross-sectional view cut along the EE' direction of FIG. 10a. FIG. 10c is a cross-sectional view cut along the FF' direction of FIG. 10a. Fig. 10d is an example of a variation of the structure of Fig. 10c. FIG. 11a is a plan view of a first region of a circuit board according to a fourth embodiment. FIG. 11b is a cross-sectional view taken along the GG' direction of FIG. 10a. FIG. 12 is a cross-sectional view showing a semiconductor package according to an embodiment. FIG. 13a is an enlarged view of the placement area of ​​the first chip of FIG. 12 according to the first embodiment. FIG. 13b is an enlarged view of the placement area of ​​the first chip of FIG. 12 according to a second embodiment. FIGS. 14 to 21 are cross-sectional views showing the manufacturing process of a circuit board according to an embodiment in process order. Specific details for implementing the invention

[0045] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols are assigned the same reference number, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" for components used in the following description are assigned or used interchangeably solely for the ease of drafting the specification and do not inherently possess distinct meanings or roles. Furthermore, in describing the embodiments disclosed in this specification, if it is determined that a detailed description of related prior art could obscure the essence of the embodiments disclosed in this specification, such detailed description will be omitted. Additionally, the attached drawings are intended only to facilitate easy understanding of the embodiments disclosed in this specification; the technical concept disclosed in this specification is not limited by the attached drawings and should be understood to include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the present invention.

[0046] Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0047] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0048] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0049] In this application, terms such as “comprising” or “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0052] - Comparison Example -

[0053] Before describing the embodiments, we will describe a comparative example that is compared with the circuit board of the embodiments of the present invention.

[0054] FIG. 1 is a cross-sectional view of a semiconductor package according to a first comparative example, and FIG. 2 is a cross-sectional view of a semiconductor package according to a second comparative example.

[0055] Referring to FIG. 1, a semiconductor package according to the first comparative example includes a circuit board and a device mounted on the circuit board.

[0056] The circuit board of the first comparative example above includes an insulating layer (10), a circuit layer (20), and a protective layer (30).

[0057] The circuit layer (20) is disposed on the upper surface of the insulating layer (10). The circuit layer (20) may represent the outermost layer among a plurality of circuit layers disposed on a circuit board. For example, the circuit layer (20) represents a circuit layer in an area where a chip is mounted on the circuit board.

[0058] For example, the circuit layer (20) represents a pad on which a multilayer ceramic capacitor is placed.

[0059] The protective layer (30) is placed on the insulating layer (10).

[0060] At this time, the protective layer (30) is disposed on the insulating layer (10) with a certain thickness. Specifically, the protective layer (30) is disposed on the insulating layer (10) with a thickness greater than the thickness of the circuit layer (20).

[0061] The protective layer (30) includes an opening (not shown) that overlaps in the thickness direction with the upper surface of the circuit layer (20). The planar area of ​​the opening of the protective layer (30) is smaller than the planar area of ​​the circuit layer (20). That is, the protective layer (30) is positioned to cover a portion of the upper surface of the circuit layer (20). The protective layer (30) overlaps in the thickness direction with at least a portion of the upper surface of the circuit layer (20), thereby not coming into contact with at least a portion of the upper surface of the circuit layer (20).

[0062] An adhesive member (50) is disposed in the opening of the protective layer (30). The adhesive member (50) may be a solder ball.

[0063] Additionally, a component (40) can be mounted on the circuit layer (20) through the adhesive member (50). The component (40) has a structure in which a body (41) and terminals (42) are formed on both sides of the body (41). That is, the component (40) is a passive component. For example, the component (40) is a multilayer ceramic capacitor.

[0064] In this case, in the first comparative example, the protective layer (30) in the area where the element (40) is mounted is positioned higher than the upper surface of the circuit layer (20). As a result, in the first comparative example, there is a problem in that the overall thickness of the semiconductor package increases by the amount of the protruding thickness of the protective layer (30).

[0065] That is, the circuit layer (20) includes a pad electrically connected to the element (40). The pad has a size corresponding to the terminal (42) of the element (40). For example, the width (w1) of the pad in the first direction exceeds 140 μm. For example, the width (w1) of the pad in the first direction exceeds 190 μm. For example, the width (w1) of the pad in the first direction exceeds 300 μm. For example, the width (w1) of the pad in the first direction exceeds 450 μm. The first direction refers to the spacing direction of the plurality of terminals (42) of the element (40).

[0066] In addition, the circuit board of the first comparative example has a spacing (w2) between a plurality of pads connected to the element (40) that exceeds 120 μm. For example, the circuit board of the first comparative example has a spacing (w2) between a plurality of pads connected to the element (40) that exceeds 200 μm. For example, the circuit board of the first comparative example has a spacing (w2) between a plurality of pads connected to the element (40) that exceeds 300 μm.

[0067] Meanwhile, the maximum width (w3) of the adhesive member (50) in the first direction has a level similar to the width (w1) of the pad. For example, the maximum width (w3) of the adhesive member (50) in the first direction has a level of 80% to 105% of the width of the pad.

[0068] Meanwhile, the thickness (t1) of the circuit layer (20) of the first comparative example has a range of 10㎛ to 20㎛. And, in the total thickness of the protective layer (30), the thickness (t2) of the portion protruding above the upper surface of the circuit layer (20) has a range of 7㎛ to 20㎛.

[0069] At this time, the adhesive member (50) is positioned with a certain thickness (t3) from the upper surface of the protective layer (30). The thickness (t3) is set based on conditions that allow the element (40) to be stably mounted on the circuit layer (20).

[0070] In this case, the thickness (t3) in the first comparative example is set based on the upper surface of the protective layer (30) rather than the upper surface of the circuit layer (20). That is, if the thickness (t3) is set based on the upper surface of the circuit layer (20), a problem may occur in which a part of the element (40) comes into contact with the upper surface of the protective layer (30) during the mounting process of the element (40). As a result, the element (40) may be mounted in a distorted state.

[0071] Accordingly, the thickness (t4) from the upper surface of the insulating layer (10) to the upper surface of the element (40) in the first comparative example reflects not only the thickness (t1) of the circuit layer (20) and the thickness (t3) of the adhesive member (50), but also the thickness (t2) of the protruding portion of the protective layer (30). Therefore, in the first comparative example, there is a problem in that the total thickness increases by the thickness (t2) of the protruding portion of the protective layer (30) in the structure in which the element (40) is mounted.

[0073] Meanwhile, in the second comparative example in FIG. 2, in order to solve the problem of the first comparative example, the protective layer (30) is not placed in the area where the element (40) is placed. Accordingly, in the second comparative example, the thickness of the semiconductor package can be reduced by the thickness (t2) of the protruding part of the protective layer (30) of the first comparative example.

[0074] That is, the thickness (t4') between the insulating layer (10) and the element (40) in the second comparative example may be smaller than the thickness (t2) of the protruding part of the protective layer (30) compared to the thickness (t4) of the first comparative example.

[0075] And in the second comparative example, since the structure does not have the protective layer (30), there is a problem that the width of the adhesive member (50) becomes relatively larger.

[0076] Specifically, the adhesive member (50) is placed on the circuit layer (20). At this time, with the adhesive member (50) placed on the circuit layer (20), it has a structure that is placed along the surface of the circuit layer (20), which is metal.

[0077] At this time, in the first comparative example, the width (w3) of the adhesive member (50) was similar to the width (w1) of the pad of the circuit layer (20) as the adhesive member (50) did not come into contact with the side of the circuit layer (20).

[0078] In contrast, the second comparative example has a structure in which the side of the circuit layer (20) is entirely exposed. Accordingly, the adhesive member (50) of the second comparative example is positioned to cover not only the upper surface but also the entire side of the circuit layer (20).

[0079] That is, the width (w3') of the adhesive member (50) in the second comparative example is greater than the width of the pad of the circuit layer (20). Specifically, the width (w3') of the adhesive member (50) in the second comparative example exceeds 130% of the width of the pad. More specifically, the width (w3') of the adhesive member (50) in the second comparative example exceeds 140% of the width of the pad.

[0080] At this time, the element (40) includes two terminals (42). In the second comparative example, as the adhesive member (50) has a structure that extends along the side of the circuit layer (20), there is a problem that the gap between the two adhesive members in contact with the two terminals becomes narrow. Furthermore, the gap between the two adhesive members becomes even narrower as the thickness or width of the circuit layer (20) increases. Accordingly, the structure in which the protective layer (30) is not placed in the second comparative example has a problem that the gap between the two contact members becomes narrow. Furthermore, the second comparative example has a problem that a circuit short occurs between the two adhesive members depending on the degree of extension of the adhesive member (50). In addition, to solve the circuit short problem, the second comparative example makes the gap (w2) between the two pads larger than in the first comparative example. Accordingly, the semiconductor package of the second comparative example can reduce its thickness compared to the semiconductor package of the first comparative example, but it has a problem of increasing in size in the horizontal direction due to the problem of reduced circuit integration density.

[0081] In addition, as the performance of electrical and electronic products has recently increased, technologies for mounting a larger number of components on a substrate of limited size are being researched, and accordingly, miniaturization of the width and spacing of circuit layers is required. However, in the case of the semiconductor packages of the first and second comparative examples, it is difficult to reduce the overall thickness, or there are limitations in reducing the spacing between circuit layers due to circuit short circuit issues. Furthermore, with the recent increase in functions processed by application processors (APs), it is becoming difficult to implement them on a single chip. However, in the comparative examples, it is difficult to mount two application processors (APs) with different functions or multiple passive components within a limited space.

[0082] The embodiment is intended to solve the problems of the comparative example by dividing the circuit board into multiple regions and ensuring that the protective layers in the multiple regions have different open structures. Accordingly, the embodiment enables the spacing between pads on which devices are mounted to be reduced without increasing the overall thickness of the semiconductor package. Through this, the embodiment improves the integration density of the circuit board, making it possible to mount multiple chips on a single circuit board. For example, the embodiment provides a circuit board with a new structure capable of mounting multiple processor chips or memory chips with different functions on a single circuit board, and a semiconductor package including the same.

[0084] -former device -

[0085] Before describing the embodiment, an electronic device including the semiconductor package of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various chips may be mounted on the semiconductor package. Broadly, the semiconductor package may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), an antenna chip, a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; logic chips such as an analog-to-digital converter and an ASIC (application-specific IC); and passive chips.

[0086] Specifically, at least one chip may be mounted in the semiconductor package of the embodiment, and the chip may include at least one of a processor chip, a passive chip, and an active chip. Specifically, an electronic component such as a chip may be mounted within the semiconductor package. The chip may be either an active chip or a passive chip. The active chip is a chip that actively utilizes the non-linear portion of the signal characteristics. The passive chip refers to a chip that does not utilize the non-linear signal characteristics even if both linear and non-linear signal characteristics exist. For example, the active chip may include transistors, IC semiconductor chips, etc., and the passive chip may include capacitors, resistors, and inductors, etc. The passive chip may increase the signal processing speed of the semiconductor chip, which is the active chip, or perform filtering functions, etc. Additionally, the chip may be a wireless communication chip capable of being used for Wi-Fi or 5G communication, etc.

[0087] Meanwhile, the product family to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0088] In addition, the electronic device may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to these, and it is obvious that it may be any other electronic device that processes data in addition to these.

[0090] - Example of Implementation -

[0091] FIG. 3 is a cross-sectional view showing the overall layer structure of a circuit board according to one embodiment.

[0092] Referring to FIG. 3, the circuit board includes a plurality of insulating layers.

[0093] At this time, the circuit board may be a core board including a core layer. However, the embodiments are not limited thereto, and the circuit board of the embodiments may be a coreless board that does not include a core layer.

[0094] However, for convenience of explanation, the circuit board of the embodiment is described below as a core board including a core layer.

[0095] In addition, although the circuit board of the embodiment is shown in the drawing as having a 5-layer structure based on the number of insulating layers, it is not limited thereto. For example, the circuit board of the embodiment may have 4 layers or fewer based on the number of insulating layers, or 6 layers or more.

[0096] Hereinafter, as an example of an embodiment, a circuit board having a five-layer insulating layer structure including a core layer will be described.

[0097] The insulating layer (110) of the embodiment includes a first insulating layer (111). The first insulating layer (111) may be an insulating layer in which copper foil is laminated on both sides. Preferably, the first insulating layer (111) may be a copper clad lamination (CCL).

[0098] In particular, the copper foil laminate is a substrate on which circuit boards are generally manufactured, and is a laminate in which copper foil is laminated onto an insulating layer. Depending on the application, the copper foil laminate may include a glass / epoxy copper foil laminate, a heat-resistant resin copper foil laminate, a paper / phenol copper foil laminate, a high-frequency copper foil laminate, a flexible copper foil laminate (e.g., a polyimide film), and a composite copper foil laminate. At this time, the first insulating layer (111) of the embodiment may use a glass / epoxy copper foil laminate for manufacturing double-sided circuit boards and multilayer circuit boards, but is not limited thereto.

[0099] The first insulating layer (111) may have a thickness in the range of 100 μm to 500 μm. Preferably, the first insulating layer (111) may have a thickness in the range of 120 μm to 480 μm. More preferably, the first insulating layer (111) may have a thickness in the range of 150 μm to 450 μm.

[0100] If the thickness of the first insulating layer (111) is less than 100 μm, the rigidity and bending characteristics of the circuit board may be reduced. Additionally, if the thickness of the first insulating layer (111) exceeds 500 μm, the thickness of the circuit layer disposed on the first insulating layer (110), the line width of the circuit layer, the spacing between the circuit layers, and the thickness of the through electrode may increase.

[0101] The insulating layer (110) may include a plurality of insulating layers stacked on the upper and lower surfaces, respectively, of the first insulating layer (111). For example, the insulating layer (110) may include a second insulating layer (112) disposed on the upper surface of the first insulating layer (111), a third insulating layer (113) disposed on the upper surface of the second insulating layer (112), a fourth insulating layer (114) disposed on the lower surface of the first insulating layer (111), and a fifth insulating layer (115) disposed on the lower surface of the fourth insulating layer (114).

[0102] The second to fifth insulating layers (115) may include prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, with epoxy resin or the like, and then performing heat pressing. However, the embodiments are not limited thereto, and the prepreg constituting the second to fifth insulating layers (115) may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

[0103] In addition, at least one of the second to fifth insulating layers (115) may be rigid or flexible. For example, at least one of the second to fifth insulating layers (115) may include RCC (Resin Coated Copper), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric Resin), BT, etc.

[0104] Each of the second to fifth insulating layers (115) may have a thickness in the range of 10 μm to 60 μm. Preferably, each of the second to fifth insulating layers (115) may have a thickness in the range of 12 μm to 50 μm. More preferably, each of the second to fifth insulating layers (115) may have a thickness in the range of 15 μm to 40 μm.

[0105] If the thickness of each of the second to fifth insulating layers (115) is less than 10 μm, the circuit layer included in the circuit board may not be stably protected. If the thickness of each of the second to fifth insulating layers (115) exceeds 60 μm, the thickness of the circuit board and the semiconductor package including it may increase. If the thickness of each of the second to fifth insulating layers (115) exceeds 60 μm, the thickness of the circuit layer and the thickness of the through electrode may increase accordingly. And if the thickness of the circuit layer and the thickness of the through electrode increase, the signal transmission loss may increase.

[0107] The circuit board of the embodiment includes a circuit layer.

[0108] The circuit layer may be disposed on each surface of the insulating layer (110). For example, the circuit layer may include a first circuit layer (121) disposed on the upper surface of the first insulating layer (111), a second circuit layer (122) disposed on the upper surface of the second insulating layer (112), a third circuit layer (123) disposed on the upper surface of the third insulating layer (113), a fourth circuit layer (124) disposed on the lower surface of the first insulating layer (111), a fifth circuit layer (125) disposed on the lower surface of the fourth insulating layer (114), and a sixth circuit layer (126) disposed on the lower surface of the fifth insulating layer (115).

[0109] At least one of the first circuit layer (121), second circuit layer (122), third circuit layer (123), fourth circuit layer (124), fifth circuit layer (125) and sixth circuit layer (126) may have a thickness of 10 μm to 25 μm. Preferably, at least one of the first circuit layer (121), second circuit layer (122), third circuit layer (123), fourth circuit layer (124), fifth circuit layer (125) and sixth circuit layer (126) may each have a thickness of 12 μm to 23 μm. More preferably, at least one of the first circuit layer (121), second circuit layer (122), third circuit layer (123), fourth circuit layer (124), fifth circuit layer (125) and sixth circuit layer (126) may have a thickness of 15 μm to 20 μm.

[0110] The first circuit layer (121), second circuit layer (122), third circuit layer (123), fourth circuit layer (124), fifth circuit layer (125) and sixth circuit layer (126) may include a conductive material. For example, the first circuit layer (121), second circuit layer (122), third circuit layer (123), fourth circuit layer (124), fifth circuit layer (125) and sixth circuit layer (126) may include at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn). Preferably, the first circuit layer (121), the second circuit layer (122), the third circuit layer (123), the fourth circuit layer (124), the fifth circuit layer (125), and the sixth circuit layer (126) can be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0111] The first circuit layer (121), second circuit layer (122), third circuit layer (123), fourth circuit layer (124), fifth circuit layer (125) and sixth circuit layer (126) can be manufactured using conventional circuit board manufacturing processes such as the Additive Process, Subtractive Process, Modified Semi Additive Process (MSAP), and Semi Additive Process (SAP), and a detailed description is omitted here.

[0112] The circuit board includes a through electrode. For example, the circuit board includes a through electrode that penetrates the insulating layer and electrically connects circuit layers disposed on different layers.

[0113] For example, the through electrode includes a first through electrode (131) that penetrates the first insulating layer (111). The first through electrode (131) can electrically connect the first circuit layer (121) and the fourth circuit layer (124).

[0114] Additionally, the through electrode includes a second through electrode (132) that penetrates the second insulating layer (112). The second through electrode (132) can electrically connect the first circuit layer (121) and the second circuit layer (122).

[0115] Additionally, the penetrating electrode includes a third penetrating electrode (133) that penetrates the third insulating layer (113). The third penetrating electrode (133) can electrically connect the second circuit layer (122) and the third circuit layer (123).

[0116] Additionally, the through electrode includes a fourth through electrode (134) that penetrates the fourth insulating layer (114). The fourth through electrode (134) can electrically connect the fourth circuit layer (124) and the fifth circuit layer (125).

[0117] Additionally, the through electrode includes a fifth through electrode (135) that penetrates the fifth insulating layer (115). The fifth through electrode (135) can electrically connect the fifth circuit layer (125) and the sixth circuit layer (126).

[0118] Additionally, the circuit board includes a protective layer. The protective layer may be disposed on the uppermost or lowermost side of the circuit board. The protective layer may protect the surface of a circuit layer or an insulating layer disposed on the uppermost or lowermost side of the circuit board.

[0119] Preferably, the protective layer may include a first protective layer (140) disposed on the upper surface of the third insulating layer (113). The first protective layer (140) may protect the upper surface of the third insulating layer (113) and the upper surface of the third circuit layer (123). Additionally, the first protective layer (140) may include a first opening (not shown) that overlaps in the thickness direction with at least a portion of the upper surface of the third circuit layer (123). The first opening may be formed to correspond to the mounting location of an electronic component or the contact location with an external substrate.

[0120] Additionally, the protective layer may include a second protective layer (150) disposed on the lower surface of the fifth insulating layer (115). The second protective layer (150) may protect the lower surface of the fifth insulating layer (115) and the lower surface of the sixth circuit layer (126). Additionally, the second protective layer (150) may include a second opening (not shown) that overlaps in the thickness direction with at least a portion of the lower surface of the sixth circuit layer (126). The second opening may be formed to correspond to the mounting location of an electronic component or the connection location with an external substrate.

[0121] At this time, the first protective layer (140) and the second protective layer (150) may be solder resist, but are not limited thereto.

[0123] Meanwhile, the circuit board of the embodiment may include a plurality of regions. For example, the circuit board may include a first region (R1), a second region (R2), and a third region (R3). For example, the insulating layer (110) may include a first region (R1), a second region (R2), and a third region (R3). For example, the circuit layer (120) may include a first region (R1), a second region (R2), and a third region (R3). For example, the first protective layer (140) may include a first region (R1), a second region (R2), and a third region (R3).

[0124] At this time, the first protective layer (140) in the embodiment may have different structures for each region. For example, the first protective layer (140) of the embodiment may have different heights or open structures in the first region (R1), the second region (R2), and the third region (R3). Below, the outermost insulating layer, the outermost circuit layer, and the outermost protective layer will be described. Preferably, below, the insulating layer disposed on the uppermost side of the circuit board, the circuit layer disposed on the uppermost side, and the protective layer disposed on the uppermost side will be described. The insulating layer, circuit layer, and protective layer described below may refer to the insulating layer, circuit layer, and protective layer disposed on the uppermost side of the circuit board, but are not limited thereto. For example, the insulating layer, circuit layer, and protective layer described below may refer to the insulating layer, circuit layer, and protective layer disposed on the lowermost side of the circuit board.

[0125] Accordingly, below, the third insulating layer (113) placed at the top of the circuit board is referred to as the insulating layer (110), the third circuit layer (123) placed at the top is referred to as the circuit layer (120), and the first protective layer (140) placed at the top is referred to as the protective layer (140).

[0126] The first region (R1), the second region (R2), and the third region (R3) may be distinguished based on differences in the structure of the open region of the protective layer (140). The first region (R1), the second region (R2), and the third region (R3) may be distinguished based on the type of configuration disposed on the circuit board. The first region (R1), the second region (R2), and the third region (R3) may be distinguished based on the line width and spacing of the pads and traces of the circuit layer (120) disposed on the insulating layer (110).

[0127] The first region (R1) may refer to an area where a chip, such as a passive component, is mounted on a circuit board. The second region (R2) may refer to an area where an application chip is mounted on a circuit board. The third region (R3) may refer to an area where a separate upper substrate (e.g., a memory substrate) is attached to the circuit board. Accordingly, the structure of the opening of the protective layer (140) in the first region (R1), the second region (R2), and the third region (R3) may differ from one another.

[0128] Hereinafter, the first region (R1), second region (R2), and third region (R3) of the embodiment will be described in detail.

[0129] For the convenience of explanation, the structures of the second region (R2) and the third region (R3) will be explained first, and finally, the structure of the third region (R3) will be explained.

[0130] FIG. 4 is a diagram showing the structure of a second region of a circuit board according to a first embodiment, and FIG. 5 is a diagram showing the structure of a second region of a circuit board according to a second embodiment.

[0131] Referring to FIG. 4, a second pattern portion (120-2) of a circuit layer (120) is disposed on a second region (R2) of an insulating layer (110). FIG. 4 (a) is a plan view of a second region of a circuit board according to a first embodiment, and FIG. 4 (b) is a cross-sectional view cut along the AA' direction of FIG. 4 (a).

[0132] At this time, the second region (R2) may refer to an area where a microcircuit is required for mounting a processor chip or a driver IC. Hereinafter, the explanation will assume that the chip mounted in the second region (R2) is a processor chip.

[0133] The second pattern portion (120-2) may refer to a circuit pattern disposed in a second chip mounting area in the circuit layer (120) where a processor chip is mounted. The second pattern portion (120-2) includes a second pad (120-21) corresponding to a terminal of the processor chip and a second trace (120-22) connected to the second pad (120-21).

[0134] The second pattern section (120-2) is required to be miniaturized. For example, within the limited space of the second region (R2), traces connected to the pads connected to the terminals must be arranged while placing pads connected to all terminals of the processor chip. Accordingly, the second pattern section (120-2) may include a fine pattern.

[0135] Furthermore, the number of functions processed by processor chips has recently increased. Consequently, it is difficult to implement all functions with a single processor chip. Therefore, it is required to mount two or more processor chips with different functions on a single circuit board.

[0136] Accordingly, when the processor chip includes a first and a second processor chip, miniaturization of the second pattern portion (120-2) is required to connect all wiring between the first processor chip and the second processor chips within a limited space.

[0137] In addition, due to reasons such as 5G, the Internet of Things (IOT), increased image quality, and increased communication speed, the number of terminals within the first processor chip and the second processor chip is gradually increasing. Accordingly, recently, the connection wiring between the first processor chip and the second processor chip may be more than twice, more than three times, or more than ten times that of the conventional wiring.

[0138] Accordingly, in order to mount the first processor chip and the second processor chip on a single circuit board while minimizing the gap between them and to connect the first processor chip and the second processor chip to each other within a limited space, ultra-miniaturization of the second pattern portion (120-2) is required.

[0139] The second pad (120-21) of the second pattern section (120-2) corresponds to a terminal of a processor chip to be mounted on the circuit board. Accordingly, the number of the second pads (120-21) corresponds to the number of terminals of the processor chip.

[0140] The width of the second pad (120-21) in the first direction and the width in the second direction perpendicular to the first direction may differ from each other. In this case, the width of the second pad (120-21) in the direction of separation from an adjacent pad or trace may be smaller than the width in the direction perpendicular to the separation direction. Furthermore, among the widths of the second pad (120-21), the width in the separation direction has a significant effect on the circuit integration density.

[0141] That is, the second pad (120-21) may have an elliptical shape in which the width in the spacing direction is smaller than the width in the direction perpendicular to the spacing direction. However, the embodiment is not limited thereto. For example, the second pad (120-21) may have a circular shape having a width in the spacing direction overall.

[0142] The width (W1) of the second pad (120-21) may be 3 µm to 30 µm. For example, the width (W1) of the second pad (120-21) may be 4 µm to 28 µm. For example, the width (W1) of the second pad (120-21) may be 5 µm to 25 µm.

[0143] If the width (W1) of the second pad (120-21) is less than 3 μm, it may be difficult to place an adhesive member that is stably connected to the terminal of the processor chip. If the width (W1) of the second pad (120-21) is less than 3 μm, the reliability of the connection between the second pad (120-21) and the processor chip may be reduced. If the width (W1) of the second pad (120-21) is greater than 30 μm, it may be difficult to place all patterns connected to the processor chip within a limited space. If the width (W1) of the second pad (120-21) is greater than 30 μm, the size of the circuit board may increase. If the width (W1) of the second pad (120-21) is greater than 30 μm, the spacing between neighboring patterns becomes narrower, and this may cause reliability problems such as circuit shorts.

[0144] The second pattern section (120-2) placed in the second area (R2) includes a second trace (120-22) connected to the second pad (120-21). The second trace (120-22) may refer to a long, thin signal line connected to the second pad (120-21). Additionally, when two processor chips are mounted on the second pattern section (120-2), the second trace (120-22) may include a signal line connecting the two chips.

[0145] The second trace (120-22) may include an ultra-fine pattern. For example, the line width (W2) of the second trace (120-22) may satisfy a range of 1 µm to 10 µm. For example, the line width (W2) of the second trace (120-22) may satisfy a range of 1.2 µm to 8 µm. For example, the line width (W2) of the second trace (120-22) may satisfy a range of 1.5 µm to 7 µm. If the line width (W2) of the second trace (120-22) is smaller than 1 µm, the resistance of the second trace (120-22) increases, and normal communication with processor chips may be difficult as a result. Additionally, if the line width (W2) of the second trace (120-22) is smaller than 1 µm, it may be difficult to apply a general circuit pattern manufacturing process. If the line width (W2) of the second trace (120-22) is smaller than 1 μm, physical reliability issues may occur where the second trace (120-22) collapses due to various factors. If the line width (W2) of the second trace (120-22) is larger than 10 μm, it may be difficult to place all signal lines connected to the terminals of the processor within a limited space. For example, if the line width (W2) of the second trace (120-22) is larger than 10 μm, it may be difficult to place all traces for connecting multiple processor chips within a limited space. For example, if the line width (W2) of the second trace (120-22) is larger than 10 μm, the area of ​​the second region (R2) increases, and the overall size of the circuit board and semiconductor package may increase accordingly.

[0146] Meanwhile, the second pattern section (120-2) may be spaced apart from each other by a certain distance (W3) on the second area (R2). The distance (W3) may refer to the spacing between the second pads (120-21) of the second pattern section (120-2). Additionally, the distance (W3) may refer to the spacing between the second traces of the second pattern section (120-2). Furthermore, the distance (W3) may refer to the spacing between adjacent second pads (120-21) and second traces (120-22) of the second pattern section (120-2).

[0147] The above spacing (W3) may have a range of 1 µm to 10 µm. The above spacing (W3) may have a range of 1.2 µm to 8 µm. The above spacing (W3) may have a range of 1.5 µm to 7 µm. If the above spacing (W3) is smaller than 1 µm, there is a problem where mutually adjacent second traces or second pads are connected to each other, causing an electrical short circuit. For example, if the above spacing (W3) is larger than 10 µm, it may be difficult to place all traces for connecting multiple processor chips within a limited space.

[0148] As described above, relatively dense circuit patterns are arranged in the second region (R2). For example, a second pattern section (120-2) with a smaller width and spacing compared to the first region (R1) or the third region (R3) is arranged in the second region (R2). Furthermore, it may be difficult to form an SRO on the second pad (120-21) of the second pattern section (120-2) with the exposure resolution of a typical solder resist. Accordingly, as shown in FIG. 4 (b), the protective layer (140) may not be arranged in the second region (R2). In other words, the protective layer (140) may not overlap vertically with the second region (R2). That is, the second pattern portion (120-2) placed in the second region (R2) is a fine pattern, and due to the resolution limit for forming the SRO of the protective layer (140), it may be difficult to form the SRO of the protective layer (140) corresponding to the fine pattern in the second region (R2).

[0149] Meanwhile, referring to FIG. 5, the second trace (120-22) placed in the second region (R2) is a fine pattern and is a pattern placed on the outermost layer. The second trace (120-22) has a structure that protrudes over the upper surface of the insulating layer (110). Accordingly, damage may be applied to the second trace (120-22) while the manufacturing process is in progress with the second trace (120-22) formed. As a result, a problem may arise with the physical reliability of the second trace (120-22).

[0150] Accordingly, a second protective pattern (142) of the protective layer (140) can be formed in the second region (R2a) of the second embodiment.

[0151] At this time, the second protection pattern (142) may have the same height or thickness overall on the second region (R2a). Here, the fact that the second protection pattern (142) has the same height or thickness overall may mean that the height difference of the upper surface of the second protection pattern (142) in the second region (R2a) is 3㎛ or less, 2㎛ or less, 1㎛ or less, and 0.5㎛ or less.

[0152] At this time, the thickness (T1) of the second pattern portion (120-2) placed in the second region (R2a) may be 10㎛ to 25㎛.

[0153] Additionally, the second protective pattern (142) of the protective layer (140) may have a thickness (T2) smaller than the thickness (T1) of the second pattern portion (120-2). For example, the thickness (T2) of the second protective pattern (142) may satisfy a range of 40% to 90% of the thickness (T1) of the second pattern portion (120-2). Preferably, the thickness (T2) of the second protective pattern (142) may satisfy a range of 45% to 85% of the thickness (T1) of the second pattern portion (120-2). For example, the thickness (T2) of the second protective pattern (142) may satisfy a range of 50% to 80% of the thickness (T1) of the second pattern portion (120-2).

[0154] For example, the thickness (T2) of the second protective pattern (142) may be 4 µm to 22 µm. For example, the thickness (T2) of the second protective pattern (142) may be 4.5 µm to 21 µm. For example, the thickness (T2) of the second protective pattern (142) may be 5 µm to 20 µm.

[0155] If the thickness (T2) of the second protective pattern (142) is less than 40% of the thickness (T1) of the second pattern portion (120-2), the protective effect of the second pattern portion (120-2) by the second protective pattern (142) may be insufficient. Additionally, if the thickness (T2) of the second protective pattern (142) is greater than 90% of the thickness (T1) of the second pattern portion (120-2), residual resin of the protective layer (140) may exist on the upper surface of the second pattern portion (120-2). If residual resin is present, a problem with electrical reliability may occur.

[0156] As in the first embodiment, the upper and side surfaces of the second pattern portion (120-2) in the second region (R2) may not come into contact with the protective layer (140) entirely.

[0157] Additionally, the upper surface of the second pattern portion (120-2) in the second region (R2a) of the second embodiment may not come into contact with the protective layer (140) entirely. Furthermore, the side surface of the second pattern portion (120-2) in the second region (R2a) of the second embodiment may be partially covered by the protective layer (140). For example, at least a portion of the side surface of the second pattern portion (120-2) may be covered by the protective layer (140), while the remaining at least portion may not come into contact with the protective layer (140).

[0158] That is, in the second embodiment, a protective layer is formed on the second region (R2a) and covers the upper surface of the second pattern portion (120-2) entirely. Then, a process of thinning the protective layer (e.g., corresponding to the process of forming the protective layer of the first region described below) can be carried out. Accordingly, the protective layer (140) of the second embodiment is placed on the second region (R2a), and a protective pattern having a height lower than the upper surface of the second pattern portion (120-2) can be formed overall.

[0160] FIG. 6 is a diagram showing the structure of a third region of a circuit board according to an embodiment.

[0161] FIG. 6(a) is a plan view of the third region of the circuit board of the embodiment, and FIG. 6(b) is a cross-sectional view cut along the BB' direction of FIG. 6(a).

[0162] Referring to FIG. 6 (a) and (b), a third pattern part (120-3) is disposed in the third region (R3) and has a relatively larger width and spacing than the second pattern part (120-2) disposed in the second region (R2).

[0163] The above third region (R3) refers to an area where pads or bumps connected to a separate package substrate, such as a memory substrate, are placed.

[0164] The third pattern section (120-3) includes a third pad (120-31) and a third trace (120-3).

[0165] The width (W4) of the third pad (120-31) satisfies a range of 30 µm to 70 µm. For example, the width (W4) of the third pad (120-31) satisfies a range of 35 µm to 65 µm. For example, the width (W4) of the third region (R3) satisfies a range of 35 µm to 50 µm.

[0166] Additionally, the spacing (W5) between adjacent patterns in the third region (R3) satisfies a range of 10 µm to 40 µm. For example, the spacing (W5) between adjacent patterns in the third region (R3) satisfies a range of 12 µm to 30 µm. For example, the spacing (W5) between adjacent patterns in the third region (R3) satisfies a range of 13 µm to 25 µm.

[0167] And, unlike the second region (R2), the third trace (120-3) of the third pad (120-31) placed in the third region (R3) does not require a fine line width or fine spacing.

[0168] Accordingly, a protective layer (140) having a structure different from that of the second region (R2) is formed in the third region (R3).

[0169] For example, the protective layer (140) includes a third protective pattern (143) placed in the third region (R3).

[0170] The third protective pattern (143) is positioned in the third region (R3) with a thickness greater than that of the third pad (120-31). At this time, the third protective pattern (143) may be positioned to cover at least a portion of the upper surface of the third pad (120-31). Additionally, the third protective pattern (143) includes an opening (143-1) that overlaps in the thickness direction with at least a portion of the upper surface of the third pad (120-31).

[0171] That is, the side of the third pad (120-31) can be entirely covered with the third protective pattern (143) of the protective layer (140).

[0172] And, the upper surface of the third pad (120-31) may be partially covered with the third protective pattern (143) of the protective layer (140).

[0173] Specifically, the third pad (120-31) may include a first portion (120-31a) that overlaps in the thickness direction with the opening (143-1) of the third protective pattern (143) of the protective layer (140), and a second portion (120-31b) that is covered by the third protective pattern (143).

[0174] Additionally, the upper surface of the third trace (120-3) may be entirely covered by the third protective pattern (143) of the protective layer (140). However, the embodiment is not limited thereto, and in the third trace (120-3), a portion of the upper surface adjacent to the third pad (120-31) may not come into contact with the third protective pattern (143) of the protective layer (140).

[0175] In conclusion, the protective layer (140) in the third region (R3) may have an SMD structure.

[0176] As described above, the protective layer (140) of the embodiment has different structures in the second region (R2) and the third region (R3).

[0177] For example, the protective layer (140) may not be placed in the second region (R2). Alternatively, the protective layer (140) may not come into full contact with the upper surface of the second pattern portion (120-2) in the second region (R2a). For example, the protective layer (140) may be located lower than the upper surface of the second pattern portion (120-2) in the second region (R2a).

[0178] Additionally, the protective layer (140) may be positioned higher than the upper surface of the third pattern portion (120-3) in the third region (R3). For example, the protective layer (140) may cover at least a portion of the upper surface of the third pattern portion (120-3) in the third region (R3). For example, the protective layer (140) may have an SMD structure in the third region (R3).

[0180] Meanwhile, the protective layer (140) in the first region (R1) may have a different structure from the second region (R2) and / or the third region (R3). Here, a different structure may mean that the structure of the open portion formed in the protective layer (140) is different, and may mean that the height or thickness is different.

[0182] FIG. 7a is a plan view of a first region of a circuit board according to a first embodiment, FIG. 7b is a cross-sectional view cut along the CC' direction of FIG. 7a, FIG. 7c is a cross-sectional view cut along the DD' direction of FIG. 7a, and FIG. 8 is a perspective view showing a component mounted in the first region of a circuit board according to one embodiment.

[0183] Hereinafter, with reference to FIGS. 7a to 8, the first region of the circuit board according to the embodiment will be described in detail.

[0184] In the first region (R1), a first pattern section (120-1) is disposed having a relatively larger width and spacing than the pattern sections disposed in the second region (R2) and the third region (R3). At this time, the first pattern section (120-1) includes a plurality of pads. At this time, there may be no traces in the first region (R1). That is, the first pattern section (120-1) may include only a plurality of pads. For example, the first pattern section (120-1) may be disposed in the first region (R1) and may include only island pads that are not directly connected to other patterns disposed on the upper surface of the insulating layer (110). However, the embodiment is not limited thereto, and depending on the case, a trace connected to the first pattern section (120-1) may be disposed in the first region (R1).

[0185] The first pattern section (120-1) includes a first pad. For example, the first pattern section (120-1) includes a first-1 pad (120-11) and a first-2 pad (120-12) connected to a first chip.

[0186] The first-1 pad (120-11) may be a pad connected to the first terminal of the first chip, and the first-2 pad (120-12) may be a pad connected to the second terminal of the first chip. Although the drawing shows a first pad connected to one first chip, it is not limited thereto. For example, a plurality of first pads connected to at least two first chips each may be arranged in the first region (R1). Each of the plurality of first pads may include the first-1 pad and the first-2 pad.

[0187] The above-mentioned first-1 pad (120-11) and first-2 pad (120-12) may be large-area pads. For example, the terminals of the first chip have a relatively large size. Here, having a relatively large size may mean that the size of each terminal provided on the first chip is larger than the size of each terminal of the second chip, such as the processor chip.

[0188] The first-1 pad (120-11) and the first-2 pad (120-12) may be spaced apart from each other in a first direction. The first direction may refer to the width direction, the x-axis direction, and the horizontal direction in the drawing.

[0189] The above first-1 pad (120-11) and first-2 pad (120-12) may each have a width (W6) in the first direction that is larger than the width (W7) in the second direction that is perpendicular to the first direction.

[0190] The width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may satisfy a range of 125% to 220% of the width (W7) in the second direction. The width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may satisfy a range of 130% to 210% of the width (W7) in the second direction. The width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may satisfy a range of 140% to 200% of the width (W7) in the second direction.

[0191] If the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) is less than 125% of the width (W7) in the second direction, it may be difficult to stably place the first chip. If the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) is less than 125% of the width (W7) in the second direction, the mountingability of the first chip or electrical reliability with the first chip may be reduced. If the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) exceeds 220% of the width (W7) in the second direction, the placement space of the first pattern portion (120-1) increases, and accordingly, the size of the circuit board may increase.

[0192] For example, the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may have a range of 210 µm ± 15 µm. And, if the width (W6) in the first direction has a range of 210 µm ± 15 µm, the width (W7) in the second direction may have a range of 140 µm ± 15 µm.

[0193] For example, the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may have a range of 310 µm ± 15 µm. And, if the width (W6) in the first direction has a range of 310 µm ± 15 µm, the width (W7) in the second direction may have a range of 190 µm ± 15 µm.

[0194] For example, the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may have a range of 660 µm ± 15 µm. And, if the width (W6) in the first direction has a range of 660 µm ± 15 µm, the width (W7) in the second direction may have a range of 450 µm ± 15 µm.

[0195] Preferably, the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may exceed 195 μm. Preferably, the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may exceed 295 μm. Preferably, the width (W6) in the first direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may exceed 645 μm.

[0196] Preferably, the width (W7) in the second direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may exceed 125 μm. Preferably, the width (W7) in the second direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may exceed 175 μm. Preferably, the width (W7) in the second direction of each of the first-1 pad (120-11) and the first-2 pad (120-12) may exceed 435 μm.

[0197] Meanwhile, the gap (W8) between the first-1 pad (120-11) and the first-2 pad (120-12) in the first region (R1) may satisfy a range of 70% to 120% of the width (W7) in the second direction of each of the first-1 pad (120-11) and the first-2 pad (120-12). The gap (W8) between the first-1 pad (120-11) and the first-2 pad (120-12) in the first region (R1) may satisfy a range of 75% to 115% of the width (W7) in the second direction of each of the first-1 pad (120-11) and the first-2 pad (120-12). The gap (W8) between the first-1 pad (120-11) and the first-2 pad (120-12) in the first region (R1) can satisfy a range of 80% to 110% of the width (W7) in the second direction of each of the first-1 pad (120-11) and the first-2 pad (120-12).

[0198] If the gap (W8) between the first-1 pad (120-11) and the first-2 pad (120-12) in the first region (R1) is less than 70% of the width (W7) in the second direction of each of the first-1 pad (120-11) and the first-2 pad (120-12), a circuit short problem may occur due to the connection between multiple adhesive members during the mounting process of the first chip. If the gap (W8) between the first-1 pad (120-11) and the first-2 pad (120-12) in the first region (R1) exceeds 120% of the width (W7) in the second direction of each of the first-1 pad (120-11) and the first-2 pad (120-12), connectivity with the first chip may be reduced.

[0199] As described above, a first pattern portion (120-1) having a relatively large width and a relatively large gap is disposed in the first region (R1) of the circuit board. Accordingly, the open structure of the protective layer (140) in the first region (R1) generally has an SMD structure. That is, as in the first comparative example, the protective layer (140) in the first region of a general circuit board has an SMD structure that covers at least a portion of the upper surface of the first pattern portion.

[0200] In contrast, in the embodiment, a protective layer (140) is disposed in the first region (R1), and a new open structure is provided so as not to affect the increase in thickness of the semiconductor package by the protective layer (140).

[0201] That is, the protective layer (140) includes a first protective pattern (141) placed in the first region (R1).

[0202] The first protective pattern (141) may have different heights depending on the location. Preferably, the first protective pattern (141) does not come into contact with the upper surface of the first pattern portion (120-1) but comes into contact with at least a portion of the side surface of the first pattern portion (120-1). Here, the fact that the first protective pattern (141) comes into contact with at least a portion of the side surface of the first pattern portion (120-1) means that at least a portion of the side surface of the first pattern portion (120-1) does not come into contact with the first protective layer (140).

[0203] The first protection pattern (141) includes a first part (141-1) adjacent to the first pattern part (120-1) in the first area (R1) and a second part (141-2) other than the first part (141-1).

[0204] The first part (141-1) may be placed in an area adjacent to the first pattern part (120-1) in the first area (R1). Additionally, the second part (141-2) may be placed in an edge area of ​​the first area (R1) excluding the first part (141-1).

[0205] For example, the first portion (141-1) of the first protection pattern (141) may be positioned in the surrounding area of ​​the side of the first-1 pad (120-11) and the first-2 pad (120-12). Additionally, the first portion (141-1) of the first protection pattern (141) may be positioned in the area between the first-1 pad (120-11) and the first-2 pad (120-12). For example, the first portion (141-1) of the first protection pattern (141) includes a first sub-part (141-11) positioned between the first-1 pad (120-11) and the first-2 pad (120-12). Additionally, the first part (141-1) of the first protective pattern (141) includes a second sub-part (141-12) positioned to surround the side of the first-1 pad (120-11), the side of the first-2 pad (120-12), and the side of the first sub-part (141-11).

[0206] That is, the first part (141-1) of the first protection pattern (141) can be arranged on the first area (R1) to surround the surrounding area of ​​the first pattern part (120-1), including the area between the first-1 pad (120-11) and the first-2 pad (120-12).

[0207] The upper surface of the first part (141-1) of the first protection pattern (141) may be positioned lower than the upper surface of the first pattern part (120-1). That is, the thickness (T2) of the first part (141-1) of the first protection pattern (141) may be smaller than the thickness (T1) of the first pattern part (120-1).

[0208] The thickness (T1) of the first pattern portion (120-1) may be 10 µm to 25 µm. Preferably, the thickness (T1) of the first pattern portion (120-1) may be 12 µm to 23 µm. More preferably, the thickness (T1) of the first pattern portion (120-1) may have a thickness of 12 µm to 20 µm.

[0209] The thickness (T2) of the first part (141-1) of the first protection pattern (141) may be 3 µm to 21 µm. The thickness (T2) of the first part (141-1) of the first protection pattern (141) may be 4 µm to 19 µm. The thickness (T2) of the first part (141-1) of the first protection pattern (141) may be 5 µm to 16 µm.

[0210] If the thickness (T2) of the first part (141-1) of the first protective pattern (141) is 3 μm or less, the effect produced by the first part (141-1) of the first protective pattern (141) may be insufficient according to the embodiment. For example, if the thickness (T2) of the first part (141-1) of the first protective pattern (141) is 3 μm or less, the short-circuit prevention effect between a plurality of adhesive members to be placed on the first-1 pad (120-11) and the first-2 pad (120-12) may be insufficient. For example, if the thickness (T2) of the first part (141-1) of the first protective pattern (141) is 3 μm or less, there may be a limit to reducing the gap between the first-1 pad (120-11) and the first-2 pad (120-12). For example, if the thickness (T2) of the first part (141-1) of the first protective pattern (141) exceeds 21 μm, a problem may occur in which residual resin of the protective layer (140) remains on the first-1 pad (120-11) or the first-2 pad (120-12). For example, if the thickness (T2) of the first part (141-1) of the first protective pattern (141) exceeds 21 μm, a reliability problem may occur in which at least a portion of the upper surface of the first-1 pad (120-11) or the first-2 pad (120-12) is covered by the first protective pattern (141) due to process errors.

[0211] Additionally, the thickness (T2) of the first part (141-1) of the first protection pattern (141) may satisfy a range of 40% to 90% of the thickness (T1) of the first pattern part (120-1). Preferably, the thickness (T2) of the first part (141-1) of the first protection pattern (141) may satisfy a range of 45% to 85% of the thickness (T1) of the first pattern part (120-1). For example, the thickness (T2) of the first part (141-1) of the first protection pattern (141) may satisfy a range of 50% to 80% of the thickness (T1) of the first pattern part (120-1).

[0212] Meanwhile, in the embodiment, the height difference (TΔ) between the upper surface of the first pattern part (120-1) and the upper surface of the first part (141-1) of the first protection pattern (141) is 3 μm or more. Preferably, in the embodiment, the height difference (TΔ) between the upper surface of the first pattern part (120-1) and the upper surface of the first part (141-1) of the first protection pattern (141) is 3.5 μm or more. More preferably, in the embodiment, the height difference (TΔ) between the upper surface of the first pattern part (120-1) and the upper surface of the first part (141-1) of the first protection pattern (141) is 4 μm or more. At this time, the upper surface of the first pattern part (120-1) may not be flat, and the upper surface of the first protection pattern (141) may also not be flat. The height difference (TΔ) at this time may refer to the height difference between the top of the first pattern part (120-1) and the top of the first protection pattern (141).

[0213] If the height difference (TΔ) between the upper surface of the first pattern part (120-1) and the upper surface of the first part (141-1) of the first protective pattern (141) is less than 3 μm, a problem may occur in which residual resin remains on the upper surface of the first pattern part (120-1) or in which at least a portion of the upper surface of the first pattern part (120-1) is covered by the first part (141-1) of the first protective pattern (141) due to process error.

[0214] Preferably, the height difference (TΔ) between the upper surface of the first pattern portion (120-1) and the upper surface of the first part (141-1) of the first protective pattern (141) is 3㎛ to 10㎛. By doing so, the first part (141-1) of the first protective pattern (141) having an optimal height can be provided regardless of the thickness of the first pattern portion (120-1). That is, if the height difference (TΔ) exceeds 10㎛, the effect produced by the first part (141-1) may be insufficient.

[0215] Meanwhile, the first protection pattern (141) includes a second part (141-2) disposed around the first part (141-1). The second part (141-2) of the first protection pattern (141) may have a greater thickness than the first part (141-1). Additionally, the second part (141-2) of the first protection pattern (141) may have a greater thickness than the first pattern part (120-1).

[0216] Preferably, the upper surface of the second part (141-2) of the first protection pattern (141) may be positioned higher than the upper surface of the first part (141-1) of the first protection pattern (141). Furthermore, the upper surface of the second part (141-2) of the first protection pattern (141) may be positioned higher than the upper surface of the first pattern part (120-1).

[0217] The thickness (T3) of the second part (141-2) of the first protective pattern (141) may be 17 µm to 45 µm. Preferably, the thickness (T3) of the second part (141-2) of the first protective pattern (141) may be 19 µm to 43 µm. More preferably, the thickness (T3) of the second part (141-2) of the first protective pattern (141) may have a thickness of 19 µm to 40 µm.

[0218] The second part (141-2) of the first protection pattern (141) is arranged to surround the first part (141-1) of the first protection pattern (141).

[0219] At this time, the width (W9) between the first pattern portion (120-1) and the second portion (141-2) of the first part (141-1) of the first protection pattern (141) may have a range of 13 µm to 25 µm. Preferably, the width (W9) between the first pattern portion (120-1) and the second portion (141-2) of the first part (141-1) of the first protection pattern (141) may have a range of 15 µm to 23 µm. The width (W9) between the first pattern portion (120-1) and the second portion (141-2) of the first part (141-1) of the first protection pattern (141) may have a range of 16 µm to 20 µm.

[0220] Specifically, the first-1 pad (120-11) includes a plurality of sides. The plurality of sides of the first-1 pad (120-11) include a first-1 side facing the side of the first-2 pad (120-12) and a first-2 side other than the first-1 side. And, the width (W9) may refer to the horizontal distance between the first-2 side of the first-1 pad (120-11) and the inner wall of the second part (141-2) of the first protective pattern (141) adjacent to the first-2 side.

[0221] Additionally, the first-2 pad (120-12) includes a plurality of sides. The plurality of sides of the first-2 pad (120-12) include a second-1 side facing the first-1 side of the first-1 pad (120-11), and a second-2 side excluding the second-1 side. Furthermore, the width (W9) may refer to the horizontal distance between the second-2 side of the first-2 pad (120-12) and the inner wall of the second portion (141-2) of the first protective layer (140) adjacent to the second-2 side.

[0222] If the width (W9) is less than 13 μm, a problem may occur in which the second part (141-2) of the protective layer (140) overlaps with the first chip in the thickness direction due to manufacturing process errors. For example, the design of the first-1 pad (120-11) and the first-2 pad (120-12) is made considering process errors in the placement process of the first chip. For example, the first chip may be placed on the first-1 pad (120-11) and the first-2 pad (120-12) with a certain error range. And, the width (W9) may take into account the error range. At this time, if the width (W9) is less than 13 μm, a problem may occur in which the error range is not sufficiently covered, and accordingly, a problem may occur in which at least a part of the first chip comes into contact with the second part (141-2) of the first protective pattern (141) during the mounting process of the first chip. In addition, if the width (W9) exceeds 25㎛, the area of ​​the first region (R1) increases, and the overall size of the circuit board may increase accordingly.

[0224] Meanwhile, referring to FIG. 8, the design of the first region (R1) as described above is set based on the size of the first chip (200) placed on the first-1 pad (120-11) and the first-2 pad (120-12). At this time, the first chip (200) may be various chips, but as an example, it may be a multilayer ceramic capacitor.

[0225] The first chip (200) includes a body (210). Additionally, the first chip (200) includes a first terminal (220) disposed on one side of the body (210) and connected to the first-1 pad (120-11). Additionally, the first chip (200) includes a second terminal (230) disposed on the other side of the body (210) and connected to the first-2 pad (120-12). The first terminal (220) and the second terminal (230) may be disposed spaced apart in a second direction, which is the spacing direction between the first-1 pad (120-11) and the first-2 pad (120-12).

[0226] The first chip (200) may have a width (L) in the second direction that is greater than the width (W) in the first direction that is perpendicular to the second direction.

[0227] The width (L) of the first chip (200) in the second direction may satisfy a range of 125% to 220% of the width (W) in the first direction. The width (L) of the first chip (200) in the second direction may satisfy a range of 130% to 210% of the width (W) in the first direction. The width (L) of the first chip (200) in the second direction may satisfy a range of 140% to 200% of the width (W) in the first direction.

[0228] For example, the width (W) in the first direction of the first chip (200) may have a range of 200㎛ ± 15㎛, and the width (L) in the second direction may have a range of 400㎛ ± 15㎛. Also, the thickness (T) of the first chip (200) may have a range of 200㎛ ± 50㎛.

[0229] As another example, the width (W) in the first direction of the first chip (200) may have a range of 300㎛ ± 15㎛, and the width (L) in the second direction may have a range of 600㎛ ± 15㎛. Also, the thickness (T) of the first chip (200) may have a range of 400㎛ ± 100㎛.

[0230] As another example, the width (W) in the first direction of the first chip (200) may have a range of 500 µm ± 15 µm, and the width (L) in the second direction may have a range of 1000 µm ± 15 µm. In this case, the thickness (T) of the first chip (200) may have a range of 450 µm ± 250 µm.

[0231] As another example, the width (W) in the first direction of the first chip (200) may have a range of 800㎛ ± 15㎛, and the width (L) in the second direction may have a range of 1500㎛ ± 15㎛.

[0232] As another example, the width (W) in the first direction of the first chip (200) may have a range of 1300㎛ ± 15㎛, and the width (L) in the second direction may have a range of 2000㎛ ± 15㎛.

[0233] As another example, the width (W) in the first direction of the first chip (200) may have a range of 2000㎛ ± 15㎛, and the width (L) in the second direction may have a range of 2500㎛ ± 15㎛.

[0234] As another example, the width (W) in the first direction of the first chip (200) may have a range of 1500㎛ ± 15㎛, and the width (L) in the second direction may have a range of 3000㎛ ± 15㎛.

[0235] As another example, the width (W) in the first direction of the first chip (200) may have a range of 2500㎛ ± 15㎛, and the width (L) in the second direction may have a range of 3200㎛ ± 15㎛.

[0236] As another example, the width (W) in the first direction of the first chip (200) may have a range of 1600㎛ ± 15㎛, and the width (L) in the second direction may have a range of 4500㎛ ± 15㎛.

[0237] As another example, the width (W) in the first direction of the first chip (200) may have a range of 3000㎛ ± 15㎛, and the width in the second direction may have a range of 4600㎛ ± 15㎛.

[0238] As another example, the width (W) in the first direction of the first chip (200) may have a range of 250㎛ ± 15㎛, and the width (L) in the second direction may have a range of 5000㎛ ± 15㎛.

[0239] As another example, the width (W) in the first direction of the first chip (200) may have a range of 3200㎛ ± 15㎛, and the width (L) in the second direction may have a range of 6300㎛ ± 15㎛.

[0240] As another example, the width (W) in the first direction of the first chip (200) may have a range of 6300㎛ ± 15㎛, and the width in the second direction may have a range of 6900㎛ ± 15㎛.

[0241] As another example, the width (W) in the first direction of the first chip (200) may have a range of 5100㎛ ± 15㎛, and the width (L) in the second direction may have a range of 7400㎛ ± 15㎛.

[0243] The circuit board of the embodiment includes a first region where a first chip is disposed. In the first region of the insulating layer, a first pattern portion and a first protective pattern of the protective layer are disposed. The first protective pattern does not contact the upper surface of the first pattern portion, but contacts at least a portion of the side surface of the first pattern portion. That is, the first protective pattern includes a first portion disposed in a surrounding area adjacent to the first pattern portion and a second portion surrounding the first portion. Furthermore, the first portion of the first protective pattern does not contact the upper surface of the first pattern portion, but contacts at least a portion of the side surface of the first pattern portion. For example, the upper surface of the first portion of the first protective pattern is disposed lower than the upper surface of the first pattern portion. Accordingly, in the embodiment, the thickness and width of the contact member disposed on the first pattern portion can be reduced by utilizing the first portion of the first protective pattern. For example, in the first comparative example, the thickness of the contact member increased due to the placement of the protective layer, and in the second comparative example, the degree of expansion of the contact member increased due to the non-placement of the protective layer, thereby increasing the width of the contact member. In contrast, in the embodiment, the degree of expansion of the contact member can be reduced through the combination of the first and second parts of the first protective pattern, thereby reducing the width of the contact member. Furthermore, in the embodiment, since only the first part of the first protective pattern exists in the area where the first chip is placed, the problem of the thickness of the contact member increasing due to the placement of the protective layer can be resolved.

[0244] Accordingly, in the embodiment, the thickness of the semiconductor package on which the first chip is mounted on the circuit board can be reduced, and thus miniaturization can be achieved. Furthermore, in the embodiment, the degree of expansion of the contact member can be reduced to solve the problem of circuit shorting between adjacent contact members. Accordingly, in the embodiment, the electrical reliability and product reliability of the semiconductor package can be improved. Furthermore, in the embodiment, by solving the circuit shorting problem, it is not necessary to increase the spacing between the first pattern portions, and accordingly, the circuit integration density can be improved.

[0245] In addition, the embodiment can solve the problem of an adhesive member penetrating between the insulating layer and the pad by utilizing the first portion of the first protection pattern, and thereby further improve product reliability.

[0247] Meanwhile, it was explained that the vertical cross-section of the first pattern part (120-1) in the first embodiment has a square shape, and accordingly, the upper surface of the first pattern part (120-1) is flat, and at least a portion of the side of the first pattern part (120-1) does not come into contact with the first protective pattern (141) of the protective layer (140).

[0248] FIG. 9 is a plan view of a first region of a circuit board according to a second embodiment.

[0249] Referring to FIG. 9, the first pattern portion (120-1a) may undergo deformation during the circuit pattern formation process. For example, the upper surface of the first pattern portion (120-1a) may have a curved surface rather than a flat surface.

[0250] Accordingly, the upper surface of the first pad (120-11a) and the second pad (120-12a) of the first pattern part (120-1a) may have a height that varies along the horizontal direction.

[0251] Also, as shown in FIG. 9, when the upper surfaces of the first pad (120-11a) and the second pad (120-12a) have curved surfaces, it may be difficult to determine exactly where the upper surfaces of the first pad (120-11a) and the second pad (120-12a) extend.

[0252] At this time, the upper surface of the first pad (120-11a) and the second pad (120-12a) in the second embodiment may refer to the area from the beginning to the end of the curved surface.

[0253] Accordingly, the first portion (141-1) of the first protective pattern (141) of the protective layer (140) may cover the entire side of the first pad (120-11a) and the second pad (120-12a), or it may cover only a part of it.

[0254] However, the uppermost part (UM2) of the first part (141-1) of the first protection pattern (141) may be positioned lower than the uppermost part (UM1) of the first pad (120-11a) and the second pad (120-12a).

[0256] FIG. 10a is a plan view of a first region of a circuit board according to a third embodiment, FIG. 10b is a cross-sectional view cut along the EE' direction of FIG. 10a, FIG. 10c is a cross-sectional view cut along the FF' direction of FIG. 10a, and FIG. 10d is a modified example of the structure of FIG. 10c.

[0257] Hereinafter, with reference to FIGS. 10a to 10d, the first region of the circuit board according to the third embodiment will be described in detail.

[0258] The first pattern portion (120-1) is disposed in the first region (R1a) of the third embodiment. The first pattern portion (120-1) includes a first-1 pad (120-11) and a first-2 pad (120-12).

[0259] A first protective pattern (141a) of the protective layer (140) is disposed in the first region (R1a).

[0260] The first protective pattern (141a) may have different heights depending on the location. Preferably, the first protective pattern (141a) does not contact the upper surface of the first pattern portion (120-1) but contacts at least a portion of the side surface of the first pattern portion (120-1). Here, the fact that the first protective pattern (141) contacts at least a portion of the side surface of the first pattern portion (120-1) means that at least a portion of the side surface of the first pattern portion (120-1) does not contact the first protective layer (140).

[0261] The first protection pattern (141a) includes a first part (141-1a) adjacent to the first pattern part (120-1) in the first region (R1a) and a second part (141-2a) other than the first part (141-1a).

[0262] For example, the first portion (141-1a) of the first protective pattern (141a) may be placed in at least a portion of the periphery area on the side of the first-1 pad (120-11) and the first-2 pad (120-12). In this case, the first portion (141-1) of the previous embodiment is placed to completely surround the periphery area of ​​the first pad (120-11) and the second pad (120-12). The first portion (141-1) of the previous embodiment is placed to surround the periphery area of ​​the first pad (120-11) and the second pad (120-12) in a closed-loop shape.

[0263] Alternatively, the first portion (141-1a) of the first protection pattern (141a) in the third embodiment may be placed in at least a portion of the surrounding area of ​​the side of the first-1 pad (120-11) and the first-2 pad (120-12). That is, the first portion (141-1a) of the first protection pattern (141a) may not be placed in at least a portion of the surrounding area of ​​the first pad (120-11) and the second pad (120-12). For example, the first portion (141-1a) of the first protection pattern (141a) is placed to surround the surrounding area of ​​the first pad (120-11) and the second pad (120-12) in a closed-loop shape.

[0264] That is, as shown in FIG. 10b, the first portion (141-1a) of the first protection pattern (141a) includes a first sub-part (141-11a) disposed between the first-1 pad (120-11) and the first-2 pad (120-12). Additionally, the first portion (141-1a) of the first protection pattern (141a) includes a second sub-part (141-12a) disposed to surround the side of the first-1 pad (120-11), the side of the first-2 pad (120-12), and the side of the first sub-part (141-11a). The second sub-part (141-12a) may not come into contact with at least a portion of the side of the first-1 pad (120-11) and the side of the first-2 pad (120-12).

[0265] Meanwhile, the first protective pattern (141a) includes a second part (141-2a) disposed around the first part (141-1a). The second part (141-2a) of the first protective pattern (141a) may have a greater thickness than the first part (141-1a). Additionally, the second part (141-2a) of the first protective pattern (141a) may have a greater thickness than the first pattern part (120-1a).

[0266] The second part (141-2a) of the first protection pattern (141a) is arranged to surround the first part (141-1a) of the first protection pattern (141a).

[0267] Additionally, at least a portion of the second part (141-2a) of the first protective pattern (141a) may be in direct contact with the side of the first-1 pad (120-11) and the side of the first-2 pad (120-12).

[0268] For example, the first-1 pad (120-11) includes a plurality of sides. The plurality of sides of the first-1 pad (120-11) include a first-1 side facing the side of the first-2 pad (120-12) and a first-2 side opposite to the first-1 side. And, the second portion (141-2a) of the first protective pattern (141a) can come into direct contact with at least a portion of the first-2 side of the first-1 pad (120-11).

[0269] Additionally, the first-2 pad (120-12) includes a plurality of sides. The plurality of sides of the first-2 pad (120-12) include a second-1 side facing the first-1 side of the first-1 pad (120-11) and a second-2 side opposite to the second-1 side. Furthermore, the second portion (141-2a) of the first protective pattern (141a) may come into direct contact with at least a portion of the second-2 side of the first-2 pad (120-12).

[0270] Accordingly, the embodiment can prevent the adhesive member from moving outward from the first-1 pad (120-11) and the first-2 pad (120-12) by using the second part (141-2a), thereby improving reliability. However, although it was stated that the second part (141-2a) is in direct contact with a part of the side of the first-1 pad (120-11) and the first-2 pad (120-12), in such a structure, when a first chip is mounted on the first-1 pad (120-11) and the first-2 pad (120-12), the structure has a structure that does not overlap with the first chip of the second part (141-2a) in the thickness direction.

[0271] Meanwhile, as shown in FIG. 10d, the second part (141-2a) may be in contact with one side of the first pad (120-11) and the first pad (120-12), but not with the other side.

[0272] That is, the second part (141-2a) may include a first sub-part (141-22a) that is in direct contact with at least a portion of the first-2 side of the first-1 pad (120-11).

[0273] Additionally, the second part (141-2a) may include a second sub-part (141-21a) positioned around the first part (141-1a) without contacting the entire side of the first-second pad (120-12).

[0275] FIG. 11a is a plan view of a first region of a circuit board according to a fourth embodiment, and FIG. 11b is a cross-sectional view cut along the GG' direction of FIG. 10a.

[0276] Hereinafter, with reference to FIGS. 11a to 11b, the first region of the circuit board according to the fourth embodiment will be described in detail.

[0277] The first pattern portion (120-1) is disposed in the first region (R1b) of the fourth embodiment. The first pattern portion (120-1) includes a first-1 pad (120-11) and a first-2 pad (120-12).

[0278] A first protective pattern (141b) of the protective layer (140) is disposed in the first region (R1b).

[0279] The first protective pattern (141b) may have different heights depending on the location. Preferably, the first protective pattern (141b) may partially contact the upper surface of the first pattern portion (120-1) and partially contact the side surface of the first pattern portion (120-1).

[0280] The first protection pattern (141b) includes a first part (141-1b) adjacent to the first pattern part (120-1) in the first region (R1b) and a second part (141-2b) other than the first part (141-1b).

[0281] For example, the first portion (141-1b) of the first protective pattern (141b) may be placed in at least a portion of the periphery area on the side of the first-1 pad (120-11) and the first-2 pad (120-12). In this case, the first portion (141-1) of the previous embodiment is placed to completely surround the periphery area of ​​the first pad (120-11) and the second pad (120-12). The first portion (141-1) of the previous embodiment is placed to surround the periphery area of ​​the first pad (120-11) and the second pad (120-12) in a closed-loop shape.

[0282] Alternatively, the first portion (141-1b) of the first protection pattern (141b) in the fourth embodiment may be placed in at least a portion of the surrounding area of ​​the side of the first-1 pad (120-11) and the first-2 pad (120-12). That is, the first portion (141-1b) of the first protection pattern (141b) may not be placed in at least a portion of the surrounding area of ​​the first pad (120-11) and the second pad (120-12). For example, the first portion (141-1b) of the first protection pattern (141b) may be placed to surround the surrounding area of ​​the first pad (120-11) and the second pad (120-12) in a closed-loop shape.

[0283] That is, as shown in FIG. 11a and FIG. 11b, the first part (141-1b) of the first protection pattern (141b) is placed between the first-1 pad (120-11) and the first-2 pad (120-12).

[0284] Additionally, the first part (141-1b) of the first protection pattern (141b) may come into contact with at least a portion of the side of the first-1 pad (120-11) and the side of the first-2 pad (120-12).

[0285] Meanwhile, the first protective pattern (141b) includes a second part (141-2b) disposed around the first part (141-1b). The second part (141-2b) of the first protective pattern (141b) may have a greater thickness than the first part (141-1b). Additionally, the second part (141-2b) of the first protective pattern (141b) may have a greater thickness than the first pattern part (120-1b).

[0286] The second part (141-2b) of the first protection pattern (141b) is arranged to surround the first part (141-1b) of the first protection pattern (141b).

[0287] Additionally, at least a portion of the second part (141-2b) of the first protection pattern (141b) may be in direct contact with the upper and side surfaces of the first-1 pad (120-11) and the upper and side surfaces of the first-2 pad (120-12).

[0288] For example, the first-1 pad (120-11) includes a plurality of sides. The plurality of sides of the first-1 pad (120-11) include a first-1 side facing the side of the first-2 pad (120-12) and a first-2 side (S12) opposite to the first-1 side (S11). And, the second portion (141-2b) of the first protection pattern (141b) may contact the first-2 side (S12) of the first-1 pad (120-11) and a portion of the upper surface of the first-1 pad (120-11) adjacent to the first-2 side (S12).

[0289] Additionally, the first-2 pad (120-12) includes a plurality of sides. The plurality of sides of the first-2 pad (120-12) include a second-1 side (S21) facing the first-1 side (S11) of the first-1 pad (120-11), and a second-2 side (S22) opposite to the second-1 side (S21). Furthermore, the second portion (141-2b) of the first protective pattern (141b) may come into contact with the second-2 side (S22) of the first-2 pad (120-12) and a portion of the upper surface of the first-2 pad (120-12) adjacent to the second-2 side (S22).

[0290] Accordingly, the embodiment can prevent the adhesive member from moving outward from the first-1 pad (120-11) and the first-2 pad (120-12) by using the second part (141-2b), thereby improving reliability. However, although it was stated that the second part (141-2b) is in direct contact with parts of the upper and side surfaces of the first-1 pad (120-11) and the first-2 pad (120-12), in such a structure, when a first chip is mounted on the first-1 pad (120-11) and the first-2 pad (120-12), the structure has a structure that does not overlap with the first chip in the thickness direction of the second part (141-2b).

[0292] FIG. 12 is a cross-sectional view showing a semiconductor package according to an embodiment, FIG. 13a is an enlarged view of the placement area of ​​the first chip of FIG. 12 according to a first embodiment, and FIG. 13b is an enlarged view of the placement area of ​​the first chip of FIG. 12 according to a second embodiment.

[0293] The semiconductor package of the embodiment may have a structure in which a chip is mounted on at least one circuit board previously described.

[0294] For example, the semiconductor package may include a first connection portion (310) disposed on a first pattern portion (121) of the circuit layer (120).

[0295] The first connection part (310) may include a spherical shape. For example, the cross-section of the first connection part (310) may include a circular shape or a semicircular shape. For example, the cross-section of the first connection part (310) may include a partially or entirely rounded shape. The cross-sectional shape of the first connection part (310) may be flat on one side and curved on the other side. The first connection part (310) may be a solder ball, but is not limited thereto.

[0296] Alternatively, the first connecting part (310) may have a cuboid shape. For example, the cross-section of the first connecting part (310) may include a rectangular shape. The cross-section of the first connecting part (310) may include a rectangle or a square.

[0297] A first chip (200) may be mounted on the first connection portion (310). The first chip (200) may be a passive chip. For example, the first chip (200) may be a multilayer ceramic capacitor, but is not limited thereto. Meanwhile, although the drawing shows that one first chip (200) is placed in a semiconductor package, a plurality of first chips may substantially be placed in the first region of the embodiment.

[0298] Additionally, the semiconductor package includes a second connection portion (320) disposed on a second pattern portion (122) of the circuit layer (120).

[0299] And, a second chip (400) is placed on the second connection part (320). The second chip (420) may be a processor chip. For example, the second chip (400) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller.

[0300] At this time, a terminal (425) may be included on the lower surface of the second chip (400), and the terminal (425) may be electrically connected to the second pattern portion (120-2) of the circuit board through the second connection portion (320).

[0301] Meanwhile, the semiconductor package of the embodiment may be configured such that a plurality of second chips are arranged on a single circuit board at a mutually spaced interval. For example, the second chips may include a second-1 chip and a second-2 chip that are spaced apart from each other.

[0302] Also, the 2-1 chip and the 2-2 chip may be different types of application processor (AP) chips.

[0303] Meanwhile, the 2-1 chip and the 2-2 chip may be spaced apart at a certain distance on the circuit board. For example, the spacing between the 2-1 chip and the 2-2 chip may be 150 μm or less. For example, the spacing between the 2-1 chip and the 2-2 chip may be 120 μm or less. For example, the spacing between the 2-1 chip and the 2-2 chip may be 100 μm or less.

[0304] Preferably, for example, the spacing between the second-1 chip and the second-2 chip may range from 60 µm to 150 µm. For example, the spacing between the second-1 chip and the second-2 chip may range from 70 µm to 120 µm. For example, the spacing between the second-1 chip and the second-2 chip may range from 80 µm to 110 µm. For example, if the spacing between the second-1 chip and the second-2 chip is less than 60 µm, problems with the operational reliability of the second-1 chip or the second-2 chip may occur due to mutual interference between the second-1 chip and the second-2 chip. For example, if the spacing between the second-1 chip and the second-2 chip is greater than 150 µm, signal transmission loss may increase as the distance between the second-1 chip and the second-2 chip increases.

[0305] Additionally, the semiconductor package further includes a third connection portion (330) disposed in a third region (R3). The third connection portion (330) may be disposed on a third pattern portion (120-3) of the circuit layer (120) of the embodiment. The third connection portion (330) may be a connection portion for connecting to a separate external substrate (e.g., a memory substrate).

[0306] Additionally, the semiconductor package may include a molding layer (500). The molding layer (500) may be disposed to cover the first chip (200) and the second chip (400). For example, the molding layer (500) may be an EMC (Epoxy Mold Compound) formed to protect the mounted first chip (200) and the second chip (400), but is not limited thereto. The molding layer (500) may include an opening that exposes the upper surface of the third connection portion (330). For example, the upper surface of the third connection portion (330) may not come into contact with the molding layer (500). The third connection portion (330) may be a solder ball, or alternatively, a post bump.

[0307] At this time, the molding layer (500) may have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding layer (500) may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer (500) may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer (500) may be 0.8 to 5. Accordingly, in the embodiment, the molding layer (500) is made to have a low dielectric constant so that heat dissipation characteristics for heat generated from the first chip (200) and the second chip (400) can be enhanced.

[0308] Meanwhile, the package substrate may include a fourth connection portion (340) disposed at the lowest side of the circuit board. The fourth connection portion (340) may be for joining between the semiconductor package and an external substrate (e.g., the main board of an external device).

[0309] Meanwhile, as shown in FIG. 13a, in the embodiment, a first connection part (310) is placed on the first-1 pad (120-11) and the first-2 pad (120-12) of the first pattern part (120-1).

[0310] At this time, the first connection portion (310) contacts at least a portion of the side of the first-1 pad (120-11) and the first-2 pad (120-12). And, the first connection portion (310) does not contact at least a portion of the side of the first-1 pad (120-11) and the first-2 pad (120-12). For example, the first connection portion (310) may contact the upper surface of the first portion (141-1) of the first protective pattern (141) of the protective layer (140).

[0311] Accordingly, the lowest end of the first connection part (310) in the embodiment may be positioned higher than the upper surface of the insulating layer (110). Additionally, the lowest end of the first connection part (310) in the embodiment is positioned higher than the lower surface of the first pattern part (120-1) and lower than the upper surface.

[0312] Accordingly, in the embodiment, the width (W10) of the first connection part (310) can be reduced compared to the comparative example. For example, the width (W10) of the first connection part (310) may be 125% or less of the width in the second direction of the first-1 pad (120-11) and the first-2 pad (120-12). For example, the width (W10) of the first connection part (310) may be 120% or less of the width in the second direction of the first-1 pad (120-11) and the first-2 pad (120-12). Accordingly, in the embodiment, the gap (W11) between the first connection part placed on the first-1 pad (120-11) and the first connection part placed on the first-2 pad (120-12) can be increased compared to the comparative example.

[0313] For example, if the spacing between the first-1 pad and the first-2 pad of the comparative example and the embodiment is the same, the spacing (W11) between the plurality of first connection parts of the embodiment may be 90% or less, 80% or less, and further 70% or less of the spacing between the plurality of first connection parts of the comparative example.

[0314] Meanwhile, the first connection part (310) in FIG. 13a had the shape of a circular solder ball.

[0315] Alternatively, as illustrated in FIG. 13b, the first connection portion (310B) of the second embodiment may have a solder fillet form. For example, the first connection portion (310B) of the second embodiment may be a paste.

[0316] And, the first connection portion (310B) can form a solder fillet that extends to the side of the first chip (200B) as the first chip (200B) is seated while the first connection portion (310B) is positioned on the first-1 pad (120-11) and the first-2 pad (120-12).

[0317] In addition, when the first connection part (310B) of the second embodiment is applied and the first chip (200B) is mounted, the distance between the first pattern part (120-1) and the first chip (200B) (e.g., distance in the vertical direction or thickness direction) can be further reduced compared to the first embodiment. At this time, when the first connection part (310B) of the second embodiment is applied, the first part (141-1) of the first protection pattern (141) of the protection layer (140) between the first-1 pad (120-11) and the first-2 pad (120-12) may be omitted. However, even when the first connection part (310B) of the second embodiment is applied, a problem may occur in which the first connection part (310B) penetrates between the insulating layer and the first pattern part. Furthermore, a circuit short problem may occur in which the first-1 pad (120-11) and the first-2 pad (120-12) are electrically connected to each other by the first connection part (310B). Accordingly, in the second embodiment, a first part (141-1) of the first protection pattern (141) of the protection layer (140) is placed between the first-1 pad (120-11) and the first-2 pad (120-12), thereby resolving the reliability problem caused by the flow of the first connection part (310B).

[0319] The circuit board of the embodiment includes a first region where a first chip is disposed. In the first region of the insulating layer, a first pattern portion and a first protective pattern of the protective layer are disposed. The first protective pattern does not contact the upper surface of the first pattern portion, but contacts at least a portion of the side surface of the first pattern portion. That is, the first protective pattern includes a first portion disposed in a surrounding area adjacent to the first pattern portion and a second portion surrounding the first portion. Furthermore, the first portion of the first protective pattern does not contact the upper surface of the first pattern portion, but contacts at least a portion of the side surface of the first pattern portion. For example, the upper surface of the first portion of the first protective pattern is disposed lower than the upper surface of the first pattern portion. Accordingly, in the embodiment, the thickness and width of the contact member disposed on the first pattern portion can be reduced by utilizing the first portion of the first protective pattern. For example, in the first comparative example, the thickness of the contact member increased due to the placement of the protective layer, and in the second comparative example, the degree of expansion of the contact member increased due to the non-placement of the protective layer, thereby increasing the width of the contact member. In contrast, in the embodiment, the degree of expansion of the contact member can be reduced through the combination of the first and second parts of the first protective pattern, thereby reducing the width of the contact member. Furthermore, in the embodiment, since only the first part of the first protective pattern exists in the area where the first chip is placed, the problem of the thickness of the contact member increasing due to the placement of the protective layer can be resolved.

[0320] Accordingly, in the embodiment, the thickness of the semiconductor package on which the first chip is mounted on the circuit board can be reduced, and thus miniaturization can be achieved. Furthermore, in the embodiment, the degree of expansion of the contact member can be reduced to solve the problem of circuit shorting between adjacent contact members. Accordingly, in the embodiment, the electrical reliability and product reliability of the semiconductor package can be improved. Furthermore, in the embodiment, by solving the circuit shorting problem, it is not necessary to increase the spacing between the first pattern portions, and accordingly, the circuit integration density can be improved.

[0321] In addition, the embodiment can solve the problem of an adhesive member penetrating between the insulating layer and the pad by utilizing the first portion of the first protection pattern, and thereby further improve product reliability.

[0323] FIGS. 14 to 21 are cross-sectional views showing the manufacturing process of a circuit board according to an embodiment in process order.

[0324] Referring to FIG. 14, in an embodiment, a first insulating layer (111) that serves as the basis for manufacturing a circuit board is prepared. The first insulating layer (111) may be a core layer, but is not limited thereto.

[0325] Next, the embodiment forms a first penetrating electrode (131) that penetrates the first insulating layer (111). Then, the embodiment proceeds with the process of forming a first circuit layer (121) on the upper surface of the first insulating layer (111) and forming a fourth circuit layer (124) on the lower surface of the first insulating layer (111) together with the formation of the first penetrating electrode (131).

[0326] Next, referring to FIG. 15, the embodiment laminates a second insulating layer (112) on the upper surface of the first insulating layer (111) and laminates a fourth insulating layer (114) on the lower surface of the first insulating layer (111).

[0327] Subsequently, the embodiment proceeds with the process of forming a second through electrode (132) and a second circuit layer (122) on the second insulating layer (112). Additionally, the embodiment proceeds with the process of forming a fourth through electrode (132) and a fifth circuit layer (125) on the fourth insulating layer (114).

[0328] Next, referring to FIG. 16, the embodiment laminates a third insulating layer (113) on the upper surface of the second insulating layer (112) and laminates a fifth insulating layer (115) on the lower surface of the fourth insulating layer (114).

[0329] Subsequently, the embodiment proceeds with the process of forming a third through electrode (133) and a third circuit layer (123) on the third insulating layer (113). Additionally, the embodiment proceeds with the process of forming a fifth through electrode (135) and a sixth circuit layer (126) on the fifth insulating layer (115).

[0330] Next, referring to FIG. 17, the embodiment forms a first solder resist layer (140L) on a third insulating layer (113) and a second solder resist layer (150L) under a fifth insulating layer (115). At this time, the first solder resist layer (140L) is positioned to completely cover the third circuit layer (123) on the third insulating layer (113). Additionally, the second solder resist layer (150L) is positioned to completely cover the sixth circuit layer (126) under the fifth insulating layer (115).

[0331] Next, referring to FIG. 18, the embodiment may proceed with a process of partially exposing and curing the first solder resist layer (140L) and the second solder resist layer (150L), respectively.

[0332] Accordingly, the first solder resist layer (140L) in the embodiment may undergo separate exposure and curing in the first region (R1), the second region (R2), and the third region (R3), respectively. Accordingly, the first region (R1) may include a cured region (140L1) and an uncured region (140L2). At this time, the cured region (140L1) in the first region (R1a) does not overlap perpendicularly with the third circuit layer (123) placed in the first region (R1a).

[0333] Additionally, the second region (R2) may include only an uncured region (140L2). Additionally, the third region (R3) may include a cured region (140L1) and an uncured region (140L2).

[0334] Next, referring to FIG. 19, in the embodiment, a thinning process can be performed to develop the uncured area (140L2). By the thinning process, the height of the uncured area (140L2) can be reduced. At this time, the height of the uncured area (140L2) can be freely adjusted by controlling the thinning process conditions (e.g., process time).

[0335] The above thinning process may include a process of thinning an uncured area (140L2) using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline), etc.

[0336] Next, referring to FIG. 20, in the embodiment, a process of curing the uncured area (140L2) of the first region (R1) can be carried out. At this time, according to the first embodiment, since the second region (R2) has a structure in which the protective layer (140) is not disposed therein, the uncured area (140L2) in the second region (R2) may not be cured. However, since the second protective pattern (142) remains in the second region (R2) of the second embodiment, a process of curing the uncured area of ​​the second region (R2) can be carried out.

[0337] Next, referring to FIG. 21, the embodiment may proceed with a process of removing all of the protective layer (140) present in the second region (R2) by thinning the uncured region of the second region (R2).

[0339] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0340] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0341] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0342] Although the above description has focused on embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art to which the embodiments pertain will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

Claim 1 Insulating layer; circuit layer disposed on the insulating layer; The circuit layer comprises a protective layer disposed on the insulating layer, wherein the circuit layer comprises a first pattern portion disposed on a first region of the insulating layer and including a first-1 pad and a first-2 pad spaced apart from each other, and the protective layer comprises a first protective pattern disposed on the first region of the insulating layer, wherein the first protective pattern comprises a first portion disposed in an adjacent region of the first pattern portion including a region between the first-1 pad and the first-2 pad in the first region and having a thickness smaller than the thickness of the first pattern portion, and a second portion disposed in an edge region of the first region excluding the adjacent region and having a thickness larger than the thickness of the first pattern portion, wherein each of the first-1 pad and the first-2 pad has a width in a first direction and a width in a second direction different from each other, and the first-1 pad comprises a first-1 side facing the first-2 pad and a first-2 side opposite to the first-1 side, and the first-2 pad comprises a second-1 side facing the first-1 side and the A circuit board comprising a second-2 side opposite to a second-1 side, wherein each of the first-1 side and the second-1 side is in direct contact with the first part and not with the second part, and a portion of each of the first-2 side and the second-2 side is in direct contact with the first part, and the remainder of each of the first-2 side and the second-2 side is in direct contact with the second part. Claim 2 A circuit board according to claim 1, wherein the thickness of the first portion of the first protection pattern satisfies a range of 40% to 90% of the thickness of the first pattern portion. Claim 3 A circuit board according to claim 1 or 2, wherein the thickness of the first pattern portion satisfies the range of 10㎛ to 25㎛, and the thickness of the first portion of the first protection pattern satisfies the range of 3㎛ to 21㎛. Claim 4 A circuit board according to claim 1 or 2, wherein the difference between the thickness of the first pattern portion and the thickness of the first portion of the first protection pattern is 3㎛ to 10㎛. Claim 5 A circuit board according to claim 4, wherein the upper surface of the first pattern portion includes a curved surface, and the difference between the thickness of the first pattern portion and the thickness of the first part of the first protection pattern is the vertical distance between the top of the first pattern portion and the top of the first part of the first protection pattern. Claim 6 In paragraph 3, the thickness of the second portion of the first protection pattern satisfies the range of 17㎛ to 45㎛, a circuit board. Claim 7 A circuit board according to claim 1, wherein the first-1 pad and the first-2 pad are spaced apart in the second direction perpendicular to the first direction on the first region of the insulating layer, and the width of each of the first-1 pad and the first-2 pad in the first direction has a range of 125% to 220% of the width of each of the first-1 pad and the first-2 pad in the second direction. Claim 8 A circuit board according to claim 7, wherein the width of each of the first-1 pad and the first-2 pad in the first direction exceeds 195 μm, and the width of each of the first-1 pad and the first-2 pad in the second direction exceeds 125 μm. Claim 9 A circuit board according to claim 7 or 8, wherein the gap between the first-1 pad and the first-2 pad satisfies a range of 70% to 120% of the width in the second direction of each of the first-1 pad and the first-2 pad. Claim 10 A circuit board according to claim 1, wherein the inner wall of the second portion of the first protection pattern is spaced apart from the side of the first pattern portion by a distance of 15 μm to 23 μm. Claim 11 In claim 1, the circuit board, wherein the first pattern portion does not overlap with the protective layer in the thickness direction. Claim 12 In claim 1, the second portion of the first protection pattern is in direct contact with at least a portion of the side of the first-1 pad and the side of the first-2 pad, a circuit board. Claim 13 In claim 11, the first-1 pad further comprises a first-3 side and a first-4 side disposed between the first-1 side and the first-2 side, and the first-2 pad further comprises a second-3 side and a second-4 side disposed between the second-1 side and the second-2 side, wherein each of the first-3 side, the first-4 side, the second-3 side, and the second-4 side is in direct contact with the first part and not in contact with the second part, a circuit board. Claim 14 A circuit board according to claim 1, wherein the circuit layer is disposed on a second region of the insulating layer and includes a second pattern portion comprising a second pad and a second trace, wherein the second pad has a width in the range of 3 μm to 30 μm, the second trace has a width in the range of 1 μm to 10 μm, and the gap between the second pad and the second trace has a range of 1 μm to 10 μm. Claim 15 In paragraph 14, the circuit board, wherein the protective layer is not disposed on the second region of the insulating layer. Claim 16 A circuit board according to claim 14, wherein the protective layer comprises a second protective pattern disposed on the second region, the second protective pattern does not overlap with the second pattern portion in the thickness direction, and the upper surface of the second protective pattern is positioned lower than the upper surface of the second pattern portion. Claim 17 A circuit board according to claim 1, wherein the circuit layer is disposed on a third region of the insulating layer and includes a third pattern portion comprising a plurality of third pads and a plurality of third traces, the width of the third pad satisfies a range of 30 μm to 70 μm, and the spacing between the third pads and the third traces satisfies a range of 10 μm to 40 μm, and the protective layer is disposed on the third region covering at least a portion of the upper surface of the third pad and includes a third protective pattern comprising an opening that overlaps in the thickness direction with the remaining portion of the upper surface of the third pad. Claim 18 Insulating layer; a first pattern portion comprising a first-1 pad and a first-2 pad spaced apart from each other and disposed on a first region of the insulating layer; a first connection portion comprising a first-1 connection portion disposed on the first-1 pad and a first-2 connection portion disposed on the first-2 pad; a first chip disposed on the first connection portion; and includes a protective layer disposed on the insulating layer, wherein the protective layer includes a first protective pattern disposed on the first region, and the first protective pattern includes a first portion disposed in an adjacent region of the first pattern portion, which includes the area between the first-1 pad and the first-2 pad in the first region, and has a thickness smaller than the thickness of the first pattern portion, and a second portion disposed in an edge region of the first region excluding the adjacent region and has a thickness larger than the thickness of the first pattern portion, wherein each of the first-1 pad and the first-2 pad has a width in the first direction and a width in the second direction different from each other, and the first-1 pad includes a first-1 side facing the first-2 pad and a first-2 side opposite to the first-1 side, and the first-2 pad includes a second-1 side facing the first-1 side and a second-2 side opposite to the second-1 side, and each of the first-1 side and the second-1 side is in direct contact with the first portion and with the second portion A semiconductor package that does not come into contact, wherein a portion of each of the first-2 side and the second-2 side is in direct contact with the first portion, and the remainder of each of the first-2 side and the second-2 side is in direct contact with the second portion. Claim 19 A semiconductor package according to claim 18, wherein the first-1 pad further comprises a first-3 side and a first-4 side disposed between the first-1 side and the first-2 side, and the first-2 pad further comprises a second-3 side and a second-4 side disposed between the second-1 side and the second-2 side, and each of the first-3 side, the first-4 side, the second-3 side, and the second-4 side is in direct contact with the first part and not with the second part. Claim 20 A semiconductor package according to claim 18, further comprising: a second pattern portion disposed on a second region of the insulating layer; a second connection portion disposed on the second pattern portion; and a second chip disposed on the second connection portion, wherein the second chip comprises a processor chip, and the protective layer is not disposed on the second region of the insulating layer. Claim 21 A semiconductor package according to claim 18, comprising: a third pattern portion disposed on a third region of the insulating layer; and a third connection portion disposed on the third pattern portion, wherein the protective layer comprises a third protective pattern that covers at least a portion of the upper surface of the third pattern portion and includes an opening that overlaps in the thickness direction with the remaining portion of the upper surface of the third pattern portion.

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