Multilayer ceramic capacitor

Abstract

Providing a highly reliable multilayer ceramic capacitor with suppressed insulation resistance degradation. An inner layer portion having a first internal electrode layer and a second internal electrode layer alternately stacked with a dielectric layer formed of a ceramic dielectric in between, a first main surface which is a surface in the stacking direction, a second main surface which is a surface opposite to the first main surface, a first side surface which is a surface in the width direction orthogonal to the first main surface and the second main surface and has the first internal electrode layer and the second internal electrode layer drawn out, a second side surface which is a surface opposite to the first side surface and has the first internal electrode layer and the second internal electrode layer drawn out, a first cross-section which is a surface in the length direction orthogonal to the first main surface, the second main surface, the first side surface, and the second side surface and has the first internal electrode layer drawn out, and a second cross-section which is a surface opposite to the first cross-section and has the second internal electrode layer drawn out, an inner layer portion formed of a ceramic dielectric and covering the first main surface from the stacking direction, and a first outer layer portion formed of a ceramic dielectric and covering the second main surface A second outer layer portion covering from the stacking direction is formed of a ceramic dielectric, and the inner layer portion, the first outer layer portion, and the second outer layer portion are covered from one side in the width direction by a first side margin portion formed of a ceramic dielectric, and the inner layer portion, the first outer layer portion, and the second outer layer portion are covered from the other side in the width direction by a second side margin portion, and a pair of external electrodes are provided on the first cross section and the second cross section and connected to each of the first internal electrode layer and the second internal electrode layer, and the dielectric particles constituting each of the ceramic dielectrics constituting the inner layer portion, the first side margin portion, and the second side margin portion include dielectric particles having empty holes inside, and the ratio of empty holes within the particles at the central portion of the inner layer portion (inner layer central portion) (N[inner layer central portion]) and the ratio of empty holes within the particles at the first side margin portion and the second side margin portion (N[side margin portion]) are given by the formula: N[inner layer Satisfying the relationship [Central] < N [Side Margin],A multilayer ceramic capacitor in which the diameter D50 of a dielectric particle at the widthwise end (inner layer W end) of the inner layer (D5[(inner layer W end)) and the diameter D50 of a dielectric particle at the center (inner layer center) of the inner layer (D50[inner layer center]) satisfy the relationship: 1.00 ≤ D50[inner layer W end] / D50[inner layer center] ≤ 1.40.

Description

Technology Field

[0001] The present invention relates to a multilayer ceramic capacitor. Background Technology

[0002] With the miniaturization of electronic devices, including mobile phones, and the increase in CPU speeds, the demand for Multilayer Ceramic Capacitors (MLCCs) is steadily rising. Multilayer Ceramic Capacitors contain thin, high-dielectric constant dielectric layers. Consequently, they possess large capacitance while remaining compact. Although MLCCs made from various materials are known, those utilizing ceramic dielectrics such as barium titanate (BaTiO3) for the dielectric layer and non-metals such as nickel (Ni) for the internal electrode layer are widely used because they offer high performance at a low cost.

[0003] A multilayer ceramic capacitor comprises an inner layer portion in which dielectric layers formed of ceramic dielectrics and internal electrode layers are alternately stacked, an outer layer portion covering the upper and lower parts of the inner layer portion, and a side margin portion covering the inner and outer layers in the width direction. The inner layer portion acts as a capacitive element. The outer layer portion and the side margin portion are regions provided around the inner layer portion that do not include internal electrode layers. It can be said that they serve to protect the inner layer portion, which acts as a capacitive element, from the external environment.

[0004] Multilayer ceramic capacitors are required to increase the capacitance per unit volume (volume capacitance) while simultaneously increasing the rated voltage. To increase volume capacitance, it is effective to thin the thickness of the dielectric layer and the internal electrode layer, and to increase the number of layers as much as possible so that they are electrically connected in parallel—that is, to make them multilayer. In addition, it is also effective to reduce the volume of the outer layer, the side margin, and the internal electrode lead portion among the components of the multilayer ceramic capacitor. As a result, the volume of the inner layer, which functions as a capacitive element, becomes relatively larger, making it possible to increase the volume capacitance.

[0005] Meanwhile, the ceramic dielectric of a multilayer ceramic capacitor is fabricated by firing dielectric powders such as BaTiO3 powder. Dielectric powders are synthesized using methods such as the solid-state method, hydrothermal method, sol-gel method, alkoxide method, sorbothermal method, or oxalate method. Among these, the hydrothermal method (hydrothermal synthesis method) is a method of synthesizing inorganic powders using an aqueous solution under high temperature and pressure, and it has the advantage of being able to manufacture fine powders with uniform particle sizes at a relatively low cost. Therefore, manufacturing multilayer ceramic capacitors using dielectric powders synthesized by the hydrothermal method (hydrothermal synthesis powder) enables thinning of the dielectric layer and high capacitance. Furthermore, since non-uniformity in the particle size of the dielectric particles is suppressed, it becomes possible to improve dielectric constant and reliability.

[0006] In the hydrothermal method, hydroxides are used as raw materials. For example, Ba sources such as barium hydroxide (Ba(OH)2) and Ti sources such as metatitanate (TiO(OH)2) or titanium oxide (TiO2) are reacted in water at high temperature and high pressure, and the resulting reaction product is heat-treated to obtain BaTiO3 powder. The OH groups contained in the hydroxides are detached from the raw materials during heat treatment, but this results in the formation of voids (voids within the particles) inside the particles constituting the dielectric powder. When a multilayer ceramic capacitor is manufactured using dielectric powder having voids within the particles, voids within the particles remain in the resulting capacitor. In contrast, when dielectric powder synthesized by a method other than the hydrothermal method is used, voids within the particles are not formed.

[0007] Patent Document 1 discloses the use of hydrothermally synthesized powder in the dielectric layer of a multilayer ceramic capacitor. Specifically, a method for manufacturing a ceramic capacitor is disclosed, comprising a manufacturing process for producing a green sheet using a ceramic slurry containing a first ceramic powder synthesized by a hydrothermal method and a second ceramic powder synthesized by a method other than hydrothermal method, and a process for firing the obtained green sheet (Claim 5 of Patent Document 1). Additionally, Patent Document 1 also states that piezoelectric distortion is mitigated by pores (empty holes) present within the ceramic particles, which leads to crack suppression (

[0031] of Patent Document 1). Prior art literature

[0008] Japanese Patent Publication No. JP 2019-102655 The problem to be solved

[0009] With the advancement of electronic components and devices, further miniaturization and increased capacitance of multilayer ceramic capacitors (MLCCs) are anticipated. Furthermore, as the applications of MLCCs expand, the demand for improved reliability is steadily rising. Consequently, there is a demand for the development of MLCCs that exhibit excellent reliability and minimal insulation resistance degradation while advancing thinning. However, while conventional technologies have shown some effectiveness, there was still room for improvement.

[0010] The inventors have conducted a thorough examination in light of these problems. They have found that by providing internal voids in the dielectric particles in the inner layer and side margin portions of the multilayer ceramic capacitor, and by controlling the internal void ratio and the D50 diameter of the dielectric particles, a highly reliable multilayer ceramic capacitor with suppressed insulation resistance degradation can be obtained.

[0011] The present invention is completed based on such findings and aims to provide a highly reliable multilayer ceramic capacitor with suppressed insulation resistance degradation. means of solving the problem

[0012] The present invention includes the following embodiments. Meanwhile, the expression "~" in this specification includes numerical values ​​at both ends. That is, "X~Y" means "X or greater and Y or less." Furthermore, in this specification, any combination of suitable embodiments may be adopted as long as technical compatibility is achieved. For example, one side of a suitable numerical range and the other side may be arbitrarily combined.

[0013] According to one aspect of the present invention, a first internal electrode layer and a second internal electrode layer are alternately stacked with a dielectric layer formed of a ceramic dielectric in between, and an inner layer portion having a first main surface which is a surface in the stacking direction, a second main surface which is a surface opposite to the first main surface, a first side surface which is a surface in the width direction orthogonal to the first main surface and the second main surface and on which the first internal electrode layer and the second internal electrode layer are drawn out, a second side surface which is a surface opposite to the first side surface and on which the first internal electrode layer and the second internal electrode layer are drawn out, a first end surface which is a surface in the length direction orthogonal to the first main surface, the second main surface, the first side surface, and the second side surface and on which the first internal electrode layer is drawn out, and a second end surface which is a surface opposite to the first end surface and on which the second internal electrode layer is drawn out.

[0014] A first outer layer formed of a ceramic dielectric, covering the first main surface from the stacking direction,

[0015] A second outer layer formed of a ceramic dielectric and covering the second main surface from the stacking direction,

[0016] A first side margin portion formed of a ceramic dielectric, covering the inner layer, the first outer layer, and the second outer layer from one side in the width direction,

[0017] A second side margin portion formed of a ceramic dielectric, covering the inner layer, the first outer layer, and the second outer layer from the other side in the width direction, and

[0018] A pair of external electrodes provided on the first cross section and the second cross section, and connected to each of the first internal electrode layer and the second internal electrode layer, and

[0019] The dielectric particles constituting each of the ceramic dielectrics constituting the inner layer, the first side margin, and the second side margin include dielectric particles having empty holes inside, and

[0020] The ratio of empty holes within particles in the central part of the inner layer (inner layer central part) (N[inner layer central part]) and the ratio of empty holes within particles in the first side margin part and the second side margin part (N[side margin part]) satisfy the relationship: N[inner layer central part] < N[side margin part],

[0021] A multilayer ceramic capacitor is provided, wherein the diameter D50 of a dielectric particle at the widthwise end (inner layer W end) of the inner layer (D50 [inner layer W end]) and the diameter D50 of a dielectric particle at the center (inner layer center) of the inner layer (D50 [inner layer center]) satisfy the relationship: 1.00 ≤ D50 [inner layer W end] / D50 [inner layer center] ≤ 1.40. Effects of the invention

[0022] According to the present invention, a highly reliable multilayer ceramic capacitor with suppressed insulation resistance degradation is provided. Brief explanation of the drawing

[0023] Figure 1 is a perspective view showing the external appearance of a multilayer ceramic capacitor. Figure 2 is a cross-sectional view schematically showing the internal structure of a multilayer ceramic capacitor. Figure 3 is a cross-sectional view schematically showing the internal structure of a multilayer ceramic capacitor. Figure 4 is a drawing providing an explanation of the inner layer central part and the inner layer W end part. Figure 5 is a diagram showing the distribution of empty holes within particles in a dielectric layer. Figure 6 is a diagram provided for the explanation of polar IR generation rate measurement. Figure 7 is a drawing provided for the explanation of the bending test. Specific details for implementing the invention

[0024] Specific embodiments of the present invention (hereinafter referred to as "the present embodiments") will be described. Meanwhile, the present invention is not limited to the following embodiments, and various modifications are possible within the scope of not altering the essence of the present invention.

[0025] <<1. Multilayer Ceramic Capacitor>>

[0026] The multilayer ceramic capacitor of the present embodiment has an inner layer, a first outer layer, a second outer layer, a first side margin, a second side margin, and a pair of external electrodes. The inner layer is a region in which a first internal electrode layer and a second internal electrode layer are alternately stacked with a dielectric layer formed of a ceramic dielectric in between. The inner layer has a first main surface, a second main surface, a first side surface, a second side surface, a first cross-section, and a second cross-section. The first main surface is a surface in the stacking direction of the dielectric layer, the first internal electrode layer, and the second electrode layer. The second main surface is a surface on the opposite side from the first main surface. The first side surface is a surface in the width direction orthogonal to the first main surface and the second main surface. The second side surface is a surface on the opposite side from the first side surface. The first cross-section is a surface in the length direction orthogonal to the first main surface, the second main surface, the first side surface, and the second side surface, and is a surface in which the first internal electrode layer is drawn out. The second cross-section is a surface opposite to the first cross-section and is a surface on which the second internal electrode layer is drawn out. The first outer layer is formed of a ceramic dielectric and covers the first main surface from the stacking direction. The second outer layer is formed of a ceramic dielectric and covers the second main surface from the stacking direction. The first side margin is formed of a ceramic dielectric and covers the inner layer, the first outer layer, and the second outer layer from one side in the width direction. The second side margin is formed of a ceramic dielectric and covers the inner layer, the first outer layer, and the second outer layer from the other side in the width direction. A pair of external electrodes are provided on the first cross-section and the second cross-section and are connected to either the first internal electrode layer or the second internal electrode layer. Dielectric particles constituting each of the ceramic dielectrics constituting the inner layer, the first side margin, and the second side margin include dielectric particles having empty holes inside. The ratio of empty particles in the central part of the inner layer (N[central part of inner layer]) and the ratio of empty particles in the first side margin and the second side margin (N[side margin]) satisfy the relationship: N[central part of inner layer] < N[side margin].The D50 diameter of the dielectric particle at the widthwise end of the inner layer (inner layer W end) (D50[inner layer W end]) and the D50 diameter of the dielectric particle at the center of the inner layer (inner layer center) (D50[inner layer center]) satisfy the relationship: 1.00 ≤ D50[inner layer W end] / D50[inner layer center] ≤ 1.40.

[0027] An embodiment of a multilayer ceramic capacitor is described using FIGS. 1 to 3. FIG. 1 is a perspective view showing the external appearance of a multilayer ceramic capacitor. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 1.

[0028] A multilayer ceramic capacitor (100) comprises a body portion (6) and a pair of external electrodes (8a, 8b) provided on both ends (14a, 14b) of the body portion (6). The multilayer ceramic capacitor (100) and the body portion (6) have a roughly rectangular shape. A roughly rectangular shape includes not only a rectangular shape but also a rectangular shape in which the corners and / or ridges are rounded.

[0029] The multilayer ceramic capacitor (100) and the body portion (6) have a first outer surface (10a) and a second outer surface (10b) facing in the thickness direction (T), a first outer surface (12a) and a second outer surface (12b) facing in the width direction (W), and a first outer cross-sectional surface (14a) and a second outer cross-sectional surface (14b) facing in the length direction (L). Here, the thickness direction (T) is the direction in which the dielectric layer (2) and the internal electrode layer (4) included in the body portion (6) are stacked. The length direction (L) is orthogonal to the thickness direction (T) and is the direction in which the outer cross-sectional surfaces (14a, 14b) face each other. The width direction (W) is a direction orthogonal to the thickness direction (T) and the length direction (L). A plane including the thickness direction (T) and the width direction (W) is defined as the WT plane, a plane including the width direction (W) and the length direction (L) is defined as the LW plane, and a plane including the length direction (L) and the thickness direction (T) is defined as the LT plane.

[0030] The body part (6) is composed of an inner layer part (16), a first outer layer part (18a), a second outer layer part (18b), a first side margin part (20a), and a second side margin part (20b).

[0031] The inner layer (16) is an area in which internal electrode layers (4) are alternately stacked with dielectric layers (2) in between. The dielectric layer (2) is formed of a ceramic dielectric. The internal electrode layer (4) is composed of a plurality of first internal electrode layers (4a) and a plurality of second internal electrode layers (4b).

[0032] The inner layer (16) has a first main surface, a second main surface, a first side surface, a second side surface, a first cross surface, and a second cross surface. The first main surface is a surface perpendicular to the stacking direction of the dielectric layer (2) and the internal electrode layers (4a, 4b). The second main surface is a surface on the opposite side (opposing surface) from the first main surface. The first side surface is a surface orthogonal to the first main surface and the second main surface, i.e., a surface perpendicular to the width direction (W). The second side surface is a surface on the opposite side (opposing surface) from the first side surface. The first cross surface is a surface orthogonal to the first main surface, the second main surface, the first side surface, and the second side surface, i.e., a surface perpendicular to the length direction (L). The second cross surface is a surface on the opposite side (opposing surface) from the first cross surface. The internal electrode layers (4a, 4b) are drawn out on the first side surface and the second side surface. That is, the ends of the internal electrode layer are exposed on both the first side and the second side. In the first cross section, the first internal electrode layer (4a) is drawn out, but the second internal electrode layer (4b) is not drawn out. In the second cross section, the second internal electrode layer (4b) is drawn out, but the first internal electrode layer (4a) is not drawn out.

[0033] The first outer layer (18a) is an area covering the first main surface of the inner layer (16) from the stacking direction (thickness direction (T)). The second outer layer (18b) is an area covering the second main surface of the inner layer (16) from the stacking direction. The first side margin (20a) is an area covering the inner layer (16), the first outer layer (18a), and the second outer layer (18b) from one side in the width direction (first side side). The second side margin (20a) is an area covering the inner layer (16), the first outer layer (18a), and the second outer layer (18b) from the other side in the width direction (second side side). The first outer layer (18a), the second outer layer (18b), the first side margin (20a), and the second side margin (20b) are formed of a ceramic dielectric.

[0034] The external electrodes (8a, 8b) consist of a first external electrode (8a) provided on the first outer surface (14a) of the body part (6) and a second external electrode (8b) provided on the second outer surface (14b). The first external electrode (8a) and the second external electrode (8b) are not in contact and are electrically separated.

[0035] The size of the multilayer ceramic capacitor (100) or the body part (6) is not particularly limited. For example, the length direction (L) dimension is 0.2 mm or more and 3.2 mm or less, the width direction (W) dimension is 0.1 mm or more and 2.5 mm or less, and the stacking direction (T) dimension is 0.1 mm or more and 2.5 mm or less. Meanwhile, in FIGS. 1 to 3, the length direction (L) dimension is shown to be larger than the width direction (W) dimension, but the multilayer ceramic capacitor of this embodiment is not limited to having such dimensions. The length direction (L) dimension may be smaller than the width direction (W) dimension.

[0036] <Inner Layer - Genome Layer>

[0037] The inner layer is a region in which internal electrode layers (first internal electrode layer, second internal electrode layer) are alternately stacked with dielectric layers formed of ceramic dielectrics in between. The dielectric layer is composed of a ceramic dielectric produced by firing a green sheet for the inner layer containing a dielectric raw material. The ceramic dielectric is composed of a sintered polycrystalline body (ceramic) in which a plurality of dielectric particles are bonded through grain boundaries and triple points. That is, it contains dielectric particles (dielectric grains) as a main component. Meanwhile, the main component is the component with the largest content ratio in the ceramic dielectric, i.e., a component of 50 mass% or more.

[0038] The dielectric particles are composed of perovskite-type oxides. The perovskite-type oxides have a composition represented by the general formula: ABO3 and have a crystal structure similar to a cube, such as a cubic, tetragonal, orthorhombic, or rhombohedral crystal at room temperature. Additionally, atoms of the A-site element (hereinafter referred to as "A-site atoms") and atoms of the B-site element (hereinafter referred to as "B-site atoms") are each ionized to occupy the A-site and B-site of the perovskite structure. Examples of A-site elements include elements with relatively large ion sizes such as barium (Ba), calcium (Ca), and strontium (Sr), and examples of B-site elements include elements with relatively small ion sizes such as titanium (Ti), zirconium (Zr), and hafnium (Hf). The combination of A-site elements and B-site elements is not particularly limited as long as the perovskite-type structure is maintained. Each of the A-site element and B-site element may include only one type of element or may include a combination of multiple elements. Additionally, as long as the perovskite-type structure is maintained, the molar ratio of the A-site element to the B-site element may be shifted from 1:1.

[0039] Specific examples of perovskite-type oxides include barium titanate (BaTiO3)-based compounds, calcium titanate (CaTiO3)-based compounds, strontium titanate (SrTiO3)-based compounds, and mixtures or solid solutions thereof. Preferably, the A-site element includes barium (Ba) and the B-site element includes titanium (Ti). That is, suitably, the perovskite-type oxide is a barium titanate (BaTiO3)-based compound. BaTiO3-based compounds have a high dielectric constant. Therefore, they are particularly suitable for increasing the capacitance of multilayer ceramic capacitors. Meanwhile, BaTiO3-based compounds include not only BaTiO3 but also those in which a portion of Ba in BaTiO3 is substituted with other A-site elements such as Sr and / or Ca, or a portion of Ti is substituted with other B-site elements such as Zr and / or Hf.

[0040] The ceramic dielectric may include minor components. Examples of minor components, though not limited thereto, include rare earth elements (RE), magnesium (Mg), manganese (Mn), iron (Fe), chromium (Cr), cobalt (Co), nickel (Ni), silicon (Si), aluminum (Al), vanadium (V), and compounds thereof. Additionally, dysprosium (Dy) is preferred as the rare earth element (RE). As minor components, the aforementioned components may be included individually or in combination of multiple components. The form in which the minor components exist is not limited. They may be included in any one of dielectric particles, grain boundaries, and triple points.

[0041] The dielectric particles may include core-shell particles. A core-shell particle is a particle having a structure in which at least a portion of the minor component is dissolved at a high concentration in the surface layer (shell portion) of the particle, and the minor component is dissolved at a low concentration or is not dissolved in the central portion (core portion) of the particle (core structure). Alternatively, the dielectric particles may include particles in which the minor component is dissolved throughout the entire particle.

[0042] The thickness of the dielectric layer occupying the inner layer is suitably 0.6 μm or more and 3.0 μm or less. By making the thickness of the dielectric layer greater than a predetermined value, it becomes possible to suppress the occurrence of insulation breakdown and the deterioration of lifespan when using the multilayer ceramic capacitor. In addition, by making the thickness of the dielectric layer less than a predetermined value, the dielectric layer becomes thinner, and it becomes possible to increase the capacitance of the multilayer ceramic capacitor further. The number of dielectric layers is not particularly limited. Suitably, the number of dielectric layers constituting the inner layer is 100 or more and 2000 or less.

[0043] <Inner Layer - Internal Electrode Layer>

[0044] The internal electrode layer (first internal electrode layer, second internal electrode layer) is composed of a counter electrode portion and a lead electrode portion, and together with the dielectric layer, forms an inner layer portion. The counter electrode portion inserts the dielectric layer and functions as a capacitive element. The lead electrode portion functions to electrically connect the counter electrode portion and the external electrode. The internal electrode layer includes a conductive metal. As the conductive metal, known electrode materials such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), silver (Ag)-palladium (Pd) alloy, and / or gold (Au) may be used. The internal electrode layer is manufactured by sintering a conductive paste layer printed on the surface of a green sheet for the inner layer.

[0045] The internal electrode layer may include components other than conductive metals. As other components, ceramic components acting as co-materials may be cited. Additionally, the thickness of the internal electrode layer is suitably 0.40 μm or more and 1.5 μm or less. By making the internal electrode thickness greater than a predetermined value, the occurrence of problems such as electrode breakage can be prevented. Also, by making it less than a predetermined value, the decrease in the proportion of the dielectric layer within the capacitor can be prevented, and this contributes to increasing the capacitance. Additionally, the number of layers of the internal electrode layer is suitably 100 or more and 2000 or less.

[0046] <Outer layer>

[0047] The outer layers (first outer layer and second outer layer) are provided above and below the inner layer, respectively. The outer layers are composed of a ceramic dielectric and are regions that do not include an internal electrode layer. The outer layers are manufactured by firing a green sheet for the outer layer containing a dielectric material.

[0048] <Side Margin Section>

[0049] Side margin portions (first side margin portions, second side margin portions) are provided along the sides of a multilayer ceramic capacitor to accommodate the inner layer and the outer layer. Side margin portions are also referred to as side gap portions or side portions. Side margin portions are composed of a ceramic dielectric and are regions that do not contain an internal electrode layer. By providing side margin portions, it is possible to prevent moisture from intruding into the inner layer from the side.

[0050] The side margin is formed separately from the inner and outer layers during the manufacturing of multilayer ceramic capacitors. Specifically, a green body for the side margin is fabricated by attaching a green body to the side of the multilayer chip that constitutes the inner and outer layers, and the side margin is manufactured by firing this green body. In this case, the composition and / or microstructure of the ceramic dielectric constituting the side margin may not be continuous with that of the ceramic dielectric constituting the inner and / or outer layers. Consequently, a physical or chemical boundary may exist between the side margin and the inner and / or outer layers.

[0051] <External Electrode>

[0052] The external electrodes (first external electrode and second external electrode) function as input / output terminals of the multilayer ceramic capacitor. The first external electrode and the second external electrode are provided on both ends of the multilayer ceramic capacitor. The first external electrode is connected to the first internal electrode layer, and the second external electrode is connected to the second internal electrode layer. As the external electrodes, a known configuration may be adopted. For example, it may include a lower electrode layer and a plating layer disposed thereon. Alternatively, the external electrode may be composed solely of a plating layer without providing a lower electrode layer.

[0053] <Ratio of empty holes within particles>

[0054] In the multilayer ceramic capacitor of the present embodiment, each of the ceramic dielectrics constituting the inner layer, the first side margin, and the second side margin includes a dielectric particle having an internal void (an internal void). That is, an internal void exists in at least some of the dielectric particles constituting the ceramic dielectric. Here, an internal void refers to a void existing inside the dielectric particle. In other words, it is a region existing inside the dielectric particle that does not contain solid components, such as the main component constituting the dielectric particle or intentionally added minor component. Therefore, it is distinguished from an external void existing at the interface between particles or at the triple point. A dielectric particle having an internal void is called a particle with a void. A ceramic dielectric having such a particle with a void is manufactured using hydrothermal synthesis powder.

[0055] By including particles with voids in the ceramic dielectric constituting the inner layer (hereinafter collectively referred to as "inner layer ceramic"), the degradation of the insulation resistance (IR) of the multilayer ceramic capacitor can be suppressed, thereby improving reliability. Although this should not be interpreted as a limitation, the following points are considered as reasons for this.

[0056] When the dielectric layer and internal electrode layer are multilayered to increase the capacitance per unit volume, i.e., volumetric capacitance, the surface area of ​​the interface between the layers increases. If the smoothness of this interface is compromised, the electric field becomes concentrated when voltage is applied, making it prone to IR degradation. Consequently, it becomes difficult to achieve a fixed rated voltage for the multilayer ceramic capacitor. On the other hand, since hydrothermal synthetic powder has a shape close to spherical, using it smooths the interface between the dielectric layer and the internal electrode before firing, and maintains this state after firing. Therefore, it is desirable to use hydrothermal synthetic powder as a raw material for the dielectric layer in the inner layer, and among them, it is particularly desirable to use hydrothermal synthetic powder with BaTiO3-based compounds that exhibit high dielectric constant as the main component. By using hydrothermal synthetic powder, particles with voids are formed within the ceramic dielectric.

[0057] In addition, by including particles with voids in the ceramic dielectric (hereinafter collectively referred to as "side margin ceramic") constituting the side margin portions (first side margin portion, second side margin portion), it is possible to improve volumetric capacitance and further suppress IR degradation. Although this should not be interpreted as a limiting factor, the following points are considered as reasons for this.

[0058] To increase the volumetric capacitance of a multilayer ceramic capacitor, it is effective to reduce the thickness of the side margin in the width (W) direction. Furthermore, such a multilayer ceramic capacitor can be easily manufactured by employing a process in which the inner layer precursor and the side margin precursor are prepared separately, bonded together, and then fired as a single unit. In this case, it is preferable to use hydrothermal synthesis powder as the raw material for the side margin, specifically hydrothermal synthesis powder with BaTiO3-based compounds as the main component, which is identical to the inner layer. This is because hydrothermal synthesis powder has high fluidity, so using this powder enables improved adhesion between the side margin precursor and the inner layer precursor, which leads to the suppression of IR degradation.

[0059] As described above, it is known that employing hydrothermal synthetic powder in the inner layer and side margins leads to the suppression of IR degradation. In addition, the inventors have repeatedly examined the situation from the perspective of suppressing IR degradation and have discovered a relationship that allows for more suitable suppression of IR degradation by appropriately controlling the ratio of voids within particles remaining in the inner layer and side margins after firing. Specifically, in the multilayer ceramic capacitor of the present embodiment, the ratio of voids within particles (N[Inner Layer Center]) in the central part of the inner layer (Inner Layer Center) and the ratio of voids within particles (N[Side Margin]) in the side margins (First Side Margin and Second Side Margin) satisfy the relationship: N[Inner Layer Center] < N[Side Margin]. That is, the magnetic structure is controlled so that the ratio of voids within particles of the ceramic dielectric in the side margins is greater than the ratio of voids within particles of the ceramic dielectric in the inner layer center. Meanwhile, the inner layer center refers to the region occupying the vicinity of the center of the inner layer and is determined by the method described below. Additionally, the particle void ratio is the number of particle voids per unit area at the cross-sectional plane (WT plane) traversing the longitudinal center of the multilayer ceramic capacitor, and is measured by the method described below.

[0060] The inventors experimentally discovered that by controlling the ratio of voids within particles in the inner layer center and side margins to satisfy the relationship described above, it is possible to more effectively suppress the degradation of insulation resistance (IR).

[0061] In the multilayer ceramic capacitor of the present embodiment, the D50 diameter of the dielectric particle at the widthwise end (inner layer W end) of the inner layer (D50[inner layer W end]) and the D50 diameter of the dielectric particle at the center (inner layer center) of the inner layer (D50[inner layer center]) satisfy the relationship given by the equation: 1.00 ≤ D50[inner layer W end] / D50[inner layer center] ≤ 1.40. That is, the difference between the D50 diameter of the dielectric particle at the inner layer center and the D50 diameter of the dielectric particle at the inner layer W end is relatively small. This allows for more effective suppression of IR degradation. Although this should not be interpreted as a limiting factor, the following points are considered as reasons for this. Meanwhile, the inner layer center is a region occupying the vicinity of the center of the inner layer, and the inner layer W end is a region occupying the width (W) direction end of the inner layer. These are determined by the method described below.

[0062] As described above, grain growth is more likely at the inner layer W end compared to the inner layer center. Furthermore, if grain growth proceeds at the inner layer W end, the number of dielectric particles in the dielectric layer thickness direction decreases, leading to IR degradation. Conversely, if the ratio of the D50 diameter at the inner layer W end to the D50 diameter at the inner layer center is controlled to satisfy the aforementioned relationship, grain growth at the inner layer W end is suppressed. As a result, the number of dielectric particles in the dielectric layer thickness direction can be secured, which leads to the suppression of IR degradation. From the perspective of suppressing IR degradation, it is desirable for D50[inner layer W end] and D50[inner layer center] to satisfy the relationship Equation: 1.00 ≤ D50[inner layer W end] / D50[inner layer center] ≤ 1.17, and it is more desirable for them to satisfy the relationship Equation: 1.00 ≤ D50[inner layer W end] / D50[inner layer center] ≤ 1.06.

[0063] As long as D50 [central part of inner layer] and D50 [W-end part of inner layer] satisfy the relationship described above, their respective values ​​are not limited. However, by increasing the particle size to an appropriate degree, the effect of improving the crystallinity of the particle and the various properties associated therewith can be fully realized. On the other hand, by suppressing the particle size to an appropriate degree, further thinning of the dielectric layer can be achieved. D50 [central part of inner layer] is preferably 150 nm or more and 360 nm or less. In addition, D50 [W-end part of inner layer] is also preferably 150 nm or more and 500 nm or less. Meanwhile, the D50 diameters described above (D50 [central part of inner layer], D50 [W-end part of inner layer]) are the D50 diameters for all dielectric particles, including not only particles with cavities but also particles that do not contain cavities.

[0064] The central part of the inner layer is determined as follows. A dielectric layer is designated at approximately half the thickness (T) dimension in the body portion from which the external electrodes have been removed from the multilayer ceramic capacitor. In this designated dielectric layer, the region located at approximately half the length (L) dimension and approximately half the width (W) dimension of the body portion is designated as the central part of the inner layer (Fig. 4).

[0065] The number of voids within particles in the center of the inner layer is determined by transmission electron microscopy (TEM) observation. Specifically, TEM observation is performed by selecting a field of view from within the region defined by 10 µm (W direction) × 10 µm (L direction) × dielectric layer thickness (T direction) in the center of the inner layer. Additionally, the D50 diameter of the dielectric particles in the center of the inner layer (D50 [center of inner layer]) is determined by scanning electron microscopy (SEM) observation. Specifically, on the WT plane, a region defined by 3 µm (W direction) × dielectric layer thickness (T direction) in the center of the inner layer is established, the particle diameters of the dielectric particles included in this region are measured, and the average value is calculated as D50. SEM observation may be performed, for example, under conditions of a magnification of 25,000x. Furthermore, when measuring particle diameters, the particle diameters of particles without voids are measured as well as those of particles containing voids.

[0066] The inner layer W end is determined as follows. When determining the inner layer center, the dielectric layer designated is taken into account, and the boundary between the inner electrode layer and the side margin is determined with respect to this dielectric layer. Specifically, the W-direction ends of a pair of opposing inner electrode layers, with the aforementioned dielectric layer in between, are defined as the boundary. At this time, if the ends of each of the pair of inner electrode layers are offset from the W direction, the end closer to the inner layer center is used as the boundary. Then, starting from this boundary, the portion of the dielectric layer included within a distance of up to 3 μm toward the inner layer center is defined as the inner layer W end (Fig. 4).

[0067] The number of voids within the particles at the inner layer W end is determined by TEM observation of the inner layer W end. The D50 diameter (D50 [inner layer W end]) is determined by SEM observation of the inner layer W end. SEM observation may be performed, for example, under conditions of a magnification of 25,000x. In addition, when measuring particle size, the particle size of particles that do not contain voids is measured as well as the particle size of particles that do not contain voids.

[0068] Preferably, the ratio of voids within particles (N[center of inner layer]) in the center of the inner layer is 10 particles / ㎛ 2 The following applies. By reducing N [center of the inner layer], the problem of polarity IR can be suppressed. Here, polarity IR refers to a phenomenon in which the value of insulation resistance (IR) changes depending on the direction (polarity) of the applied voltage. That is, in a multilayer ceramic capacitor, the external electrode and the internal electrode are connected. Therefore, if the polarity of the voltage applied to the external electrode is reversed, the direction of the voltage applied to the dielectric ceramic in the inner layer is reversed. At that time, the value of IR may change depending on the direction of the voltage. This is called polarity IR. If polarity IR is large enough to be negligible, the value of IR changes significantly depending on the mounting direction of the multilayer ceramic capacitor. Since this causes non-uniformity of IR values ​​in actual operation, it is desirable to suppress polarity IR as much as possible.

[0069] As a reason why polar IR can be suppressed by making N [central part of the inner layer] smaller, the following points are considered, although this should not be interpreted as a limited interpretation.

[0070] As described above, using hydrothermal synthetic powder is advantageous for suppressing IR degradation because the interface between the dielectric layer and the internal electrode layer becomes smooth. However, when using hydrothermal synthetic powder, particles with voids remain in the dielectric layer. While there is no problem if these voids are located at an equidistant distance from either of the pair of internal electrodes facing the dielectric layer, polar IR is generated if they are located close to either one. This is because the method of applying the electric field around the voids changes, and the electric field strength distribution changes when the direction of voltage application is changed. Voids tend to remain among dielectric particles that do not grow during firing. In the dielectric layer (inner layer), dielectric particles with a small degree of grain growth may solidify and be distributed (Fig. 5). Under such a distribution of dielectric particle sizes, the distribution of voids within the particles becomes uneven, so the difference in electric field strength when the direction of voltage application is changed becomes apparent, which causes the generation of polar IR.

[0071] In contrast, when the ratio of empty holes within the particles (N[center of inner layer]) in the inner layer center is small, the empty holes can be considered to be randomly distributed (Fig. 5). Furthermore, since the number of empty holes themselves is small, the change in the way the electric field is applied around the empty holes becomes negligibly small. Therefore, polar IR is significantly suppressed.

[0072] When the thickness of the dielectric layer is 3.0㎛ or less, to suppress the generation rate of polar IR, N [center of the inner layer] is 0 / ㎛ 2 Exceeding 10 particles / ㎛ 2 The following is preferable, and 0 pieces / ㎛ 2 Exceeding 7 particles / ㎛ 2 The following is more preferable, with 0 pieces / ㎛ 2 Exceeding 4 / piece µm 2 The following is more preferable. N [central part of inner layer] is 1 / ㎛ 2 It is okay if it is more than that.

[0073] Furthermore, as long as the relationship between N[central part of the inner layer] and N[side margin part] described above is satisfied, the ratio of empty holes within the particles in the side margin part (N[side margin part]) is not limited. However, from the perspective of further enhancing the effect of suppressing IR degradation, N[side margin part] is 5 holes / ㎛ 2 26 or more / ㎛ 2 The following is preferable, and 10 pieces / ㎛ 2 26 or more / ㎛ 2 The following is more preferable, and 15 pieces / ㎛ 2 26 or more / ㎛ 2 The following is more desirable.

[0074] Meanwhile, the side margin portion includes a first side margin portion and a second side margin portion. The ratio of voids within particles in the first side margin portion and the ratio of voids within particles in the second side margin portion may be the same or different. However, preferably, both are greater than the ratio of voids within particles in the central portion of the inner layer.

[0075] Preferably, the ceramic dielectric constituting the outer layer (first outer layer, second outer layer) (hereinafter collectively referred to as "outer layer ceramic") includes particles having voids. By doing so, the occurrence of cracks in the multilayer ceramic capacitor can be effectively suppressed. Although this should not be interpreted as a limiting factor, the following points are considered as reasons for this.

[0076] During the firing process for manufacturing multilayer ceramic capacitors, dielectric particles in the outer layer, as well as in the side margins, are more prone to grain growth compared to those in the inner layer. When grain growth occurs, not only does the D50 diameter of the dielectric particles increase, but the grain size distribution also widens. In a ceramic sintered body, high mechanical strength is maintained as the stress received from adjacent particles is balanced overall. In a sintered body with a grain size distribution, the coordination number and diameter of adjacent particles differ for each dielectric particle, and from a microscopic perspective, this causes non-uniformity in strength. Consequently, when a multilayer ceramic capacitor is subjected to a bending test on a mounting substrate, it becomes prone to cracking.

[0077] In contrast, by incorporating internal voids into the dielectric particles of the outer layer to suppress grain growth and minimize the grain size distribution, the microscopic mechanical strength becomes uniform, and as a result, crack formation is effectively suppressed.

[0078] Preferably, the ratio of voids within particles in the central part of the inner layer (inner layer central part) (N[inner layer central part]) and the ratio of voids within particles in the first outer layer and the second outer layer (N[outer layer]) satisfy the relationship: N[inner layer central part] < N[outer layer]. By doing so, the occurrence of cracks in the multilayer ceramic capacitor can be suppressed even more significantly. Although this should not be interpreted as a limiting factor, the following points are considered as reasons for this.

[0079] When mounting a multilayer ceramic capacitor onto a printed circuit board, if the outer layer (W direction) is perpendicular to the surface of the board, tensile stress is applied to the side margin when the board is bent. Conversely, if the outer layer (W direction) is parallel to the surface of the board, tensile stress is applied to the outer layer when the board is bent. Typically, since the mounting direction is random, tensile stress due to board bending is applied to either the outer layer or the side margin. When the ratio of cavities within the particles in the side margin is greater than the ratio of cavities within the particles in the inner layer and the ratio of cavities within the particles in the outer layer is greater than the ratio of cavities within the particles in the inner layer, even if tensile stress is applied to either the side margin or the outer layer, the microscopic mechanical strength becomes uniform due to the presence of cavities within the particles that are relatively high in proportion, which leads to crack prevention.

[0080] Since the particle size of dielectric particles containing voids is relatively small, the grain boundary area of ​​the side margin and outer layer containing such dielectric particles is increased. This implies an increased grain boundary area, which leads to crack prevention from this perspective as well. In other words, by making the ratio of voids within the particles in the side margin larger than the ratio of voids within the particles in the inner layer, and by making the ratio of voids within the particles in the outer layer larger than the ratio of voids within the particles in the inner layer, it becomes possible to suppress crack occurrence even more significantly. Specifically, in a bending test with a bending amount of 2.5 mm, the crack occurrence rate can be suppressed to 5% or less.

[0081] From the perspective of reducing the crack occurrence rate in the bending test of a mounted substrate, the ratio of empty holes within particles in the outer layer (N[outer layer]) is 1 / ㎛ 2 25 or more / ㎛ 2 The following is preferable, and 8 pieces / ㎛ 2 25 or more / ㎛ 2 The following is more preferable, and 12 pieces / ㎛ 2 25 or more / ㎛2 The following is more preferable. Meanwhile, the outer layer includes a first outer layer and a second outer layer. The ratio of empty holes within particles in the first outer layer and the ratio of empty holes within particles in the second outer layer may be the same or different. However, if N[central part of the inner layer] and N[outer layer] satisfy the relationship described above (N[central part of the inner layer] < N[outer layer]), it is preferable that both the ratio of empty holes within particles in the first outer layer and the ratio of empty holes within particles in the second outer layer satisfy this relationship.

[0082] According to a suitable embodiment, the zirconium concentration of the ceramic dielectric constituting the inner layer (Zr[inner layer]) and the zirconium concentration of the ceramic dielectric constituting the side margin (Zr[side margin]) satisfy Zr[side margin] < Zr[inner layer]. As described below, when manufacturing a multilayer ceramic capacitor, if a grain growth promoter such as Zr is added to the green sheet for the inner layer or the green sheet for the side margin and the amount is controlled, the ratio of voids within the particles can be adjusted. Furthermore, in that case, in the multilayer ceramic capacitor finally obtained, the concentration of the grain growth promoter (Zr, etc.) in the inner layer becomes higher than that in the side margin.

[0083] According to another suitable embodiment, the dielectric particles included in the inner layer and the side margin are composed of a perovskite-type oxide having a composition represented by ABO3. Preferably, the molar ratio (A / B ratio) of the dielectric particles included in the side margin is greater than the molar ratio (A / B ratio) of the dielectric particles included in the inner layer. As described below, when manufacturing a multilayer ceramic capacitor, controlling the molar ratio (A / B ratio) of the main component powder included in the inner layer green sheet or the side margin green sheet allows for adjustment of the ratio of voids within the particles. Furthermore, in that case, in the finally obtained multilayer ceramic capacitor, the molar ratio of the dielectric particles included in the side margin becomes greater than the molar ratio of the dielectric particles included in the inner layer.

[0084] The multilayer ceramic capacitor of the present embodiment includes dielectric particles (particles with empty holes) having empty holes inside in the inner layer and side margin portions, and additionally, the ratio of empty holes within the particles (N [center of inner layer], N [side margin portion]) is controlled to satisfy a predetermined relationship. As a result, the degradation of insulation resistance (IR) is suppressed, and it has the advantage of high reliability. Although not limited to, for example, it is possible to have an average time to failure (MTTF) of 30 hours or more, 50 hours or more, or 70 hours or more in a super accelerated life test (HALT). Meanwhile, the average time to failure is obtained by the method described in the embodiments to be described later or by a method equivalent thereto.

[0085] Although not limited to this, the multilayer ceramic capacitor of the present embodiment can suppress polar IR by controlling the ratio of empty holes within particles (N [center of inner layer]) in the center of the inner layer to within a predetermined range. For example, it is possible to set the polar IR generation rate to 3% or less, or 1% or less. Meanwhile, the polar IR generation rate is obtained as follows. First, a forward voltage is applied to the multilayer ceramic capacitor to obtain the insulation resistance (IR). Next, a reverse voltage is applied to obtain the insulation resistance (IR) (Fig. 6). The difference between each IR (insulation resistance) value measured by changing the direction of voltage application and converting it into a common logarithm is calculated, and the ratio of the number of samples in which the absolute value of the difference exceeds 0.3 (the number of decimal places exceeds 0.3) is obtained as the polar IR generation rate. More specifically, it is obtained by the method described in the embodiment to be described later or a method equivalent thereto.

[0086] Although not limited to this, the multilayer ceramic capacitor of the present embodiment may effectively suppress crack occurrence by including particles with empty holes in the outer layer and additionally controlling the ratio of empty holes within the particles (N [central part of inner layer], N [outer layer]). For example, it is possible to set the crack occurrence rate in a bending test with a bending amount of 2.5 mm of the mounting substrate to 5% or less, 3% or less, or 1% or less. Meanwhile, the bending test is obtained by the method described in the embodiments to be described later or a method equivalent thereto.

[0087] <<2. Method for Manufacturing Multilayer Ceramic Capacitors>>

[0088] As long as the multilayer ceramic capacitor of the present embodiment satisfies the requirements described above, the manufacturing method thereof is not limited. However, a suitable manufacturing method comprises the following processes: a process of synthesizing a main component powder for a ceramic dielectric (synthesis process); a process of mixing a minor component raw material with the main component powder to obtain a dielectric raw material (mixing process); a process of adding and mixing a binder and a solvent to the dielectric raw material to form a slurry, and forming an inner layer green sheet and an outer layer green sheet from the obtained slurry (forming process); a process of using a conductive paste for internal electrodes to form a patterned conductive paste layer on the surface of the inner layer green sheet (printing process); a process of stacking multiple inner layer green sheets with the conductive paste layer formed thereon, stacking outer layer green sheets above and below them, and compressing the entire structure to produce a stacked block (stacking process); a process of cutting the obtained stacked block to form a stacked chip (cutting process); a process of attaching a side margin green body to the side of the obtained stacked chip to produce a green body part (side margin part formation process); a process of performing de-binding treatment and firing treatment on the obtained green body part to form a body part (firing process); and forming an external electrode on the obtained body part to form a stacked ceramic The process includes a process for manufacturing a capacitor (external electrode formation process). In addition, in the obtained multilayer ceramic capacitor, the manufacturing conditions are controlled such that each ceramic dielectric constituting the inner layer and the side margin (first side margin and second side margin) contains particles with voids, satisfies the relationship N[center of inner layer] < N[side margin], and additionally satisfies the relationship 1.00 ≤ D50[inner layer W end] / D50[center of inner layer] ≤ 1.40. The details of each process are described below.

[0089] <Synthesis Process>

[0090] In the synthesis process, the main component powder used for forming the ceramic dielectric is synthesized. The main component powder is a dielectric powder having a perovskite-type structure (ABO3), such as a BaTiO3-based compound. Hydrothermally synthesized powder is used as the main component powder for the ceramic dielectric. This makes it possible to fabricate a multilayer ceramic capacitor containing dielectric particles with internal cavities (particles with cavities).

[0091] The synthesis of hydrothermal synthetic powder is carried out by hydrothermally reacting a raw material containing an A-site element constituting a perovskite-type structure (A-site raw material) and a raw material containing a B-site element (B-site raw material) under high temperature and high pressure. Specifically, the raw materials are placed in a sealed container, such as an autoclave, along with water, and heated to induce a hydrothermal reaction. Hydroxides such as barium hydroxide (Ba(OH)2) are used as the A-site raw material. Oxides such as titanium oxide (TiO2) or metatitonic acid (TiO(OH)2) or their hydrates are used as the B-site raw material. The heating temperature is not limited, but it should be between 150°C and 250°C. The product obtained by the hydrothermal reaction can be dried to obtain dielectric powder. Additionally, to increase the crystallinity of the dielectric powder, heat treatment may be performed on the product. Heat treatment can be performed, for example, at a temperature between 800°C and 1000°C.

[0092] <Mixing Process>

[0093] In the mixing process, a dielectric material is obtained by mixing a secondary component (Ni, RE, Mg, Mn, Si, Al, V, etc.) raw material with the main component powder. Known ceramic raw materials, such as oxides, carbonates, hydroxides, nitrates, organic acid salts, alkoxides, and / or chelate compounds, may be used as the secondary component raw material. In addition, a composition control agent for the main component powder may be added in addition to the secondary component raw material. For example, if the main component powder is barium titanate (BaTiO3) powder, adding a Ba raw material such as barium carbonate (BaCO3) allows for the control of the main component composition (A / B ratio) of the ceramic dielectric contained in the multilayer ceramic capacitor. The mixing method is not particularly limited. For example, a method may be used in which the weighed main component powder and secondary component raw material are wet-mixed and ground using a ball mill together with a grinding medium and pure water. If wet mixing is performed, the mixture may be dried.

[0094] <Molding Process>

[0095] In the molding process, a binder and a solvent are added to and mixed with the dielectric raw material to form a slurry, and an inner layer green sheet and an outer layer green sheet are molded from the obtained slurry. As the binder, known organic binders, such as polyvinyl butyral-based binders, may be used. In addition, known organic solvents, such as toluene or ethanol, may be used as the solvent. Additives such as plasticizers may be added as necessary. Molding may be carried out using known methods such as the lip method. The sheet thickness after molding is, for example, 4 μm or less.

[0096] <Printing Process>

[0097] In the printing process, a conductive paste is used to form a patterned conductive paste layer on the surface of a green sheet for the inner layer. The conductive paste layer becomes an internal electrode layer after firing. As the conductive metal included in the conductive paste, conductive materials such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), and alloys containing these may be used. Additionally, a ceramic component acting as a filler may be added to the conductive paste. As the ceramic component, the main component powder of the dielectric layer may be used. The method of forming the conductive paste layer is not particularly limited. Examples include screen printing and gravure printing.

[0098] <Lamination Process>

[0099] In the lamination process, multiple inner layer green sheets with a conductive paste layer formed thereon are laminated, and outer layer green sheets are laminated above and below them. Then, the entire structure is compressed to produce a laminated block. The inner layer green sheets undergo a firing process to become the ceramic dielectric (inner layer ceramic) that constitutes the inner layer of the multilayer ceramic capacitor. The outer layer green sheets become the ceramic dielectric (outer layer ceramic) that constitutes the outer layer. The number of laminated green sheets can be adjusted to obtain the required capacitance.

[0100] <Cutting Process>

[0101] In the cutting process, the obtained laminated block is cut to form a laminated chip. The cutting is performed such that a chip of a predetermined size is obtained and the conductive paste layer is exposed on the cross-section and side of the laminated chip.

[0102] <Side Margin Formation Process>

[0103] In the side margin formation process, a side margin green body is attached to the side of the stacked chip to produce the green body portion. The conductive paste layer exposed on the side of the stacked chip is covered by the side margin green body. Additionally, the side margin green body becomes the side margin portion of the multilayer ceramic capacitor after firing. As the raw material for the side margin green body (side margin raw material powder), the main component powder and minor component raw material used in the production of inner layer green sheets can be used.

[0104] The fabrication and attachment of the side margin green body may be carried out using known methods. For example, a green sheet may be fabricated from a dielectric material that serves as the raw material for the side margin, and the green sheet may be adhered to the side of the stacked chip. At that time, to ensure the adhesion of the green sheet, an adhesion aid such as an organic solvent may be applied to the side of the stacked chip in advance. Alternatively, a paste may be fabricated from the dielectric material, and the paste may be applied to and dried on the side of the stacked chip. The side margin green body may be a single layer or a stacked body consisting of multiple layers. A side margin green body consisting of a stacked body can be obtained by a method of stacking multiple green sheets on the side of the stacked chip or by a method of repeatedly applying and drying the paste.

[0105] If necessary, barrel polishing treatment may be performed on the obtained green body. This treatment makes it possible to round the edges and / or ridges of the green body.

[0106] <Sintering Process>

[0107] In the firing process, the green body is subjected to debinding and firing treatments to form the body. Through the firing treatment, the conductive paste layer and the inner layer green sheet are co-sintered to become the inner electrode layer and the ceramic dielectric constituting the inner layer. The outer layer green sheet is sintered to become the ceramic dielectric constituting the outer layer. The side margin green body is sintered to become the ceramic dielectric constituting the side margin.

[0108] The conditions for the debinder treatment should be determined based on the type of organic binder included in the green sheet and conductive paste layer. Additionally, the sintering treatment should be performed at a temperature where the laminated chip is sufficiently densified. For example, it should be performed under conditions where the temperature is maintained between 1200°C and 1400°C for 0 minutes or more and 10 minutes or less. Furthermore, the sintering should be carried out in an atmosphere where the oxidation of the conductive material is suppressed without reducing the main component compounds, such as BaTiO3. For example, an oxygen partial pressure of 1.7 × 10⁻⁶ -7 ~5.8×10 -10 It may be carried out in a stream of MPa N2-H2-H2O. Additionally, anilment treatment may be performed after firing.

[0109] <External Electrode Formation Process>

[0110] In the external electrode formation process, external electrodes are formed on the body portion to form a multilayer ceramic capacitor. The formation of the external electrodes may be carried out using known methods. For example, a conductive paste, primarily composed of conductive components such as Cu or Ni, is applied and baked onto the exposed end surface where the internal electrode of the body portion is drawn out to form a lower layer. The lower layer may also be formed by applying conductive paste to both end surfaces of the green body portion prior to firing, followed by a firing treatment. After forming the lower layer, electroplating is performed to form a plating film of Ni, Sn, etc., on the surface of the lower layer. Thus, a multilayer ceramic capacitor is manufactured.

[0111] <Control of the ratio of empty holes within particles>

[0112] In the manufacturing method of the present embodiment, the manufacturing conditions are controlled such that, in the obtained multilayer ceramic capacitor, each ceramic dielectric constituting the inner layer and the side margin (first side margin and second side margin) contains particles with voids. Specifically, hydrothermal synthetic powder is used as the main component powder included in at least the inner layer green sheet and the side margin green sheet. As the main component powder, only hydrothermal synthetic powder may be used, or a combination of hydrothermal synthetic powder and powder synthesized by a method other than hydrothermal may be used. Examples of methods other than hydrothermal methods include, but are not limited to, the solid-state method, the sol-gel method, the alkoxide method, the sorbothermal method, or the oxalate method. Additionally, the particle size may be adjusted by grinding the main component powder after synthesis.

[0113] On the other hand, hydrothermally synthesized powder may be used as the main component powder included in the green sheet for the outer layer, or dielectric powder synthesized by a method other than hydrothermal may be used. However, it is preferable to use hydrothermally synthesized powder. This makes it possible to have particles with pores in the ceramic dielectric constituting the outer layer.

[0114] In addition, in the manufacturing method of the present embodiment, the manufacturing conditions are controlled such that in the obtained multilayer ceramic capacitor, the ratio of empty holes within particles in the inner layer center (N[inner layer center]) and the ratio of empty holes within particles in the side margins (first side margins and second side margins) (N[side margins]) satisfy the relationship: N[inner layer center] < N[side margins], and additionally, the D50 diameter of the dielectric particle in the inner layer W end (D50[inner layer W end]) and the D50 diameter of the dielectric particle in the inner layer center (D50[inner layer center]) satisfy the relationship: 1.00 ≤ D50[inner layer W end] / D50[inner layer center] ≤ 1.40.

[0115] The method for controlling the ratio of voids within the particles or the D50 diameter is not limited. For example, a method can be used in which a grain growth promoter or a grain growth inhibitor is added to the main component powder and the amount is adjusted. Examples of grain growth promoters include zirconium (Zr), silicon (Si), vanadium (V), and / or aluminum (Al). During the firing process, dielectric particles grow. At that time, as grain growth progresses, the voids within the particles become smaller and, in some cases, disappear. Therefore, by adding a grain growth promoter to the inner layer green sheet, the outer layer green sheet, or the side margin green sheet and adjusting the amount, the ratio of voids within the particles in each part can be controlled.

[0116] Alternatively, one method involves adjusting the composition of the main component powder. The main component powder is a perovskite-type oxide having a composition represented by the formula ABO3, typified by BaTiO3. In perovskite-type oxides, grain growth is promoted as the molar ratio (A / B ratio) of A-site elements (e.g., Ba) to B-site elements (e.g., Ti) decreases. Therefore, by adjusting the molar ratio (A / B ratio) of the main component powder contained in the inner layer green sheet, the outer layer green sheet, or the side margin green sheet, the ratio of voids within the particles in each part can be controlled.

[0117] In addition, a method of adjusting the particle size of raw material particles, such as the main component powder, can be used. Particle growth proceeds as the raw material particles become smaller. Therefore, by adjusting the particle size of the main component powder in the inner layer green sheet, outer layer green sheet, or side margin green sheet, the ratio of voids within the particles in each part can be controlled.

[0118] As another method, dielectric powder synthesized by a method other than the hydrothermal method, for example, by the solid-state method, can be added to the main component powder. As mentioned above, hydrothermally synthesized powder has voids within the particles, whereas dielectric powder synthesized by a method other than the hydrothermal method does not have voids within the particles. Therefore, by using hydrothermally synthesized powder and dielectric powder synthesized by a method other than the hydrothermal method in combination and adjusting their ratio, the ratio of voids within the particles in each part can be controlled.

[0119] In the multilayer ceramic capacitor finally obtained, if the ratio of voids within particles or the D50 diameter of the inner layer, outer layer, and side margin can be controlled to satisfy a predetermined relationship, the method is not limited.

[0120] Examples

[0121] The present embodiment will be explained in more detail by the following examples. However, the present invention is not limited to the following examples.

[0122] (1) Fabrication of a multilayer ceramic capacitor

[0123] [Example 1]

[0124] In Example 1, barium titanate (BaTiO3) powder synthesized by the hydrothermal method was used as the main component powder to produce an inner layer green sheet, an outer layer green sheet, and a side margin green body, and these were used to produce a multilayer ceramic capacitor. The specific manufacturing procedure is shown below.

[0125] <Synthesis of Main Component Powder>

[0126] Barium titanate (BaTiO3) powder was synthesized by the hydrothermal method. First, titanium oxide (TiO2) powder and barium hydroxide (Ba(OH)2) powder were weighed, and pure water was added to prepare a slurry. The prepared slurry was then placed in a sealed container, and the temperature of the slurry was raised to 200–250°C while stirring. The liquid-phase reaction was carried out by maintaining the temperature at 200–250°C for 4–24 hours. Afterward, the internal pressure of the sealed container was returned to atmospheric pressure, heating was stopped, and the slurry was left to stand. After cooling, the slurry was removed from the sealed container and placed in a dryer to evaporate the moisture. In this way, hydrothermally synthesized BaTiO3 powder with an average particle size of 130 nm was obtained.

[0127] <Production of Green Sheets for Inner Layers>

[0128] Apart from the hydrothermally synthesized BaTiO3 powder, dysprosium oxide (Dy2O3), magnesium carbonate (MgCO3), manganese carbonate (MnCO3), silicon oxide (SiO2), and vanadium oxide (V2O5) were prepared as auxiliary raw materials. Additionally, barium carbonate (BaCO3) and zirconium oxide (ZrO2) were prepared. These auxiliary raw materials, BaCO3, and ZrO2 were added to BaTiO3 powder (average particle size 130 nm), and the resulting mixture was wet-milled (combined) in water for 24 hours using a ZrO2 ball mill, followed by drying to be used as a dielectric raw material for the inner layer. The amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the ceramic dielectric (inner layer ceramic) constituting the inner layer of the finally obtained multilayer ceramic capacitor was 1.0027. Meanwhile, the Ba / Ti ratio is a ratio in molar amounts. In addition, the amount of ZrO2 added was set to 0.55 mass% relative to the BaTiO3 powder. Subsequently, a polyvinyl butyral-based binder and an organic solvent, ethanol, were added to the obtained dielectric raw material and wet-mixed using a ball mill for a predetermined time to produce a slurry. This slurry was sheet-molded to produce a green sheet for the inner layer.

[0129] <Production of Green Sheets for the Outer Layer>

[0130] Apart from the hydrothermally synthesized BaTiO3 powder, dysprosium oxide (Dy2O3), magnesium carbonate (MgCO3), manganese carbonate (MnCO3), silicon oxide (SiO2), and vanadium oxide (V2O5) were prepared as auxiliary raw materials. Additionally, barium carbonate (BaCO3) and zirconium oxide (ZrO2) were prepared. These auxiliary raw materials, BaCO3, and ZrO2 were added to BaTiO3 powder (average particle size 130 nm), and the resulting mixture was wet-milled (combined) in water for 24 hours using a ZrO2 ball mill, followed by drying to be used as a dielectric raw material for the outer layer. The amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the ceramic dielectric (outer layer ceramic) constituting the outer layer of the finally obtained multilayer ceramic capacitor was 1.0027. Furthermore, the amount of ZrO2 added was set to 0.55 mass% relative to the BaTiO3 powder. Next, a polyvinyl butyral-based binder and an organic solvent, ethanol, were added to the obtained dielectric raw material and wet-mixed using a ball mill for a predetermined time to produce a slurry. This slurry was sheet-molded to produce a green sheet for the outer layer.

[0131] <Production of Side Margin Green Font>

[0132] Apart from the hydrothermally synthesized BaTiO3 powder, dysprosium oxide (Dy2O3), magnesium carbonate (MgCO3), manganese carbonate (MnCO3), silicon oxide (SiO2), and vanadium oxide (V2O5) were prepared as auxiliary raw materials. Additionally, barium carbonate (BaCO3) was prepared. These auxiliary raw materials and BaCO3 were added to BaTiO3 powder (average particle size 130 nm), and the resulting mixture was wet-milled (mixed) in water for 12 hours using a ZrO2 ball mill, followed by drying to obtain a dielectric raw material for a side margin green body. The amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the ceramic dielectric (side margin ceramic) constituting the side margin of the finally obtained multilayer ceramic capacitor was 1.0040. Subsequently, a polyvinyl butyral-based binder and ethanol, an organic solvent, were added to the obtained dielectric raw material and wet-mixed using a ball mill for a predetermined time to produce a slurry. This slurry was sheet-molded to produce a side margin green body.

[0133] <Fabrication of Laminated Structures>

[0134] A conductive paste based on Ni was screen-printed onto the surface of the obtained inner layer green sheet to form a pattern of the conductive paste layer serving as the internal electrode layer. Subsequently, multiple inner layer green sheets with the conductive paste layer formed thereon were laminated, and outer layer green sheets without the conductive paste layer formed thereon were placed above and below them. The entire structure was then compressed to produce a laminated block. The resulting laminated block was then cut using a dicing saw to form a laminated chip. Lamination was performed such that the ends from which the conductive paste layer was drawn out were staggered. Additionally, cutting was performed such that the conductive paste layer was exposed on the side, while the drawn-out portion of the conductive paste layer was exposed on the cross-section.

[0135] A green body part was fabricated by attaching side margin green bodies to both sides of the cut laminated chip where the conductive paste layer was exposed.

[0136] The obtained green body was heat-treated in an N2 stream at a maximum temperature of 270°C, and additionally heat-treated in an N2-H2O-H2 stream at a maximum temperature of 800°C. Subsequently, it was calcined in an N2-H2O-H2 stream. Calcination was performed at a maximum temperature of 1250–1320°C, a pressure increase rate of 20–60°C / sec, a holding time of 60 minutes, and an oxygen partial pressure of 3.2 × 10⁻⁶. -9 ~6.4×10 -10 It was carried out under MPa conditions. Subsequently, heat treatment was performed under conditions of a maximum temperature of 1050℃ for 60 minutes in an N2-H2O-H2 stream. Thus, a body part was obtained.

[0137] A conductive paste with copper (Cu) as the main component was applied to the cross-section of the internal electrode layer drawn out of the body part obtained by firing. Then, the applied conductive paste was baked at 900°C to form a lower layer of the external electrode. Additionally, Ni plating and Sn plating were performed in this order on the surface layer of the lower layer by wet plating. In this way, a multilayer ceramic capacitor was fabricated.

[0138] The fabricated multilayer ceramic capacitor had a length (L) dimension of 1.0 mm, a width (W) dimension of 0.5 mm, and a thickness (T) dimension of 0.5 mm. In addition, the thickness of the dielectric layer in the inner layer was 0.80 μm, the thickness of the internal electrode layer was 0.47 μm, and the number of dielectric layers was 345.

[0139] [Example 2]

[0140] In Example 2, when producing the inner layer green sheet, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the inner layer ceramic was 1.0015. In addition, the amount of ZrO2 added was changed from 0.55 mass% to 0.3 mass%. Furthermore, when producing the outer layer green sheet, the amount of ZrO2 added was changed from 0.55 mass% to 0.3 mass%. Except for this, a multilayer ceramic capacitor was produced in the same manner as in Example 1.

[0141] [Example 3]

[0142] In Example 3, when fabricating the side margin green body, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the side margin ceramic was 1.0027. In addition, ZrO2 was added along with BaCO3, and the amount added (amount of ZrO2 added) was set to 0.3 mass% relative to the BaTiO3 powder. Additionally, the grinding time was changed from 12 hours to 24 hours. Except for this, a multilayer ceramic capacitor was fabricated in the same manner as in Example 1.

[0143] [Example 4]

[0144] In Example 4, when fabricating the side margin green body, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the side margin ceramic was 1.0027. In addition, ZrO2 was added along with BaCO3, and the amount added (amount of ZrO2 added) was set to 0.3 mass% relative to the BaTiO3 powder. Except for this, a multilayer ceramic capacitor was fabricated in the same manner as in Example 1.

[0145] [Example 5]

[0146] In Example 5, the amount of ZrO2 added during the production of the inner layer ceramic green sheet was changed from 0.55 mass% to 0.4 mass%. A multilayer ceramic capacitor was produced in the same manner as in Example 1.

[0147] [Example 6]

[0148] In Example 6, the amount of ZrO2 added during the production of the inner layer ceramic green sheet was changed from 0.55 mass% to 0.3 mass%. A multilayer ceramic capacitor was produced in the same manner as in Example 1.

[0149] [Example 7]

[0150] In Example 7, the amount of ZrO2 added during the production of the ceramic green sheet for the outer layer was changed from 0.55 mass% to 0.3 mass%. A multilayer ceramic capacitor was produced in the same manner as in Example 1.

[0151] [Example 8]

[0152] In Example 8, the amount of ZrO2 added during the production of the ceramic green sheet for the outer layer was changed from 0.55 mass% to 0.4 mass%. A multilayer ceramic capacitor was produced in the same manner as in Example 1.

[0153] [Example 9]

[0154] In Example 9, hydrothermal synthesized BaTiO3 powder (average particle size 160 nm) was used instead of hydrothermal synthesized BaTiO3 powder (average particle size 130 nm) when making the green sheet for the outer layer. Except for that, a multilayer ceramic capacitor was made in the same manner as in Example 1. Meanwhile, hydrothermal synthesized BaTiO3 powder (average particle size 160 nm) was synthesized by the same procedure as hydrothermal synthesized BaTiO3 powder (average particle size 130 nm), except that the slurry temperature during hydrothermal synthesis was increased.

[0155] [Example 10]

[0156] In Example 10, when preparing the green sheet for the outer layer, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the outer layer ceramic was 1.0040. Also, ZrO2 was not added. Additionally, the grinding time was changed from 24 hours to 12 hours. Except for that, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0157] [Example 11]

[0158] In Example 11, when producing the green sheet for the outer layer, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the outer layer ceramic was 1.0040, and ZrO2 was not added. Additionally, the grinding time was changed from 24 hours to 12 hours.

[0159] In addition, when fabricating the side margin green body, hydrothermal synthesized BaTiO3 powder (average particle size 100 nm) was used instead of hydrothermal synthesized BaTiO3 powder (average particle size 130 nm). Additionally, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the side margin ceramic was 1.0045. Except for this, a multilayer ceramic capacitor was fabricated in the same manner as in Example 1. Meanwhile, hydrothermal synthesized BaTiO3 powder (average particle size 100 nm) was synthesized using the same procedure as hydrothermal synthesized BaTiO3 powder (average particle size 130 nm), except that the slurry temperature during hydrothermal synthesis was lowered.

[0160] [Example 12]

[0161] In Example 12, hydrothermal synthesized BaTiO3 powder (average particle size 100 nm) was used instead of hydrothermal synthesized BaTiO3 powder (average particle size 130 nm) when preparing the green sheet for the outer layer. In addition, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the outer layer ceramic was 1.0045, and ZrO2 was not added. Additionally, the grinding time was changed from 24 hours to 12 hours. Except for these changes, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0162] [Example 13]

[0163] In Example 13, the amount of ZrO2 added during the production of the inner layer ceramic green sheet was changed from 0.55 mass% to 0.2 mass%. A multilayer ceramic capacitor was produced in the same manner as in Example 1.

[0164] [Comparative Example 1]

[0165] In Comparative Example 1, hydrothermal synthesized BaTiO3 powder (average particle size 150 nm) was used instead of hydrothermal synthesized BaTiO3 powder (average particle size 130 nm) when fabricating the side margin green body. Additionally, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the side margin ceramic was 1.0027. Furthermore, ZrO2 was added along with BaCO3, and the amount added (amount of ZrO2 added) was set to 0.55 mass% relative to the BaTiO3 powder. Additionally, the grinding time was changed from 12 hours to 24 hours. Except for these changes, a multilayer ceramic capacitor was fabricated in the same manner as in Example 1. Meanwhile, hydrothermal synthesized BaTiO3 powder (average particle size 150 nm) was synthesized using the same procedure as hydrothermal synthesized BaTiO3 powder (average particle size 130 nm), except that the slurry temperature during hydrothermal processing was increased.

[0166] The manufacturing conditions of the multilayer ceramic capacitors of Examples 1 to 13 and Comparative Example 1 are summarized in Table 1 below.

[0167]

[0168] (2) Evaluation

[0169] For the multilayer ceramic capacitors fabricated in Examples 1 to 13 and Comparative Example 1, various characteristics were evaluated as follows.

[0170] <TEM Observation>

[0171] Using a transmission electron microscope (TEM), the void ratio within the particles was investigated for the inner layer center, inner layer W end, side margin, and outer layer of a multilayer ceramic capacitor as follows. First, the WT surface was exposed by polishing the multilayer ceramic capacitor until the dimension in the length (L) direction was reduced to approximately 1 / 2. Subsequently, a dielectric layer located at approximately 1 / 2 of the thickness (T) dimension in the polished body was designated, and the region located at approximately 1 / 2 of the width (W) dimension was defined as the inner layer center (Fig. 4). Furthermore, the boundary between the internal electrode layer and the side margin was defined for the designated dielectric layer, and the portion of the dielectric layer included within a distance of up to 3 μm toward the inner layer center from this boundary was defined as the inner layer W end (Fig. 4). In this case, if the ends of each pair of internal electrode layers were offset in the W direction, the end closer to the inner layer center was used as the boundary (Fig. 4). Samples for the inner layer center and the inner layer W end were cut separately to include each designated area, and each was thinned down to 100 nm or less to serve as TEM observation samples for investigating the void ratio within the particles of the inner layer center and the inner layer W end. For the side margin, a sample was cut from the body portion after polishing at a position approximately 1 / 2 of the thickness (T) dimension and also approximately 1 / 2 of the side margin width, and thinned down to 100 nm or less to serve as TEM samples for investigating the void ratio within the particles. For the outer layer, a sample was cut from the body portion after polishing at a position approximately 1 / 2 of the width (W) dimension and also approximately 1 / 2 of the outer layer thickness, and thinned down to 100 nm or less to serve as TEM samples for investigating the void ratio within the particles.

[0172] Then, TEM observations were performed on the inner layer center, inner layer W end, outer layer, and side margins, respectively. From the fabricated TEM observation samples, the number of vacant holes present in the dielectric particles was counted, and the obtained number was [calculated] for the area of ​​the ceramic part (10㎛). 2Based on the above) divided by unit area (1㎛) 2 The number of ) per was calculated. The same operation was performed at three locations (n=3) each of the inner layer center, inner layer W end, side margin, and outer layer, and the average value of the number of empty holes in the particles per unit area was calculated as the ratio of empty holes in the particles.

[0173] <SEM Observation>

[0174] Using a scanning electron microscope (SEM), the WT plane of a multilayer ceramic capacitor was observed to investigate the thickness of the dielectric layer. Specifically, the multilayer ceramic capacitor was polished to the center in the L direction to expose the cut surface (WT plane). Then, on the exposed cut surface, the thickness of the dielectric layer located near the center in the thickness direction was measured on a total of five lines: a center line in the W direction and two lines drawn at equal intervals on both sides from the center line in the W direction, and the average value was taken as the thickness of the dielectric layer.

[0175] In addition, under conditions of a magnification of 25,000x, an acceleration voltage of 15 kV, and a field of view of 4 µm × 5 µm, an SEM image of dielectric particles within the dielectric layer was captured at the WT cross-section near the center in the L direction. At this time, imaging was performed to include the dielectric layer portion at the center of the inner layer near the center in the W and T directions, and also to include the W end portion of the inner layer of the same dielectric layer. Subsequently, using image processing software, the edges (equivalent to grain boundaries) of all dielectric particles included within an area defined by a length of 3 µm in the W direction and the dielectric layer thickness were recognized. Then, the cross-sectional area of ​​each recognized particle was calculated, a virtual circle equal to this area was conceived, and the diameter of this virtual circle (circle equivalent diameter) was defined as the particle diameter. Excluding dielectric particles where a portion of the particle was pushed out beyond the designated area, the circle equivalent diameters of all dielectric particles included within the captured range were measured. Then, the D50 diameter of the inner layer center (D50[inner layer center]) and the D50 diameter of the inner layer W end (D50[inner layer W end]) were determined. Meanwhile, the D50 diameter is the cumulative 50% diameter based on the cross-sectional area of ​​the dielectric particle. That is, the cross-sectional areas of all measured dielectric particles are summed to obtain the total cross-sectional area, and the cross-sectional area is normalized so that this becomes 100%. Subsequently, the cross-sectional areas are all added in order starting from the particle with the smallest cross-sectional area to obtain the cumulative cross-sectional area, and the particle circle equivalent diameter when the cumulative cross-sectional area reaches 50% of the total cross-sectional area is determined as the D50 diameter.

[0176] <HALT>

[0177] A super-accelerated life test (HALT) was performed using a multilayer ceramic capacitor as a sample, and the mean time to failure (MTTF) was calculated. In the test, a load of 150°C and 50V was applied to the sample. The time at which the insulation resistance (IR) became 200kΩ or less was defined as the time to failure. The time to failure was measured for 72 samples fabricated under the same conditions.

[0178] Next, the obtained data was plotted on a Weibull probability plot to obtain the Weibull distribution. From the obtained Weibull distribution, the relationship between the failure time and the cumulative failure rate was linearly regressed, and the slope was calculated as the shape parameter (m). In addition, the failure time at which the cumulative failure rate reaches 63.2% was determined, and the mean time to failure (MTTF) was determined using this failure time and the shape parameter (m) corresponding to the slope of the regression line.

[0179] <Polar IR>

[0180] For 100 samples, a voltage of 25V was applied at room temperature for 60 seconds, and the current flowing through the sample at that time was measured to calculate the forward IR using Ohm's law. Next, the voltage application method was reversed, and a voltage of 25V was applied at room temperature for 60 seconds, and the current flowing through the sample at that time was measured to calculate the reverse IR using Ohm's law. After calculating the common logarithm of the forward IR and the reverse IR, the absolute value of the difference between the two (IR difference) was calculated. The number of samples for which the absolute value of the IR difference exceeded 0.3 was counted, and the ratio to the number of measured samples was calculated as the polar IR generation rate (%).

[0181] <Bending Test>

[0182] A multilayer ceramic capacitor was soldered (vertically mounted) onto a glass epoxy substrate (FR-4, 1.6 mm thick) so that the outer layer was perpendicular to the surface of the substrate (Fig. 7). A load was applied from above at a speed of 1.0 mm / second to the center of the ceramic body of the multilayer ceramic capacitor, and the load was maintained for 5 ± 1 seconds starting from the point when the bending amount reached 2.0 mm and 2.5 mm. Afterward, the LW surface of the maintained multilayer ceramic capacitor was polished in the T direction, which is perpendicular to this surface, until the T-direction dimension was reduced to half. The polished surface was observed to check for the presence or absence of cracks, and the results obtained were recorded. The number of samples for this vertical mounting bending test was set to 10.

[0183] Next, a separate multilayer ceramic capacitor was prepared and soldered (horizontally mounted) so that the outer layer was parallel to the surface of a glass epoxy substrate (Fig. 7). A load was applied from above at a speed of 1.0 mm / second to the center of the ceramic body of the multilayer ceramic capacitor, and the load was maintained for 5 ± 1 seconds starting from the point when the bending amount reached 2.0 mm and 2.5 mm. Afterward, the LT surface of the maintained multilayer ceramic capacitor was polished in the W direction, which is perpendicular to this surface, until it became half the W dimension. The polished surface was observed to check for the presence or absence of cracks, and the results obtained were recorded. The number of samples for this horizontal mounting bending test was set to 10.

[0184] Then, from the results of the vertical mounting test and the horizontal mounting test, the crack occurrence rate was calculated according to the following equation (1). In the following equation (1), n[vertical] represents the number of samples in which cracks occurred in the vertical mounting test, and n[horizontal] represents the number of samples in which cracks occurred in the horizontal mounting test. Also, N[total] is the total number of samples (20) provided for the test (vertical mounting test, horizontal mounting test).

[0185]

[0186] (3) Evaluation results

[0187] The evaluation results obtained for Examples 1 to 13 and Comparative Example 1 are summarized in Table 2.

[0188] In Examples 1 to 13, the ratio of voids within particles in the side margin (N[side margin]) was greater than the ratio of voids within particles in the inner layer center (N[inner layer center]). Additionally, the ratio of the average particle diameter of the dielectric particles in the inner layer center to the D50 diameter of the dielectric particles in the inner layer W end (D50[inner layer W end] / D50[inner layer center]) satisfied a relationship of 1.00 or greater and 1.40 or less. Consequently, the mean time to failure (MTTF) was relatively long, exceeding 30 hours.

[0189] In Examples 1 to 12, polar IR was suppressed in addition to the effects described above. Specifically, the ratio of vacant particles in the central part of the inner layer was 10 / µm. 2 It is less than that, and for that reason, the polar IR generation rate was low at 3% or less.

[0190] In Examples 7, 8, and 10 to 12, in addition to the effects described above, crack occurrence was suppressed. Specifically, the ratio of empty holes within particles in the outer layer (N[outer layer]) was greater than the ratio of empty holes within particles in the center of the inner layer (N[outer layer]). As a result, the crack occurrence rate in a bending test with a bending amount of 2.5 mm was low at 5% or less.

[0191] In contrast, in Comparative Example 1, the ratio of voids within particles in the side margin region (N[side margin region]) was smaller than the ratio of voids within particles in the inner layer center region (N[inner layer center region]). As a result, the MTTF was relatively short at 27 hours.

[0192]

[0193] From the above results, it is understood that according to the present embodiment, a highly reliable multilayer ceramic capacitor with suppressed insulation resistance degradation is provided. Explanation of the symbols

[0194] 2: Dielectric layer 4: Internal electrode layer 6: Body part 8a: First external electrode 8b: Second external electrode 10a: First outer surface 10b: Second outer surface 12a: First outer surface 12b: Second outer surface 14a: First outer cross-sectional surface 14b: Second outer section 16: Inner layer 18a: 1st outer layer 18b: 2nd outer layer 20a: First side margin section 20b: Second side margin section 22: Internal area 100: Multilayer ceramic capacitor

Claims

Claim 1 An inner layer portion having a first internal electrode layer and a second internal electrode layer alternately stacked with a dielectric layer formed of a ceramic dielectric in between, a first main surface which is a surface in the stacking direction, a second main surface which is a surface opposite to the first main surface, a first side surface which is a surface in the width direction orthogonal to the first main surface and the second main surface and from which the first internal electrode layer and the second internal electrode layer are drawn, a second side surface which is a surface opposite to the first side surface and from which the first internal electrode layer and the second internal electrode layer are drawn, a first end surface which is a surface in the length direction orthogonal to the first main surface, the second main surface, the first side surface, and the second side surface and from which the first internal electrode layer is drawn, and a second end surface which is a surface opposite to the first end surface and from which the second internal electrode layer is drawn, a first outer layer portion formed of a ceramic dielectric and covering the first main surface from the stacking direction, and a ceramic dielectric A multilayer ceramic capacitor comprising: a second outer layer portion formed and covering the second main surface from the stacking direction; a first side margin portion formed of a ceramic dielectric and covering the inner layer portion, the first outer layer portion, and the second outer layer portion from one side in the width direction; a second side margin portion formed of a ceramic dielectric and covering the inner layer portion, the first outer layer portion, and the second outer layer portion from the other side in the width direction; and a pair of external electrodes provided on the first cross section and the second cross section and connected to each of the first internal electrode layer and the second internal electrode layer, wherein the dielectric particles constituting each of the ceramic dielectrics constituting the inner layer portion, the first side margin portion, and the second side margin portion include dielectric particles having empty holes inside, and the ratio of empty holes within the particles (N[inner layer center portion]) at the central portion of the inner layer portion (inner layer center portion), and the ratio of empty holes within the particles (N[side The margin region satisfies the relationship N[inner layer center] < N[side margin region], andA multilayer ceramic capacitor, wherein the ratio of voids within the particles is the number of voids within the particles per unit area in a cross-sectional plane traversing the longitudinal center of the multilayer ceramic capacitor, and the D50 diameter of the dielectric particle at the widthwise end (inner layer W end) of the inner layer (D50[inner layer W end]) and the D50 diameter of the dielectric particle at the center (inner layer center) of the inner layer (D50[inner layer center]) satisfy the relationship: 1.00 ≤ D50[inner layer W end] / D50[inner layer center] ≤ 1.

40. Claim 2 In claim 1, the ratio of empty holes within particles (N[central part of inner layer]) in the central part of the inner layer is 0 / ㎛ 2 Exceeding 10 particles / ㎛ 2 Multilayer ceramic capacitor. Claim 3 A multilayer ceramic capacitor according to claim 1 or 2, wherein the ceramic dielectric constituting the first outer layer and the second outer layer comprises dielectric particles having empty holes inside, and the ratio of empty holes within the particles (N[central part of inner layer]) in the central part of the inner layer (central part of inner layer) and the ratio of empty holes within the particles (N[outer layer]) in the first outer layer and the second outer layer satisfy the relationship: N[central part of inner layer] < N[outer layer].

Images