Redistribution layer structure, method of forming redistribution layer structure, semiconductor package device including redistribution layer structure, and method of manufacturing semiconductor package device including redistribution layer structure

Abstract

A rearrangement layer structure, a method for forming the rearrangement layer structure, a semiconductor package device including the rearrangement layer structure, and a method for manufacturing the semiconductor package device including the rearrangement layer structure are disclosed. The disclosed semiconductor package device may include a chip and a rearrangement layer structure electrically connected to the chip, wherein the rearrangement layer structure has one or more openings that are open to a target area within a size range of a given target area, wherein the one or more openings are areas where an electrical identical element is formed to which the same electrical signal is applied, and wherein an unetched portion for improving the flatness of the rearrangement layer structure is provided in the remaining area excluding the one or more openings in a space corresponding to the target area, and wherein the unetched portion may include a first insulating layer disposed between two or more of the openings or disposed such that more than half thereof is surrounded by one of the openings, and a first wiring member layer disposed on the first insulating layer to at least partially fill the one or more openings and including the electrical identical element formed within the one or more openings.

Description

Technology Field

[0001] The present invention relates to electronic devices / semiconductor devices, components thereof, and methods for manufacturing the same, and more specifically, to a rearrangement layer structure, a device including the same, and methods for manufacturing the same. Background Technology

[0002] The redistribution layer (RDL) process can be one of the critical steps in the manufacturing process of semiconductor devices / electrical devices. For example, the RDL process can be usefully applied in packaging chips (i.e., dies) and connecting them to external circuits during the manufacturing of semiconductor devices.

[0003] RDL can serve the role of rearranging the electrode pad array of a semiconductor chip or the electrode pad array of a package substrate. RDL can be used as a method to overcome design limitations of chips manufactured during the semiconductor preprocess (i.e., front-end process) through packaging. Furthermore, as various package interconnection designs may be required to apply chips to diverse systems according to customer demands, using RDL can be highly useful as it can replace the redesign of electrical terminals. In addition, in advanced packaging processes such as fan-out processes and processes for packaging multiple chips together, RDL technology can be effectively applied to form fine connection patterns and rearrange I / O terminals. Moreover, RDL can be related to enhancing the signal transmission capabilities and thermal management of semiconductor chips, and can play a role in improving the performance and efficiency of semiconductor chips in various aspects.

[0004] The RDL process may include steps such as forming an insulating layer with via holes, forming a seed layer, forming a mask pattern, electroplating a wiring layer, and removing the mask pattern. It is necessary to secure via holes of an appropriate size to connect signal traces to electrode pads on the chip or substrate. To improve electrical connectivity, it may be desirable to have large via hole sizes. However, if the via hole size is large, topology problems may occur after electroplating the wiring layer. As chip size is reduced and pattern size is miniaturized, the diameter of the via hole can be reduced to tens of micrometers or less; however, it may still be large enough to cause topology problems, which can lead to reliability issues. For example, if the via hole size is large, bending and sagging (sagging of the pattern area) may occur in the RDL layer, which can lead to electrical short circuits, an increase in the failure rate, and a decrease in reliability. The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide a rearrangement layer (RDL) structure capable of improving reliability by improving topology and flatness, and a device including the same (e.g., a semiconductor package device).

[0006] In addition, the technical problem to be solved by the present invention is to provide a method for forming the aforementioned rearrangement layer (RDL) structure and a method for manufacturing a device (e.g., a semiconductor package device) to which the same is applied.

[0007] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be understood by those skilled in the art from the description below. means of solving the problem

[0008] According to one embodiment of the present invention, a semiconductor package device is provided comprising: a chip; and a rearrangement layer structure electrically connected to the chip; wherein the rearrangement layer structure has one or more openings that are open to a target area within a size range of a given target area, and the one or more openings are areas where electrical identical elements are formed to which the same electrical signal is applied, and an unetched portion for improving the flatness of the rearrangement layer structure is provided in the remaining area excluding the one or more openings in a space corresponding to the target area, and the unetched portion is disposed between two or more of the openings or is disposed such that more than half thereof is surrounded by one of the openings; and a first wiring member layer disposed on the first insulating layer to at least partially fill the one or more openings and includes the electrical identical elements formed within the one or more openings.

[0009] The first insulating layer may include a plurality of openings formed spaced apart from each other on the target area, and the unetched portion may be provided between the plurality of openings.

[0010] The first insulating layer may include an opening having a ring structure or a partial ring structure on the target area, and the unetched portion may be provided to be surrounded by the ring structure or the partial ring structure.

[0011] At least a portion of the above-mentioned unetched portion may be located in an area corresponding to the center of the above-mentioned target area.

[0012] The above one or more openings may have a diameter or line width in the range of about 1 to 10 μm.

[0013] The above target area may be a given surface area of ​​one electrode pad or a corresponding area.

[0014] The above rearrangement layer structure may further include a second insulating layer disposed on the first insulating layer to at least partially cover the first wiring member layer; and a second wiring member layer disposed on the second insulating layer.

[0015] The above target area may be a first target area, the above one or more openings may be a first opening, the above unetched part may be a first unetched part, and the above electrical identical element may be a first electrical identical element. The second insulating layer may have one or more second openings that are opened to the second target area within the size range of the given second target area of ​​the first wiring member layer, and the one or more second openings may be an area where a second electrical identical element is formed to which the same electrical signal is applied, and the second insulating layer may have a second unetched part for improving the flatness of the rearrangement layer structure in the remaining area excluding the one or more second openings in the space corresponding to the second target area, and the second unetched part may be arranged between two or more of the second openings or arranged so that more than half thereof is surrounded by one of the second openings. The second wiring member layer may be disposed on the second insulating layer to at least partially fill the one or more second openings and may include the second electrical identical element formed within the one or more second openings.

[0016] The second insulating layer may include a plurality of second openings formed spaced apart from each other on the second target area, and the second non-etching portion may be provided between the plurality of second openings.

[0017] The second insulating layer may include a second opening having a ring structure or a partial ring structure on the second target area, and the second unetched portion may be provided to be surrounded by the ring structure or the partial ring structure.

[0018] According to another embodiment of the present invention, a method for forming a rearrangement layer structure is provided, comprising: a step of forming a first insulating layer having one or more openings that are open to a target area within a size range of a given target area, wherein the one or more openings are areas where electrical identical elements are formed to which the same electrical signal is applied, and wherein an unetched portion for improving the flatness of the rearrangement layer structure is provided in the remaining area excluding the one or more openings in a space corresponding to the target area, and wherein the unetched portion is disposed between two or more of the openings or wherein more than half thereof is surrounded by one of the openings; and a step of forming a first wiring member layer disposed on the first insulating layer to at least partially fill the one or more openings and comprising the electrical identical elements formed within the one or more openings.

[0019] The first insulating layer may include a plurality of openings formed spaced apart from each other on the target area, and the unetched portion may be provided between the plurality of openings.

[0020] The first insulating layer may include an opening having a ring structure or a partial ring structure on the target area, and the unetched portion may be provided to be surrounded by the ring structure or the partial ring structure.

[0021] The above target area may be a given surface area of ​​one electrode pad or a corresponding area.

[0022] The method for forming the above rearrangement layer structure may further include the step of forming a second insulating layer on the first insulating layer that at least partially covers the first wiring member layer; and the step of forming a second wiring member layer on the second insulating layer.

[0023] The above target area may be a first target area, the above one or more openings may be a first opening, the above unetched part may be a first unetched part, and the above electrical identical element may be a first electrical identical element. The second insulating layer may have one or more second openings that are opened to the second target area within the size range of the given second target area of ​​the first wiring member layer, and the one or more second openings may be an area where a second electrical identical element is formed to which the same electrical signal is applied, and the second insulating layer may have a second unetched part for improving the flatness of the rearrangement layer structure in the remaining area excluding the one or more second openings in the space corresponding to the second target area, and the second unetched part may be arranged between two or more of the second openings or arranged so that more than half thereof is surrounded by one of the second openings. The second wiring member layer may be disposed on the second insulating layer to at least partially fill the one or more second openings and may include the second electrical identical element formed within the one or more second openings.

[0024] The second insulating layer may include a plurality of second openings formed spaced apart from each other on the second target area, and the second non-etching portion may be provided between the plurality of second openings.

[0025] The second insulating layer may include a second opening having a ring structure or a partial ring structure on the second target area, and the second unetched portion may be provided to be surrounded by the ring structure or the partial ring structure.

[0026] According to another embodiment of the present invention, a method for manufacturing a semiconductor package device comprising a chip and a rearrangement layer structure electrically connected to the chip is provided, comprising the step of forming the rearrangement layer structure using the method described above.

[0027] The method for manufacturing the above semiconductor package device can be performed, for example, in a WLP (wafer level package) or PLP (panel level package) manner. Effects of the invention

[0028] According to embodiments of the present invention, a rearrangement layer (RDL) structure capable of improving reliability by improving topology and flatness, and a device including the same (e.g., a semiconductor package device) can be implemented. By using the rearrangement layer (RDL) structure according to the embodiment, excellent electrical connectivity between components can be secured, while preventing problems such as bending or sagging (sagging of the pattern portion) caused by large-sized via holes (openings), thereby reducing the defect rate of the device and improving reliability.

[0029] For example, the rearrangement layer (RDL) structure and the method for forming the same according to the embodiments of the present invention can be usefully applied to advanced packaging processes such as fan-in processes, fan-out processes, and integrated packaging processes that package multiple chips together. Furthermore, the rearrangement layer (RDL) structure and the method for forming the same according to the embodiments of the present invention can be applied to chip-first (i.e., die-first) processes and chip-last (i.e., die-last) processes. Additionally, the rearrangement layer (RDL) structure and the method for forming the same according to the embodiments of the present invention can be applied to a substrate for packaging. Furthermore, the rearrangement layer (RDL) structure and the method for forming the same according to the embodiments of the present invention can be applied to the manufacture of various electronic devices / semiconductor devices.

[0030] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention. Brief explanation of the drawing

[0031] FIG. 1a is a cross-sectional view illustrating a redistribution layer structure according to one embodiment of the present invention. FIG. 1b is a plan view showing the shape and arrangement of a plurality of openings in the first insulating layer of FIG. 1a. FIG. 2a is a cross-sectional view illustrating a rearrangement layer structure according to another embodiment of the present invention. FIG. 2b is a plan view showing the shape of the opening of the first insulating layer of FIG. 2a. FIG. 3a is a cross-sectional view illustrating the rearrangement layer structure according to a comparative example. Figure 3b is a plan view showing the shape of the opening of the first insulating layer of Figure 3a. FIGS. 4 to 7 are plan views illustrating, exemplarily, the arrangement of a plurality of openings that a first insulating layer may have, which can be applied to a rearrangement layer structure according to another embodiment of the present invention. FIG. 8 is a plan view exemplarily showing the shape and arrangement of an opening that a first insulating layer may have, which can be applied to a rearrangement layer structure according to another embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating the rearrangement layer structure and its problems according to a comparative example. FIG. 10 is a cross-sectional view illustrating a rearrangement layer structure according to another embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating the rearrangement layer structure and its problems according to a comparative example. FIG. 12 is a cross-sectional view illustrating a rearrangement layer structure according to another embodiment of the present invention. FIGS. 13a to 13c are cross-sectional views showing a method for forming a rearrangement layer structure according to an embodiment of the present invention. FIGS. 14a to 14d are cross-sectional views showing a method for forming a rearrangement layer structure according to another embodiment of the present invention. FIGS. 15a to 15d are cross-sectional views showing a method for manufacturing a semiconductor package device by applying a method for forming a rearrangement layer structure according to one embodiment of the present invention. FIGS. 16a to 16e are cross-sectional views showing a method for manufacturing a semiconductor package device by applying a method for forming a rearrangement layer structure according to another embodiment of the present invention. Figure 17 is a cross-sectional photographic image showing a part of a semiconductor package device manufactured according to a comparative example. FIG. 18 is a cross-sectional photographic image showing a part of a semiconductor package device manufactured according to an embodiment of the present invention. FIG. 19 is a photographic image showing a portion of the surface of a semiconductor package device manufactured according to an embodiment of the present invention. Specific details for implementing the invention

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0033] The embodiments of the present invention described below are provided to more clearly explain the present invention to those skilled in the art, and the scope of the present invention is not limited by the following embodiments, and the following embodiments may be modified in various other forms.

[0034] The terms used herein are for describing specific embodiments and are not intended to limit the invention. Terms used herein in the singular form may include plural forms unless the context clearly indicates otherwise. Additionally, the terms “comprise” and / or “comprising” used herein specify the presence of the mentioned features, steps, numbers, actions, components, elements, and / or groups thereof, and do not exclude the presence or addition of one or more other features, steps, numbers, actions, components, elements, and / or groups thereof. Furthermore, the term “connected” used herein means not only that components are directly connected, but also includes the concept of indirectly connecting components through the interposition of additional components between them.

[0035] Furthermore, when a component is described in this specification as being located "on" another component, this includes not only cases where a component is in contact with another component, but also cases where another component exists between the two components. The term "and / or" as used in this specification includes any one of the listed items and all combinations of one or more thereof. Additionally, terms of degree such as "about" and "substantially" as used in this specification are used to mean a range of numerical values ​​or degrees or approximate values, taking into account inherent manufacturing and material tolerances, and are used to prevent an infringer from unfairly exploiting the disclosures in which precise or absolute figures provided to aid in understanding this specification are mentioned.

[0036] Embodiments of the present invention will be described in detail below with reference to the attached drawings. The sizes or thicknesses of the areas or parts depicted in the attached drawings may be slightly exaggerated for the clarity of the specification and convenience of explanation. Throughout the detailed description, the same reference numerals indicate the same components.

[0037] FIG. 1a is a cross-sectional view illustrating a redistribution layer structure according to an embodiment of the present invention. FIG. 1b is a plan view showing the shape and arrangement of a plurality of openings in the first insulating layer of FIG. 1a.

[0038] Referring to FIGS. 1a and 1b, a rearrangement layer structure according to an embodiment of the present invention may include a first insulating layer (NL10) disposed on a predetermined support surface (substrate surface) and a first wiring member layer (WL10) disposed on the first insulating layer (NL10). The first insulating layer (NL10) may have one or more openings (V10) that are open to a given target area (R10 in FIG. 1b). The one or more openings (V10) may be open to the target area (R10) within a size range of the target area (R10). The first wiring member layer (WL10) may be disposed on the first insulating layer (NL10) to at least partially fill the one or more openings (V10). In this embodiment, the first insulating layer (NL10) may have a plurality of openings (V10). The openings (V10) may be referred to as via holes or vias. When viewed from above, the opening (V10) may have a shape such as a circle, ellipse, square, or a square with rounded corners. The target area (R10) is an area where a plurality of openings (V10) are formed, and may also be referred to as the area of ​​interest. When viewed from above, the target area (R10) may have a shape such as a circle, ellipse, square, or a square with rounded corners.

[0039] The above one or more openings (V10), i.e., multiple openings (V10), may be regions where electrical identical elements (identical bodies) to which the same electrical signal is applied are formed. The same electrical signal may be applied simultaneously to the electrical identical elements. In the space corresponding to the target region (R10), an unetched portion (U10) for improving the flatness of the rearrangement layer structure may be provided in the remaining region of the first insulating layer (NL10), excluding the one or more openings (V10), i.e., multiple openings (V10). The unetched portion (U10) is a portion of the first insulating layer (NL10) that has not been etched (removed) and may be disposed between two or more openings (V10), i.e., between multiple openings (V10). The unetched region of the first insulating layer (NL10) may also extend to the outside of the target region (R10).

[0040] The first wiring member layer (WL10) may include the electrical identical element (identical body) formed within the one or more openings (V10), that is, the plurality of openings (V10). The same electrical signal may be simultaneously applied to the electrical identical element formed within the plurality of openings (V10). The electrical identical element may be a conductor that at least partially fills the openings (V10).

[0041] In this embodiment, the first insulating layer (NL10) may include a plurality of openings (V10) formed spaced apart from each other on the target area (R10). In other words, a plurality of segmented openings (V10) may be arranged spaced apart from each other on the target area (R10). As a non-limiting example, the plurality of openings (V10) may be arranged to be placed at each vertex of a square approximately. Also, as a non-limiting example, the plurality of openings (V10) may be arranged to be in contact with the edges (ends) of the target area (R10). An unetched portion (U10) may be provided between the plurality of openings (V10). In this case, according to one example, at least a portion of the unetched portion (U10) may be positioned corresponding to the center of the target area (R10).

[0042] The above one or more openings (V10) may have a diameter or line width in the range of, for example, about 1 to 10 μm. In the embodiment of FIG. 1b, the plurality of openings (V10) may have a diameter (D1) in the range of, for example, about 1 to 10 μm or about 3 to 10 μm. The spacing (S1) between the plurality of openings (V10) may be, for example, about 0.1 to 20 μm. Meanwhile, the diameter (RD1) (or width) of the target area (R10) may be, for example, about 10 to 30 μm. According to a specific example, the diameter (RD1) of the target area (R10) may be about 20 μm, the diameter (D1) of the opening (V10) may be about 5 μm, and the minimum spacing (S1) between two adjacent openings (V10) may be about 5.61 μm. However, the size of the aforementioned target area (R10), the size of the opening (V10), and the range of spacing between the openings (V10) are merely exemplary and may vary.

[0043] According to an embodiment of the present invention, the target area (R10) may be a given surface area of ​​one electrode pad (PD10) or a corresponding area. The electrode pad (PD10) may be formed on a predetermined substructure. For example, the electrode pad (PD10) may be an electrode pad (bonding pad) of a chip (i.e., die) or an electrode pad (bonding pad) of a substrate for a package. A plurality of openings (V10) may be formed for one electrode pad (PD10), and an electrical identical element (a type of via wiring) connected to the electrode pad (PD10) may be formed within the plurality of openings (V10).

[0044] The above rearrangement layer structure may further include a second insulating layer (NL20) disposed to at least partially cover a first wiring member layer (WL10) on a first insulating layer (NL10), and a second wiring member layer (WL20) disposed on the second insulating layer (NL20). However, the second insulating layer (NL20) and the second wiring member layer (WL20) may not be provided. Additionally, if necessary, an additional insulating layer and an additional wiring member layer may be alternately formed one or more times on the second wiring member layer (WL20).

[0045] The first and second insulating layers (NL10, NL20) may be formed as organic insulating layers or inorganic insulating layers. The first and second insulating layers (NL10, NL20) may be formed of the same material or different materials. The first and second wiring member layers (WL10, WL20) may be formed of conductive materials such as metals, alloys, or metal compounds. Each of the first and second wiring member layers (WL10, WL20) may be formed, for example, by forming a seed layer on the entire surface of the substrate, forming a mask pattern on the seed layer, forming a wiring layer by electroplating from the portion of the seed layer exposed by the mask pattern, and then removing the mask pattern and the portion of the seed layer underneath. The first and second wiring member layers (WL10, WL20) may include, for example, Cu wiring, but the material of the wiring is not limited to Cu and can be varied in many ways. The wiring material used in a general rearrangement layer may be applicable to the first and second wiring member layers (WL10, WL20).

[0046] According to an embodiment of the present invention, instead of forming a large opening (via) corresponding to the entire target area (R10), a plurality of small openings (vias) (i.e., V10) spaced apart from each other are formed with respect to the target area (R10) to leave an unetched portion (U10) given on the target area (R10), thereby improving the topology and flatness of the rearrangement layer structure. Accordingly, while ensuring excellent electrical connectivity between components, problems such as bending or sagging (sagging of the pattern portion) caused by large-sized openings (vias) can be prevented, and as a result, the defect rate of the device can be lowered and reliability can be improved.

[0047] FIG. 2a is a cross-sectional view illustrating a rearrangement layer structure according to another embodiment of the present invention. FIG. 2b is a plan view showing the shape of an opening in the first insulating layer of FIG. 2a.

[0048] Referring to FIGS. 2a and 2b, a rearrangement layer structure according to the present embodiment may include a first insulating layer (NL11) disposed on a predetermined support surface (substrate surface) and a first wiring member layer (WL11) disposed on the first insulating layer (NL11). The first insulating layer (NL11) may have one or more openings (V11) that are open to a given target area (R10 in FIG. 2b). The one or more openings (V11) may be open to the target area (R10) within a size range of the target area (R10). The first wiring member layer (WL11) may be disposed on the first insulating layer (NL11) to at least partially fill the one or more openings (V11). In the present embodiment, the first insulating layer (NL11) may have one opening (V11).

[0049] The above one or more openings (V11), i.e., one opening (V11), may be an area where an electrical identical element (identical body) to which the same electrical signal is applied is formed. The same electrical signal may be applied simultaneously to the electrical identical element. In the space corresponding to the target area (R10), an unetched portion (U11) for improving the flatness of the rearrangement layer structure may be provided in the remaining area of ​​the first insulating layer (NL11) excluding the one or more openings (V11), i.e., one opening (V11). The unetched portion (U11) is a part of the first insulating layer (NL11) that is not etched (removed), and may be arranged so that more than half thereof is surrounded by one opening (V11). An unetched area of ​​the first insulating layer (NL11) may also exist outside the target area (R10).

[0050] The first wiring member layer (WL11) may include one or more openings (V11), that is, the electrical identical element (identical body) formed within one opening (V11). The same electrical signal may be simultaneously applied to the electrical identical element formed within one opening (V11). The electrical identical element may be a conductor that at least partially fills the opening (V11).

[0051] In this embodiment, the first insulating layer (NL11) may have an opening (V11) having a ring structure or a partial ring structure on the target area (R10). The unetched portion (U11) may be provided to be surrounded by the opening (V11) having the ring structure or the partial ring structure. For example, the opening (V11) may have a ring structure, in which case the unetched portion (U11) may be completely surrounded by the ring structure. The ring structure may be referred to as a donut structure, and the partial ring structure may be referred to as a partial donut structure. According to one example, at least a portion of the unetched portion (U11) may be located in an area corresponding to the center of the target area (R10).

[0052] The above one or more openings (V11) may have a diameter or line width in the range of, for example, about 1 to 10 μm. In the embodiment of FIG. 2b, the opening (V11) may have a line width (D2) in the range of, for example, about 1 to 10 μm or about 3 to 10 μm. The width (S2) (or diameter) of the unetched portion (U11) may be, for example, about 0.1 to 20 μm or about 1 to 20 μm. Meanwhile, the diameter (RD1) (or width) of the target area (R10) may be, for example, about 10 to 30 μm. According to a specific example, the diameter (RD1) of the target area (R10) may be about 20 μm, the line width (D2) of the opening (V11) may be about 6.5 μm, and the width (S2) of the unetched area (U11) may be about 7.0 μm. However, the aforementioned ranges of the size of the target area (R10), the size of the opening (V11), and the size of the unetched area (U11) are merely exemplary and may vary in many ways.

[0053] According to an embodiment of the present invention, the target area (R10) may be a given surface area of ​​one electrode pad (PD11) or a corresponding area. The electrode pad (PD11) may be formed on a predetermined substructure. For example, the electrode pad (PD11) may be an electrode pad (bonding pad) of a chip (i.e., die) or an electrode pad (bonding pad) of a substrate for a package. An opening (V11) in the shape of a ring or partial ring may be formed on one electrode pad (PD11), and an electrical identical element (a type of via wiring) connected to the electrode pad (PD11) may be formed within the opening (V11).

[0054] The above rearrangement layer structure may further include a second insulating layer (NL21) disposed to at least partially cover a first wiring member layer (WL11) on a first insulating layer (NL11), and a second wiring member layer (WL21) disposed on the second insulating layer (NL21). The second insulating layer (NL21) and the second wiring member layer (WL21) may not be provided. An additional insulating layer and an additional wiring member layer may be alternately formed one or more times on the second wiring member layer (WL21).

[0055] According to an embodiment of the present invention, instead of forming a large opening (via) corresponding to the entire target area (R10), a ring or partial ring-shaped opening (via) (i.e., V11) is formed for the target area (R10) to leave an unetched portion (U11) given on the target area (R10), thereby improving the topology and flatness of the rearrangement layer structure. Accordingly, while ensuring excellent electrical connectivity between components, problems such as bending or sagging (sagging of the pattern portion) caused by large-sized openings (vias) can be prevented, and as a result, the defect rate of the device can be lowered and reliability can be improved.

[0056] FIG. 3a is a cross-sectional view illustrating the rearrangement layer structure according to a comparative example. FIG. 3b is a plan view showing the shape of the opening of the first insulating layer of FIG. 3a.

[0057] Referring to FIG. 3a and FIG. 3b, a rearrangement layer structure according to a comparative example may include a first insulating layer (NL50), a first wiring member layer (WL50), a second insulating layer (NL60), and a second wiring member layer (WL60) disposed on a substructure including an electrode pad (PD50). The first insulating layer (NL50) may have an opening (V50) that exposes the electrode pad (PD50), and the first wiring member layer (WL50) may be formed to extend over the first insulating layer (NL50) while largely filling the opening (V50).

[0058] In the above comparative example, the opening (V50) may have a diameter (width) of, for example, about 20 μm. As such, if the size of the opening (V50) is relatively large, problems with topology and flatness may occur in the rearrangement layer structure formed thereon due to the opening (V50), which may cause relatively large bending and sagging (sagging of the pattern part). As a result, in some cases, an electrical short circuit may occur, and problems such as an increased failure rate and reduced reliability may occur.

[0059] However, according to embodiments of the present invention, as previously described with reference to FIGS. 1a to 2b, the topology and flatness problems of the rearrangement layer structure can be improved by forming a plurality of mutually spaced openings (vias) in the target area (R10) or by forming openings having a ring or partial ring shape.

[0060] In an embodiment of the present invention, when a plurality of mutually spaced openings (vias) are formed with respect to a target area (R10), the number and arrangement of the plurality of openings (vias) may vary. Various variations are illustrated in FIGS. 4 to 7.

[0061] FIGS. 4 to 7 are plan views illustrating, exemplarily, the arrangement of a plurality of openings that a first insulating layer may have, which can be applied to a rearrangement layer structure according to another embodiment of the present invention.

[0062] Referring to FIG. 4, a plurality of openings (V12) may be formed in a target area (R10), and an etching portion (U12) may be provided between them. The plurality of openings (V12) may have an arrangement similar to FIG. 1b, but with a shape that is somewhat modified from FIG. 1b. One of the plurality of openings (V12) may be positioned to correspond to the central part of the target area (R10) or a part adjacent thereto.

[0063] Referring to FIG. 5, a plurality of openings (V13) may be formed in the target area (R10), and an etching portion (U13) may be provided between them. The plurality of openings (V13) may have an arrangement similar to FIG. 4, but with a shape that is somewhat modified from FIG. 4. The openings placed at the edges of the target area (R10) may be arranged, for example, to correspond approximately to each vertex of a triangle.

[0064] Referring to FIG. 6, a plurality of openings (V14) may be formed in a target area (R10), and an unetched portion (U14) may be provided between them. The plurality of openings (V14) may have an arrangement similar to FIG. 1b, but with a shape that is somewhat modified from FIG. 1b. The plurality of openings (V14) may be arranged, for example, to correspond approximately to each vertex of a hexagon.

[0065] Referring to FIG. 7, a plurality of openings (V15) may be formed in the target area (R10), and an etching portion (U15) may be provided between them. A relatively large number of openings (V15) may be formed in the target area (R10) spaced apart from each other.

[0066] However, the number, shape, and arrangement of the multiple openings shown in FIGS. 4 to 7 are exemplary, and various other variations may be possible.

[0067] In addition, in an embodiment of the present invention, when a ring or partial ring-shaped opening (via) is formed in the target area (R10), the number and arrangement of the openings (vias) may vary. One variation is illustrated in FIG. 8.

[0068] FIG. 8 is a plan view exemplarily showing the shape and arrangement of an opening that a first insulating layer may have, which can be applied to a rearrangement layer structure according to another embodiment of the present invention.

[0069] Referring to FIG. 8, a plurality of openings (V16) may be formed in a target area (R10), and unetched portions (U16) may be provided between and around them. At least one of the plurality of openings (V16) may have a ring structure or a partial ring structure. For example, the plurality of openings (V16) may have a ring structure and may have different sizes. The plurality of openings (V16) may be arranged concentrically from the center of the target area (R10) outward. An opening (V16) formed on the inside may be referred to as a first opening (V16a), and an opening (V16) formed on the outside may be referred to as a second opening (V16b). In the present embodiment, at least two unetched portions (U16) may be provided spaced apart from each other.

[0070] However, the number, shape, and arrangement of the openings shown in FIG. 8 are exemplary, and various other variations are possible.

[0071] FIG. 9 is a cross-sectional view illustrating the rearrangement layer structure and its problems according to a comparative example.

[0072] Referring to FIG. 9, the rearrangement layer structure according to the comparative example may have a structure similar to that described in FIG. 3. The rearrangement layer structure according to the comparative example may include a first insulating layer (NL51), a first wiring member layer (WL51), a second insulating layer (NL61), and a second wiring member layer (WL61) disposed on a lower structure (ST51) including an electrode pad (PD51). The first insulating layer (NL51) may have an opening (V51) that exposes the electrode pad (PD51), and the first wiring member layer (WL51) may be formed to extend over the first insulating layer (NL51) while approximately filling the opening (V51).

[0073] If the size of the opening (V51) of the first insulating layer (NL51) is large, even if the opening (V51) is filled to some extent with a metallic material through the plating process forming the first wiring member layer (WL51), a relatively large curvature may occur in the first wiring member layer (WL51). Consequently, the surfaces of the second insulating layer (NL61) and the second wiring member layer (WL61) above the opening (V51) may be distorted due to the step height of the opening (V51), as shown in FIG. 9. In other words, difficulties may arise in forming subsequent layers due to the high topology.

[0074] FIG. 10 is a cross-sectional view illustrating a rearrangement layer structure according to another embodiment of the present invention.

[0075] Referring to FIG. 10, the rearrangement layer structure according to the present embodiment may have a configuration corresponding to the rearrangement layer structure described in FIG. 1a or FIG. 2a. The rearrangement layer structure according to the present embodiment may include a first insulating layer (NL17), a first wiring member layer (WL17), a second insulating layer (NL27), and a second wiring member layer (WL27) disposed on a lower structure (ST17) including an electrode pad (PD17). The first insulating layer (NL17) may have one or more openings (V17) that expose the electrode pad (PD17), and the first wiring member layer (WL17) may be formed to extend onto the first insulating layer (NL17) while at least partially filling one or more openings (V17).

[0076] One or more openings (V17) may be opened into the target area within a given target area size range. One or more openings (V17) may be areas where electrical identical elements (identical bodies) to which the same electrical signal is applied are formed. In the space corresponding to the target area, an unetched portion (U17) may be provided in the remaining area of ​​the first insulating layer (NL17), excluding one or more openings (V17), to improve the flatness of the rearrangement layer structure. The unetched portion (U17) may be positioned between two or more of the openings or positioned so that more than half thereof is surrounded by one of the openings. For example, the first insulating layer (NL17) and one or more openings (V17) may have a configuration corresponding to any one of the embodiments described with reference to FIGS. 1a, FIGS. 1b, FIGS. 2a, FIGS. 2b, FIGS. 4 through 8. The first wiring member layer (WL17) may include the electrical identical element formed within one or more openings (V17).

[0077] In an embodiment of the present invention, the problems of the comparative example described in FIG. 9 can be overcome by dividing a single large opening (via) into several small openings (vias) or by forming an opening (via) having a ring (donut) structure or a partial ring (donut) structure. The opening (V17) of the first insulating layer (NL17) according to an embodiment of the present invention can be filled better by a plating method, and the influence of the step height at the opening (V17) of the first insulating layer (NL17) on the second insulating layer (NL27) and the second wiring member layer (WL27) can be reduced, thereby greatly improving the flatness of the layers. Accordingly, the process of forming subsequent layers can be facilitated after the formation of the first wiring member layer (WL17).

[0078] The layer illustrated as the first wiring member layer (WL17) in FIG. 10 may be a first wiring element, and the layer illustrated as the second wiring member layer (WL27) may be a second wiring element. The first wiring element and the second wiring element may or may not be electrically connected to each other. Additionally, although only the first and second wiring elements are illustrated here for convenience, the first wiring member layer (WL17) may include other wiring elements in addition to the first wiring element, and the second wiring member layer (WL27) may include other wiring elements in addition to the second wiring element.

[0079] FIG. 11 is a cross-sectional view illustrating the rearrangement layer structure and its problems according to a comparative example.

[0080] Referring to FIG. 11, a rearrangement layer structure according to a comparative example may include a first insulating layer (NL52), a first wiring member layer (WL52), a second insulating layer (NL62), and a second wiring member layer (WL62) disposed on a substructure (ST52) including an electrode pad (PD52). The first insulating layer (NL52) may have a first opening (V52) that exposes the electrode pad (PD52), and the first wiring member layer (WL52) may be formed to extend over the first insulating layer (NL52) while approximately filling the first opening (V52). The second insulating layer (NL62) may have a second opening (V62) that exposes the first wiring member layer (WL52), and the second wiring member layer (WL62) may be formed to extend over the second insulating layer (NL62) while partially filling the second opening (V62). A portion of the first wiring member layer (WL52) and a portion of the second wiring member layer (WL62) can be in direct contact with each other.

[0081] As illustrated in FIG. 11, when the openings (vias) are stacked, that is, when a second opening (V62) is formed on a first opening (V52), it is more difficult to fill the stacked openings (vias) with wiring material, so a high topology exists in the rearrangement layer structure above the stacked openings (vias) and a large bend may be created.

[0082] FIG. 12 is a cross-sectional view illustrating a rearrangement layer structure according to another embodiment of the present invention.

[0083] Referring to FIG. 12, the rearrangement layer structure according to the present embodiment may include a first insulating layer (NL18), a first wiring member layer (WL18), a second insulating layer (NL28), and a second wiring member layer (WL28) disposed on a substructure (ST18) including an electrode pad (PD18). The first insulating layer (NL18) may have one or more first openings (V18) that expose the electrode pad (PD18), and the first wiring member layer (WL18) may be formed to extend onto the first insulating layer (NL18) while at least partially filling one or more first openings (V18). The second insulating layer (NL28) may have one or more second openings (V28) that expose the first wiring member layer (WL18), and the second wiring member layer (WL28) may be formed to extend onto the second insulating layer (NL28) while at least partially filling one or more second openings (V28).

[0084] One or more first openings (V18) may be opened into the first target area within the size range of a given first target area. One or more first openings (V18) may be areas where a first electrical identical element (identical body) to which the same electrical signal is applied is formed. A first unetched portion (U18) may be provided in the remaining area of ​​the first insulating layer (NL18), excluding one or more first openings (V18) in the space corresponding to the first target area, to improve the flatness of the rearrangement layer structure. The first unetched portion (U18) may be positioned between two or more of the first openings or positioned so that more than half thereof is surrounded by one of the first openings. For example, the first insulating layer (NL18) and one or more first openings (V18) may have a configuration corresponding to any one of the embodiments described with reference to FIG. 1a, FIG. 1b, FIG. 2a, FIG. 2b, FIG. 4 through FIG. 8. The first wiring member layer (WL18) may include the first electrical identical element formed within one or more first openings (V18).

[0085] The second insulating layer (NL28) may have one or more second openings (V28) that are open to the second target area within the size range of a given second target area of ​​the first wiring member layer (WL18). One or more second openings (V28) may be areas where a second electrical identical element (identical body) to which the same electrical signal is applied is formed. The same electrical signal may be applied simultaneously to the second electrical identical element. The second insulating layer (NL28) may have a second unetched portion (U28) to improve the flatness of the rearrangement layer structure in the remaining area excluding one or more second openings (V28) in the space corresponding to the second target area. The second unetched portion (U28) may be positioned between two or more of the second openings or positioned so that more than half thereof is surrounded by one of the second openings. The second wiring member layer (WL28) may be disposed on the second insulating layer (NL28) to at least partially fill one or more second openings (V28) and may include said second electrical identical elements formed within one or more second openings (V28). said second electrical identical elements may be electrically connected to said first electrical identical elements.

[0086] One or more second openings (V28) may have a planar structure identical or similar to one or more openings described in the embodiments of FIG. 1a, FIG. 1b, FIG. 2a, FIG. 2b, FIG. 4 to FIG. 8. Accordingly, the second insulating layer (NL28) may include a plurality of second openings (V28) formed spaced apart from each other on the second target area, and a second unetched portion (U28) may be provided between the plurality of second openings (V28). Alternatively, the second insulating layer (NL28) may include a second opening (V28) having a ring structure or a partial ring structure on the second target area, and the second unetched portion (U28) may be provided to be surrounded by the ring structure or the partial ring structure. Additionally, one or more second openings (V28) may be positioned so as not to overlap with one or more first openings (V18), or to partially overlap, or to be offset. Furthermore, the shape and arrangement of one or more second openings (V28) may vary.

[0087] According to an embodiment of the present invention, openings (vias) having a relatively small width (diameter / line width) can be applied to the first insulating layer (NL18) and the second insulating layer (NL28) in an staggered or partially overlapping manner, thereby preventing direct stacking of the openings (vias) and improving the filling characteristics of the openings (vias). Through this, the surface of the second wiring member layer (WL28) can be made significantly flat compared to the comparative example of FIG. 11.

[0088] The layer illustrated as the first wiring member layer (WL18) in FIG. 12 may be a first wiring element, and the layer illustrated as the second wiring member layer (WL28) may be a second wiring element. The first wiring element and the second wiring element may be electrically connected to each other. Additionally, although only the first and second wiring elements are illustrated here for convenience, the first wiring member layer (WL18) may include other wiring elements in addition to the first wiring element, and the second wiring member layer (WL28) may include other wiring elements in addition to the second wiring element.

[0089] FIGS. 13a to 13c are cross-sectional views showing a method for forming a rearrangement layer structure according to an embodiment of the present invention.

[0090] Referring to FIG. 13a, a substructure (ST17) including an electrode pad (PD17) may be provided. The substructure (ST17) may be a chip (semiconductor chip) or a substrate for a package. A first insulating layer (NL17) may be formed on the substructure (ST17). The first insulating layer (NL17) may have one or more openings (V17) that expose the electrode pad (PD17). One or more openings (V17) may be opened into the target area within a size range of a given target area. One or more openings (V17) may be an area where an electrical identical element (identical element) to which the same electrical signal is applied is formed. The target area may be a given surface area of ​​the electrode pad (PD17) or a corresponding area. The first insulating layer (NL17) may have an etched portion (U17) for improving the flatness of the rearrangement layer structure in the remaining area excluding one or more openings (V17) in the space corresponding to the target area. The etched portion (U17) may be positioned between two or more of the openings or positioned so that more than half thereof is surrounded by one of the openings.

[0091] Referring to FIG. 13b, a first wiring member layer (WL17) may be formed on a first insulating layer (NL17) such that it at least partially fills one or more openings (V17). The first wiring member layer (WL17) may include the electrical identical elements formed within one or more openings (V17).

[0092] Referring to FIG. 13c, a second insulating layer (NL27) can be formed on the first insulating layer (NL17) to at least partially cover the first wiring member layer (WL17), and a second wiring member layer (WL27) can be formed on the second insulating layer (NL27). The rearrangement layer structure of FIG. 13c can correspond to the rearrangement layer structure described in FIG. 10.

[0093] FIGS. 14a to 14d are cross-sectional views showing a method for forming a rearrangement layer structure according to another embodiment of the present invention.

[0094] Referring to FIG. 14a, a substructure (ST18) including an electrode pad (PD18) may be provided. The substructure (ST18) may be a chip (semiconductor chip) or a substrate for a package. A first insulating layer (NL18) may be formed on the substructure (ST18). The first insulating layer (NL18) may have one or more first openings (V18) that expose the electrode pad (PD18). One or more first openings (V18) may be opened into the first target area within a size range of a given first target area. One or more first openings (V18) may be areas where a first electrical identical element (identical element) to which the same electrical signal is applied is formed. The first target area may be a given surface area of ​​the electrode pad (PD18) or a corresponding area. The first insulating layer (NL18) may have a first unetched portion (U18) for improving the flatness of the rearrangement layer structure in the remaining area excluding one or more first openings (V18) in the space corresponding to the first target area. The first unetched portion (U18) may be positioned between two or more of the first openings or positioned so that more than half thereof is surrounded by one of the first openings.

[0095] Referring to FIG. 14b, a first wiring member layer (WL18) may be formed on a first insulating layer (NL18) such that one or more first openings (V18) are at least partially filled. The first wiring member layer (WL18) may include the first electrical identical elements formed within one or more first openings (V18).

[0096] Referring to FIG. 14c, a second insulating layer (NL28) may be formed on the first insulating layer (NL18) to at least partially cover the first wiring member layer (WL18). The second insulating layer (NL28) may have one or more second openings (V28) that expose the first wiring member layer (WL18). One or more second openings (V28) may be opened into the second target area within a size range of a given second target area. One or more second openings (V28) may be areas where a second electrical identical element (identical body) to which the same electrical signal is applied is formed. The second target area may be a given surface area of ​​the first wiring member layer (WL18). The second insulating layer (NL28) may have a second unetched portion (U28) for improving the flatness of the rearrangement layer structure in the remaining area excluding one or more second openings (V28) in the space corresponding to the second target area. The second unetched portion (U28) may be positioned between two or more of the second openings or positioned so that more than half thereof is surrounded by one of the second openings.

[0097] Referring to FIG. 14d, a second wiring member layer (WL28) may be formed on the second insulating layer (NL28) to at least partially fill one or more second openings (V28). The second wiring member layer (WL28) may include the second electrical identical elements formed within one or more second openings (V28). The rearrangement layer structure of FIG. 14d may correspond to the rearrangement layer structure described in FIG. 12.

[0098] A method for forming a rearrangement layer structure according to an embodiment of the present invention may be applied to a method for manufacturing a semiconductor package device. A method for manufacturing a semiconductor package device according to an embodiment may include a step of forming the rearrangement layer structure using the method described above, in a method for manufacturing a semiconductor package device comprising a chip (die) and a rearrangement layer structure electrically connected to said chip. The method for manufacturing the semiconductor package device may be performed, as a non-limiting example, in a WLP (wafer level package) or PLP (panel level package) manner.

[0099] FIGS. 15a to 15d are cross-sectional views showing a method for manufacturing a semiconductor package device by applying a method for forming a rearrangement layer structure according to one embodiment of the present invention.

[0100] Referring to FIG. 15a, an adhesive layer (AL10) can be provided on a carrier substrate (CS10), and a plurality of chips (C10) can be attached on the adhesive layer (AL10). In other words, a plurality of chips (C10) can be attached on the carrier substrate (CS10) with the adhesive layer (AL10) in between. The carrier substrate (CS10) may be a wafer or a panel. The plurality of chips (C10) may be attached on the carrier substrate (CS10), for example, in a face-down manner. The adhesive layer (AL10) may be an adhesive film.

[0101] Referring to FIG. 15b, a molding layer (ML10) covering a plurality of chips (C10) can be formed on a carrier substrate (CS10). The molding layer (ML10) may include a polymer material. For example, the molding layer (ML10) may include a molding compound.

[0102] Referring to FIG. 15c, the carrier substrate (CS10 in FIG. 15b) can be removed from a plurality of chips (C10) and a molding layer (ML10). At this time, the adhesive layer (AL10 in FIG. 15b) can also be removed together.

[0103] Referring to FIG. 15d, a rearrangement layer structure (RS10) can be formed on a plurality of chips (C10) and a molding layer (ML10). The rearrangement layer structure (RS10) may include a configuration according to an embodiment of the present invention. The rearrangement layer structure (RS10) may be formed to contact the active surface portion of the plurality of chips (C10). Additionally, a plurality of electrical connection elements (CE10) may be further formed on the rearrangement layer structure (RS10). The plurality of electrical connection elements (CE10) may include, for example, solder balls or bumps, but are not limited to specific examples. The plurality of chips (C10), the molding layer (ML10), the rearrangement layer structure (RS10), and the plurality of electrical connection elements (CE10) may be said to constitute a package structure.

[0104] Next, although not illustrated, the above package structure can be divided (cut) into package element units. This can be performed according to a general cutting method. Through this, individualized semiconductor package elements can be obtained.

[0105] FIGS. 16a to 16e are cross-sectional views showing a method for manufacturing a semiconductor package device by applying a method for forming a rearrangement layer structure according to another embodiment of the present invention.

[0106] Referring to FIG. 16a, an adhesive layer (AL11) can be provided on a carrier substrate (CS11), and a rearrangement layer structure (RS11) can be formed on the adhesive layer (AL11). The rearrangement layer structure (RS11) may include a configuration according to an embodiment of the present invention. The carrier substrate (CS11) may be a wafer or a panel.

[0107] Referring to FIG. 16b, a plurality of chips (C11) can be attached to a rearrangement layer structure (RS11). The plurality of chips (C11) can be attached to the rearrangement layer structure (RS11) in a face-down manner, for example.

[0108] Referring to FIG. 16c, a molding layer (ML11) covering a plurality of chips (C11) can be formed on a rearrangement layer structure (RS11). The molding layer (ML11) may include a polymer material.

[0109] Referring to FIG. 16d, the carrier substrate (CS11 in FIG. 16c) can be removed from a plurality of chips (C11) and a molding layer (ML11). At this time, the adhesive layer (AL11 in FIG. 16c) can also be removed. The adhesive layer (AL11 in FIG. 16c) can also serve as an adhesive release layer.

[0110] Referring to FIG. 16e, a plurality of electrical connection elements (CE11) can be formed on a rearrangement layer structure (RS11). The plurality of electrical connection elements (CE11) may include, for example, solder balls or bumps, without limitation. A plurality of chips (C11), a molding layer (ML11), a rearrangement layer structure (RS11), and a plurality of electrical connection elements (CE11) can be said to constitute a package structure. Although not illustrated, the package structure can be divided (cut) into package element units. Through this, individualized semiconductor package elements can be obtained.

[0111] The method for forming a rearrangement layer structure according to embodiments of the present invention can be applied to semiconductor packages of the WLP (wafer level package) or PLP (panel level package) type. Furthermore, the method for forming the rearrangement layer structure can be applied not only to fan-out type semiconductor packages but also to fan-in type semiconductor packages. The method for forming the rearrangement layer structure can be applied to chip-first (i.e., die-first) and chip-last (i.e., die-last) type semiconductor packages. The method for forming the rearrangement layer structure can be applied to face-down and face-up type semiconductor packages. In addition, the method for forming the rearrangement layer structure can be applied to forming a rearrangement layer on a package substrate having a plurality of electrode pads, and in this case, a semiconductor package process can be performed on the package substrate on which the rearrangement layer is formed.

[0112] A semiconductor package device according to an embodiment of the present invention may include a chip (semiconductor chip) and a rearrangement layer structure electrically connected to the chip, and the rearrangement layer structure may include the features of the rearrangement layer structure according to the embodiment described with reference to FIGS. 1a to 2b, FIGS. 4 to 8, FIGS. 10, and FIG. 12.

[0113] Additionally, the rearrangement layer structure and the method for forming the same according to the embodiments of the present invention may be applicable to the manufacture of electronic devices other than semiconductor packages. The embodiments of the present invention may be applicable to all electronic devices / semiconductor devices to which the rearrangement layer structure is applied.

[0114] Figure 17 is a cross-sectional photographic image showing a part of a semiconductor package device manufactured according to a comparative example.

[0115] Referring to FIG. 17, solder balls may be formed on a rearrangement layer structure according to a comparative example. The rearrangement layer structure may have large curvature and height differences (steps) on its surface due to the influence of relatively large via holes. This may cause sinking problems of the solder balls and sagging problems of the pattern portion. This may have a negative impact on the reliability and performance of the semiconductor package device.

[0116] FIG. 18 is a cross-sectional photographic image showing a part of a semiconductor package device manufactured according to an embodiment of the present invention.

[0117] Referring to FIG. 18, solder balls may be formed on a rearrangement layer structure according to an embodiment. The rearrangement layer structure may be configured to include, for example, a plurality of small via arrays or vias having at least a partial ring (donut) structure. In this case, the topology and flatness of the rearrangement layer structure may be improved. The sinking problem of the solder balls may also be reduced. Accordingly, the reliability and performance of the semiconductor package device may be improved.

[0118] FIG. 19 is a photographic image showing a portion of the surface of a semiconductor package device manufactured according to an embodiment of the present invention.

[0119] Referring to FIG. 19, the area labeled A1 may include the configuration of the rearrangement layer described in FIG. 12. For example, the area labeled A1 may include a configuration similar to the second insulating layer (NL28) and the second wiring member layer (WL28) described in FIG. 12. Thus, the area labeled A1 may have improved surface flatness.

[0120] According to the embodiments of the present invention described above, a rearrangement layer (RDL) structure capable of improving reliability by improving topology and flatness, and a device including the same (e.g., a semiconductor package device) can be realized. By using the rearrangement layer (RDL) structure according to the embodiments, excellent electrical connectivity between components can be secured while preventing problems such as bending or sagging (sagging of the pattern portion) caused by large-sized via holes (openings), thereby reducing the defect rate of the device and improving reliability. For example, the rearrangement layer (RDL) structure and the method of forming the same according to the embodiments of the present invention can be usefully applied to advanced packaging processes such as fan-in processes, fan-out processes, and integrated packaging processes that package multiple chips together. In addition, the rearrangement layer (RDL) structure and the method of forming the same according to the embodiments of the present invention can be applied to chip-first (i.e., die-first) processes and chip-last (i.e., die-last) processes. In addition, the rearrangement layer (RDL) structure and the method for forming the same according to the embodiments of the present invention can be applied to a substrate for a package. Furthermore, the rearrangement layer (RDL) structure and the method for forming the same according to the embodiments of the present invention can be applied to the manufacture of various electronic devices / semiconductor devices.

[0121] This specification discloses preferred embodiments of the present invention. Although specific terms have been used, they are used merely in a general sense to facilitate the explanation of the technical content of the invention and to aid in understanding the invention, and are not intended to limit the scope of the invention. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, other variations based on the technical concept of the present invention are possible. Those skilled in the art will understand that the rearrangement layer structure, the method for forming the rearrangement layer structure, the semiconductor package device including the rearrangement layer structure, and the method for manufacturing the semiconductor package device including the rearrangement layer structure, according to the embodiments described with reference to FIGS. 1a to 2b, FIGS. 4 to 8, FIGS. 10, FIG. 12, FIGS. 13a to 16e, FIGS. 18, and FIGS. 19, may be substituted, changed, and modified in various ways within the scope of the technical concept of the present invention. Therefore, the scope of the invention should not be determined by the described embodiments but by the technical concept described in the claims. Explanation of the symbols

[0122] * Explanation of symbols for major parts of the drawing * AL10, AL11: Adhesive layer C10, C11: Chip CE10, CE11: Electrical connection elements CS10, CS11: Carrier substrates ML10, ML11: Molding layer NL10, NL11, NL17, NL18: First insulating layer NL20, NL21, NL27, NL28: Second insulating layer PD10, PD11, PD17, PD18: Electrode pads R10: Target area RS10, RS11: Rearrangement layer structure ST17, ST18: Substructure U10~U18: Unetched parts U28 : 2nd Unidentified Section V10~V18 : Opening V28 : Second opening WL10, WL11, WL17, WL18: First wiring member layer WL20, WL21, WL27, WL28: Second wiring member layer

Claims

Claim 1 A chip; and a rearrangement layer structure electrically connected to the chip; wherein the rearrangement layer structure comprises: one or more openings that open to a target area within a given target area size range, wherein the one or more openings are areas where electrical identical elements are formed to which the same electrical signal is applied, and wherein an unetched portion for improving the flatness of the rearrangement layer structure is provided in the remaining area excluding the one or more openings in a space corresponding to the target area, and wherein the unetched portion is disposed between two or more of the openings or wherein more than half thereof is surrounded by one of the openings; a first insulating layer disposed on the first insulating layer to at least partially fill the one or more openings and comprising the electrical identical elements formed within the one or more openings; and wherein the rearrangement layer structure comprises: a second insulating layer disposed on the first insulating layer to at least partially cover the first wiring member layer; and a second wiring member layer disposed on the second insulating layer.The invention further comprises, wherein the target area is a first target area, the one or more openings are a first opening, the unetched portion is a first unetched portion, the electrical identical element is a first electrical identical element, the second insulating layer has one or more second openings that open into the second target area within a size range of the given second target area of ​​the first wiring member layer, the one or more second openings are areas where a second electrical identical element is formed to which the same electrical signal is applied, the second insulating layer has a second unetched portion for improving the flatness of the rearrangement layer structure in the remaining area excluding the one or more second openings in the space corresponding to the second target area, the second unetched portion is disposed between two or more of the second openings or is disposed such that more than half thereof is surrounded by one of the second openings, the second wiring member layer is disposed on the second insulating layer to at least partially fill the one or more second openings, and the second electrical element formed within the one or more second openings A semiconductor package device containing identical elements.; Claim 2 In claim 1, the first insulating layer comprises a plurality of openings formed spaced apart from each other on the target area, and the unetched portion is provided between the plurality of openings. Claim 3 A semiconductor package device according to claim 1, wherein the first insulating layer comprises the opening having a ring structure or a partial ring structure on the target area, and the unetched portion is provided to be surrounded by the ring structure or the partial ring structure. Claim 4 A semiconductor package device according to claim 1, wherein at least a portion of the unetched portion is located in a region corresponding to the central portion of the target region. Claim 5 In claim 1, the semiconductor package device having one or more openings having a diameter or line width in the range of 1 to 10 μm. Claim 6 A semiconductor package device according to claim 1, wherein the target area is a given surface area of ​​one electrode pad or a corresponding area. Claim 7 delete Claim 8 delete Claim 9 In claim 1, the second insulating layer comprises a plurality of second openings formed spaced apart from each other on the second target area, and the second unetched portion is provided between the plurality of second openings. Claim 10 A semiconductor package device according to claim 1, wherein the second insulating layer comprises the second opening having a ring structure or a partial ring structure on the second target region, and the second unetched portion is provided to be surrounded by the ring structure or the partial ring structure. Claim 11 A method for forming a rearrangement layer structure comprises: forming a first insulating layer having one or more openings that open to a given target area within a size range of the target area, wherein the one or more openings are areas where electrical identical elements are formed to which the same electrical signal is applied, and having an unetched portion for improving the flatness of the rearrangement layer structure in the remaining area excluding the one or more openings in a space corresponding to the target area, wherein the unetched portion is disposed between two or more of the openings or is disposed such that more than half thereof is surrounded by one of the openings; and forming a first wiring member layer disposed on the first insulating layer to at least partially fill the one or more openings and including the electrical identical elements formed within the one or more openings; and forming a second insulating layer on the first insulating layer that at least partially covers the first wiring member layer; and forming a second wiring member layer on the second insulating layer.The invention further comprises, wherein the target area is a first target area, the one or more openings are a first opening, the unetched portion is a first unetched portion, the electrical identical element is a first electrical identical element, the second insulating layer has one or more second openings that open to the second target area within a size range of the given second target area of ​​the first wiring member layer, the one or more second openings are areas where a second electrical identical element is formed to which the same electrical signal is applied, the second insulating layer has a second unetched portion for improving the flatness of the rearrangement layer structure in the remaining area excluding the one or more second openings in the space corresponding to the second target area, the second unetched portion is disposed between two or more of the second openings or is disposed such that more than half thereof is surrounded by one of the second openings, the second wiring member layer is disposed to at least partially fill the one or more second openings on the second insulating layer, and the second electrical element formed within the one or more second openings A method for forming a rearrangement layer structure including identical elements.; Claim 12 A method for forming a rearrangement layer structure according to claim 11, wherein the first insulating layer comprises a plurality of openings formed spaced apart from each other on the target area, and the unetched portion is provided between the plurality of openings. Claim 13 A method for forming a rearrangement layer structure according to claim 11, wherein the first insulating layer comprises the opening having a ring structure or a partial ring structure on the target area, and the unetched portion is provided to be surrounded by the ring structure or the partial ring structure. Claim 14 A method for forming a rearrangement layer structure according to claim 11, wherein the target area is a given surface area of ​​one electrode pad or a corresponding area. Claim 15 delete Claim 16 delete Claim 17 A method for forming a rearrangement layer structure according to claim 11, wherein the second insulating layer comprises a plurality of second openings formed spaced apart from each other on the second target area, and the second unetched portion is provided between the plurality of second openings. Claim 18 A method for forming a rearrangement layer structure according to claim 11, wherein the second insulating layer comprises the second opening having a ring structure or a partial ring structure on the second target area, and the second unetched portion is provided to be surrounded by the ring structure or the partial ring structure. Claim 19 A method for manufacturing a semiconductor package device comprising a chip and a rearrangement layer structure electrically connected to the chip, comprising the step of forming the rearrangement layer structure using a method described in any one of claims 11 to 14, 17 and 18. Claim 20 In claim 19, the method for manufacturing the semiconductor package device is a method for manufacturing the semiconductor package device performed in a WLP (wafer level package) or PLP (panel level package) manner.

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