Decoding device and operating method of the decoding device for determining whether to decode data unit

Abstract

The decoding device can determine a candidate data unit among a plurality of data units in parallel with the operation of decoding a target data unit among a plurality of data units included in a single data chunk. The decoding device can then determine whether to decode the candidate data unit, and after executing decoding for the target data unit, decode the candidate data unit based on the decision to decode the candidate data unit.

Description

Technology Field

[0001] Embodiments of the present invention relate to a decoding device for determining whether to decode a data unit and a method of operating the decoding device. Background Technology

[0002] A storage device is a device that stores data based on requests from external devices, such as computers, mobile terminals like smartphones and tablets, or various electronic devices.

[0003] The storage device may further include a controller for controlling memory (e.g., volatile memory / non-volatile memory), and such a controller may receive a command from an external device and, based on the received command, execute or control operations to read, write, or erase data in the memory included in the storage device.

[0004] Meanwhile, a decoding operation on the data may be performed while the storage device is reading or writing data. The decoding operation may be executed directly by the storage device or by a separate decoding device. The problem to be solved

[0005] Embodiments of the present invention can provide a decoding device and a method of operating the decoding device that can reduce the time and power required for decoding unnecessary data units. means of solving the problem

[0006] In one aspect, embodiments of the present invention may provide a decoding device comprising i) a decoder that performs decoding for one or more of a plurality of data units included in one data chunk, and ii) a preliminary processing device that determines a candidate data unit among the plurality of data units and determines whether to decode the candidate data unit using the decoder.

[0007] In another aspect, embodiments of the present invention may provide a method of operation of a decoding device comprising: i) a step of determining a candidate data unit among a plurality of data units in parallel with an operation of decoding a target data unit among a plurality of data units included in one data chunk; ii) a step of determining whether to decode the candidate data unit; and iii) a step of decoding the candidate data unit or skipping decoding the candidate data unit depending on whether to decode the candidate data unit after performing decoding for the target data unit. Effects of the invention

[0008] According to embodiments of the present invention, the time and power required for decoding unnecessary data units can be reduced. Brief explanation of the drawing

[0009] FIG. 1 is a schematic diagram of a storage device according to embodiments of the present invention. Figure 2 is a block diagram schematically showing the memory of Figure 1. FIG. 3 is a diagram showing the schematic structure of a decoding device according to embodiments of the present invention. FIG. 4 is a diagram showing an example of the structure of a data unit according to embodiments of the present invention. FIG. 5 is a diagram showing the schematic operation of a decoder according to embodiments of the present invention. FIG. 6 is a diagram showing an example of a bit-flip check formula according to embodiments of the present invention. FIG. 7 is a diagram showing the schematic operation of a preprocessing device according to embodiments of the present invention. FIG. 8 is a diagram showing an example of the difference between a bit-flip check formula and a preprocessing check formula according to embodiments of the present invention. FIG. 9 is a diagram showing another example of the difference between a bit-flip check formula and a preprocessing check formula according to embodiments of the present invention. FIG. 10 is a flowchart illustrating an example of an operation in which a decoding device according to embodiments of the present invention determines whether to decode a candidate data unit. FIG. 11 is a diagram showing the operation method of a decoding device according to embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0011] FIG. 1 is a schematic diagram of a storage device (100) according to embodiments of the present invention.

[0012] Referring to FIG. 1, a storage device (100) according to embodiments of the present invention may include a memory (110) for storing data and a controller (120) for controlling the memory (110).

[0013] The memory (110) includes a plurality of memory blocks and operates in response to the control of the controller (120). Here, the operation of the memory (110) may include, for example, a read operation, a program operation (also called a "write operation"), and an erase operation.

[0014] The memory (110) may include a memory cell array comprising a plurality of memory cells (also simply called "cells") that store data. Such a memory cell array may exist within a memory block.

[0015] For example, memory (110) can be implemented in various types such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND Flash Memory, 3D NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase-Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin Transfer Torque Random Access Memory (STT-RAM).

[0016] Meanwhile, the memory (110) can be implemented as a three-dimensional array structure. Embodiments of the present invention can be applied to flash memory in which the charge storage layer is composed of a conductive floating gate, as well as to charge trap flash (CTF) in which the charge storage layer is composed of an insulating film.

[0017] The memory (110) receives commands and addresses, etc. from the controller (120) and can access an area selected by the address among the memory cell array. That is, the memory (110) can perform an operation instructed by the command on the area selected by the address.

[0018] For example, the memory (110) can perform program operations, read operations, and erase operations. In this regard, when performing a program operation, the memory (110) can program data in an area selected by an address. When performing a read operation, the memory (110) can read data from an area selected by an address. When performing an erase operation, the memory (110) can erase data stored in an area selected by an address.

[0019] The controller (120) can control write (program), read, erase, and background operations for memory (110). Here, background operations may include one or more of, for example, garbage collection (GC), wear leveling (WL), read reclaim (RR), or bad block management (BBM) operations.

[0020] The controller (120) can control the operation of the memory (110) in response to a request from a device (e.g., a host) located outside the storage device (100). On the other hand, the controller (120) can also control the operation of the memory (110) independently of the request from the host.

[0021] A HOST is a computer, UMPC (Ultra Mobile PC), workstation, PDA (Personal Digital Assistants), tablet, mobile phone, smartphone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, smart television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, storage constituting a data center, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, RFID (radio frequency identification) device, and a mobile device capable of driving under human control or autonomous driving (e.g. It can be vehicles, robots, drones, etc.

[0022] The host may include at least one operating system (OS). The operating system can manage and control the overall functions and operations of the host and provide interaction between the host and the storage device (100). The operating system can be classified into a general operating system and a mobile operating system depending on the mobility of the host.

[0023] Meanwhile, the controller (120) and the host (HOST) may be separate devices. In some cases, the controller (120) and the host (HOST) may be implemented as a single integrated device. For convenience of explanation, the following description uses an example where the controller (120) and the host (HOST) are separate devices.

[0024] Referring to FIG. 1, the controller (120) may include a memory interface (122) and a control circuit (123), and may further include a host interface (121), etc.

[0025] The host interface (121) provides an interface for communication with a host. For example, the host interface (121) provides an interface that uses at least one of various interface protocols, such as USB (Universal Serial Bus) protocol, MMC (multimedia card) protocol, PCI (peripheral component interconnection) protocol, PCI-E (PCI-express) protocol, ATA (Advanced Technology Attachment) protocol, Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, SMBus (System Management Bus) protocol, I2C (Inter-Integrated Circuit) protocol, I3C (Improved Inter-Integrated Circuit) protocol, and IDE (Integrated Drive Electronics) protocol, private protocol, etc.

[0026] When the control circuit (123) receives a command from the host (HOST), it can receive the command through the host interface (121) and perform an operation to process the received command.

[0027] The memory interface (122) can be connected to the memory (110) and provide an interface for communication with the memory (110). That is, the memory interface (122) can be configured to provide an interface between the memory (110) and the controller (120) in response to the control of the control circuit (123).

[0028] The control circuit (123) controls the operation of the memory (110) by performing overall control operations of the controller (120). To this end, for example, the control circuit (123) may include one or more of a processor (124), a working memory (125), etc., and may optionally include an error detection and correction circuit (ECC Circuit, 126), etc.

[0029] The processor (124) can control the general operations of the controller (120) and perform logical operations. The processor (124) can communicate with the host (HOST) through the host interface (121) and with the memory (110) through the memory interface (122).

[0030] The processor (124) can perform the function of a Flash Translation Layer (FTL). The processor (124) can convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the Flash Translation Layer (FTL). The Flash Translation Layer (FTL) can receive a logical block address (LBA) as input using a mapping table and convert it into a physical block address (PBA).

[0031] There are various address mapping methods in the Flash Translation Layer depending on the mapping unit. Representative address mapping methods include the Page mapping method, the Block mapping method, and the Hybrid mapping method.

[0032] The processor (124) can render data received from the host (HOST). For example, the processor (124) can render data received from the host (HOST) using a set rendering seed. The rendered data is provided to memory (110) and can be programmed into a memory cell array of memory (110).

[0033] The processor (124) can deranderize data received from memory (110) during a read operation. For example, the processor (124) can deranderize data received from memory (110) using a deranderizing seed. The deranderized data can be output to a host (HOST).

[0034] The processor (124) can control the operation of the controller (120) by executing firmware. In other words, the processor (124) can execute (drive) the firmware loaded into the working memory (125) at boot time to control the general operation of the controller (120) and perform logical operations. The operation of the storage device (100) described below in the embodiments of the present invention can be implemented in such a way that the processor (124) executes the firmware in which the operation is defined.

[0035] Firmware is a program executed within a storage device (100) to operate the storage device (100), and may include various functional layers. For example, the firmware may include binary data in which code for executing each of the aforementioned functional layers is defined.

[0036] For example, the firmware may include one or more of the following: a Flash Translation Layer (FTL) that performs a conversion function between a logical address requested by a host (HOST) to a storage device (100) and a physical address of memory (110); a Host Interface Layer (HIL) that interprets a command requested by a host (HOST) to a storage device (100) and transmits it to the Flash Translation Layer (FTL); and a Flash Interface Layer (FIL) that transmits a command directed by the Flash Translation Layer (FTL) to memory (110).

[0037] This firmware may be loaded into working memory (125) from, for example, memory (110) or a separate non-volatile memory (e.g., ROM, NOR Flash) located outside of memory (110). When the processor (124) executes a boot operation after power-on, it may first load all or part of the firmware into working memory (125).

[0038] The processor (124) can perform logical operations defined in the firmware loaded in the working memory (125) to control the overall operation of the controller (120). The processor (124) can store the result of performing the logical operations defined in the firmware in the working memory (125). The processor (124) can control the controller (120) to generate a command or signal according to the result of performing the logical operations defined in the firmware. If the part of the firmware where the logical operations to be performed are defined is stored in the memory (110) but is not loaded in the working memory (125), the processor (124) can generate an event (e.g., an interrupt) to load the corresponding part of the firmware from the memory (110) to the working memory (125).

[0039] Meanwhile, the processor (124) can load metadata required to run the firmware from the memory (110). The metadata is data for managing the memory (110) and may include management information for user data stored in the memory (110).

[0040] Meanwhile, the firmware may be updated while the storage device (100) is being produced or while the storage device (100) is running. The controller (120) may download new firmware from outside the storage device (100) and update the existing firmware to the new firmware.

[0041] The working memory (125) can store firmware, program code, commands, or data required to drive the controller (120). This working memory (125) may include, for example, one or more of volatile memory such as SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM).

[0042] The error detection and correction circuit (126) can detect an error bit of the target data using an error correction code and correct the detected error bit. Here, the target data may be, for example, data stored in the working memory (125) or data read from the memory (110).

[0043] The error detection and correction circuit (126) can be implemented to decode data into an error correction code. The error detection and correction circuit (126) can be implemented with various code decoders. For example, a decoder that performs unsystematic code decoding or a decoder that performs systematic code decoding may be used.

[0044] For example, the error detection and correction circuit (126) can detect error bits in sector units set for each of the read data. That is, each read data can be composed of multiple sectors. A sector can refer to a data unit smaller than a page, which is the read unit of the flash memory. The sectors constituting each read data can correspond to each other via an address.

[0045] The error detection and correction circuit (126) can calculate the bit error rate (BER) and determine whether correction is possible on a sector basis. For example, the error detection and correction circuit (126) can determine that a sector is uncorrectable (or fail) if the bit error rate (BER) is higher than a set reference value. On the other hand, if the bit error rate (BER) is lower than the reference value, the sector can be determined to be correctable (or pass).

[0046] The error detection and correction circuit (126) can sequentially perform error detection and correction operations for all read data. If a sector included in the read data is correctable, the error detection and correction circuit (126) may omit the error detection and correction operation for that sector for the next read data. When the error detection and correction operation for all read data is completed, the error detection and correction circuit (126) can detect the sector determined to be uncorrectable until the very end. There may be one or more sectors determined to be uncorrectable. The error detection and correction circuit (126) can transmit information (e.g., address information) about the sector determined to be uncorrectable to the processor (124).

[0047] The bus (127) may be configured to provide a channel between the components (121, 122, 124, 125, 126) of the controller (120). This bus (127) may include, for example, a control bus for transmitting various control signals, commands, etc., and a data bus for transmitting various data.

[0048] Meanwhile, some of the aforementioned components (121, 122, 124, 125, 126) of the controller (120) may be deleted, or some of the aforementioned components (121, 122, 124, 125, 126) of the controller (120) may be integrated into one. In some cases, one or more other components may be added in addition to the aforementioned components of the controller (120).

[0049] Below, the memory (110) will be described in more detail with reference to FIG. 2.

[0050] FIG. 2 is a block diagram schematically showing the memory (110) of FIG. 1.

[0051] Referring to FIG. 2, a memory (110) according to embodiments of the present invention may include a memory cell array (210), an address decoder (220), a read and write circuit (230), control logic (240), and a voltage generation circuit (250), etc.

[0052] The memory cell array (210) may include a plurality of memory blocks (BLK1 to BLKz, where z is a natural number greater than or equal to 2).

[0053] In a plurality of memory blocks (BLK1~BLKz), a plurality of word lines (WL) and a plurality of bit lines (BL) are arranged, and a plurality of memory cells (MC) can be arranged.

[0054] Multiple memory blocks (BLK1 to BLKz) can be connected to an address decoder (220) via multiple word lines (WL). Multiple memory blocks (BLK1 to BLKz) can be connected to a read and write circuit (230) via multiple bit lines (BL).

[0055] Each of the multiple memory blocks (BLK1~BLKz) may include multiple memory cells. For example, the multiple memory cells may be non-volatile memory cells and may be composed of non-volatile memory cells having a vertical channel structure.

[0056] The memory cell array (210) may be configured as a memory cell array with a two-dimensional structure, and in some cases, may be configured as a memory cell array with a three-dimensional structure.

[0057] Meanwhile, each of the plurality of memory cells included in the memory cell array (210) can store at least 1 bit of data. For example, each of the plurality of memory cells included in the memory cell array (210) may be a Single-Level Cell (SLC) that stores 1 bit of data. For another example, each of the plurality of memory cells included in the memory cell array (210) may be a Multi-Level Cell (MLC) that stores 2 bits of data. For yet another example, each of the plurality of memory cells included in the memory cell array (210) may be a Triple-Level Cell (TLC) that stores 3 bits of data. For yet another example, each of the plurality of memory cells included in the memory cell array (210) may be a Quad-Level Cell (QLC) that stores 4 bits of data. For yet another example, the memory cell array (210) may include a plurality of memory cells that each store 5 bits or more of data.

[0058] At this time, the number of bits of data stored in each of the multiple memory cells can be dynamically determined. For example, a single-level cell storing 1 bit of data can be changed to a triple-level cell storing 3 bits of data.

[0059] Referring to FIG. 2, an address decoder (220), a read and write circuit (230), a control logic (240), and a voltage generation circuit (250), etc., can operate as peripheral circuits that drive the memory cell array (210).

[0060] The address decoder (220) can be connected to the memory cell array (210) through a plurality of word lines (WL).

[0061] The address decoder (220) can be configured to operate in response to the control of the control logic (240).

[0062] The address decoder (220) can receive an address through an input / output buffer inside the memory (110). The address decoder (220) can be configured to decode a block address among the received addresses. The address decoder (220) can select at least one memory block according to the decoded block address.

[0063] The address decoder (220) can receive a read voltage (Vread) and a pass voltage (Vpass) from the voltage generation circuit (250).

[0064] The address decoder (220) can apply a read voltage (Vread) to a selected word line (WL) within a selected memory block and apply a pass voltage (Vpass) to the remaining unselected word lines (WL) during a read operation.

[0065] When the address decoder (220) performs a program verification operation, it can apply a verification voltage generated by the voltage generation circuit (250) to a selected word line (WL) within a selected memory block and apply a pass voltage (Vpass) to the remaining unselected word lines (WL).

[0066] The address decoder (220) may be configured to decode column addresses among the received addresses. The address decoder (220) may transmit the decoded column addresses to the read and write circuit (230).

[0067] The read operation and program operation of the memory (110) can be performed in page units. The address received when requesting the read operation and program operation may include one or more of a block address, a row address, and a column address.

[0068] The address decoder (220) can select one memory block and one word line according to the block address and row address. The column address can be decoded by the address decoder (220) and provided to the read and write circuit (230).

[0069] The address decoder (220) may include one or more of a block decoder, a row decoder, a column decoder, and an address buffer.

[0070] The read and write circuit (230) may include a plurality of page buffers (PB). The read and write circuit (230) may operate as a "read circuit" during a read operation of the memory cell array (210) and as a "write circuit" during a write operation.

[0071] The aforementioned read and write circuit (230) is also referred to as a page buffer circuit or data register circuit that includes a plurality of page buffers (PB). Here, the read and write circuit (230) may include a data buffer responsible for data processing functions, and, in some cases, may additionally include a cache buffer responsible for caching functions.

[0072] A plurality of page buffers (PB) can be connected to a memory cell array (210) through a plurality of bit lines (BL). During read operations and program verification operations, the plurality of page buffers (PB) can continuously supply a sensing current to the bit lines (BL) connected to the memory cells to sense the threshold voltage (Vth) of the memory cells, and can detect through a sensing node that the amount of current flowing changes according to the program state of the corresponding memory cell and latch it as sensing data.

[0073] The read and write circuit (230) can operate in response to page buffer control signals output from the control logic (240).

[0074] The read and write circuit (230) senses the data of the memory cell during a read operation, temporarily stores the read data, and then outputs the data (DATA) to the input / output buffer of the memory (110). As an exemplary embodiment, the read and write circuit (230) may include a column selection circuit, etc., in addition to page buffers (PB) or page registers.

[0075] The control logic (240) can be connected to an address decoder (220), a read and write circuit (230), and a voltage generation circuit (250), etc. The control logic (240) can receive a command (CMD) and a control signal (CTRL) through the input / output buffer of the memory (110).

[0076] The control logic (240) may be configured to control the general operation of the memory (110) in response to a control signal (CTRL). The control logic (240) may output a control signal to adjust the precharge potential level of the sensing nodes of a plurality of page buffers (PB).

[0077] The control logic (240) can control the read and write circuit (230) to perform a read operation of the memory cell array (210). The voltage generation circuit (250) can generate a read voltage (Vread) and a pass voltage (Vpass) used during a read operation in response to a voltage generation circuit control signal output from the control logic (240).

[0078] Meanwhile, each memory block of the aforementioned memory (110) may be composed of multiple pages corresponding to multiple word lines (WL) and multiple strings corresponding to multiple bit lines (BL).

[0079] In a memory block (BLK), multiple word lines (WL) and multiple bit lines (BL) may be arranged in an alternating manner. For example, each of the multiple word lines (WL) may be arranged in a row direction, and each of the multiple bit lines (BL) may be arranged in a column direction. As another example, each of the multiple word lines (WL) may be arranged in a column direction, and each of the multiple bit lines (BL) may be arranged in a row direction.

[0080] A memory cell connected to one of a number of word lines (WL) and one of a number of bit lines (BL) can be defined. A transistor can be placed in each memory cell.

[0081] For example, a transistor placed in a memory cell (MC) may include a drain, a source, and a gate, etc. The drain (or source) of the transistor may be connected directly to the corresponding bit line (BL) or via another transistor. The source (or drain) of the transistor may be connected directly to a source line (which may be ground) or via another transistor. The gate of the transistor may include a floating gate surrounded by an insulator and a control gate to which a gate voltage is applied from a word line (WL).

[0082] In each memory block, a first selection line (also called a source selection line or drain selection line) may be further disposed outside the first outermost word line that is more adjacent to the read and write circuit (230) among the two outermost word lines, and a second selection line (also called a drain selection line or source selection line) may be further disposed outside the other second outermost word line.

[0083] In some cases, one or more dummy word lines may be placed between the first outermost word line and the first selection line. Additionally, one or more dummy word lines may be placed between the second outermost word line and the second selection line.

[0084] The read operation and program operation (write operation) of the aforementioned memory block can be performed on a page basis, and the erase operation can be performed on a memory block basis.

[0085] FIG. 3 is a diagram showing the schematic structure of a decoding device (300) according to embodiments of the present invention.

[0086] Referring to FIG. 3, the decoding device (300) may include a decoder (310) and a preprocessing device (320).

[0087] The decoder (310) can perform decoding for one or more of the plurality of data units (DU). The decoder (310) may decode one data unit per cycle, or may decode one or more data units in parallel.

[0088] Each of the multiple data units (DU) can indicate information about data of a specific number of bits (e.g., 128 bits). The multiple data units (DU) can be included in a single data chunk (DC). The data chunk (DC) may be referred to as a codeword, code unit, etc.

[0089] When the decoder (310) performs decoding for the data unit (DU), the decoder (310) can search for a bit that has an error among the bits of the data indicated by the data unit (DU) and perform a bit-flip on the bit that has an error.

[0090] Meanwhile, the decoder (310) may perform bit-flips on the bits of data indicated by the data unit (DU) that have errors, and then repeatedly perform decoding on the data unit (DU) when the number of bit-flips in the data unit (DU) is greater than or equal to the set threshold number of bit-flips.

[0091] The preliminary processing unit (320) can determine a candidate data unit (DU_CAND) among a plurality of data units (DU). The preliminary processing unit (320) can also determine whether to decode the candidate data unit (DU_CAND) using a decoder (310).

[0092] That is, the preprocessing unit (320) can determine whether to decode the candidate data unit (DU_CAND) or skip the operation of the decoder (310) decoding the candidate data unit (DU_CAND) after the decoder (310) has completed decoding the data unit currently being decoded.

[0093] When the preprocessing unit (320) decides to decode the candidate data unit (DU_CAND) using the decoder (310), the decoder (310) can receive the candidate data unit (DU_CAND) as input and perform decoding for the candidate data unit (DU_CAND).

[0094] On the other hand, if the preprocessing unit (320) decides to skip the operation of the decoder (310) decoding the candidate data unit (DU_CAND), the decoder (310) does not execute the operation of decoding the candidate data unit (DU_CAND).

[0095] In embodiments of the present invention, the reason why the decoding device (300) determines whether to decode a candidate data unit (DU_CAND) using the preprocessing device (320) is as follows.

[0096] Among the multiple data units (DU) to be processed by the decoding device (300), there may be data units that are unlikely to cause errors. In this case, if the decoder (310) performs decoding even for data units that are unlikely to cause errors, the decoder (310) may consume time and power by performing unnecessary decoding.

[0097] Accordingly, the preliminary processing unit (320) can determine in advance whether it is necessary to decode a candidate data unit (DU_CAND) among a plurality of data units (DU) using the decoder (310). At this time, the time and power required when the preliminary processing unit (320) determines whether to decode the candidate data unit (DU_CAND) is less than the time and power required when the decoder (310) performs decoding on the candidate data unit (DU_CAND).

[0098] The preprocessing unit (320) can control the decoder (310) to decode the candidate data unit (DU_CAND) when it is necessary to decode the candidate data unit (DU_CAND), and control the decoder (310) to skip the operation of decoding the candidate data unit (DU_CAND) when it is not necessary to decode the candidate data unit (DU_CAND).

[0099] Since the decoder (310) does not perform decoding for candidate data units (DU_CAND) that do not require decoding, the time and power consumed by the decoder (310) in performing decoding can be reduced.

[0100] At this time, the decoder (310) and the preprocessing unit (320) can operate in parallel. That is, while the decoder (310) is performing decoding for one of the multiple data units (DU), the preprocessing unit (320) can determine whether decoding is required for one of the remaining data units among the multiple data units (DU), excluding the data unit that the decoder (310) is currently decoding.

[0101] Meanwhile, the decoding device (300) can be implemented in various ways. For example, the decoding device (300) may be the controller (120) of the storage device (100) described in FIG. 1. In this case, the decoder (310) and the preprocessing device (320) may be the processor (124) or the error detection and correction circuit (126) of FIG. 1. And the data chunk (DC) and the plurality of data units (DU) included in the data chunk (DC) may be stored in the memory (110) of the storage device (100).

[0102] As another example, the decoding device (300) may be a separate computing device distinct from the storage device (100) described in FIG. 1.

[0103] Hereinafter, the structure of the data unit (DU) in which the decoder (310) performs decoding is explained through FIG. 4.

[0104] FIG. 4 is a diagram showing an example of the structure of a data unit (DU) according to embodiments of the present invention.

[0105] Referring to FIG. 4, the data unit (DU) may include a plurality of nodes (NODE). In this case, each of the plurality of nodes (NODE) ​​may include a data bit (NODE_BIT) and state information (NODE_STATE).

[0106] The data bit (NODE_BIT) of a node may be the bit value of the data indicated by the node. The state information (NODE_STATE) of a node may be a value indicating the state of the data bit indicated by the node (e.g., reliability of the data bit).

[0107] For example, when a data unit (DU) indicates K (e.g., 128) bits of data, the data unit (DU) may include K nodes (NODE). Among the K nodes (NODE), the i-th node (NODE_i) may include the i-th data bit of the K bits of data and state information of the i-th node (NODE_i).

[0108] In FIG. 4, the value of the data bit (NODE_BIT) included in the i-th node (NODE_i) may be 0 or 1. And the value of the state information (NODE_STATE) included in the i-th node (NODE_i) may be 0 or 1.

[0109] For example, the value of state information (NODE_STATE) included in the i-th node (NODE_i) may represent the reliability of the value of the data bit (NODE_BIT) included in the i-th node (NODE_i). For example, if the reliability of the data bit (NODE_BIT) included in the i-th node (NODE_i) is strong, the value of state information (NODE_STATE) included in the i-th node (NODE_i) may be 0, and if the reliability of the data bit (NODE_BIT) included in the i-th node (NODE_i) is weak, the value of state information (NODE_STATE) included in the i-th node (NODE_i) may be 1.

[0110] The decoder (310) of the storage device (300) can change the values ​​of the data bits (NODE_BIT) and state information (NODE_STATE) of the nodes (NODE) ​​included in the data unit (DU) during the process of decoding the data unit (DU).

[0111] For example, the decoder (310) can flip the data bit (NODE_BIT) of the node (NODE) ​​when it determines that the data bit (NODE_BIT) of the node (NODE) ​​is very unreliable while the state information (NODE_STATE) of the node (NODE) ​​is 0. Meanwhile, the decoder (310) can change the state information (NODE_STATE) of the node (NODE) ​​from 0 to 1 when it determines that the data bit (NODE_BIT) of the node (NODE) ​​is unreliable while the state information (NODE_STATE) of the node (NODE) ​​is 0.

[0112] As another example, the decoder (310) can flip the data bit (NODE_BIT) of the node (NODE) ​​when it determines that the data bit (NODE_BIT) of the node (NODE) ​​is unreliable while the state information (NODE_STATE) of the node (NODE) ​​is 1.

[0113] Meanwhile, the decoder (310) can determine whether the data bit (NODE_BIT) of the corresponding node (NODE) ​​is very unreliable or unreliable through the operation result associated with the corresponding node (NODE).

[0114] FIG. 5 is a diagram showing the schematic operation of a decoder (310) according to embodiments of the present invention.

[0115] Referring to FIG. 5, the decoder (310) receives a target data unit (TGT_DU) among the aforementioned multiple data units (DU) and can perform decoding on the target data unit (TGT_DU).

[0116] At this time, the decoder (310) can execute M bit-flip check formulas (CN_BF) (M is a natural number) based on the nodes included in the target data unit (TGT_DU). Then, based on the result of executing the M bit-flip check formulas (CN_BF), the decoder (310) can determine whether to change the data bit or state information for each of the nodes (NODE) ​​included in the target data unit (TGT_DU).

[0117] For example, the decoder (310) can calculate flip scores for nodes (NODE) ​​included in the target data unit (TGT_DU) based on the result of executing M bit-flip check formulas (CN_BF). The flip score for a specific node included in the target data unit (TGT_DU) may be information indicating whether to perform a bit-flip for that node.

[0118] At this time, the flip score for a specific node included in the target data unit (TGT_DU) can be determined based on the sum of the execution results of the bit-flip check formulas (CN_BF) that use the corresponding node among the M bit-flip check formulas. Meanwhile, the result of an XOR operation on the accumulated change information for the data bits of the corresponding node can be added to the flip score for the corresponding node.

[0119] The decoder (310) can change the data bits or state information contained in the nodes (NODE) ​​contained in the target data unit (TGT_DU) based on the flip score for the nodes (NODE) ​​contained in the target data unit (TGT_DU).

[0120] At this time, each of the M bit-flip check formulas (CN_BF) may be a formula that performs a target operation on one or more of the data bits included in the nodes (NODE) ​​included in the target data unit (TGT_DU).

[0121] Meanwhile, which nodes among the nodes included in the target data unit (TGT_DU) correspond to each of the M bit-flip check formulas (CN_BF) can be defined through a matrix.

[0122] The matrix can have M rows and as many columns as the number of nodes included in the target data unit (TGT_DU).

[0123] At this time, the value of the (i, j) element of the matrix may indicate whether the i-th bit-flip check formula among the M bit-flip check formulas (CN_BF) executes the target operation on the data bit contained in the j-th node among the nodes contained in the target data unit (TGT_DU).

[0124] FIG. 6 is a diagram showing an example of a bit-flip check formula (CN_BF) according to embodiments of the present invention.

[0125] Referring to FIG. 6, the bit flip check formula (CN_BF) may be a formula that performs a target operation ◎ on data bits (NODE_BIT) included in specific nodes (NODE_1, NODE_3, ..., NODE_N-2, NODE_N) among a plurality of nodes (NODE) ​​included in the target data unit (TGT_DU).

[0126] At this time, the result of executing the bit flip check formula (CN_BF) can be expressed by the following mathematical formula.

[0127] [Mathematical Formula 1]

[0128] result(CN_BF) = NODE_BIT(NODE_1) ◎ NODE_BIT(NODE_3) ◎ ... ◎ NODE_BIT(NODE_N-2) ◎ NODE_BIT(NODE_N)

[0129] In this case, the target operation ◎ can be an XOR operation.

[0130] The general operation of the decoder (310) according to the embodiments of the present invention has been described above. The general operation of the preprocessing device (320) will be described below.

[0131] FIG. 7 is a diagram showing the schematic operation of a pre-processing device (320) according to embodiments of the present invention.

[0132] Referring to FIG. 7, the preprocessing unit (320) can execute N (N is a natural number) preprocessing check formulas (CN_LA) for the aforementioned candidate data unit (DU_CAND).

[0133] And, the preprocessing unit (320) can calculate flip scores for the nodes included in the candidate data unit (DU_CAND) based on the results of executing N preprocessing check formulas (CN_LA).

[0134] At this time, the flip score for a specific node included in the candidate data unit (DU_CAND) can be determined based on the sum of the execution results of the preprocessing check formulas that use the corresponding node among the N preprocessing check formulas (CN_LA).

[0135] Meanwhile, the method by which the decoder (310) calculates the flip score for a specific node in FIG. 5 and the method by which the preprocessing unit (320) calculates the flip score for a specific node in FIG. 7 may be different from each other. For example, the number of preprocessing check formulas used by the preprocessing unit (320) to calculate the flip score for a specific node may be smaller than the number of bit-flip check formulas used by the decoder (310) to calculate the flip score for a specific node.

[0136] The preprocessing unit (320) can determine whether to decode the candidate data unit (DU_CAND) using the decoder (310) based on the flip score for the nodes included in the candidate data unit (DU_CAND).

[0137] At this time, each of the N preliminary processing check formulas (CN_LA) may be a formula that executes a target operation on one or more of the data bits included in the nodes (NODE) ​​included in the candidate data unit (DU_CAND).

[0138] Below, the difference between the bit-flip check formula (CN_BF) described in FIG. 5 and the pre-processing check formula (CN_LA) described in FIG. 7 will be explained.

[0139] FIG. 8 is a diagram showing an example of the difference between a bit-flip check formula (CN_BF) and a preprocessing check formula (CN_LA) according to embodiments of the present invention.

[0140] Referring to FIG. 8, the number of bit-flip check formulas (CN_BF) used by the decoder (310) M is smaller than the number of preprocessing check formulas (CN_LA) used by the preprocessing unit (320) N.

[0141] This means that the number of formulas used by the preprocessing unit (320) to determine whether to decode the data unit (DU) using the decoder (310) is smaller than the number of formulas used by the decoder (310) to decode the data unit (DU). Therefore, the preprocessing unit (320) can quickly determine whether to decode the data unit (DU) using the decoder (310).

[0142] FIG. 9 is a diagram showing another example of the difference between a bit-flip check formula (CN_BF) and a preprocessing check formula (CN_LA) according to embodiments of the present invention.

[0143] Referring to Fig. 9, the number of nodes (NODE) ​​K used by the bit-flip check formula (CN_BF) is greater than the number of nodes (NODE) ​​K' used by the preprocessing check formula (CN_LA).

[0144] This means that the formula used by the preprocessing unit (320) to determine whether to decode the data unit (DU) using the decoder (310) is simpler than the formula used by the decoder (310) to decode the data unit (DU). Therefore, the preprocessing unit (320) can quickly determine whether to decode the data unit (DU) using the decoder (310).

[0145] FIG. 10 is a flowchart illustrating an example of an operation in which a decoding device (300) according to embodiments of the present invention determines whether to decode a candidate data unit (DU_CAND).

[0146] Referring to FIG. 10, the preprocessing unit (320) of the decoding device (300) can first determine a candidate data unit (DU_CAND) (S1010).

[0147] And the preprocessing unit (320) can execute N preprocessing check formulas (CN_LA) on the nodes (NODE) ​​of the candidate data unit (DU_CAND) as described in FIG. 7 (S1020).

[0148] And the preprocessing unit (320) can calculate flip scores for the nodes (NODE) ​​of the candidate data unit (DU_CAND) (S1030).

[0149] The pre-processing unit (320) can determine whether the number of nodes among the nodes included in the candidate data unit (DU_CAND) whose flip score is greater than or equal to the threshold score is greater than or equal to the threshold count (S1040).

[0150] When the number of nodes (NODE) ​​included in the candidate data unit (DU_CAND) whose flip score is greater than or equal to the threshold score is greater than or equal to the threshold count (S1030-Y), the preprocessing unit (320) may decide to decode the candidate data unit (DU_CAND) using the decoder (310) (S1040). This is because there is a high probability that errors exist in the candidate data unit (DU_CAND), so it is necessary to correct the errors existing in the candidate data unit (DU_CAND) using the decoder (310).

[0151] On the other hand, when the number of nodes (NODE) ​​included in the candidate data unit (DU_CAND) whose flip score is greater than or equal to the threshold score is less than the threshold count (S1030-N), the preprocessing unit (320) may decide to skip decoding for the candidate data unit (DU_CAND) (S1050). This is because there is a need to reduce the time and power used for decoding the candidate data unit (DU_CAND) since there is a low probability that an error exists in the candidate data unit (DU_CAND).

[0152] FIG. 11 is a diagram showing the operation method of a decoding device (300) according to embodiments of the present invention.

[0153] Referring to FIG. 11, the operation method of the decoding device (300) may include the step (S1110) of determining a candidate data unit (DU_CAND) in parallel with the operation of decoding a target data unit (TGT_DU) among a plurality of data units (DU) included in one data chunk (DC).

[0154] At this time, each of the plurality of data units (DU) may include a plurality of nodes (NODE). And each of the plurality of nodes (NODE) ​​may include data bits (NODE_BIT) and state information (NODE_STATE).

[0155] And the method of operation of the decoding device (300) may include a step (S1120) of determining whether to decode the candidate data unit (DU_CAND).

[0156] And the method of operation of the decoding device (300) may include a step (S1130) of decoding a candidate data unit (DU_CAND) depending on whether to decode the candidate data unit (DU_CAND) after performing decoding for the target data unit (TGT_DU).

[0157] For example, the step of decoding a candidate data unit (DU_CAND) (S1130) may include: i) executing M bit-flip check formulas (CN_BF) based on the nodes (NODE) ​​included in the candidate data unit (DU_CAND) (M is a natural number); and ii) determining whether to change data bits (NODE_BIT) or state information (NODE_STATE) for the nodes included in the candidate data unit (DU_CAND) based on the result of executing the M bit-flip check formulas (CN_BF).

[0158] In this case, each of the M bit-flip check formulas (CN_BF) may be a formula that performs a target operation on one or more of the data bits included in the nodes included in the candidate data unit (DU_CAND). The target operation may be, for example, an XOR operation.

[0159] Meanwhile, the step (S1120) of determining whether to decode a candidate data unit (DU_CAND) may include: i) executing N (N is a natural number) preliminary processing check formulas based on the nodes included in the candidate data unit (DU_CAND); ii) calculating flip scores for the nodes (NODE) ​​included in the candidate data unit (DU_CAND) based on the result of executing N preliminary processing check formulas (CN_LA); and iii) determining whether to decode the candidate data unit (DU_CAND) based on the flip scores for the nodes included in the candidate data unit (DU_CAND).

[0160] Each of the N preliminary processing check formulas (CN_LA) may be a formula that executes a target operation on one or more of the data bits included in the nodes included in the candidate data unit (DU_CAND).

[0161] In this case, for example, M can be greater than N.

[0162] For example, the number of nodes used by each of the M bit-flip check formulas (CN_BF) may be greater than the number of nodes used by each of the N preprocessing check formulas (CN_LA).

[0163] Meanwhile, the step of determining whether to decode the candidate data unit (DU_CAND) based on the flip scores of the nodes included in the candidate data unit (DU_CAND) may, for example, determine to decode the candidate data unit (DU_CAND) when the number of nodes among the nodes included in the candidate data unit (DU_CAND) whose flip score is greater than or equal to the threshold score is greater than or equal to the threshold count.

[0164] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Furthermore, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and thus the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0165] 100: Storage device 110: Memory 120: Controller 121: Host Interface 122: Memory interface 123: Control circuit 124: Processor 125: Working Memory 126: Error Detection and Correction Circuit 210: Memory cell array 220: Address decoder 230: Lead and Write Circuit 240: Control Logic 250: Voltage generation circuit

Claims

Claim 1 A decoding device comprising: a decoder that performs decoding for one or more of a plurality of data units included in a single data chunk; and a preprocessing unit that determines a candidate data unit among the plurality of data units and determines whether to decode the candidate data unit using the decoder; wherein each of the plurality of data units includes a plurality of nodes, and each of the plurality of nodes includes data bits and state information, and the decoder receives a target data unit among the plurality of data units and determines whether to change the data bits or state information for each of the nodes included in the target data unit based on the result of executing M (M is a natural number) bit-flip check formulas based on the nodes included in the target data unit. Claim 2 delete Claim 3 In claim 1, each of the M bit-flip check formulas is a decoding device that performs a target operation on one or more of the data bits included in the nodes included in the target data unit. Claim 4 In paragraph 3, the decoding device wherein the target operation is an XOR operation. Claim 5 In paragraph 3, the preprocessing device calculates a flip score for the nodes included in the candidate data unit based on the result of executing N (N is a natural number) preprocessing check formulas based on the nodes included in the candidate data unit, and determines whether to decode the candidate data unit using the decoder based on the flip score for the nodes included in the candidate data unit, and each of the N preprocessing check formulas is a decoding device that executes the target operation on one or more of the data bits included in the nodes included in the candidate data unit. Claim 6 In paragraph 5, the above M is a decoding device larger than the above N. Claim 7 In paragraph 5, a decoding device in which the number of nodes used by each of the M bit-flip check formulas is greater than the number of nodes used by each of the N preprocessing check formulas. Claim 8 In claim 5, the preprocessing device is a decoding device that decides to decode the candidate data unit using the decoder when the number of nodes among the nodes included in the candidate data unit whose flip score is greater than or equal to a threshold score is greater than or equal to a threshold count. Claim 9 A method of operation of a decoding device comprising: a step of determining a candidate data unit among a plurality of data units in parallel with an operation of decoding a target data unit among a plurality of data units included in a single data chunk; a step of determining whether to decode the candidate data unit; and a step of decoding the candidate data unit according to whether to decode the candidate data unit after performing decoding for the target data unit, wherein each of the plurality of data units includes a plurality of nodes, and each of the plurality of nodes includes data bits and state information, and the step of decoding the candidate data unit includes: a step of executing M (M is a natural number) bit-flip check formulas based on the nodes included in the candidate data unit; and a step of determining whether to change the data bits or state information for the nodes included in the candidate data unit based on the result of executing the M bit-flip check formulas. Claim 10 delete Claim 11 In claim 9, the method of operation of a decoding device wherein each of the M bit-flip check formulas is a formula that performs a target operation on one or more of the data bits included in the nodes included in the candidate data unit. Claim 12 In paragraph 11, the above target operation is a method of operation of a decoding device in which the target operation is an XOR operation. Claim 13 A method of operation of a decoding device according to claim 11, wherein the step of determining whether to decode the candidate data unit comprises: executing N (N is a natural number) preliminary processing check formulas based on the nodes included in the candidate data unit; calculating a flip score for the nodes included in the candidate data unit based on the result of executing the N preliminary processing check formulas; and determining whether to decode the candidate data unit based on the flip score for the nodes included in the candidate data unit; wherein each of the N preliminary processing check formulas is a formula that executes the target operation on one or more of the data bits included in the nodes included in the candidate data unit. Claim 14 In paragraph 13, the above M is a method of operation of a decoding device larger than the above N. Claim 15 In paragraph 13, a method of operation of a decoding device in which the number of nodes used by each of the M bit-flip check formulas is greater than the number of nodes used by each of the N pre-processing check formulas. Claim 16 In claim 13, the step of determining whether to decode the candidate data unit based on flip scores for nodes included in the candidate data unit is a method of operation of a decoding device that determines to decode the candidate data unit when the number of nodes among the nodes included in the candidate data unit whose flip score is greater than or equal to a threshold score is greater than or equal to a threshold count. Claim 17 A storage device comprising: a memory for storing a plurality of data units included in a single data chunk; and a controller for performing decoding on one or more of the plurality of data units, determining a candidate data unit among the plurality of data units, and determining whether to decode the candidate data unit using a decoder, wherein each of the plurality of data units includes a plurality of nodes, and each of the plurality of nodes includes data bits and state information, and wherein the decoder receives a target data unit among the plurality of data units and determines whether to change the data bits or state information for each of the nodes included in the target data unit based on the result of executing M (M is a natural number) bit-flip check formulas based on the nodes included in the target data unit.

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