The Method and Apparatus for Detecting a 5G-NR Sidelink Synchronization Signal Robust to AGC Initial Delay

Abstract

The present invention relates to a 5G-NR sidelink synchronization signal detection method and apparatus robust to AGC initial delay, wherein only the signal after the completion of the AGC operation is passed for a received signal having a repeated symbol structure, and a sliding cumulative value is calculated by performing a delay correlation operation on the passed signal for a length longer than CP, wherein the window length for the correlation operation is determined variably according to the completion time of the AGC operation, and the symbol timing is detected based on the peak point of the calculated sliding cumulative value.

Description

Technology Field

[0001] The present invention relates to a 5G-NR sidelink synchronization signal detection method and apparatus robust to AGC initial delay, wherein only the signal after the completion of the AGC operation is passed for a received signal having a repeated symbol structure, and a sliding cumulative value is calculated by performing a delay correlation operation on the passed signal for a length longer than CP, wherein the window length for the correlation operation is determined variably according to the completion time of the AGC operation, and the symbol timing is detected based on the peak point of the calculated sliding cumulative value. Background Technology

[0003] With the rapid advancement of mobile communication technology and the commercialization of 5th generation (5G) New Radio (NR) systems, the demand for ultra-high-speed, ultra-low-latency, and high-reliability communication services is surging. In particular, Sidelink technology, which enables direct communication between terminals without passing through base stations, plays a key role in various fields such as Vehicle-to-Everything (V2X) communication and public safety networks. In such Sidelink communication systems, for a receiving device to accurately demodulate a signal sent by a transmitting device, a synchronization process must first be performed to identify the start time of the received signal and the frequency error.

[0004] Generally, wireless communication systems utilize a structure in which a specific pattern is repeated at the beginning of the transmitted signal to achieve fast and accurate synchronization. The receiving device uses this repeating structure to perform correlation operations between the received signal and a signal delayed by a certain period of time, and obtains synchronization by detecting the resulting peak point.

[0005] However, conventional synchronization detection methods tend to rely excessively on correlation characteristics using short-length Cyclic Prefixes (CPs) inserted to prevent inter-symbol interference. In sidelink channels with high mobility and poor propagation environments, such as V2X, delay spreading due to multipath propagation frequently exceeds the CP length, leading to severe inter-symbol interference. Furthermore, high noise levels often make it difficult to secure sufficient synchronization detection energy (power) using only short-length correlations. Consequently, this increases synchronization detection failures or errors, ultimately degrading overall communication reliability.

[0006] Furthermore, in wireless channel environments, the power level of the received signal changes frequently due to path loss, fading, etc., so an automatic gain control (AGC) function is essential to prevent ADC saturation of the receiving device and maintain the optimal operating range. However, a certain initial delay time is required for the AGC circuit to properly stabilize the received gain. Conventional methods often indiscriminately include distorted signal components from this initial unstable AGC period in the correlation calculation, which dulls the correlation peaks or induces false peaks, thereby further deteriorating synchronization performance.

[0007] Therefore, there is a need to develop technology that can effectively implement robust synchronization signal detection required in 5G-NR sidelink systems in harsh environments. The problem to be solved

[0009] The present invention aims to provide a 5G-NR sidelink synchronization signal detection method and apparatus robust to AGC initial delay, wherein for a received signal having a repeated symbol structure, only the signal after the AGC operation is completed is passed, and a delay correlation operation is performed on the passed signal for a length longer than CP to calculate a sliding cumulative value, wherein the window length for the correlation operation is determined variably according to the completion time of the AGC operation, and the symbol timing is detected based on the peak point of the calculated sliding cumulative value. means of solving the problem

[0011] In order to solve the above problem, in one embodiment of the present invention, a synchronization signal detection method performed in a receiving device of a 5G-NR sidelink wireless communication system comprises: a signal receiving step of receiving a receiving signal having a structure in which a second OFDM symbol is repeatedly arranged to have the same waveform as a first OFDM symbol in order to perform automatic gain control (AGC); a gate control step of controlling a gate to pass only the signal after a completion signal indicating that the AGC operation has been completed is generated, for the signal that has passed through the gate, by multiplying the complex conjugate of a delayed signal delayed by a predetermined sample length and the current signal that has not been delayed; and an accumulation value calculation step of calculating a sliding accumulation value in the form of a complex number by shifting the generated correlation value by a predetermined window length and summing them. The present invention provides a synchronization signal detection method comprising: a synchronization detection step for detecting symbol timing and frequency offset for synchronization based on a point where power corresponding to the magnitude of the sliding accumulated value is maximum; wherein the window length is determined by subtracting the length of the interval required from the start of the AGC operation until the completion signal is generated and the gate is opened from the sample length.

[0012] In one embodiment of the present invention, the received signal is composed of a time slot including a PSCCH (Physical Sidelink Control Channel) and a PSSCH (Physical Sidelink Shared Channel) of a 5G-NR sidelink system, and the first OFDM symbol is positioned at the very beginning of the time slot to serve as a preamble for AGC operation, and the second OFDM symbol is positioned immediately after the first OFDM symbol.

[0013] In one embodiment of the present invention, the gate control step can block the transient section in which the gain of the received signal changes due to the AGC operation, and control the gate to pass the signal from the section in which the level of the received signal has stabilized in response to the completion signal.

[0014] In one embodiment of the present invention, the sample length is set to the sum of the length of the first OFDM symbol and the length of the CP (Cyclic Prefix) paired with the corresponding OFDM symbol, so that the correlation value generation step can perform delayed auto-correlation between the first OFDM symbol and the second OFDM symbol.

[0015] In one embodiment of the present invention, the sliding accumulated value is calculated as complex data including a real part and an imaginary part, and the synchronization detection step derives the power by summing the square of the real part and the square of the imaginary part, derives an index of the point in time when the power has a maximum value, and determines the corresponding point in time as the symbol timing.

[0016] In one embodiment of the present invention, the synchronization detection step can extract the phase value of the sliding accumulated value at the point where the power is maximum, and calculate the frequency offset according to the following mathematical formula using the phase value.

[0017]

[0018] (Here, Phase is the phase value at the power maximum point, N is the length of the first OFDM symbol, M is the sample length, and SCS is the preset subcarrier interval)

[0019] In order to solve the above problem, in one embodiment of the present invention, a receiving device of a 5G-NR sidelink wireless communication system performing a synchronization signal detection method comprises: a signal receiving unit that receives a receiving signal having a structure in which a second OFDM symbol is repeatedly arranged to have the same waveform as a first OFDM symbol to perform automatic gain control (AGC); a gate control unit that controls a gate to pass only the signal after a completion signal indicating that the AGC operation has been completed is generated, for the signal that has passed through the gate, a correlation value generating unit that generates a correlation value by multiplying the complex conjugate of a delayed signal delayed by a predetermined sample length and the current signal that has not been delayed; and an accumulation value calculation unit that calculates a sliding accumulation value in the form of a complex number by shifting the generated correlation value by a predetermined window length and summing them. The present invention provides a receiving device of a wireless communication system comprising: a synchronization detection unit that detects symbol timing and frequency offset for synchronization based on a point where power corresponding to the magnitude of the sliding accumulated value is maximum; wherein the window length is determined by subtracting the length of the interval required from the start of the AGC operation until the completion signal is generated and the gate is opened from the sample length. Effects of the invention

[0021] In one embodiment of the present invention, unlike the conventional method using a short CP (Cyclic Prefix) interval, correlation operations are performed by utilizing a long repetition interval corresponding to the entire length of the OFDM symbol, thereby securing a high correlation processing gain to maximize the correlation signal-to-noise ratio (SNR), and thereby enabling robust synchronization detection performance even in poor channel environments where severe noise and fading exist.

[0022] In one embodiment of the present invention, by selectively passing only the signal after the point in time when the AGC operation is completed and the received signal is stabilized, it is possible to fundamentally prevent the problem of signal distortion and noise occurring in the initial transient response period of AGC being introduced into the correlation operation and lowering the accuracy of synchronization detection.

[0023] In one embodiment of the present invention, by performing an adaptive control method that actively varies the window length of the correlator according to the time required for AGC stabilization, it is possible to achieve the effect of maintaining stable and robust synchronization acquisition performance by always using only the optimal effective signal interval even in various channel environments where the power level of the received signal changes rapidly.

[0024] In one embodiment of the present invention, by preventing unnecessary computational operations of the correlator during an invalid signal interval (AGC instability interval), the digital signal processing load of the receiving device can be reduced and the overall power consumption can be efficiently reduced. Brief explanation of the drawing

[0026] FIG. 1 schematically illustrates an overall block diagram of a receiving device of a 5G-NR sidelink wireless communication system according to one embodiment of the present invention. FIG. 2 schematically illustrates the components of a received signal according to one embodiment of the present invention. FIG. 3 schematically illustrates the relevant parameters for a received signal and a delay signal according to one embodiment of the present invention. FIG. 4 schematically illustrates a block diagram for explaining the internal operation principle of a correlator in a receiving device according to one embodiment of the present invention. FIG. 5 schematically illustrates the process of performing the cumulative value calculation step according to one embodiment of the present invention. FIG. 6 schematically illustrates the process of performing a synchronization detection procedure according to one embodiment of the present invention. FIG. 7 schematically illustrates the process of calculating a frequency offset according to symbol timing according to one embodiment of the present invention. FIG. 8 exemplarily illustrates a preset SCS in 5G-NR sidelink wireless communication according to one embodiment of the present invention. FIG. 9 schematically illustrates a preset threshold criterion and a correction coefficient applied to power according to one embodiment of the present invention. Specific details for implementing the invention

[0027] Hereinafter, various embodiments and / or aspects are disclosed with reference to the drawings. For illustrative purposes, numerous specific details are disclosed in the following description to aid in a general understanding of one or more aspects. However, it will also be recognized by those skilled in the art that these aspects may be practiced without such specific details. The following description and the accompanying drawings describe specific exemplary aspects of one or more aspects in detail. However, these aspects are exemplary, and some of the various methods in the principles of the various aspects may be used, and the description is intended to include all such aspects and their equivalents.

[0029] In addition, various aspects and features will be presented by a system that may include multiple devices, components and / or modules, etc. It should also be understood and recognized that various systems may include additional devices, components and / or modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in relation to the drawings.

[0030] Terms such as “embodiment,” “example,” “aspect,” “example,” etc. as used herein may not be interpreted as implying that any aspect or design described is superior or more advantageous than other aspects or designs. Terms used below, such as “part,” “component,” “module,” “system,” “interface,” etc., generally refer to computer-related entities and may, for example, refer to hardware, a combination of hardware and software, or software.

[0031] Additionally, the terms “comprising” and / or “comprising” should be understood to mean that the relevant feature and / or component is present, but not to exclude the presence or addition of one or more other features, components and / or groups thereof.

[0032] Additionally, terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0033] Furthermore, in the embodiments of the present invention, all terms used herein, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the embodiments of the present invention.

[0035] FIG. 1 schematically illustrates an overall block diagram of a receiving device of a 5G-NR sidelink wireless communication system according to one embodiment of the present invention.

[0037] As illustrated in FIG. 1, a synchronization signal detection method performed at a receiving device of a 5G-NR sidelink wireless communication system comprises: a signal receiving step (S100) receiving a receiving signal having a structure in which a second OFDM symbol is repeatedly arranged to have the same waveform as a first OFDM symbol in order to perform automatic gain control (AGC); a gate control step (S200) controlling a gate to pass only the signal after a completion signal indicating that the AGC operation has been completed is generated, and the gate is controlled to pass the signal after the AGC operation has been completed; a correlation value generation step (S300) generating a correlation value by multiplying the complex conjugate of a delayed signal delayed by a predetermined sample length and the current signal that has not been delayed for the signal that has passed through the gate; and a cumulative value calculation step (S400) calculating a sliding cumulative value in the form of a complex number by shifting the generated correlation value by a predetermined window length and summing them. and a synchronization detection step (S500) for detecting symbol timing and frequency offset for synchronization based on the point where the power corresponding to the magnitude of the sliding accumulated value is maximum; wherein the window length is determined by subtracting the length of the interval required from the start of the AGC operation until the completion signal is generated and the gate is opened from the sample length.

[0038] Additionally, as a receiving device of a 5G-NR sidelink wireless communication system performing a synchronization signal detection method, a signal receiving unit receiving a receiving signal having a structure in which a second OFDM symbol is repeatedly arranged to have the same waveform as a first OFDM symbol to perform automatic gain control (AGC); a gate control unit controlling a gate to pass only the signal after a completion signal indicating that the AGC operation has been completed is generated, for the signal that has passed through the gate; a correlation value generating unit generating a correlation value by multiplying the complex conjugate of a delayed signal delayed by a predetermined sample length and the current signal that has not been delayed for the signal that has passed through the gate; and an accumulation value calculating unit calculating a sliding accumulation value in the form of a complex number by shifting the generated correlation value by a predetermined window length and summing them. and a synchronization detection unit that detects symbol timing and frequency offset for synchronization based on the point where the power corresponding to the magnitude of the sliding accumulated value is maximum; wherein the window length is determined by subtracting the length of the interval required from the start of the AGC operation until the completion signal is generated and the gate is opened from the sample length.

[0040] Specifically, the receiving device of the present invention performs a gating and correlation method linked with an automatic gain control (AGC) operation to obtain stable synchronization from a wireless signal received through an antenna.

[0041] The receiving device of the present invention is broadly configured to include a signal receiving unit that performs a signal receiving step (S100), a gate control unit that performs a gate control step (S200), a correlation value generating unit that performs a correlation value generating step (S300), a cumulative value calculating unit that performs a cumulative value calculating step (S400), and a synchronization detection unit that performs a synchronization detection step (S500). The detailed operation of each component is as follows.

[0043] First, a 5G-NR sidelink wireless signal is received through an antenna. This received signal is input to a signal receiving unit. The signal receiving step (S100) performs the role of down-converting an analog signal in the RF band to baseband and converting it into a digital signal. In particular, the received signal input to the present invention is characterized by having a specific frame structure (e.g., a repeated synchronization signal block) in which the second OFDM symbol has the same waveform as the first OFDM symbol, in order to perform efficient synchronization detection and AGC.

[0045] The received signal converted into digital is transmitted to the gate control unit. More specifically, the gate control unit may include an AGC control unit and a gate control unit. The gate control step (S200) performs an AGC operation by the AGC control unit to measure the power of the input received signal and appropriately adjust the gain.

[0046] Subsequently, when the AGC operation is completed and it is determined that the power level of the received signal has stabilized, a completion signal is generated and transmitted to the gate control unit.

[0047] The gate control step (S200) activates the gate enable signal (Gate_Enable) by the gate control unit from the time the completion signal is received. The gate control unit opens and closes the signal path according to the gate enable signal. That is, during the initial period when the AGC is unstable, the gate enable signal is deactivated to block the input signal, and only the stable signal after the AGC is completed and the gate enable signal is activated is passed through and transmitted to the subsequent correlator. The correlator is a component that integrally performs the functions of the correlation value generation unit and the cumulative value calculation unit.

[0049] The correlation value generation step (S300) generates a correlation value for each sample by multiplying the input signal and the delayed signal, which is obtained by delaying the signal by a predetermined sample length and taking the complex conjugate. The cumulative value calculation step (S400) calculates a sliding cumulative value in the form of a complex number by summing the multiple correlation values ​​generated in this way while shifting them by a predetermined window length.

[0050] In this case, the window length is not a fixed value, but is determined by subtracting the time elapsed from the start of the AGC operation until the gate opens (AGC initial delay time) from the sample length. In other words, the longer it takes for AGC stabilization, the shorter the window length used for correlation becomes.

[0051] The calculated sliding accumulated value is input to the synchronization detection unit. The synchronization detection step (S500) calculates power corresponding to the magnitude of the sliding accumulated value and detects the peak point where the power value is maximum. Since the corresponding peak point corresponds to the boundary of the repeating symbol, the accurate symbol timing is determined based on this, and furthermore, if necessary, the frequency offset is also detected to complete the final synchronization acquisition.

[0053] Generally, OFDM systems use short CPs to prevent inter-symbol interference, and conventionally, synchronization is performed using these CP intervals.

[0054] However, in packet-based sidelink communication, AGC operations must be performed at the beginning of the received packet. If the transient time required for AGC to stabilize becomes longer than the short CP interval, problems arise where the CP signal required for synchronization detection is distorted or lost. In other words, a short CP structure is very vulnerable to AGC initial delay.

[0055] In contrast, the present invention has a structure that repeats the entire OFDM symbol, having a section much longer than the CP. Therefore, even if the leading part of the symbol is partially lost due to the AGC operation, a valid signal section of sufficient length that can still be utilized for synchronization detection is secured, thereby ensuring synchronization performance robust against the initial delay of AGC.

[0057] FIG. 2 schematically illustrates the components of a received signal according to one embodiment of the present invention.

[0059] As illustrated in FIG. 2, the received signal is composed of a time slot including a PSCCH (Physical Sidelink Control Channel) and a PSSCH (Physical Sidelink Shared Channel) of a 5G-NR sidelink system, wherein the first OFDM symbol is positioned at the very beginning of the time slot to serve as a preamble for AGC operation, and the second OFDM symbol is positioned immediately after the first OFDM symbol.

[0061] Specifically, the input signal handled in the present invention is configured in the form of a time slot including a PSCCH (Physical Sidelink Control Channel) and a PSSCH (Physical Sidelink Shared Channel) in accordance with the 5G-NR sidelink communication standard.

[0062] The slot signal consists of multiple OFDM symbols (OFDM Symbol #0, #1, #2, …) arranged consecutively in the time domain and Cyclic Prefixes (CPs) added to the front of each symbol to prevent interference between each symbol.

[0063] The most significant feature of the receiving signal structure according to the present invention is that the first OFDM symbol located at the very front of the slot is copied and arranged to have the same waveform as the second OFDM symbol placed immediately thereafter.

[0065] Specifically, the first OFDM symbol of the present invention is designed to serve as a preamble for automatic gain control (AGC) on the receiving side rather than for data transmission itself. Since sidelink communication receives signals in burst form due to the direct communication characteristics between terminals, a certain amount of time is required for the receiver to detect the power level of the signal and stabilize the amplifier gain.

[0066] Accordingly, the present invention enables stable reception in the second OFDM symbol section containing actual valid data by replicating the second OFDM symbol (Symbol #1) as is and placing it before the first OFDM symbol (Symbol #0), so that even if the signal is distorted due to AGC operation in the first OFDM symbol section, stable reception is possible in the second OFDM symbol section containing actual valid data.

[0067] Furthermore, this symbol repetition structure serves as a key prerequisite for enabling delayed autocorrelation-based synchronization detection, as described in FIGS. 3 to 6, beyond the AGC protection function. That is, because two adjacent symbols have the same pattern, the receiving device can secure a long correlation interval to perform high-precision symbol timing detection and frequency offset estimation.

[0069] FIG. 3 schematically illustrates the relevant parameters for a received signal and a delay signal according to one embodiment of the present invention.

[0071] As illustrated in FIG. 3, the gate control step (S200) blocks the transient section in which the gain of the received signal changes due to the AGC operation, and controls the gate to pass the signal from the section in which the level of the received signal has stabilized in response to the completion signal.

[0072] In addition, the sample length is set to the sum of the length of the first OFDM symbol and the length of the CP (Cyclic Prefix) paired with the corresponding OFDM symbol.

[0074] Specifically, FIG. 3 is a timing diagram for explaining the signal gating and delayed signal generation process according to an AGC operation according to an embodiment of the present invention. As shown in FIG. 3, the temporal relationship between the 'After-AGC Signal' input to the receiving device, the 'AGC Done' signal indicating the completion of the AGC operation, the valid signal that has passed through the gate, and the 'M-Delayed Signal' that has been delayed is illustrated.

[0076] First, looking at the 'After-AGC Signal' at the top, it can be seen that the AGC operation is performed during the first OFDM symbol (OFDM Symbol #0) section located at the very beginning of the received packet. At the initial stage when a sidelink packet is received, a process is required for the receiver's amplifier gain to be adjusted to match the input signal level, which inevitably causes an 'AGC transient section (AGC Transient A)' where the signal level changes unstably.

[0077] Data included in the corresponding transient interval (A) is severely distorted, so there is a concern that using it for correlation operations may degrade synchronization detection performance. Therefore, the gate control unit of the present invention monitors the 'AGC Done' completion signal output from the AGC unit.

[0078] The above completion signal transitions from 'Low' to 'High' when gain control is stabilized, and the gate passes only the signal after this signal is activated, while blocking or masking the previous transient section (Part A) to 0.

[0079] As a result, the signal passing through the gate starts from the stable section remaining after the transient section (A) among the first OFDM symbols is removed, i.e., the normal section (Normal Park, K). At this time, the length of the effective section, i.e., the window length, for which correlation values ​​can be summed in the cumulative value calculation unit is determined by the mathematical relationship K=MA. Preferably, M is the total delay sample length (N+C), and A is the length of the AGC transient section.

[0081] Meanwhile, at the bottom of FIG. 3, an 'M-Delayed Signal' is shown, which is a signal passing through the gate delayed by M samples. Since the delay value M is set to be equal to the sum (N+C) of the length of the first OFDM symbol and the length of the corresponding CP, the second OFDM symbol section of the currently input signal and the first OFDM symbol section of the delayed signal are aligned on the time axis.

[0082] The present invention performs a correlation operation in this aligned section. As shown in FIG. 3, since the front part (A) of the first OFDM symbol is removed by a gate, the actual correlation operation is performed in the remaining section of length K.

[0083] In other words, FIG. 3 illustrates the signal processing strategy of the present invention, which excludes the front part (A) lost due to the AGC operation and selects only the reliable back part (K) to utilize for synchronization detection.

[0085] FIG. 4 schematically illustrates a block diagram for explaining the internal operation principle of a correlator in a receiving device according to one embodiment of the present invention.

[0087] As illustrated in FIG. 4, the correlation value generation step (S300) performs delayed auto-correlation between the first OFDM symbol and the second OFDM symbol.

[0088] In addition, the sliding accumulated value is calculated as complex data including a real part and an imaginary part, and the synchronization detection step (S500) derives the power by summing the square of the real part and the square of the imaginary part.

[0090] Specifically, the correlator described above in FIG. 1 may include a delay unit (Delay M), a conjugate unit (Conj()), and a multiplier to process an input signal and output a final sliding accumulation value, and may be configured in conjunction with a subsequent buffer and adder according to the embodiment.

[0092] First, the input signal (r[n]) that has passed through the gate enters the correlator. Here, n represents the sample index. The input signal is branched and transmitted via the first path and the second path.

[0093] The first path is a path that generates a delayed signal. The input signal is fed into a delay unit and delayed by a preset sample length (M). The said M corresponds to the total repeating symbol length (CP length + OFDM symbol length). Therefore, the signal passing through the delay unit becomes r[nM], which is the signal M samples prior to the current time point n. Subsequently, this delayed signal is fed into the conjugate converter. The conjugate converter inverts the sign of the imaginary part of the input complex signal and outputs a conjugate complex signal. This output signal becomes the conjugate of the delayed signal.

[0095] The second path is a path in which the input signal is transmitted directly to the other input of the multiplier without delay or conjugate conversion. That signal becomes the current signal.

[0096] The above multiplier multiplies the conjugate of the delayed signal received through the first path with the current signal received through the second path at every sample time point. The result of this multiplication operation becomes the instantaneous correlation value at that time point.

[0097] Referring to the numerical example in Fig. 4, if the input signal at the current time point (n) is 3+4j and the signal at the time point M samples prior is 5+2j, the conjugate value of the delayed signal becomes 5-2j. Therefore, the multiplier performs a complex operation on the two signals and outputs a correlation value of 23+14j.

[0099] Meanwhile, although not illustrated in FIG. 4, as an embodiment, a series of correlation values ​​output from a multiplier for each sample are input into an accumulation block composed of a buffer and an adder. The accumulation block calculates a sliding accumulation value by calculating a moving sum of a predetermined window length.

[0100] In this case, the window length used for summation is not a fixed value but a variable value. As previously explained, the window length is determined based on the length of the normal interval determined by the completion time of the AGC operation. The buffer temporarily stores a number of recent correlation values ​​corresponding to this variable window length. At each time point, the summer adds up all the correlation values ​​corresponding to the window length stored in the buffer to output the final sliding cumulative value.

[0102] The technical significance of the above-described configuration is as follows. Assuming that the current time point n is located in the second OFDM symbol interval, the delay signal r[nM] corresponds to the signal in the first OFDM symbol interval exactly M samples earlier. Since the first symbol and the second symbol have the same waveform in the signal structure of the present invention, r[n]=r[nM] holds true in an ideal environment free from noise and frequency offset.

[0103] In this case, the output of the multiplier is the product of the same complex number and its conjugate complex number (A x A * =|A| 2...and a positive real value corresponding to the square of the signal magnitude (power) is derived. In a real environment, a complex value containing a phase rotation component is output due to the frequency offset, but at the point where the correlation between the two signals is maximized (synchronization point), the summer accumulates these correlation values ​​by the window length, thereby outputting a sliding accumulated value in the form of a peak with very large energy.

[0105] FIG. 5 schematically illustrates the process of performing the cumulative value calculation step (S400) according to one embodiment of the present invention.

[0107] As illustrated in FIG. 5, a synchronization signal detection method performed at a receiving device of a 5G-NR sidelink wireless communication system includes a cumulative value calculation step (S400) of calculating a sliding cumulative value in the form of a complex number by moving the generated correlation value by a predetermined window length and summing them.

[0109] The cumulative value calculation unit of the present invention performs calculations on a series of correlation value data (X) output from the correlation value generation unit by sequentially moving a window having a preset window length along the time axis.

[0110] Specifically, the top of FIG. 5 shows a state in which a window is set based on a specific time point (t-3) and includes correlation values ​​(X(t-5), X(t-4), X(t-3)) contained within the window. The subsequent middle and bottom sections illustrate the process in which the window moves one sample to the right as time progresses, thereby including correlation values ​​of the next time points (t-2, t-1) within the window.

[0111] In this process, the cumulative value calculation unit calculates the sliding cumulative value by summing all correlation values ​​existing within the window at each sample time point. Expressed as a formula, the sliding cumulative value (S(n)) at a specific time point n can be expressed as [Equation 1] below.

[0113] [Mathematical Formula 1]

[0114]

[0115] Preferably, C is the input correlation value and K is the window length.

[0117] By applying this sliding accumulation method, randomly occurring noise components tend to cancel each other out during the summation process, while highly correlated signal components reinforce each other and accumulate. Consequently, the present invention can secure a higher signal-to-noise ratio (SNR) than when using a single sample, thereby enabling clearer and more reliable synchronization signal detection.

[0119] FIG. 6 schematically illustrates the process of performing a synchronization detection procedure according to one embodiment of the present invention.

[0121] As illustrated in FIG. 6, the sliding cumulative value is calculated as complex data including a real part and an imaginary part, and the synchronization detection step (S500) derives the power by summing the square of the real part and the square of the imaginary part, derives an index of the point in time when the power has a maximum value, and determines the corresponding point in time as the symbol timing.

[0123] Referring to Fig. 6, the temporal relationship between the signal after the completion of the AGC aligned for the synchronization detection process and the M-delayed signal delayed by a predetermined number of samples is illustrated. Additionally, the trend of change in the Power Output calculated as a result of the correlation operation between these two signals is shown at the bottom.

[0124] In the present invention, the delay value M is set as the sum of the data length (N) of the first OFDM symbol and the CP length (C) (M=N+C). Therefore, the M-delay signal is delayed by exactly M compared to the currently input signal.

[0125] As the sliding window moves, the overlap interval between the two signals changes. In particular, since the first OFDM symbol is a copy of the second OFDM symbol due to the structure of the received signal, there exists a point in time where the second OFDM symbol interval of the current signal and the first OFDM symbol interval of the delayed signal coincide on the time axis.

[0127] The synchronization detection unit calculates power by accumulating the correlation values ​​of these two signals. Looking at the graph in Fig. 6, the power value increases as the identical waveform sections (Symbol #0 and Symbol #1) of the two signals begin to overlap, and it is desirable for the power to reach a maximum value (max) at the point where the two sections perfectly match, and then draws a triangular envelope in which the power value decreases again as the overlapping sections decrease.

[0128] In other words, the index of the peak where the power is maximum corresponds exactly to the symbol boundary of the received signal. By detecting this maximum power point, the synchronization detector determines the symbol timing, which indicates the start position of the frame.

[0130] In particular, the clarity of the maximum power point according to the present invention is a technical feature of the present invention. Conventional methods using only short CPs have short correlation operation intervals, making it easy for peaks to be distorted or for false positives to occur in noisy environments. However, as shown in FIG. 6, the present invention accumulates energy over a long interval (K=MA) that combines the effective symbol length (N) and the CP length (C).

[0131] Through such a long integration interval, signal components are strongly reinforced and noise components are effectively suppressed, resulting in the peak of the derived power output being significantly higher and sharper compared to the surrounding noise level. Consequently, this provides the technical effect of accurately detecting symbol timing without error, even in low SNR environments.

[0133] FIG. 7 schematically illustrates the process of calculating a frequency offset according to symbol timing in accordance with an embodiment of the present invention. In addition, FIG. 8 exemplarily illustrates a preset SCS in 5G-NR sidelink wireless communication in accordance with an embodiment of the present invention.

[0135] As illustrated in FIG. 7, the synchronization detection step (S500) extracts the phase value of the sliding accumulated value at the point where the power is maximum, and calculates the frequency offset according to the following mathematical formula using the phase value.

[0137] Referring to Fig. 7, the synchronization detection unit estimates the Carrier Frequency Offset (CFO) by utilizing the information of the symbol timing time determined in Fig. 6.

[0138] Generally, when a frequency offset occurs due to oscillator mismatch between a transmitter and a receiver or the Doppler effect, the received signal exhibits a phenomenon in which the phase rotates over time. The sliding cumulative value, which is the result of the delayed cross-correlation operation performed in the present invention, takes the form of a complex number, and the phase component of this complex number contains frequency offset information accumulated during the delay time (M samples).

[0140] Specifically, the synchronization detection unit extracts the sliding cumulative value at the point where the power is maximum, that is, the point where the signal component is most strongly synchronized. It then calculates the phase angle of the corresponding complex number. Since the point where the power is maximum is the point where the influence of noise is least and the signal component is strongest, it is desirable that the phase value extracted at this time include the most reliable offset information.

[0141] To convert the calculated phase value into a frequency offset (in Hz units), the present invention uses the following [Equation 2].

[0143] [Mathematical Formula 2]

[0144]

[0145] Preferably, Phase is the phase of the sliding cumulative value at the power maximum point (more preferably in radians), N is the data length of the first OFDM symbol, M is the sample length (N + CP length), and SCS is a preset subcarrier interval.

[0147] Meanwhile, the above SCS (Sub Carrier Spacing) value is not a fixed constant, but is determined according to the flexible numerology of the 5G-NR standard.

[0149] Referring to Fig. 8, the 5G-NR system supports different SCSs depending on the frequency band. For example, in FR1 (band below 6 GHz), intervals such as 15 kHz, 30 kHz, and 60 kHz are used, and in FR2 (band above 24 GHz), wider intervals such as 60 kHz, 120 kHz, and 240 kHz are used.

[0150] The receiving device of the present invention can calculate an accurate frequency offset correction value across various operating modes (FR1 or FR2) of 5G-NR by substituting an appropriate SCS value into [Equation 2] based on the setting information of the Bandwidth Part (BWP) currently communicating.

[0152] Consequently, the present invention has an efficient structure that simultaneously achieves frequency synchronization using only a simple formula by reusing the optimal correlation value obtained during the symbol timing detection process, without the need to add a separate complex frequency estimation algorithm.

[0154] FIG. 9 schematically illustrates a preset threshold criterion and a correction coefficient applied to power according to one embodiment of the present invention.

[0156] As illustrated in FIG. 9, the synchronization detection step (S500) does not detect symbol timing and frequency offset by treating the corresponding received signal as noise when the maximum value of the power is less than a preset threshold standard, and the synchronization detection step (S500) further includes: a correction coefficient calculation step that calculates a correction coefficient based on the ratio between the window length and a preset length standard; a correction power value calculation step that calculates a correction power value by multiplying the correction coefficient by the power; and a symbol timing detection step that detects the symbol timing based on a corresponding index when the maximum value of the correction power value is greater than or equal to the threshold standard.

[0158] In the present invention, the window length is defined as the value obtained by subtracting the AGC transient interval (A) from the sample length (M). In a typical wireless channel environment, particularly when the channel environment is poor, such as when the transmission distance is long or in a shadow area, a fading phenomenon may occur in which the strength of the received signal is weak or fluctuates rapidly.

[0159] In such an environment, if the AGC operation takes longer than expected depending on the receiving environment (i.e., if the A interval becomes longer), the opening time of the gate that passes the valid signal is delayed. This consequently causes a reduction in the window length for accumulating correlation values.

[0160] Even if the level of a unit sample is corrected through AGC, the sliding cumulative value is the result of summing the correlation values ​​within the window; therefore, as the window length becomes shorter, the number of samples summed decreases, and consequently, the maximum value of the calculated power also inevitably decreases in proportion. In this case, as illustrated in FIG. 9 (a), even though the actual received signal quality (SNR) is good, a problem may arise where the signal cannot be detected because the power peak does not reach the preset threshold criterion simply because the cumulative interval is short.

[0162] To this end, as illustrated in FIG. 9(b), the synchronization detection unit of the present invention performs a process of correcting and re-determining the power value according to specific conditions.

[0163] Specifically, the synchronization detection unit calculates a correction factor based on the ratio between the currently set window length and a preset length standard or a signal quality indicator. The table shown in FIG. 9(b) represents an example of a mapping table for correction factors based on this ratio. For example, if the calculated ratio is '0.5', a correction factor of '1.1' is applied to the power, and if the ratio decreases to '0.1', a higher weight of '1.5' is applied to the power to artificially boost the power value.

[0165] If the power value corrected through this process exceeds the threshold, the synchronization detection unit determines it as a valid synchronization signal. In other words, the present invention mathematically compensates for the loss of integral gain caused by the variability of the AGC operation time, thereby enabling the maintenance of constant detection performance under any AGC situation.

[0167] In one embodiment of the present invention, unlike the conventional method using a short CP (Cyclic Prefix) interval, correlation operations are performed by utilizing a long repetition interval corresponding to the entire length of the OFDM symbol, thereby securing a high correlation processing gain to maximize the correlation signal-to-noise ratio (SNR), and thereby enabling robust synchronization detection performance even in poor channel environments where severe noise and fading exist.

[0168] In one embodiment of the present invention, by selectively passing only the signal after the point in time when the AGC operation is completed and the received signal is stabilized, it is possible to fundamentally prevent the problem of signal distortion and noise occurring in the initial transient response period of AGC being introduced into the correlation operation and lowering the accuracy of synchronization detection.

[0169] In one embodiment of the present invention, by performing an adaptive control method that actively varies the window length of the correlator according to the time required for AGC stabilization, it is possible to achieve the effect of maintaining stable and robust synchronization acquisition performance by always using only the optimal effective signal interval even in various channel environments where the power level of the received signal changes rapidly.

[0170] In one embodiment of the present invention, by preventing unnecessary computational operations of the correlator during an invalid signal interval (AGC instability interval), the digital signal processing load of the receiving device can be reduced and the overall power consumption can be efficiently reduced.

[0172] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims below are also within the scope of the claims.

Claims

Claim 1 A synchronization signal detection method performed at a receiving device of a 5G-NR sidelink wireless communication system, comprising: a signal receiving step of receiving a receiving signal having a structure in which a second OFDM symbol is repeatedly arranged to have the same waveform as a first OFDM symbol to perform automatic gain control (AGC); a gate control step of controlling a gate to perform an automatic gain control (AGC) operation on the receiving signal, block a transient section in which the gain changes due to the automatic gain control operation, and allow only a stabilized signal to pass after a completion signal indicating that the automatic gain control operation has been completed is generated; a correlation value generation step of generating a correlation value by multiplying the complex conjugate of a delayed signal delayed by a predetermined sample length and the current signal that is not delayed for the signal that has passed through the gate; and a cumulative value calculation step of calculating a sliding cumulative value in the form of a complex number by shifting the generated correlation value by a predetermined window length and summing them. A synchronization detection method comprising: a synchronization detection step for detecting symbol timing and frequency offset for synchronization based on a point where power corresponding to the magnitude of the sliding accumulated value is maximum; wherein the window length is variably determined by subtracting the length of the interval required from the start of the automatic gain control operation, which is the length of the transient interval, to the point where the completion signal is generated and the gate is opened from the sample length; and wherein the synchronization detection step calculates a correction coefficient based on the ratio between the determined window length and a preset length reference, calculates a corrected power value by multiplying the correction coefficient by the power, and detects the symbol timing based on a corresponding index when the maximum value of the corrected power value is greater than or equal to a preset threshold reference. Claim 2 A synchronization signal detection method according to claim 1, wherein the received signal is composed of a time slot including a PSCCH (Physical Sidelink Control Channel) and a PSSCH (Physical Sidelink Shared Channel) of a 5G-NR sidelink system, wherein the first OFDM symbol is positioned at the very beginning of the time slot to serve as a preamble for an AGC operation, and the second OFDM symbol is placed consecutively immediately after the first OFDM symbol. Claim 3 delete Claim 4 A synchronization signal detection method according to claim 1, wherein the sample length is set to the sum of the length of the first OFDM symbol and the length of a CP (Cyclic Prefix) formed as a pair with the corresponding OFDM symbol, and the correlation value generation step performs delayed auto-correlation between the first OFDM symbol and the second OFDM symbol. Claim 5 A synchronization signal detection method according to claim 1, wherein the sliding cumulative value is calculated as complex number data including a real part and an imaginary part, and the synchronization detection step derives the power by summing the square of the real part and the square of the imaginary part, derives an index of the point in time when the power has a maximum value, and determines the corresponding point in time as the symbol timing. Claim 6 A synchronization signal detection method according to claim 1, wherein the synchronization detection step extracts the phase value of the sliding accumulated value at the point where the power is maximum, and calculates the frequency offset according to the following mathematical formula using the phase value. (Here, Phase is the phase value at the power maximum point, N is the length of the first OFDM symbol, M is the sample length, and SCS is the preset subcarrier interval) Claim 7 A receiving device of a 5G-NR sidelink wireless communication system performing a synchronization signal detection method, comprising: a signal receiving unit that receives a receiving signal having a structure in which a second OFDM symbol is repeatedly arranged to have the same waveform as a first OFDM symbol to perform automatic gain control (AGC); a gate control unit that controls a gate to perform an automatic gain control (AGC) operation on the receiving signal, block a transient section in which the gain changes due to the automatic gain control operation, and allow only a stabilized signal to pass after a completion signal indicating that the automatic gain control operation has been completed is generated; a correlation value generating unit that generates a correlation value by multiplying the complex conjugate of a delayed signal delayed by a predetermined sample length and the current signal that is not delayed for the signal that has passed through the gate; and an accumulation value calculating unit that calculates a sliding accumulation value in the form of a complex number by shifting the generated correlation value by a predetermined window length and summing them. A receiving device of a wireless communication system comprising: a synchronization detection unit that detects symbol timing and frequency offset for synchronization based on a point where power corresponding to the magnitude of the sliding accumulated value is maximum; wherein the window length is variably determined by subtracting the length of the interval required from the start of the automatic gain control operation, which is the length of the transient interval, to the point where the completion signal is generated and the gate is opened from the sample length; wherein the synchronization detection unit calculates a correction coefficient based on the ratio between the determined window length and a preset length reference, calculates a corrected power value by multiplying the correction coefficient by the power, and detects the symbol timing based on a corresponding index when the maximum value of the corrected power value is greater than or equal to a preset threshold reference.

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