Continuous approximate analog-to-digital converting device and driving method of the same

Abstract

The present invention relates to a successive approximation analog-to-digital converting device for reducing switching energy. A successive approximation analog-to-digital converting device according to one embodiment of the present invention may include an SH switch that samples an input analog signal, a CDAC that converts a digital input into an analog voltage to provide a comparison voltage that is compared with the sampled analog signal, a comparator that transmits a result value (Dcomp) obtained by comparing an output value (VTOP) of the CDAC with a comparison voltage (0v) to a control unit, and a control unit that controls the switching of a CAD converter to determine the next bit from the result value.

Description

Technology Field

[0001] The present invention relates to an SDBW for reducing the switching energy of a SAR ADC and a driving method thereof. Background Technology

[0002] The Analog-to-Digital Converter (ADC) serves as a critical interface for converting analog signals measured by sensors into a digital format for processing. As IoT technology advances and sensors are frequently used, energy efficiency and battery life have emerged as critical issues for IoT equipment, making low power consumption a priority when designing sensors for such devices. Particularly for small IoT devices, there is a demand for ADCs that satisfy both compact size and energy efficiency.

[0003] To address this, various types of ADCs are being devised, such as Flash ADCs, Pipelined ADCs, and Successive-Approximation ADCs (SAR ADCs). While Flash ADCs offer the fastest conversion speeds, they consume a lot of power and do not offer significant advantages in terms of area.

[0004] Pipelined ADCs have the advantage of being able to achieve high resolution along with decent conversion speed, although their conversion speed is slower than that of Flash. However, they have the disadvantage that the design burden is greater than that of other ADCs due to gain error or mismatch between the sub-ADCs that make up the pipelined structure. Prior art literature

[0005] Korean Patent Publication No. 10-2142083 (Registered July 31, 2020) The problem to be solved

[0006] The present invention aims to provide a successive approximation analog-to-digital converting device and a driving method thereof that can reduce the energy required for switching by eliminating unnecessary switching events in a capacitive CDAC. means of solving the problem

[0007] A successive approximation analog-to-digital converting device for reducing switching energy according to an embodiment of the present invention for solving the above technical problem may include an SH switch for sampling an input analog signal, a CDAC that converts a digital input into an analog voltage and provides a comparison voltage to be compared with the sampled analog signal, a comparator that transmits a result value (Dcomp) obtained by comparing the output value (VTOP) of the CDAC with the sampled analog signal to a control unit, and a control unit that controls the switching of the CDAC for determining the next bit from the result value.

[0008] In addition, the CDAC is composed of sub-bit capacitances in which the capacitance of all bits, including the MSB capacitance, is separated into binary weights, and the sub-bit capacitances may be individually switchable.

[0009] In addition, the CDAC can connect a capacitance corresponding to the next bit capacitance to a reference voltage and maintain the switched capacitance for determining the next bit.

[0010] In addition, the CDAC can apply switching only the sub-bit capacitance required for the next bit determination to all bit determinations until the LSB is determined.

[0011] In addition, the above CDAC may have the same binary weight for the total capacitance of the terminal capacitor and the capacitor group.

[0012] A driving method for a successive approximation analog-to-digital converting device for reducing switching energy according to another embodiment of the present invention for solving the above technical problem comprises: (a) a step of sampling an analog signal input by an SH switch; (b) a step of providing a comparison voltage to be compared with the sampled analog signal by converting a comparison voltage to an analog voltage received by a CDAC as a digital input; and (c) an output value (V) of the CDAC TOP The method may include the step of transmitting a result value obtained by comparing ) and a sampled analog signal to a control unit, and (d) the control unit controlling the switching of the CDAC for determining the next bit from the result value. Effects of the invention

[0013] According to one embodiment of the present invention described above, a successive approximation analog-to-digital converting device and a driving method thereof can be provided, which can reduce the energy required for switching by eliminating unnecessary switching events in a capacitive CDAC. Brief explanation of the drawing

[0014] Figure 1 is a diagram illustrating the circuit structure of a conventional successive approximation analog-to-digital converter. FIGS. 2 and FIGS. 3 illustrate an attempt to reduce switching energy in a conventional successive approximation analog-to-digital converter. FIG. 4 is a diagram illustrating the configuration of a continuous approximation analog-to-digital converting device according to one embodiment of the present invention. FIG. 5 is a diagram comparing the mechanism of a continuous approximation analog-to-digital converting device according to one embodiment of the present invention with that of a conventional injection pulse timing corrector. FIG. 6 is a drawing illustrating the overall architecture of a successive approximation analog-to-digital converting device according to one embodiment of the present invention. Specific details for implementing the invention

[0015] The objectives and effects of the present invention, and the technical configurations for achieving them, will become clear by referring to the embodiments described in detail below in conjunction with the accompanying drawings. In describing the present invention, if it is determined that a detailed description of known functions or configurations may unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0016] However, this is not intended to limit the invention to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0017] Furthermore, the terms described below are defined considering their functions in the present invention, and these may vary depending on the intentions or practices of the user or operator.

[0018] However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Therefore, such definition should be based on the content throughout this specification.

[0019] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0020] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0021] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. In order to facilitate an overall understanding of the present invention, the same reference numerals are used for identical components in the drawings, and redundant descriptions of identical components are omitted.

[0022] Figure 1 is a diagram illustrating the circuit structure of a conventional successive approximation analog-to-digital converter.

[0023] A successive-approximation analog-to-digital converter (SAR ADC) is a converter that converts an analog signal into a digital signal through a binary search. Basically, an ADC includes a sample-and-hold switch (S / H), a capacitive digital-to-analog converter (CDAC), a comparator, and control logic. Figure 1 shows the structure of a basic SAR ADC and the switching process of the CDAC for determining the most significant bit (MSB).

[0024] Referring to Fig. 1, an analog signal is sampled through S / H and V sampis generated. When sampling ends, C corresponding to the MSB capacitor of the CDAC N-1 ul V REF Connect to V REF Generates / 2, and V is the top plate voltage of the capacitor. TOP ul V samp - V REF It can be made to / 2. In this case, the capacitor is V TOP Compare with the reference voltage of 0V and the result D comp It passes to the control logic. The control logic is D comp The CADC can be switched to determine the next bit by reflecting the value of. When the bit-by-bit conversion process proceeds to the least significant bit (LSB), the digital value corresponding to the sampled analog signal is D out <n-1:0>It can be output as.

[0025] FIGS. 2 and FIGS. 3 illustrate an attempt to reduce switching energy in a conventional successive approximation analog-to-digital converter.

[0026] In conventional SAR ADCs, the primary factor contributing to power consumption is the power loss caused by switching in the CDAC. SAR ADCs based on binary search repeatedly charge and discharge the capacitors constituting the CDAC during each bit determination process. As the binary search proceeds from the most significant bit to the least significant bit, numerous switching operations occur, leading to high power consumption.

[0027] In SAR ADCs, since reducing power consumption due to such switching can significantly reduce the power consumed by the SAR ADC, there have been various attempts to reduce the power used for switching, i.e., switching energy.

[0028] The switching energy consumed by a capacitor is proportional to the value of the capacitor and proportional to the square of the switching voltage magnitude. For example, referring to Fig. 2, an attenuation capacitor C in the CDAC att By adding 2 compared to the total capacitor value of a typical CDAC M There was an attempt to reduce it by a factor. As a result, the switching energy decreased, but C att It is difficult to accurately manufacture the capacitor value, and C, the parasitic capacitance component par Due to this, there is a disadvantage of being non-linear.

[0029] Figure 3 is V REF V with a value of / 2 cm This indicates an attempt to add a reference voltage called. In conventional CDACs, 0V and V REF Since switching occurs between them, the switching energy is V REF 2 It becomes proportional to V cm Based switching is V cm Based on 0V and V REF As it switches to , the switching energy is (V REF / 2) 2 It becomes proportional to. However, V cm In the case of base switching, the number of switches increases compared to the basic structure, leading to increased circuit complexity and V's performance of the SAR ADC cm There is still a disadvantage in that it is sensitive to errors occurring during the voltage generation process.

[0030] FIG. 4 is a diagram illustrating the configuration of a continuous approximation analog-to-digital converting device according to one embodiment of the present invention.

[0031] Referring to FIG. 4, the successive approximation analog-to-digital converting device (100) may include an SH switch (110), a CDAC (120), a comparator (130), and a control unit (140).

[0032] The SH switch (110) can sample the input analog signal. The CDAC (120) can convert a comparison voltage to be compared with the sampled analog signal into an analog voltage through a digital input signal. Here, the CDAC (120) may be a Subdivided Binary Weighted CDAC. Additionally, the CDAC (120) may include sub-bit capacitances in which all bit capacitances, including the MSB capacitance, are separated into binary weights. Additionally, the sub-bit capacitances have the characteristic of being individually switchable.

[0033] The CDAC (120) can connect a capacitor corresponding to the next bit capacitance to a comparison voltage. The CDAC (120) can maintain the switched capacitor for determining the next bit.

[0034] Additionally, the CDAC (120) can apply switching only the sub-bit capacitance required for the next bit determination to all bit determinations until the LSB is determined.

[0035] The comparator (130) compares the output value (VTOP) of the CDAC with the reference voltage (0v) and the result value (D comp ) can be transmitted to the control unit (140). The control unit (140) can control the switching of the CDAC for determining the next bit from the result value.

[0036] FIG. 5 is a diagram comparing the switching energy of a continuous approximation analog-to-digital converting device according to one embodiment of the present invention and a conventional switching device.

[0037] Figure 5 illustrates the method of operation of the CDAC in a conventional ADC and the switching operation of the SDBW CDAC used in the proposed ADC using a 4-bit example, and compares the energy used during each switching operation.

[0038] FIG. 5 shows a diagram comparing the switching process and the switching energy reduction process of a successive approximation analog-to-digital converting device (100) with a conventional CDAC, using a 4-bit ADC as an example. In FIG. 5, the Conventional Switching at the bottom left represents a conventional CDAC, and the Proposed Switching at the bottom right represents a successive approximation analog-to-digital converting device (100) having subdivided binary weights (SDBW). That is, the CDAC (120) may include a subdivided binary weight capacitive CDAC (SDBW CDAC).

[0039] The switching process of the CDAC used in a conventional SAR ADC is as follows. To determine the MSB, the 8C capacitor corresponding to the MSB is V REF It is connected to and the comparator performs the comparison. Afterwards, if the comparator result is 0 (logic low), the 8C corresponding to the MSB capacitance is connected back to 0V, and the 4C corresponding to the next bit capacitance is connected to V REF Connect to.

[0040] On the other hand, the CDAC (120) includes a sub-bit capacitance in which the MSB capacitance of the capacitive CDAC is further separated into binary weights. Therefore, instead of connecting all 8C corresponding to the MSB capacitance to 0V, only 4C corresponding to the next bit capacitance is connected to 0V.

[0041] In addition, CDAC uses V for the next bit determination. REF The 4C that was switched can be maintained at 0V. As such, the successive approximation analog-to-digital converting device (100) allows all capacitances corresponding to each bit to be subdivided into binary weights once more, so that only the capacitance necessary for determining the next bit can be switched. This switching process is applied to all bit determinations until the LSB is determined, thereby reducing energy caused by unnecessary switching that occurs when the result of the comparator is 0. This energy reduction can be confirmed through the top graph of FIG. 5.

[0042] FIG. 6 is a drawing illustrating the overall architecture of a successive approximation analog-to-digital converting device according to one embodiment of the present invention.

[0043] Referring to FIG. 6, the SH switch (110) samples the input analog signal and retains it. Subsequently, the CDAC (120) can be switched to perform a binary search while storing the sampled analog signal. The comparator (130) compares the voltages provided by the two SDBW CDACs and D comp It can be derived. CDAC(120) is D comp The SDBW CDAC can be switched to determine the next bit according to the result input to the control logic (control unit (140)).

[0044] At this time, as shown in FIG. 6, the termination capacitor C P,ter (or C N,ter ) and C, a group of 10 capacitors P,k [k:0] (or C N,k It is composed of [k:0]), and the total capacitance value of each group can have binary weight values ​​identical to those of a capacitive CDAC. However, C P,k [k:0] is divided into k+1 capacitors, and C P,k Capacitor C constituting [k:0] P,k [i] (i = 0~k) is 2 i-1 With a capacitance value binary-weighted to C0, C P,k [i] is D derived from control logic (control unit (140)). P,k It can be switched individually by [i]. Consequently, subdivided switching can be achieved based on a structure that is further subdivided into binary weights in the capacitor of a conventional CDAC.

[0045] FIG. 7 is a diagram illustrating the flow of a driving method for a successive approximation analog-to-digital converting device for reducing switching energy according to an embodiment of the present invention.

[0046] The driving method of the successive approximation analog-to-digital converting device for reducing switching energy illustrated in FIG. 7 can be performed by the successive approximation analog-to-digital converting device (100) for reducing switching energy described through FIG. 1 to 6. Therefore, even if the details are omitted below, the details described for the successive approximation analog-to-digital converting device (100) for reducing switching energy through FIG. 1 to 6 can be applied in the same way to FIG. 7.

[0047] In step S110, the SH switch (110) can sample the input analog signal.

[0048] A step in which the CDAC receives a digital input and converts a comparison voltage to be compared with the sampled analog signal into an analog voltage and provides it.

[0049] In step S120, the CDAC (120) can provide a comparison voltage to be compared with the sampled analog signal by receiving a digital input and converting it into an analog voltage. Here, the CDAC (120) may include sub-bit capacitances in which all bit capacitances, including MSB capacitance, are separated into binary weights. Additionally, the sub-bit capacitances have the characteristic of being individually switchable.

[0050] The CDAC (120) can connect a capacitance corresponding to the next bit capacitance to a reference voltage. The CDAC (120) can maintain the switched capacitance for determining the next bit.

[0051] Additionally, the CDAC (120) can apply switching only the sub-bit capacitance required for the next bit determination to all bit determinations until the LSB is determined.

[0052] In step S130, the comparator (130) compares the output value (VTOP) of the CDAC with the comparison voltage (0v) and the result value (D comp ) can be transmitted to the control unit (140). In step S140, the control unit (140) can control the switching of the CDAC for determining the next bit from the result value.

[0053] A driving method for a successive approximation analog-to-digital converting device for reducing switching energy, according to one embodiment of the present invention, may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either individually or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the present invention, or may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc. The above-described hardware device may be configured to operate as one or more software modules to perform the operation of the present invention, and vice versa.

[0054] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong.

[0055] Therefore, details regarding such combinations and variations should be interpreted as being included within the scope of the present invention. Furthermore, although the above description has focused on embodiments, this is merely illustrative and does not limit the present invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. Differences related to such modifications and applications should be interpreted as being included within the scope of the present invention as defined in the appended claims. Explanation of the symbols

[0056] 100: Continuous approximation analog-to-digital converter 110: SH switch 120: CDAC 130: Comparator 140: Control unit

Claims

Claim 1 In a successive approximation analog-to-digital converting device for reducing switching energy, the device comprises: an SH switch for sampling an input analog signal; a capacitive digital-to-analog converter (CDAC) for converting a comparison voltage to be compared with the sampled analog signal into an analog voltage according to a digital input provided by a control unit; and an output value (V) of the CDAC. TOP The result of comparing ) and the reference voltage (0v) (D comp A successive approximation analog-to-digital converting device comprising: a comparator that transmits ) to a control unit; and a control unit that controls the switching of a CDAC for determining the next bit from the result value, wherein the CDAC includes sub-bit capacitances separated into binary weights, each bit capacitance including a capacitance corresponding to the MSB, and the sub-bit capacitances are individually switchable, and the CDAC applies switching only the sub-bit capacitances necessary for determining the next bit to each bit determination process until the LSB is determined. Claim 2 delete Claim 3 A successive approximation analog-to-digital converting device according to claim 1, wherein the CDAC connects a capacitance corresponding to the next bit capacitance to a reference voltage (0v) and maintains the capacitance switched for determining the next bit. Claim 4 In claim 1, the CDAC is a successive approximation analog-to-digital converting device that applies switching only the sub-bit capacitance required for the next bit determination to all bit determinations until the LSB is determined. Claim 5 A successive approximation analog-to-digital converting device according to claim 1, wherein the CDAC has a binary weight in which the total capacitance of the terminal capacitor and the capacitor group constituting the CDAC is the same. Claim 6 A method for driving a successive approximation analog-to-digital converting device for reducing switching energy, comprising: (a) a step in which an SH switch samples an input analog signal; (b) a step in which a CDAC converts and provides an analog voltage according to a digital input provided from a control unit; (c) an output value (V) of the CDAC TOP A driving method for a successive approximation analog-to-digital converting device, comprising: a step of transmitting a result value obtained by comparing ) and a reference voltage (0v) to a control unit; and (d) a step in which the control unit controls the switching of a CDAC for determining the next bit from the result value, wherein the CDAC includes sub-bit capacitances separated into binary weights, including all bit capacitances including a capacitance corresponding to the MSB, and the sub-bit capacitances are individually switchable, and the CDAC applies switching only the sub-bit capacitances required for determining the next bit to each bit determination process until the LSB is determined. Claim 7 delete Claim 8 A driving method for a successive approximation analog-to-digital converting device, wherein, in claim 6, the CDAC connects a capacitance corresponding to the next bit capacitance to a reference voltage (0v) and maintains the capacitance switched for determining the next bit. Claim 9 In claim 6, the above CDAC applies switching only the sub-bit capacitance required for the next bit determination to all bit determinations until the LSB is determined, a driving method for a successive approximation analog-to-digital converting device. Claim 10 A driving method for a successive approximation analog-to-digital converting device, wherein, in claim 6, the CDAC has a binary weight in which the total capacitance of the terminal capacitor and the capacitor group constituting the CDAC is the same.

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