Plasma treatment device and etching method

Abstract

A plasma processing device comprises a chamber, a substrate support, a gas supply unit, a first high-frequency power source, a voltage pulse source, a second high-frequency power source, and a control unit. The substrate support is disposed within the chamber and supports a substrate. When etching a substrate, the control unit is configured to supply a processing gas into the chamber from the gas supply unit and supply a first high-frequency power from the first high-frequency power source to plasmafy the processing gas within the chamber, supply a voltage pulse from the voltage pulse source to the substrate support, and control the supply of a second high-frequency power from the second high-frequency power source by superimposing it on the voltage pulse.

Description

Technology Field

[0001] The present disclosure relates to a plasma treatment apparatus and an etching method. Background Technology

[0002] Patent Document 1 below describes a first RF generator coupled to the first RF generator, configured to generate a first RF pulse signal including a plurality of pulse cycles, wherein each of the plurality of pulse cycles includes a first period, a second period, and a third period, and the first RF pulse signal has a first power level in the first period, a second power level in the second period, and a third power level in the third period, and the first period is 30 μs or less; a second RF generator coupled to the second RF generator, configured to generate a second RF pulse signal including the plurality of pulse cycles, wherein the frequency of the second RF pulse signal is lower than the frequency of the first RF pulse signal, and the second RF pulse signal has a fourth power level in the first period and a fifth power level in at least one of the second period and the third period; and the second RF generator to the second RF generator A plasma processing apparatus is disclosed having a third RF generating unit that is coupled and configured to generate a third RF pulse signal including the plurality of pulse cycles, wherein the frequency of the third RF pulse signal is lower than the frequency of the second RF pulse signal, and the third RF pulse signal has a sixth power level in the second period and a seventh power level in at least one of the first period and the third period. Prior art literature

[0003] Japanese Patent Publication No. 2022-048032 The problem to be solved

[0004] The present disclosure provides a technique for reducing residue. means of solving the problem

[0005] A plasma processing apparatus according to one embodiment of the present disclosure comprises a chamber, a substrate support, a gas supply unit, a first high-frequency power source, a voltage pulse source, a second high-frequency power source, and a control unit. The substrate support is disposed within the chamber and supports a substrate. The gas supply unit is configured to supply a processing gas within the chamber. The first high-frequency power source is configured to supply a first high-frequency power that plasmafies the processing gas within the chamber. The voltage pulse source is configured to supply a voltage pulse, which is a DC voltage pulsed, to the substrate support. The second high-frequency power source is configured to supply a second high-frequency power to the substrate support when etching the substrate. The control unit is configured to control the supply of a processing gas from the gas supply unit into the chamber, the supply of a first high-frequency power from the first high-frequency power source to plasmafy the processing gas within the chamber, the supply of a voltage pulse from the voltage pulse source to the substrate support, and the supply of a second high-frequency power from the second high-frequency power source by superimposing it on the voltage pulse. Effects of the invention

[0006] According to the present disclosure, residue can be reduced. Brief explanation of the drawing

[0007] Figure 1 is a diagram illustrating an example of the configuration of an inductively coupled plasma processing device. FIG. 2a is a drawing showing an example of etching of a substrate (W) according to a first embodiment. FIG. 2b is a drawing showing an example of etching of a substrate (W) according to a first embodiment. FIG. 3a is a drawing showing an example of etching of a substrate (W) according to a first embodiment. FIG. 3b is a drawing showing an example of etching of a substrate (W) according to a first embodiment. FIG. 4a is a diagram showing an example of a change in the potential of a substrate (W) in the etching method of the first reference example. FIG. 4b is a schematic diagram showing the movement of ions and radicals in the plasma in the etching method of the first reference example. FIG. 4c is a diagram showing an example of the energy distribution of ions in the etching method of the first reference example. FIG. 5a is a diagram showing an example of a change in the potential of a substrate (W) in the etching method of the second reference example. FIG. 5b is a schematic diagram showing the movement of ions and radicals in the plasma in the etching method of the second reference example. FIG. 5c is a diagram showing an example of the energy distribution of ions in the etching method of the second reference example. FIG. 6 is a drawing showing an example of residue remaining on an etched substrate according to the first embodiment. FIG. 7a is a diagram showing an example of a change in the potential of a substrate (W) in an etching method of the first embodiment. FIG. 7b is a diagram showing an example of the energy distribution of ions in the etching method of the first embodiment. FIG. 8a is a diagram illustrating the processing conditions of the etching method of the first reference example during the first verification. FIG. 8b is a diagram illustrating the processing conditions of the etching method of the first embodiment during the first verification. FIG. 9a is a diagram illustrating the processing conditions of the etching method of the first embodiment during the second verification. FIG. 9b is a diagram illustrating the processing conditions of the etching method of the first embodiment during the second verification. FIG. 10a is a diagram illustrating the processing conditions of the etching method of the first embodiment during the third verification. FIG. 10b is a diagram illustrating the processing conditions of the etching method of the first embodiment during the third verification. FIG. 11 is a flowchart showing an example of the processing sequence of an etching process according to a first embodiment. FIG. 12a is a diagram showing an example of a change in the potential of a substrate (W) in an etching method of a second embodiment. FIG. 12b is a diagram showing an example of the energy distribution of ions in the etching method of the second embodiment. FIG. 13a is a diagram illustrating the change in potential of a substrate (W) when the amplitude of the bias DC signal is changed. Figure 13b is a diagram illustrating the change in the energy distribution of ions when the amplitude of the bias DC signal is changed. FIG. 14a is a diagram illustrating the change in potential of the substrate (W) when the on period of the bias DC signal is changed. Figure 14b is a diagram illustrating the change in the energy distribution of ions when the on-period of the bias DC signal is changed. FIG. 15a is a diagram illustrating the change in potential of the substrate (W) when the amplitude of the bias RF signal is changed. Figure 15b is a diagram illustrating the change in the energy distribution of ions when the amplitude of the bias RF signal is changed. FIG. 16a is a diagram illustrating the change in potential of the substrate (W) when the off period of the bias DC signal is changed. Figure 16b is a diagram illustrating the change in the energy distribution of ions when the off period of the bias DC signal is changed. FIG. 17 is a diagram illustrating the change in potential of a substrate (W) when the overlap period of the bias RF signal is changed. FIG. 18 is a diagram illustrating the change in potential of a substrate (W) when the overlap period of the bias RF signal is changed. Specific details for implementing the invention

[0008] Hereinafter, embodiments of the plasma treatment apparatus and etching method disclosed herein will be described in detail with reference to the drawings. Furthermore, the plasma treatment apparatus and etching method disclosed herein are not limited by these embodiments.

[0009] A plasma processing device loads a substrate onto a substrate support installed inside a chamber and generates plasma inside the chamber to perform plasma processing such as etching. In the manufacture of semiconductor devices, high vertical processing performance is required. Therefore, in plasma processing devices, an etching method is known in which a DC voltage of a pulsed rectangular wave is applied to a substrate support to etch the substrate. When etching the substrate, by applying a DC voltage of a rectangular wave to the substrate support, the verticality of the ions can be improved, thereby enabling high vertical processing performance.

[0010] However, by improving the verticality of the ions, residue may remain in the corners of the etched bottom. Therefore, a technology to reduce residue is expected.

[0011] [First embodiment]

[0012] [Device Configuration]

[0013] An example of a plasma processing apparatus of the present disclosure is described. In the embodiments described below, the plasma processing apparatus of the present disclosure is described as an example of a plasma processing system configured as a system.

[0014] Below, an example of the configuration of a plasma processing system is described. Figure 1 is a diagram illustrating an example of the configuration of an inductively coupled plasma processing device.

[0015] A plasma processing system includes an inductively coupled plasma processing device (1) and a control unit (2). The inductively coupled plasma processing device (1) includes a plasma processing chamber (10), a gas supply unit (20), a power supply (30), and an exhaust system (40). The plasma processing chamber (10) corresponds to the chamber of the present disclosure. The plasma processing chamber (10) includes a dielectric window. Additionally, the plasma processing device (1) includes a substrate support (11), a gas introduction unit, and an antenna (14). The substrate support (11) is positioned within the plasma processing chamber (10). The antenna (14) is positioned above or above the plasma processing chamber (10) (i.e. above or above the dielectric window (101)). The plasma processing chamber (10) has a plasma processing space (10s) defined by the dielectric window (101), the side wall (102) of the plasma processing chamber (10), and the substrate support (11). The plasma treatment chamber (10) has at least one gas supply port for supplying at least one treatment gas to the plasma treatment space (10s) and at least one gas discharge port for discharging gas from the plasma treatment space. The plasma treatment chamber (10) is grounded.

[0016] The substrate support portion (11) includes a main body portion (111) and a ring assembly (112). The main body portion (111) has a central region (111a) for supporting a substrate (W) and a ring-shaped region (111b) for supporting a ring assembly (112). A wafer is an example of a substrate (W). The ring-shaped region (111b) of the main body portion (111) surrounds the central region (111a) of the main body portion (111) when viewed in a planar view. A substrate (W) is placed on the central region (111a) of the main body portion (111), and a ring assembly (112) is placed on the ring-shaped region (111b) of the main body portion (111) to surround the substrate (W) on the central region (111a) of the main body portion (111). Accordingly, the central region (111a) is also called a substrate support surface for supporting the substrate (W), and the ring-shaped region (111b) is also called a ring support surface for supporting the ring assembly (112).

[0017] In one embodiment, the main body (111) includes a base (1110) and an electrostatic chuck (1111). The base (1110) includes a conductive member. The conductive member of the base (1110) can function as a bias electrode. The electrostatic chuck (1111) is disposed on the base (1110). The electrostatic chuck (1111) includes a ceramic member (1111a) and an electrostatic electrode (1111b) disposed within the ceramic member (1111a). The ceramic member (1111a) has a central region (111a). In one embodiment, the ceramic member (1111a) also has an annular region (111b). Additionally, another member surrounding the electrostatic chuck (1111), such as an annular electrostatic chuck or an annular insulating member, may have an annular region (111b). In this case, the ring assembly (112) may be disposed on a ring-shaped electrostatic chuck or a ring-shaped insulating member, or on both sides of the electrostatic chuck (1111) and the ring-shaped insulating member. Additionally, at least one RF / DC electrode coupled to the RF (Radio Frequency) power source (31) and / or DC (Direct Current) power source (32) described later may be disposed within the ceramic member (1111a). In this case, at least one RF / DC electrode functions as a bias electrode. Additionally, the conductive member of the base (1110) and at least one RF / DC electrode may function as a plurality of bias electrodes. Additionally, an electrostatic electrode (1111b) may function as a bias electrode. Accordingly, the substrate support (11) includes at least one bias electrode.

[0018] The ring assembly (112) includes one or more ring-shaped members. In one embodiment, the one or more ring-shaped members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive material or an insulating material, and the cover ring is formed of an insulating material.

[0019] Additionally, the substrate support (11) may include a temperature control module configured to control at least one of the electrostatic chuck (1111), ring assembly (112), and substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path (1110a), or a combination thereof. A heat transfer fluid, such as brine or gas, flows through the flow path (1110a). In one embodiment, the flow path (1110a) is formed within the base (1110), and one or more heaters are disposed within the ceramic member (1111a) of the electrostatic chuck (1111). Additionally, the substrate support (11) may include a heat transfer gas supply unit configured to supply a heat transfer gas to the gap between the back surface of the substrate (W) and the central region (111a).

[0020] A gas inlet is configured to introduce at least one processing gas from a gas supply unit (20) into a plasma processing space (10s). In one embodiment, the gas inlet includes a center gas injector (CGI) (13). The center gas injector (13) is positioned above a substrate support (11) and is attached to a central opening formed in a dielectric window (101). The center gas injector (13) has at least one gas supply port (13a), at least one gas flow path (13b), and at least one gas inlet port (13c). Processing gas supplied to the gas supply port (13a) passes through the gas flow path (13b) and is introduced into the plasma processing space (10s) from the gas inlet port (13c). Additionally, the gas inlet may include one or more side gas injectors (SGI) attached to one or more openings formed in the side wall (102) in addition to or instead of the central gas injector (13).

[0021] The gas supply unit (20) may include at least one gas source (21) and at least one flow controller (22). In one embodiment, the gas supply unit (20) is configured to supply at least one processing gas from each corresponding gas source (21) through each corresponding flow controller (22) to the gas introduction unit. Each flow controller (22) may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit (20) may include one or more flow modulation devices that modulate or pulse the flow rate of at least one processing gas.

[0022] The power supply (30) includes an RF power supply (31) coupled to the plasma processing chamber (10) through at least one impedance matching circuit. The RF power supply (31) is configured to supply at least one RF signal (RF power) to at least one bias electrode and antenna (14). By this, plasma is formed from at least one processing gas supplied to the plasma processing space (10s). Accordingly, the RF power supply (31) can function as at least part of a plasma generation unit configured to generate plasma from one or more processing gases in the plasma processing chamber (10). Additionally, by supplying a bias RF signal to at least one bias electrode, a bias potential is generated in the substrate (W), thereby attracting ions in the formed plasma to the substrate (W).

[0023] In one embodiment, the RF power supply (31) includes a first RF generating unit (31a) and a second RF generating unit (31b). The first RF generating unit (31a) is coupled to the antenna (14) and is configured to generate a source RF signal (source RF power) for plasma generation through at least one impedance matching circuit. In one embodiment, the source RF signal has a frequency within the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit (31a) may be configured to generate a plurality of source RF signals having different frequencies. One or more generated source RF signals are supplied to the antenna (14). The first RF generating unit (31a) corresponds to the first high-frequency power supply of the present disclosure. Additionally, the source RF signal corresponds to the first high-frequency power of the present disclosure.

[0024] The second RF generation unit (31b) is configured to be coupled to at least one bias electrode through at least one impedance matching circuit to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal is preferably a frequency within the range of 1 MHz to 100 MHz, and more preferably a frequency within the range of 13 MHz to 60 MHz. In one embodiment, the second RF generation unit (31b) may be configured to generate a plurality of bias RF signals having different frequencies. One or more of the generated bias RF signals are supplied to at least one bias electrode. In addition, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed. The second RF generation unit (31b) corresponds to the second high-frequency power source of the present disclosure. Additionally, the bias RF signal corresponds to the second high-frequency power of the present disclosure.

[0025] Additionally, the power supply (30) may include a DC power supply (32) coupled to the plasma processing chamber (10). The DC power supply (32) includes a bias DC generating unit (32a). In one embodiment, the bias DC generating unit (32a) is connected to at least one bias electrode and configured to generate a bias DC signal. The generated bias DC signal is applied to at least one bias electrode.

[0026] In various embodiments, the bias DC signal may be pulsed. In this case, a sequence of voltage pulses is applied to at least one bias electrode. The voltage pulses may have a pulse waveform that is rectangular, trapezoidal, triangular, or a combination thereof.

[0027] The bias DC generator (32a) is configured to supply a bias DC signal that pulses a DC voltage. For example, the bias DC generator (32a) is configured to supply a bias DC signal that pulses a negative DC voltage by periodically turning it on and off. In one embodiment, the bias DC generator (32a) is configured to be capable of applying a DC voltage of a negative value. The bias DC generator (32a) applies a voltage pulse of a predetermined frequency as a bias DC signal to the bias electrode of the base (1110) by turning the application of the DC voltage on and off at a predetermined period. The frequency of the bias DC signal is preferably within the range of 100 kHz to 1200 kHz, and more preferably within the range of 400 kHz to 800 kHz. The bias DC generator (32a) is configured to be capable of changing the duty cycle of the bias DC signal by changing the ratio of the on / off period during one cycle. The bias DC generating unit (32a) corresponds to the voltage pulse source of the present disclosure. Additionally, the bias DC signal corresponds to the voltage pulse of the present disclosure.

[0028] The antenna (14) includes one or more coils. In one embodiment, the antenna (14) may include an outer coil and an inner coil arranged coaxially. In this case, the RF power supply (31) may be connected to both the outer coil and the inner coil, or to either the outer coil or the inner coil. In the former case, the same RF generator may be connected to both the outer coil and the inner coil, or separate RF generators may be individually connected to the outer coil and the inner coil.

[0029] During plasma processing, the plasma processing device (1) supplies a source RF signal for plasma generation from the first RF generation unit (31a) to the antenna (14). Additionally, during plasma processing, the plasma processing device (1) supplies a pulsed bias DC signal from the bias DC generation unit (32a) to the lower electrode of the base (1110). Additionally, during plasma processing, the plasma processing device (1) supplies a bias RF signal superimposed on the bias DC signal from the second RF generation unit (31b).

[0030] The exhaust system (40) may be connected, for example, to a gas outlet (10e) installed at the bottom of the plasma processing chamber (10). The exhaust system (40) may include a pressure regulating valve and a vacuum pump. The pressure within the plasma processing space (10s) is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0031] The control unit (2) processes computer-executable commands to execute various processes described in the present disclosure on the plasma processing device (1). The control unit (2) may be configured to control each element of the plasma processing device (1) to execute the various processes described herein. In one embodiment, part or all of the control unit (2) may be included in the plasma processing device (1). The control unit (2) may include a processing unit (2a1), a memory unit (2a2), and a communication interface (2a3). The control unit (2) is realized, for example, by a computer (2a). The processing unit (2a1) may be configured to perform various control operations by reading a program from the memory unit (2a2) and executing the read program. This program may be stored in the memory unit (2a2) in advance, or may be acquired through a medium when necessary. The acquired program is stored in the memory unit (2a2) and is read from the memory unit (2a2) and executed by the processing unit (2a1). The medium may be various storage media readable by the computer (2a) or a communication line connected to the communication interface (2a3). The processing unit (2a1) may be a CPU (Central Processing Unit). The storage unit (2a2) may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface (2a3) may communicate with the plasma processing device (1) through a communication line such as a LAN (Local Area Network).

[0032] [Flow of Plasma Processing]

[0033] Next, the flow of performing plasma treatment, such as plasma etching, on a substrate (W) by a plasma treatment system according to an embodiment will be briefly explained. The substrate (W) is brought into the plasma treatment chamber (10) through an unillustrated receiving outlet by a conveying mechanism such as a conveying arm, and is loaded onto the central region (111a) of the substrate support (11). The exhaust system (40) exhausts the inside of the plasma treatment chamber (10) to a predetermined vacuum level.

[0034] When etching a substrate (W), the control unit (2) controls the gas supply unit (20) to supply processing gas from the gas supply unit (20) into the plasma processing chamber (10). For example, the memory unit (2a2) stores a recipe for plasma processing on the substrate. The recipe includes the type of gas and the flow rate used in the etching. For example, the control unit (2) reads the recipe from the memory unit (2a2) and supplies the gas of the type of gas registered in the recipe from the gas supply unit (20) into the plasma processing chamber (10) at the registered flow rate.

[0035] The control unit (2) controls the first RF generation unit (31a) to supply a source RF signal from the first RF generation unit (31a) to plasmaize the processing gas inside the plasma processing chamber (10). For example, the power of the source RF signal is registered in the recipe. The control unit (2) supplies the source RF signal from the first RF generation unit (31a) to the antenna (14) with the power registered in the recipe to generate magnetic force inside the plasma processing chamber (10) and plasmaize the processing gas inside the plasma processing chamber (10) to generate inductively coupled plasma.

[0036] The control unit (2) controls the bias DC generation unit (32a) to supply a bias DC signal from the bias DC generation unit (32a) to the substrate support unit (11). The control unit (2) controls the bias DC generation unit (32a) to control the duty cycle of the bias DC signal. For example, it is preferable for the control unit (2) to control the duty cycle of the bias DC signal to 10% to 80%, and more preferable to control the duty cycle to 10% to 20%. For example, the duty cycle of the bias DC signal is registered in the recipe. The control unit (2) reads the recipe from the memory unit (2a2) and supplies a bias DC signal of the duty cycle registered in the recipe from the bias DC generation unit (32a).

[0037] The control unit (2) controls the second RF generation unit (31b) to supply a bias RF signal from the second RF generation unit (31b) to the substrate support unit (11) by superimposing it on the bias DC signal. For example, the power of the bias RF signal is registered in the recipe. For example, the control unit (2) reads the recipe from the memory unit (2a2) and supplies a bias RF signal from the second RF generation unit (31b) with the power registered in the recipe.

[0038] Here, an example of etching a substrate (W) according to a first embodiment is described. FIGS. 2a, 2b, 3a, and 3b are drawings illustrating an example of etching a substrate (W) according to a first embodiment. FIG. 2a shows a planar shape of the substrate (W) before etching as viewed from the top surface. FIG. 2b shows a cross-sectional shape of the substrate (W) before etching at the dashed line (L1) in FIG. 2a. FIG. 3a shows a planar shape of the substrate (W) after etching as viewed from the top surface. FIG. 3b shows a cross-sectional shape of the substrate (W) after etching at the dashed line (L1) in FIG. 3a.

[0039] In the substrate (W) prior to etching, a base layer (50) is formed, and a pin structure (51) having a plurality of pins (51a) is formed on the base layer (50). Then, in the substrate (W) prior to etching, a gate material (52) is deposited on the pin structure (51), and a mask (53) is formed on the gate material (52). Also, since the pin structure (51) is embedded in the gate material (52), it is not shown in FIG. 2a and FIG. 2b. The base layer (50) is a stop layer that suppresses etching to the lower layer and is formed by an oxide (Ox), for example, such as a silicon oxide film. The base layer (50) may be a metal film such as SiN, an organic film, or a tungsten film. The pin structure (51) is formed, for example, by covering the surface of a silicon layer with an oxide. A plurality of pins (51a) of the pin structure (51) are formed in parallel in one direction. The gate material (52) is formed, for example, by polycrystalline silicon (polysilicon: Poly). The mask (53) is configured, for example, by having an oxide layer (53b) (Ox) stacked on a SiN layer (53a). The mask (53) is formed by providing gaps in parallel in a cross direction with respect to one direction.

[0040] FIGS. 3A and 3B show a substrate (W) in which a gate material (52) is etched until a base layer (50) is reached, using a mask (53) as a mask. An example of a pressure condition and a processing gas for etching the substrate (W) is shown below. In addition, regarding the values ​​below, 1 sccm is approximately 1.69 × 10⁻⁶ -3 paㆍm 3 / s, and 1 mTorr is approximately 0.133 Pa.

[0041] ㆍ Pressure conditions

[0042] Pressure inside the plasma treatment chamber (10): 50~100 mTorr

[0043] ㆍ Treatment gas

[0044] Cl2 gas: 100~210 sccm

[0045] HBr gas: 70~150 sccm

[0046] O2 gas: 30~60 sccm

[0047] Ar gas: 50~300 sccm

[0048] As a result of etching, as shown in FIGS. 3a and 3b, the gate material (52) has a gate portion (52a) immediately below the mask (53) remaining, and the remaining gate portion (52a) functions as a gate. In the substrate (W), each rectangular portion (55) surrounded by the mask (53) and the pin (51a) reaches up to the base layer (50).

[0049] Next, an etching method used as a reference example will be described. Additionally, differences from the etching method of the first embodiment will be explained below.

[0050] First, the etching method of the first reference example is described. Conventionally, an etching method is known in which high-frequency power is applied as a bias to a substrate support (11) to etch a substrate (W). For example, in the etching method of the first reference example, when etching the substrate (W), a source RF signal is supplied from the first RF generating unit (31a) to plasmaize the processing gas inside the plasma processing chamber (10). Then, in the etching method of the first reference example, a bias DC signal is not supplied from the bias DC generating unit (32a), and a bias RF signal is supplied from the second RF generating unit (31b) to the lower electrode of the base (1110).

[0051] FIG. 4a is a diagram showing an example of a change in the potential of a substrate (W) in the etching method of the first reference example. As a bias RF signal, which is high-frequency power, is supplied to the lower electrode of the base (1110), the potential of the substrate (W) changes in a sinusoidal shape in accordance with the fluctuation of the bias RF signal.

[0052] FIG. 4b is a schematic diagram showing the movement of ions and radicals in the plasma in the etching method of the first reference example. In FIG. 4b, the side of the object to be etched, such as a substrate (W), is shown as the etch front. Ions and radicals in the plasma are attracted to the substrate (W) by the potential of the substrate (W) and etch the substrate (W). In the etching method of the first reference example, as the potential of the substrate (W) changes in a sinusoidal shape, ions and radicals scatter, and the angle of incidence of ions and radicals incident on the substrate (W) widens. In addition, in the etching method of the first reference example, the energy distribution of ions and radicals incident on the substrate (W) widens.

[0053] FIG. 4c is a diagram showing an example of the energy distribution of ions in the etching method of the first reference example. FIG. 4c shows an example of the result of calculating the Ion Energy Distribution Function (IEDF) of the etching method of the first reference example. The horizontal axis represents the energy of the ions [eV], and the energy is higher towards the right. The vertical axis represents the number of ions, and the number of ions is greater towards the top. In addition, FIG. 4c shows the minimum ion energy required for etching the gate material (52) as a threshold value (E th It is represented as ). Threshold value (E th ) is, for example, 25[eV].

[0054] The etching method of the first reference example is such that the energy distribution of the ions is a critical value (E th Because it is above ) it is possible to etch the gate material (52), but a peak is formed on the low-energy side of the energy distribution, and the energy range in which the peak occurs is wide. The etching method of the first reference example has a spreading in the energy distribution of ions incident on the substrate (W).

[0055] Accordingly, the etching method of the first reference example has low vertical processing performance. For example, when etching of the substrate (W) shown in FIG. 2a, FIG. 2b, FIG. 3a, and FIG. 3b is performed by the etching method of the first reference example, the sidewall of the gate portion (52a) is also etched, and the roughness of the sidewall of the gate portion (52a) deteriorates.

[0056] Next, the etching method of the second reference example is described. In the manufacture of semiconductor devices, high vertical processing performance is required. Therefore, an etching method is known in which a DC voltage of a pulsed rectangular wave is applied to a substrate support (11) to etch the substrate. For example, in the etching method of the second reference example, when etching the substrate (W), a source RF signal is supplied from the first RF generating unit (31a) to plasmaize the processing gas inside the plasma processing chamber (10). Then, in the etching method of the second reference example, a bias RF signal is not supplied from the second RF generating unit (31b), but a bias DC signal, which is a pulsed DC voltage of a negative polarity from the bias DC generating unit (32a), is supplied to the lower electrode of the base (1110).

[0057] FIG. 5a is a diagram showing an example of a change in the potential of a substrate (W) in the etching method of the second reference example. As a bias DC signal, which is a pulsed negative DC voltage, is supplied to the lower electrode of the base (1110), the potential of the substrate (W) changes in a rectangular shape in accordance with the fluctuation of the bias DC signal.

[0058] FIG. 5b is a schematic diagram showing the movement of ions and radicals in the plasma in the etching method of the second reference example. In FIG. 5b, the side of the object to be etched, such as a substrate (W), is shown as the etch front. Ions and radicals in the plasma are attracted to the substrate (W) by the potential of the substrate (W) and etch the substrate (W). The etching method of the second reference example improves the verticality of ions and radicals incident on the substrate (W) by changing the potential of the substrate (W) in a rectangular shape. In addition, the etching method of the second reference example has a narrow energy distribution of ions and radicals incident on the substrate (W), and the energy peak is raised.

[0059] FIG. 5c is a diagram showing an example of the energy distribution of ions in the etching method of the second reference example. FIG. 5c is a diagram schematically showing the ion energy distribution function (IEDF) of the etching method of the second reference example. The horizontal axis represents the energy of the ions [eV], and the energy is higher towards the right. The vertical axis represents the number of ions, and the number of ions is greater towards the top. In addition, FIG. 5c shows the threshold value (E) of the ion energy required for etching the gate material (52). th It represents ).

[0060] The etching method of the second reference example produces peaks on the high-energy and low-energy sides. On the low-energy side, the energy of the ion is a critical value (E th Since it is less than ) it does not contribute to the etching of the gate material (52). On the high energy side, the peak is high and the energy range where the peak occurs is narrow. That is, in the etching method of the second reference example, the peak on the high energy side becomes an acute energy distribution. By this, the verticality of ions or radicals incident on the substrate (W) is improved.

[0061] The etching method of the second reference example can achieve high vertical processing performance because the verticality of the ions or radicals is high. For example, when etching of the substrate (W) shown in FIG. 2a, FIG. 2b, FIG. 3a, and FIG. 3b is performed by the etching method of the second reference example, the gate portion (52a) can be etched into a vertical shape while suppressing the roughness of the sidewall of the gate portion (52a).

[0062] However, in the etching method of the second reference example, as the vertical processing performance of the ions is improved, there may be cases where residue of the gate material (52) remains in the corner portions of the etched bottom portion. FIG. 6 is a drawing showing an example of residue remaining on an etched substrate (W) according to the first embodiment. FIG. 6 shows the planar shape of the substrate (W) after etching as viewed from the top surface. On the substrate (W) after etching, residue (56) remains in each rectangular portion (55).

[0063] Thus, the etching method of the first embodiment supplies a bias DC signal, which is a pulsed negative DC voltage from the bias DC generating unit (32a), to the lower electrode of the base (1110) when etching the substrate (W). In addition, the etching method of the first embodiment supplies a bias RF signal from the second RF generating unit (31b) by superimposing it on the bias DC signal.

[0064] FIG. 7a is a diagram showing an example of a change in the potential of a substrate (W) in an etching method of the first embodiment. As a bias DC signal and a bias RF signal, which are pulsed with a negative DC voltage, are superimposed and supplied to the lower electrode of the base (1110), the potential of the substrate (W) changes in a rectangular shape in accordance with the fluctuation of the bias DC signal and vibrates in accordance with the bias RF signal.

[0065] FIG. 7b is a diagram showing an example of the energy distribution of ions in the etching method of the first embodiment. FIG. 7b is a diagram schematically showing the ion energy distribution function (IEDF) of the etching method of the first embodiment. The horizontal axis represents the energy of the ions [eV], and the energy is higher towards the right. The vertical axis represents the number of ions, and the number of ions is greater towards the top. In addition, FIG. 7b shows the threshold value (E) of the ion energy required for etching the gate material (52). th It represents ).

[0066] The etching method of the first embodiment has peaks on the high-energy and low-energy sides, and the energy range in which the peaks occur is wide. The etching method of the first embodiment can obtain high vertical processing performance by having a peak on the high-energy side. In addition, the etching method of the first embodiment has a low-energy side as well as a critical value (E th ) By making the peak appear over a wide range, the angle of incidence of the ions incident on the substrate (W) can be widened, allowing the residue (56) to be efficiently removed.

[0067] Next, an example of a verification result is described in which the amount of residue (56) is verified by actually etching the substrate (W).

[0068] In the verification, the substrate (W) was etched using the etching method of the first embodiment and the etching method of the first reference example. The etching method of the first embodiment was divided into two steps, residue removal step 1 and residue removal step 2, and residue removal step 2 was performed sequentially after residue removal step 1. Regarding the source RF signal, bias RF signal, and bias DC signal of residue removal step 1 and residue removal step 2, the common conditions during verification are as follows.

[0069] (Common conditions of the etching method of the first embodiment)

[0070] Conditions for Residue Removal Step 1

[0071] Source RF signal: Frequency 27MHz, Power 300W

[0072] Bias RF signal: Frequency 13 MHz, Power 400 W

[0073] Bias DC signal: Frequency 400kHz, -500V, Duty cycle 0~80%

[0074] Conditions for Residue Removal Step 2

[0075] Source RF signal: Frequency 27 MHz, Power 500 W

[0076] Bias RF signal: Frequency 13 MHz, Power 270 W

[0077] Bias DC signal: Frequency 400kHz, -500V, Duty cycle 0~80%

[0078] The duty cycle of the bias DC signal is the ratio of the ON period to the ON period in one cycle of turning -500V on and off. The etching method of the first embodiment performs a residue removal step 2 after a residue removal step 1, and changes the duty cycle of the bias DC signal in residue removal step 1 and residue removal step 2.

[0079] First, the results of the first verification are explained. In the first verification, the substrate (W) was etched using the etching method of the first reference example and the etching method of the first embodiment, respectively, and the amount of residue (56) on the substrate (W) was compared.

[0080] In the first verification, the source RF signal and bias RF signal of the etching method of the first reference example were set as follows.

[0081] (Conditions of the etching method of the first reference example)

[0082] Source RF signal: Frequency 27 MHz, Power 500 W

[0083] Bias RF signal: Frequency 13 MHz, Power 270 W

[0084] In addition, in the first verification, the duty ratio of the bias DC signal of the residue removal step 1 and residue removal step 2 of the etching method of the first embodiment was set as follows.

[0085] (Conditions of the etching method of the first embodiment)

[0086] Conditions for Residue Removal Step 1

[0087] Bias DC signal: No application (Duty 0%)

[0088] Conditions for Residue Removal Step 2

[0089] Bias DC signal: Frequency 400kHz, -500V, Duty cycle 80%

[0090] FIG. 8a is a diagram illustrating the processing conditions of the etching method of the first reference example during the first verification. In FIG. 8a, the conditions of the source RF signal, bias RF signal, and bias DC signal of the etching method of the first reference example are divided into residue removal step 1 and residue removal step 2 to facilitate comparison with the processing conditions of the etching method of the first embodiment shown in FIG. 8b. In FIG. 8a, the period during which the source RF signal and bias RF signal are supplied during a 400 kHz period corresponding to a 400 kHz frequency bias DC signal is shown as a diagonal pattern. The etching method of the first reference example continuously supplies the source RF signal and bias RF signal during etching. Therefore, the source RF signal and bias RF signal are shown as always being ON during a 400 kHz period, with a diagonal pattern. The source RF signal and the bias RF signal are supplied as a continuous wave (CW). Meanwhile, in the etching method of the first reference example, since the bias DC signal is not applied in the residue removal step 1 and residue removal step 2, the diagonal line pattern does not appear during one cycle of 400 kHz and always appears as off.

[0091] FIG. 8b is a diagram illustrating the processing conditions of the etching method of the first embodiment during the first verification. FIG. 8b shows the conditions of the source RF signal, bias RF signal, and bias DC signal of the etching method of the first embodiment during the first verification, divided into residue removal step 1 and residue removal step 2. In FIG. 8b, the conditions of the source RF signal, bias RF signal, and bias DC signal of residue removal step 1 are the same as those of the first reference example. In residue removal step 1, the bias DC signal is not applied, and the source RF signal and bias RF signal are supplied. In residue removal step 2, the source RF signal, bias RF signal, and bias DC signal are supplied during etching. In residue removal step 2, the bias DC signal is supplied at 400 kHz and a duty cycle of 80%. In FIG. 8b, the bias RF signal of the residue removal step 2 is shown as being on for 80% of the period, as shown in the diagonal pattern, during one cycle of 400 kHz.

[0092] In the first verification, the amount of residue (56) on the substrate (W) in the etching method of the first reference example was 1.61 [nm], and the amount of residue (56) on the substrate (W) in the etching method of the first embodiment was 1.45 [nm]. From this, the etching method of the first embodiment can reduce the amount of residue (56) compared to the etching method of the first reference example.

[0093] Next, the results of the second verification are explained. In the second verification, in the etching method of the first embodiment, the residue removal step 1 is set to the same conditions as the first reference example, and the duty ratio of the bias DC signal of the residue removal step 2 is set to 80% and 10%, respectively, and the etching of the substrate (W) is performed, and the amount of residue (56) on the substrate (W) is compared.

[0094] FIGS. 9A and 9B are drawings illustrating the processing conditions of the etching method of the first embodiment during the second verification. FIGS. 9A and 9B show periods during which a source RF signal, a bias RF signal, and a bias DC signal are supplied for each period of one cycle of 400 kHz during etching, divided into residue removal step 1 and residue removal step 2. In the second verification, in residue removal step 2, the duty cycle of the bias DC signal during etching is set to 80% ( FIG. 9A) and 10% ( FIG. 9B), respectively. The conditions of residue removal step 1 are the same as those of the first reference example.

[0095] In the second verification, the amount of residue (56) on the substrate (W) was 2.21 [nm] when the duty ratio was 80% (Fig. 9a), and the amount of residue (56) on the substrate (W) was 1.67 [nm] when the duty ratio was 10% (Fig. 9b). From this, the etching method of the first embodiment can reduce the amount of residue (56) by lowering the duty ratio of the bias DC signal. Furthermore, regarding the case where the duty ratio is 80%, the reason the amount of residue (56) differs between the first verification and the second verification is that the composition of the substrate (W) is slightly different between the first verification and the second verification.

[0096] Next, the results of the third verification are explained. In the third verification, in the etching method of the first embodiment, the duty cycle of the bias DC signal in the residue removal step 2 is set to 10%, and in the case where the bias DC signal is not applied in the residue removal step 1 and in the case where the duty cycle is set to 20%, the substrate (W) is etched, and the amount of residue (56) is compared.

[0097] FIGS. 10a and 10b are drawings illustrating the processing conditions of the etching method of the first embodiment during the third verification. FIGS. 10a and 10b show periods during which a source RF signal, a bias RF signal, and a bias DC signal are supplied for each period of one cycle of 400 kHz during etching, divided into residue removal step 1 and residue removal step 2. In the third verification, in residue removal step 1, the bias DC signal during etching is not applied (Fig. 10a) and is set to 20% (Fig. 10b), respectively. The conditions for residue removal step 2 are both set to a duty cycle of 10%.

[0098] In the third verification, in the residue removal step 1, when a bias DC signal is not applied during etching (Fig. 10a), the amount of residue (56) on the substrate (W) is 1.67 [nm], and when the duty ratio is 20% (Fig. 10b), the amount of residue (56) on the substrate (W) is 1.1 [nm]. From this, the etching method of the first embodiment can reduce the amount of residue (56) by applying a bias DC signal even in the residue removal step 1.

[0099] In the verification described above, the etching method of the first embodiment was divided into two steps, residue removal step 1 and residue removal step 2, and the substrate (W) was etched by performing residue removal step 2 after residue removal step 1. However, the etching method of the first embodiment is not limited thereto. The etching method of the first embodiment may be divided into three or more steps. In addition, the etching method of the first embodiment may etch the substrate (W) without dividing it into steps, by keeping the duty ratio of the bias DC signal constant during etching. The substrate (W) may be etched using only the steps of the etching method of the first embodiment, or it may be etched by combining the etching method of the first embodiment with other etching methods.

[0100] [Flowchart]

[0101] A flowchart of an etching process including the etching method of the present disclosure is described. FIG. 11 is a flowchart showing an example of the processing sequence of an etching process according to a first embodiment. The etching process of FIG. 11 is performed when the etching of the substrate (W) is initiated.

[0102] The control unit (2) controls the gas supply unit (20) to start supplying the processing gas from the gas supply unit (20) and supplies the processing gas into the plasma processing chamber (10) (Step S10). The control unit (2) controls the first RF generation unit (31a) to start supplying the source RF signal from the first RF generation unit (31a) and plasmaizes the processing gas inside the plasma processing chamber (10) (Step S11). The control unit (2) controls the bias DC generation unit (32a) to start supplying the bias DC signal from the bias DC generation unit (32a) and supplies the bias DC signal to the substrate support unit (11) (Step S12). The control unit (2) controls the second RF generation unit (31b) to begin supplying a bias RF signal from the second RF generation unit (31b), and supplies the bias RF signal to the substrate support unit (11) by superimposing it on the bias DC signal (step S13). Additionally, steps S11 to S13 may be reversed in order. Furthermore, steps S11 to S13 may execute some or all of the steps as a single step.

[0103] The control unit (2) determines whether the etching is finished (step S14). For example, the control unit (2) determines that the etching is finished if it satisfies a predetermined condition for finishing the etching. If the etching is not finished (step S14: No), it proceeds to step S14 again. If the etching is finished (step S14: Yes), the control unit (2) performs control to stop the supply of the processing gas, the supply of the source RF signal, the bias DC signal, and the supply of the bias RF signal, respectively, and finishes the processing.

[0104] Accordingly, the etching treatment according to the first embodiment can obtain high vertical processing performance. In addition, the etching method of the first embodiment can reduce residue (56).

[0105] Additionally, the etching process shown in FIG. 11 is an example and is not limited thereto. The etching process may include other steps. Additionally, the etching process may be performed as part of another process. For example, when etching is performed by executing a plurality of processes in sequence to etch the substrate (W) to the stop layer, the etching process shown in FIG. 11 may be performed as a process of etching that reaches the stop layer of the substrate (W). For example, when etching the substrate (W) shown in FIG. 2a, FIG. 2b, FIG. 3a, and FIG. 3b is performed, the control unit (2) may control the etching process shown in FIG. 11 to be performed when etching the bottom portion of the rectangular portion (55) that has reached the base layer (50).

[0106] (Second embodiment)

[0107] Next, a second embodiment will be described. Since the configuration of the plasma processing system according to the second embodiment is identical to the configuration of the plasma processing system according to the first embodiment shown in FIG. 1, the description will be omitted.

[0108] The bias DC generation unit (32a) supplies a pulsed bias DC signal by periodically turning a negative DC voltage on and off.

[0109] The second RF generation unit (31b) does not supply a bias RF signal during the period when the bias DC signal is on, and supplies a bias RF signal during the period when the bias DC signal is off.

[0110] The etching method of the second embodiment does not superimpose the bias RF signal during the on period when the DC voltage of the bias DC signal is turned on, and supplies the bias RF signal by superimposing it during the off period when the DC voltage of the bias DC signal is turned off.

[0111] FIG. 12a is a diagram showing an example of a change in the potential of a substrate (W) in an etching method of the second embodiment. During the off period of the bias DC signal, a bias RF signal is superimposed on the bias DC signal and supplied to the lower electrode of the base (1110), so that the potential of the substrate (W) changes into a rectangular shape in accordance with the fluctuation of the bias DC signal, and at the same time vibrates in accordance with the bias RF signal during the off period.

[0112] FIG. 12b is a diagram showing an example of the energy distribution of ions in the etching method of the second embodiment. FIG. 12b is a diagram schematically showing the ion energy distribution function (IEDF) of the etching method of the second embodiment. The horizontal axis represents the energy of the ions [eV], and the energy is higher towards the right. The vertical axis represents the number of ions, and the number of ions is greater towards the top. In addition, FIG. 12b shows the threshold value (E) of the ion energy required for etching the gate material (52). th It represents ).

[0113] The etching method of the second embodiment produces peaks on the high-energy side and the low-energy side.

[0114] In the etching method of the second embodiment, since the bias RF signal is not superimposed during the ON period of the bias DC signal, the peak on the high energy side is high and the energy width at which the peak occurs is narrow. In the etching method of the second embodiment, the peak on the high energy side becomes an acute energy distribution. As a result, the etching method of the second embodiment increases the verticality of ions or radicals, thereby enabling high vertical processing performance.

[0115] In addition, the etching method of the second embodiment has a low-energy threshold value (E) because the bias RF signal is superimposed during the off period of the bias DC signal. th) and above, a peak is formed over a wide range. As a result, the etching method of the second embodiment can widen the angle of incidence of ions incident on the substrate (W), and thus efficiently remove residue (56), thereby reducing residue (56).

[0116] In addition, the etching method of the first and second embodiments described above can independently change the height of the peak and the energy at which the peak occurs on the high energy side without changing the height of the peak and the energy at which the peak occurs on the low energy side by changing the amplitude of the bias DC signal and the on period of the bias DC signal.

[0117] FIG. 13a is a diagram illustrating the change in potential of a substrate (W) when the amplitude of a bias DC signal is changed. FIG. 13a shows a case in which the amplitude of a bias DC signal is changed by changing the negative voltage during the ON period of the bias DC signal in the etching method of the second embodiment. In FIG. 13a, the negative voltage during the ON period of the bias DC signal is changed more significantly to the right, so the change in the potential of the substrate (W) during the ON period is greater to the right. FIG. 13b is a diagram illustrating the change in the energy distribution of ions when the amplitude of a bias DC signal is changed. FIG. 13b shows a case in which the amplitude of a bias DC signal is changed by changing the negative voltage during the ON period of the bias DC signal in the etching method of the second embodiment. Depending on the potential of the substrate (W), the energy of the ions attracted to the substrate (W) changes. For this reason, by changing the amplitude of the bias DC signal, the energy range at which the high-energy peak occurs can be changed.

[0118] FIG. 14a is a diagram illustrating the change in potential of a substrate (W) when the ON period of a bias DC signal is varied. FIG. 14a shows the case where the ON period of a bias DC signal is varied in the etching method of the second embodiment. In FIG. 14a, the ON period of the bias DC signal is varied to be longer as it moves to the right, and the period (T1) during which the potential of the substrate (W) becomes negative is longer as it moves to the right. FIG. 14b is a diagram illustrating the change in the energy distribution of ions when the ON period of a bias DC signal is varied. FIG. 14b shows the case where the ON period of a bias DC signal is varied in the etching method of the second embodiment. The longer the period during which the potential of the substrate (W) becomes negative, the more ions are attracted to the substrate (W). Therefore, by varying the ON period of the bias DC signal, the height of the peak on the high-energy side can be changed.

[0119] In addition, the etching method of the first and second embodiments described above can independently change the height of the peak and the range of the peak at the low energy side without changing the height of the peak at the high energy side and the energy at which the peak occurs by changing the amplitude of the bias RF signal and the off period of the bias DC signal.

[0120] FIG. 15a is a diagram illustrating the change in potential of a substrate (W) when the amplitude of a bias RF signal is changed. FIG. 15a shows the case where the amplitude of the bias RF signal is changed in the etching method of the second embodiment. In FIG. 15a, the amplitude of the bias RF signal is changed more significantly to the right, so that the amplitude of the oscillation of the potential of the substrate (W) during the off period becomes larger to the right. FIG. 15b is a diagram illustrating the change in the energy distribution of ions when the amplitude of the bias RF signal is changed. FIG. 15b shows the case where the amplitude of the bias RF signal is changed in the etching method of the second embodiment. Depending on the potential of the substrate (W), the energy of the ions attracted to the substrate (W) changes. Therefore, by changing the amplitude of the bias RF signal, the energy range at which a low-energy peak occurs can be changed.

[0121] FIG. 16a is a diagram illustrating the change in potential of a substrate (W) when the off-period of the bias DC signal is varied. FIG. 16a shows the case where the off-period of the bias DC signal is varied in the etching method of the second embodiment. In FIG. 16a, the off-period of the bias DC signal is varied to the right, and the period (T2) during which the potential of the substrate (W) is near zero is varied to the right. FIG. 16b is a diagram illustrating the change in the energy distribution of ions when the off-period of the bias DC signal is varied. FIG. 16b shows the case where the off-period of the bias DC signal is varied in the etching method of the second embodiment. The longer the period (T2) during which the potential of the substrate (W) is near zero, the more ions are attracted to the substrate (W) during the period (T2). Therefore, by varying the off-period of the bias DC signal, the height of the peak on the low-energy side can be changed.

[0122] The on and off periods of the bias DC signal can be changed by varying the period and duty cycle of the bias DC signal. Accordingly, the etching method of the first and second embodiments can adjust the energy distribution of ions incident on the substrate (W) by varying the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal. For example, the etching method of the first and second embodiments can adjust the height of the peaks on the low-energy side and the high-energy side, and the range of energy at which the peaks occur, respectively, by varying the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal.

[0123] The control unit (2) may control the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal during the etching of the substrate (W). For example, in the etching of the substrate (W) shown in FIG. 2a, FIG. 2b, FIG. 3a, and FIG. 3b, a hole surrounded by a mask (53) and a pin (51a) is formed in the gate material (52). When forming a hole in the gate material (52) by etching, the control unit (2) controls the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal. For example, the control unit (2) controls the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the peak on the high energy side is high and the peak on the low energy side is low until the bottom part of the hole reaches the base layer (50). And, when the bottom part of the hole reaches the base layer (50), the control unit (2) controls the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that the low-energy peak is high and the energy range at which the low-energy peak occurs is wide. Accordingly, the plasma processing device (1) can obtain high vertical processing performance. In addition, the plasma processing device (1) can reduce residue (56).

[0124] In addition, the etching method of the first and second embodiments described above was explained by citing the case where the bias RF signal is superimposed over the entire off-period of the bias DC signal. However, it is not limited thereto. The etching method of the first and second embodiments described above may superimpose the bias RF signal over a part of the off-period of the bias DC signal. FIG. 17 is a diagram illustrating the change in potential of a substrate (W) when the superimposition period of the bias RF signal is varied. In FIG. 17, in the etching method of the second embodiment, the height of the low-energy peak can be varied according to the length of the superimposition period (T4) in which the bias RF signal is superimposed within the off-period (T3) of the bias DC signal.

[0125] In addition, the etching method of the first and second embodiments described above was explained by citing the case where the bias RF signal is superimposed over the entire off period of the bias DC signal. However, it is not limited thereto. In the etching method of the first and second embodiments described above, if the rectangularity of the bias DC signal is poor, the bias RF signal may not be superimposed during the transitional period in which the potential of the substrate (W) changes in response to the change in the on / off of the bias DC signal, and the bias RF signal may be superimposed after passing through the transitional period. FIG. 18 is a diagram illustrating the change in the potential of the substrate (W) when the superposition period (T4) for superimposing the bias RF signal is varied. In the potential of the substrate (W), a period (T5) occurs as a transitional period in which the bias DC signal is turned off and transitions to near 0. In FIG. 18, the bias RF signal is turned off during the period (T5) after the bias DC signal is turned off so that the bias RF signal is not superimposed on the bias DC signal, and the bias RF signal is superimposed on the bias DC signal after the period (T5) has elapsed. In the etching method of the first and second embodiments, when the rectangularity of the bias DC signal is poor, the bias RF signal is not superimposed during the transition period, but is superimposed after the transition period has elapsed, thereby allowing the signal to be divided into a low-energy side and a high-energy side, and each peak to be generated.

[0126] In addition, the etching method of the first and second embodiments described above was explained by etching the substrate (W) shown in FIG. 2a and FIG. 2b as an example. However, it is not limited thereto. The substrate (W) may have a target film to be etched formed on a base layer. The target film to be etched may be, for example, an oxide film such as a silicon oxide film, or a metal film such as a SiN film, an organic film, or a tungsten film. The base layer may be a material capable of having an etching selectivity ratio with the target film to be etched described above. The etching method of the first and second embodiments can be applied as long as it is a process of etching a hole in the target film of the substrate (W) that reaches up to the base layer.

[0127] (effect)

[0128] As described above, the plasma processing system (plasma processing device) according to the above-described embodiment comprises a plasma processing chamber (10), a substrate support (11), a gas supply unit (20), a first RF generation unit (31a) (first high-frequency power source), a bias DC generation unit (32a) (voltage pulse source), a second RF generation unit (31b) (second high-frequency power source), and a control unit (2). The substrate support (11) is disposed within the plasma processing chamber (10) and supports a substrate (W). The gas supply unit (20) is configured to supply processing gas into the plasma processing chamber (10). The first RF generation unit (31a) is configured to supply a source RF signal (first high-frequency power) that plasmafies the processing gas within the plasma processing chamber (10). The bias DC generation unit (32a) is configured to supply a bias DC signal (voltage pulse) that pulses a DC voltage to the substrate support (11). The second RF generation unit (31b) is configured to supply a bias RF signal (second high-frequency power) to the substrate support unit (11). The control unit (2) is configured to control the supply of a processing gas from the gas supply unit (20) into the plasma processing chamber (10) when etching the substrate (W), the supply of a source RF signal from the first RF generation unit (31a) to plasmaize the processing gas in the plasma processing chamber (10), the supply of a bias DC signal from the bias DC generation unit (32a) to the substrate support unit (11), and the supply of a bias RF signal from the second RF generation unit (31b) by superimposing it on the bias DC signal. Accordingly, the plasma processing system according to the embodiment can reduce residue.

[0129] Additionally, the bias DC generation unit (32a) is configured to change the duty cycle of the bias DC signal by periodically turning the negative DC voltage on and off and changing the ratio of the on / off period during one cycle. The control unit (2) is configured to control the duty cycle of the bias DC signal to 10% to 80%. Accordingly, the plasma processing system according to the embodiment can reduce residue.

[0130] In addition, the control unit (2) is configured to control the duty cycle of the bias DC signal to 10% to 20%. Accordingly, the plasma processing system according to the embodiment can reduce residue.

[0131] Additionally, a target film to be etched is formed on the base layer of the substrate (W). The control unit (2) is configured to control the duty ratio of the bias DC signal to become smaller as the bottom portion of the hole formed in the target film by etching approaches the base layer. Accordingly, the plasma processing system according to the embodiment can reduce the residue at the bottom portion of the hole.

[0132] Additionally, the bias DC generation unit (32a) is configured to supply a bias DC signal by periodically turning a negative DC voltage on and off. The second RF generation unit (31b) is configured not to supply a bias RF signal during the on period and to supply a bias RF signal during the off period. Accordingly, the plasma processing system according to the embodiment can reduce residue. In addition, the plasma processing system according to the embodiment can achieve high vertical processing performance.

[0133] Additionally, a target film to be etched is formed on the base layer of the substrate (W). The control unit (2) is configured to perform the aforementioned control when the bottom portion of the hole formed in the target film by etching reaches the base layer. Accordingly, the plasma processing system according to the embodiment can reduce the residue of the bottom portion of the hole.

[0134] Additionally, the substrate (W) has, in order, a pin structure (51) having a plurality of pins (51a) on the base layer (50), a gate material (52) deposited on the pin structure (51), and a mask (53) on the gate material (52). The control unit (2) is configured to perform the aforementioned control when etching the gate material (52) deposited between the plurality of pins (51a) of the substrate (W) until the base layer (50) is exposed. Accordingly, the plasma processing system according to the embodiment can reduce the residue (56) at the bottom of the hole (rectangular portion (55)) where the base layer (50) is exposed.

[0135] In addition, the bias DC generating unit (32a) is configured to supply a bias DC signal with a frequency of 100 kHz to 1200 kHz. Accordingly, the plasma processing system according to the embodiment can obtain high vertical processing performance.

[0136] In addition, the gate material is polycrystalline silicon. The base layer is a silicon oxide film. Accordingly, the plasma processing system according to the embodiment can reduce residue at the bottom of the hole where the silicon oxide film formed on the polycrystalline silicon is exposed. Accordingly, the plasma processing system according to the embodiment can reduce residue.

[0137] Additionally, the control unit (2) is configured to control the period, duty cycle, and amplitude of the bias DC signal and the amplitude of the bias RF signal during the etching of the substrate (W). Accordingly, the plasma processing system according to the embodiment can adjust the height of the peaks on the low-energy and high-energy sides of the energy distribution of the ions and the range of energy at which the peaks occur, respectively.

[0138] Additionally, a target film to be etched is formed on the base layer of the substrate (W). The control unit (2) is configured to control the period, duty ratio, and amplitude of the bias DC signal and the amplitude of the bias RF signal so that, until the bottom part of the hole formed in the target film by etching reaches the base layer, the peak on the high energy side of the energy distribution of ions incident on the substrate (W) becomes high and the peak on the low energy side becomes low, and when the bottom part of the hole reaches the base layer, the peak on the low energy side becomes high and the energy range in which the peak on the low energy side occurs becomes wide. Accordingly, the plasma processing system according to the embodiment can reduce residue. In addition, the plasma processing system according to the embodiment can obtain high vertical processing performance.

[0139] Although embodiments have been described above, the embodiments disclosed herein should be considered illustrative in all respects and not restrictive. In practice, the embodiments described above may be implemented in various forms. Furthermore, the embodiments described above may be omitted, substituted, or modified in various forms without departing from the scope and intent of the claims.

[0140] For example, in the above-described embodiment, the case in which plasma etching treatment is performed on a semiconductor wafer as the substrate (W) was explained as an example, but it is not limited thereto. Any substrate (W) may be used.

[0141] Furthermore, the embodiments disclosed herein should be considered illustrative in all respects and not restrictive. In practice, the above-described embodiments may be implemented in various forms. Additionally, the above-described embodiments may be omitted, substituted, or modified in various forms without departing from the appended claims and their intent.

[0142] In addition, regarding the above embodiments, the following additional notes are disclosed.

[0143] (Appendix 1)

[0144] chamber and,

[0145] A substrate support member disposed within the above chamber and supporting a substrate, and

[0146] A gas supply unit configured to supply processing gas into the above chamber, and

[0147] A first high-frequency power source configured to supply a first high-frequency power that plasmanates the processing gas in the chamber, and

[0148] A voltage pulse source configured to supply a voltage pulse, which is a pulsed DC voltage, to the substrate support above, and

[0149] A second high-frequency power source configured to supply a second high-frequency power to the substrate support portion, and

[0150] When etching the substrate, the control unit is configured to supply the processing gas into the chamber from the gas supply unit and supply a first high-frequency power from the first high-frequency power source to plasmafy the processing gas within the chamber, and to supply the voltage pulse from the voltage pulse source to the substrate support unit and to control the supply of the second high-frequency power from the second high-frequency power source by superimposing it on the voltage pulse.

[0151] Plasma processing device.

[0152] (Appendix 2)

[0153] In Book 1,

[0154] The above voltage pulse source is configured to enable a change in the duty ratio of the voltage pulse by periodically turning the negative DC voltage on and off and changing the ratio of the on and off periods during one cycle.

[0155] A plasma processing device, wherein the above control unit is configured to control the duty ratio of the above voltage pulse to 10% to 80%.

[0156] (Appendix 3)

[0157] In Book 2,

[0158] A plasma processing device, wherein the above control unit is configured to control the duty ratio of the voltage pulse to 10% to 20%.

[0159] (Appendix 4)

[0160] In Book 2 or 3,

[0161] The above substrate has a target film to be etched formed on a base layer, and

[0162] A plasma processing apparatus configured such that the control unit controls the duty ratio of the voltage pulse to become smaller as the bottom portion of the hole formed in the target film by etching approaches the base layer.

[0163] (Appendix 5)

[0164] In any one of Books 1 to 4,

[0165] The above voltage pulse source is configured to supply the voltage pulse by periodically turning a negative DC voltage on and off, and

[0166] A plasma processing device configured such that the second high-frequency power supply does not supply the second high-frequency power during the on period and supplies the second high-frequency power during the off period.

[0167] (Appendix 6)

[0168] In any one of Books 1 to 5,

[0169] The above substrate has a target film to be etched formed on a base layer, and

[0170] A plasma processing apparatus configured such that the above control unit performs the control when the bottom portion of the hole formed in the target film by etching reaches the base layer.

[0171] (Appendix 7)

[0172] In any one of Books 1 to 6,

[0173] The above substrate has, in order, a pin structure having a plurality of pins on a base layer, a gate material deposited on the pin structure, and a mask on the gate material.

[0174] A plasma processing apparatus configured such that the above control unit performs the control when etching the gate material deposited between the plurality of pins of the substrate until the base layer is exposed.

[0175] (Appendix 8)

[0176] In any one of Books 1 to 7,

[0177] A plasma processing device configured such that the above voltage pulse source supplies voltage pulses with a frequency of 100 kHz to 1200 kHz.

[0178] (Appendix 9)

[0179] In Book 7,

[0180] A plasma processing device in which the gate material is polycrystalline silicon.

[0181] (Appendix 10)

[0182] In Book 7 or 9,

[0183] A plasma treatment device in which the above base layer is a silicon oxide film.

[0184] (Appendix 11)

[0185] In any one of Books 1 to 10,

[0186] A plasma processing apparatus configured such that the control unit controls the period, duty cycle, and amplitude of the voltage pulse and the amplitude of the second high-frequency power during the etching of the substrate.

[0187] (Appendix 12)

[0188] In any one of Books 1 to 11,

[0189] The above substrate has a target film to be etched formed on a base layer, and

[0190] A plasma processing apparatus configured such that the control unit controls the period, duty ratio, and amplitude of a bias DC signal and the amplitude of a bias RF signal, so that when the bottom portion of a hole formed in the target film by etching reaches the base layer, the peak on the high energy side of the energy distribution of ions incident on the substrate becomes high and the peak on the low energy side becomes low, and when the bottom portion of the hole reaches the base layer, the peak on the low energy side becomes high and the energy range at which the peak on the low energy side occurs becomes wide.

[0191] (Appendix 13)

[0192] chamber and,

[0193] A substrate support member disposed within the above chamber and supporting a substrate, and

[0194] A gas supply unit configured to supply processing gas into the above chamber, and

[0195] A first high-frequency power source configured to supply a first high-frequency power that plasmanates the processing gas in the chamber, and

[0196] A voltage pulse source configured to supply a voltage pulse, which is a pulsed DC voltage, to the substrate support above, and

[0197] An etching method of a plasma processing apparatus having a second high-frequency power source configured to supply a second high-frequency power to the substrate support portion,

[0198] When etching the substrate, the process comprises supplying the processing gas into the chamber from the gas supply unit, supplying the first high-frequency power from the first high-frequency power source to plasmafy the processing gas within the chamber, supplying the voltage pulse from the voltage pulse source to the substrate support unit, and supplying the second high-frequency power from the second high-frequency power source by superimposing it on the voltage pulse.

[0199] Etching method. Explanation of the symbols delete

Claims

Claim 1 The apparatus comprises a chamber, a substrate support member disposed within the chamber and supporting a substrate, a gas supply member configured to supply a processing gas within the chamber, a first high-frequency power source configured to supply a first high-frequency power to plasmafy the processing gas within the chamber, a voltage pulse source configured to supply a voltage pulse formed by pulsed DC voltage to the substrate support member, a second high-frequency power source configured to supply a second high-frequency power to the substrate support member, and a control unit configured to control, when etching the substrate, to supply the processing gas into the chamber from the gas supply member, supply the first high-frequency power from the first high-frequency power source to plasmafy the processing gas within the chamber, supply the voltage pulse from the voltage pulse source to the substrate support member, and supply the second high-frequency power from the second high-frequency power source by superimposing it on the voltage pulse; wherein the voltage pulse source is configured to periodically turn a negative DC voltage on and off, and to change the duty cycle of the voltage pulse by changing the ratio of the on / off period during one cycle, and the control unit, the voltage A plasma processing device configured to control the duty cycle of the pulse to 10% to 20%. Claim 2 delete Claim 3 delete Claim 4 A plasma processing apparatus according to claim 1, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to control the duty ratio of the voltage pulse to become smaller as the bottom portion of the hole formed in the target film by etching approaches the base layer. Claim 5 A plasma processing device according to claim 1, wherein the second high-frequency power source is configured not to supply the second high-frequency power during the on period and to supply the second high-frequency power during the off period. Claim 6 A plasma processing apparatus according to claim 1, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to perform the control when the bottom portion of a hole formed in the target film by etching reaches the base layer. Claim 7 A plasma processing apparatus according to claim 1, wherein the substrate has, in order, a pin structure having a plurality of pins on a base layer, a gate material deposited on the pin structure, and a mask on the gate material, and the control unit is configured to perform the control when etching the gate material deposited between the plurality of pins of the substrate until the base layer is exposed. Claim 8 A plasma processing apparatus according to claim 1, wherein the voltage pulse source is configured to supply voltage pulses with a frequency of 100 kHz to 1200 kHz. Claim 9 A plasma processing apparatus in which, in claim 7, the gate material is polycrystalline silicon. Claim 10 A plasma treatment device in which, in claim 7, the base layer is a silicon oxide film. Claim 11 A plasma processing apparatus according to claim 1, wherein the control unit is configured to control the period, duty cycle, and amplitude of the voltage pulse and the amplitude of the second high-frequency power during the etching of the substrate. Claim 12 A plasma processing apparatus according to claim 1, wherein the substrate has a target film to be etched formed on a base layer, and the control unit is configured to control the period, duty ratio, and amplitude of a bias DC signal and the amplitude of a bias RF signal such that, until the bottom part of a hole formed in the target film by etching reaches the base layer, the peak on the high energy side of the energy distribution of ions incident on the substrate is high and the peak on the low energy side is low, and when the bottom part of the hole reaches the base layer, the peak on the low energy side is high and the energy range at which the peak on the low energy side occurs is widened. Claim 13 An etching method for a plasma processing apparatus comprising: a chamber; a substrate support member disposed within the chamber and supporting a substrate; a gas supply member configured to supply a processing gas within the chamber; a first high-frequency power source configured to supply a first high-frequency power to plasmafy the processing gas within the chamber; a voltage pulse source configured to supply a voltage pulse formed by pulsed DC voltage to the substrate support member; and a second high-frequency power source configured to supply a second high-frequency power to the substrate support member, wherein the voltage pulse source is configured to periodically turn a negative DC voltage on and off, and by changing the ratio of the on / off period during one cycle, the duty cycle of the voltage pulse is changed; when etching the substrate, the processing gas is supplied into the chamber from the gas supply member, and the first high-frequency power is supplied from the first high-frequency power source to plasmafy the processing gas within the chamber; and regarding the substrate support member, the voltage pulse is supplied from the voltage pulse source by controlling the duty cycle to 10% to 20%, and the second high-frequency power is superimposed on the voltage pulse. An etching method comprising a process of supplying the second high-frequency power from a power source.

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