Efficient seamless switching of sigma-delta modulators

Abstract

A digital microphone comprises at least one integrator; a state detection and parameter control component directly coupled to the output of the integrator; and a signal processing component coupled to the output of the state detection and parameter control component, wherein the parameter of the signal processing component includes a first value in a first operating mode and a second value in a second operating mode different from the first operating mode.

Description

Technology Field

[0001] The present invention generally relates to a system and method for efficient seamless switching of sigma-delta modulators. Background Technology

[0002] The application of microelectromechanical systems (MEMS) technology to microphones has led to the development of high-performance, compact microphones. MEMS microphones offer a high signal-to-noise ratio (SNR), low power consumption, and good sensitivity, and are available in small packages compatible with surface mount assembly processes.

[0003] MEMS microphones utilize acoustic sensors manufactured on semiconductor production lines using silicon wafers. Layers of different materials are deposited on top of the silicon wafer, and unwanted materials are subsequently etched away to create a movable membrane and a fixed backplate over a cavity on the base wafer. The sensor backplate may be a rigid perforated structure that allows air to pass through easily, while the membrane is a thin solid structure that bends in response to changes in air pressure caused by sound waves. Changes in air pressure caused by sound waves cause the thin membrane to bend, while the thicker backplate remains fixed as air passes through its perforations. The movement of the membrane causes a change in the amount of capacitance between the membrane and the backplate, which is converted into an electrical signal by an Application Specific Integrated Circuit (ASIC). The ASIC measures voltage fluctuations caused when the capacitance between the membrane and the stationary backplate changes due to the motion of the membrane in response to sound waves. In many applications, a low-noise audio Analog-to-Digital Converter (ADC) is required to convert the output of analog microphones into a digital format for processing and / or transmission. The ADC can be clocked at various frequencies in a trade-off between microphone performance and microphone power consumption.

[0004] According to one embodiment, the digital microphone comprises at least one integrator; a state detection and parameter control component directly coupled to the output of the integrator; and a signal processing component coupled to the output of the state detection and parameter control component, wherein the parameter of the signal processing component includes a first value in a first operating mode and a second value in a second operating mode different from the first operating mode.

[0005] According to one embodiment, the digital modulator comprises: an adder; at least one integrator coupled to the adder; a quantizer coupled to the at least one integrator; a state detection and control component coupled to the output of the at least one integrator; and a variable gain block coupled between the state detection and control component and the adder.

[0006] According to one embodiment, a method for operating a digital microphone comprises: monitoring the state of an integrator of the digital microphone; generating an output signal having a first level during a first state of the integrator and a second level during a second state of the integrator; controlling a parameter value of a signal processing component of the digital microphone with the output signal; and changing the operating mode of the digital microphone only during the first state of the integrator. Brief explanation of the drawing

[0007] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken together with the accompanying drawings, wherein: Figure 1a is a block diagram of an exemplary digital microphone. Figure 1b is a block diagram showing additional details of the digital modulator of the exemplary digital microphone of Figure 1a. Figure 1c is a block diagram of an exemplary digital microphone utilizing efficient (static) digital gain control. FIG. 1d is a block diagram of a digital microphone that utilizes efficient digital gain adjustment by changing the gain of a digital modulator based on the state of an integrator, according to one embodiment. FIG. 2a is a graph of input and output sequences of an integrator that generates minimum transients due to the detection of a zero integrator state during a switching event, according to one embodiment. FIG. 2b is a graph of input and output sequences of an integrator that generates significant transients due to the detection of a non-zero integrator state during a switching event, according to one embodiment. Figure 3a is a graph comparing the low-pass filter outputs for digital microphones with and without dynamic seamless switching during a switching event (for a switched modulator input). Figure 3b is a graph comparing the low-pass filter outputs for digital microphones with and without dynamic seamless switching during a switching event (for zero modulator input). FIG. 4a is a block diagram of a state detection and control component of a digital microphone illustrated in FIG. 1d according to one embodiment. FIG. 4b is a block diagram of a plurality of series-coupled integrators that can replace a single integrator of the digital microphone shown in FIG. 1d, according to one embodiment. FIG. 4c is a block diagram of an integrator including a saturation block that can be used for a single integrator of the digital microphone shown in FIG. 1d, according to one embodiment. FIG. 5a is a block diagram of a digital microphone capable of seamless dynamic parameter change in a digital modulator application example according to one embodiment. FIG. 5b is a block diagram of a digital microphone capable of seamless dynamic parameter change in an ADC application example according to one embodiment. FIG. 6a is a block diagram of an ADC capable of seamless dynamic parameter change according to one embodiment. FIG. 6b is a block diagram of a switched capacitor sigma-delta ADC capable of seamless dynamic parameter change by changing the value of the sampling capacitance according to one embodiment. FIG. 6c is a block diagram of a digital modulator (noise shaper) capable of seamless dynamic parameter change according to one embodiment. FIG. 6d is a block diagram of a digital modulator / ADC capable of seamless dynamic change by changing the sampling rate according to one embodiment. FIG. 7 is a generalized microphone block diagram capable of seamless dynamic parameter changes according to one embodiment. FIG. 8 is a block diagram of a method for operating a digital microphone that implements seamless dynamic parameter changes according to one embodiment. Specific details for implementing the invention

[0008] The manufacture and use of currently preferred embodiments are discussed in detail below. However, it should be recognized that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely examples of specific ways of manufacturing and using the present invention and do not limit the scope of the invention.

[0009] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification and in which specific embodiments in which the invention may be practiced are illustrated as examples. It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope of the invention. For example, features illustrated or described in one embodiment may be used in or together with other embodiments to yield further embodiments. The invention is intended to include such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not scaled and are for illustrative purposes only. For clarity, identical or similar elements are designated by corresponding reference numerals in different drawings unless otherwise noted.

[0010] Although embodiments of the present invention are described in detail below, additional descriptions and details of switching between digital microphones and modes of operation of digital microphones are described in U.S. Patent Application No. 16 / 773,079 titled “Configurable Microphone Using Internal Clock Changing”—this U.S. patent application is incorporated by reference in its entirety—; U.S. Patent Application No. 16 / 871,546 titled “Configurable Microphone Using Internal Clock Changing”—this U.S. patent application is incorporated by reference in its entirety—; U.S. Patent Application No. 17 / 209,853 titled “System and Method for Fast Mode Change of a Digital Microphone Using Digital Cross-Talk Compensation”—this U.S. patent application is incorporated by reference in its entirety—; and U.S. Patent Application No. 16 / 932,010 titled “Efficient Digital Gain Implementation in Digital Microphones”—this U.S. patent application is incorporated by reference in its entirety.

[0011] Digital microphones can switch between high-performance and low-power consumption operating modes, in which case the digital microphone remains in one of the two operating modes for extended periods ("static switching") or operates in one of the two modes indefinitely. However, digital microphones may also require dynamic changes to the parameters of signal processing components to compensate for environmental changes or to maintain performance requirements for other reasons. For example, the sampling clock frequency or sampling capacitor value of a sigma-delta ADC may be changed dynamically to support dynamic SNR adjustment or dynamic power saving strategies. To implement these dynamic changes, very precise gain or other adjustments within the digital microphone are sometimes required to avoid causing audible artifacts (e.g., anomalies introduced into the digital signal as a result of digital signal processing).

[0012] Digital microphone embodiments are described herein for the efficient dynamic switching of signal processing component parameters of a digital microphone that causes minimal or inaudible artifacts. In some embodiments, parameters of an analog or digital sigma-delta modulator in the digital microphone are dynamically changed. In other embodiments, parameters of an ADC in the digital microphone are dynamically changed. In embodiments, a state detection and control component monitors the output of one or more integrators in the digital microphone. When the integrator is in a zero state (integrator output equal to a digital or analog zero value) or between first and second thresholds (integrator output different from a digital or analog zero value), the parameters of the signal processing component in the digital microphone can be safely adjusted without causing audible artifacts. If the integrator is in a maximum positive state (integrator output equal to a digital plus 1 value or an analog positive voltage) or a maximum negative state (integrator output equal to a digital minus 1 value or an analog negative value) outside the first and second thresholds, then the parameters of the signal processing component in the digital microphone cannot be adjusted without causing audible artifacts. According to embodiments, adjustments can be made dynamically during or between operating modes. For example, seamless adjustments (adjustments that do not generate an audible transient response during a switching event) can be made with different levels of power saving within a power saving operating mode. Various embodiments enabling dynamic seamless parameter adjustment inside the digital microphone are described in more detail below.

[0013] FIG. 1a illustrates an exemplary digital microphone (100A). The digital microphone (100A) includes a MEMS device (106) coupled to an ASIC (108), both of which may be manufactured in a semiconductor package (102). The digital microphone (100A) receives a clock signal (CLK) (104) distributed among one or more signal processing components of the digital microphone. The MEMS device (106) may be a capacitive or piezoelectric type MEMS device that generates an analog audio output signal in response to acoustic pressure waves. The ASIC (108) includes an ADC (110), a digital filter (112), a digital gain block (114), and a digital modulator (116) for providing a single-bit output signal at an output section (118).

[0014] Accordingly, the ASIC (108) reads an analog signal from the MEMS device (106), provides analog-to-digital conversion of the analog signal, and provides additional digital signal processing. The digital modulator (116) provides a single-bit data stream, which is a requirement in certain applications. The digital filter (112) includes, for example, DC rejection functionality and low-pass filtering. The digital gain block (114) includes a plurality of individual digital gain selections to satisfy different microphone sensitivity requirements for different customer applications. Exemplary sensitivity settings include full-scale sensitivity in calibration modes and numerous other sensitivity settings lower than full-scale sensitivity for use in specific operating modes or for reasons of flexibility.

[0015] FIG. 1b is a block diagram of a digital microphone (100B) showing additional details of the digital modulator of the exemplary digital microphone (100A) of FIG. 1a, including a package (102), a clock signal (104), a MEMS device (106), an ASIC (108), a digital filter (112), a digital gain block (114), and a digital modulator (116)—all of which have been previously described.

[0016] The lower part of FIG. 1b illustrates a block diagram of a digital microphone (100B) with a more detailed representation of a digital modulator (116). In particular, the digital modulator (116) is shown to include an integrator stage (127) and a loop filter (130) in block (128). The integrator stage (127) is a reciprocal Z transform transfer function, z -1 It includes a block (126) and a summer (124) labeled as such, and a unity gain feedback loop between the output of the block (126) and the input of the summer (124). The loop filter (130) is labeled as the filter transfer function "H(z)". In the embodiments, the loop filter (130) may include a digital low-pass filter.

[0017] The digital modulator (116) also includes an "m" bit input section (120)—where "m" is an integer greater than or equal to 2—and a summer (122) having an input section coupled to the "m" bit input section (120) and an output section coupled to the input section of an integrator stage (127). The output section of the integrator stage (127) is coupled to the input section of a loop filter (130). The output section of the loop filter is coupled to the input section of a quantizer (132), which converts the integrated and filtered "m" bit digital signal into a single bit digital signal at the output section (118). A unity gain feedback path (129) couples the output section (118) to the input section of the summer (122).

[0018] FIG. 1c is a block diagram of an exemplary digital microphone (100C) utilizing efficient (static) digital gain control. The digital microphone (100C) includes a package (102), a MEMS device (106), an ASIC (108), an ADC (110), a digital filter (112), a digital gain block (114), a digital modulator (116), a single-bit output (118), an "m"-bit input (120), a summer (122), a summer (124), a block (126), a block (128), a loop filter (130), and a quantizer (132), all of which have been previously described.

[0019] For sensitivity adjustment, an efficient digital gain adjustment implementation includes a lookup table (133) interposed in the feedback path (129) of the digital modulator (116). The lookup table (133) is under the control of a gain selection block (134). Although the digital microphone (110C) advantageously provides efficient static digital gain adjustment, where dynamic gain adjustment is required, audible artifacts may occur in some applications.

[0020] According to the embodiments, a digital microphone and a corresponding method for implementing dynamic parameter changes, e.g., dynamic gain or sensitivity changes, while minimizing audible artifacts generated by dynamic parameter changes are described in detail below. According to the embodiments, a state variable of the integrator output in the digital modulator or ADC of the digital microphone is monitored. When the output of the integrator is at or near an average value (zero value or state) between a positive maximum value (positive 1 value or state) and a negative maximum value (negative 1 value or state), a desired parameter of the component of the digital microphone is changed. As illustrated and described in the examples, the integrator output oscillates around the average value according to the modulator or ADC input signal. When the integrator reaches the average value or within a threshold band around the average value, minimized transients occur when the desired parameter change (e.g., gain value, internal clock frequency, or capacitance value) is applied. When parameter changes are applied when the integrator reaches its maximum positive or negative values, significant audible transients may occur. Various digital microphones, components, and method embodiments for implementing dynamic parameter changes without causing significant audio artifacts are described in more detail below.

[0021] FIG. 1d is a block diagram of a digital microphone (100D) according to one embodiment that implements dynamic parameter changes without causing significant audio artifacts. More specifically, the digital microphone (100D) includes dynamic digital gain adjustment including a variable gain block (136) in the feedback loop of a digital modulator (116) and a state detection and gain control block (138). The digital microphone (100D) also includes a package (102), a MEMS device (106), an ASIC (108), an ADC (110), a digital filter (112), a digital gain block (114), a digital modulator (116), a single-bit output (118), an "m"-bit input (120), a summer (122), a summer (124), a block (126), a block (128), a loop filter (130), and a quantizer (132), all of which have been previously described.

[0022] A dynamic digital gain adjustment implementation located within the digital modulator (116) includes a state detection and variable gain control block (138) having an input coupled to the output of an integrator stage (127) within the digital modulator (116). The state detection and gain control block (138) monitors the output of the integrator stage (127) and determines whether the integrator stage (127) is at an average value or within threshold limits of the average value. If it is determined that the integrator stage (127) is at an average value or within threshold limits of the average value, the control portion of the state detection and gain control block (138) will generate an appropriate control signal (e.g., having a level such as logic 1) indicating that a parameter change may be made. If it is determined that the integrator stage (127) is at one of the maximum values ​​or is not within the threshold limits of the average value, the control portion of the state detection and gain control block (138) will generate an appropriate control signal (e.g., having a level such as logic zero) indicating that parameter change cannot be made. The variable gain control block (136) is interposed in the feedback loop (129) between the single-bit output portion (118) and the input portion of the summer (122). In embodiments, the variable gain control block (136) includes an adjustable digital gain block having a control input portion for receiving a control signal from the state detection and gain control block (138). In embodiments, the control signal determines whether the gain of the control block can be changed, and, if it can be changed, the desired gain change level. In embodiments, very small gain adjustments can be made frequently without causing corresponding audio artifacts.

[0023] The digital microphone (100D) can advantageously reduce or minimize switching artifacts during parameter switching events and can be applied to a wide range of applications including digital and analog modulators, dynamic changes in the gains of modulators, dynamic changes in sampling rates, and dynamic changes in sampling capacitor values, which are described in more detail below. The digital microphone (100D) advantageously provides dynamic parameter changes without additional group delay and with a circuit architecture of relatively low complexity. However, if additional delay is acceptable for a given application, additional filtering may be implemented.

[0024] FIG. 2a is a graph (202A) of the input and output sequences of an integrator that generates minimal audible transients due to the detection of a zero integrator state during a switching event, according to one embodiment. The integrator input sequence is illustrated as a series of "o" symbols (212A) clustered at the maximum positive value (204A) and the maximum negative value (208A). The integrator output sequence is illustrated as a series of "+" symbols (210A) clustered at the maximum positive value (204A), the average value (206A), and the maximum negative value (208A). The parameter switching event (214A) is indicated by a vertical solid line. It is important to note that in FIG. 2a, the parameter switching event (214A) occurs when the integrator output (210A) is at the average value (206A). Therefore, the output of the digital microphone will contain only minimal audible transients.

[0025] FIG. 2b is a graph (202B) of the input and output sequences of an integrator that will generate significant transients due to the detection of a non-zero integrator state during a switching event, according to one embodiment. The integrator input sequence is illustrated as a series of "o" symbols (212b) clustered at the maximum positive value (204B) and the maximum negative value (208B). The integrator output sequence is illustrated as a series of "+" symbols (210B) clustered at the maximum positive value (204B), the average value (206B), and the maximum negative value (208B). The parameter switching event (214B) is indicated by a vertical solid line. It is important to note that in FIG. 2b, the parameter switching event (214A) occurs when the integrator output (210A) is at the maximum positive value (204B). Accordingly, the output of the digital microphone will contain significant audible transients.

[0026] FIG. 3a is a graph (302A) comparing the low-pass filter outputs for digital microphones with and without dynamic seamless switching during a switching event (for a switched modulator input). Traces (304A, 306A, and 308A) are the low-pass filter outputs for the digital microphone associated with a good selection of the switching time moment (when the output of the digital microphone's integrator is at an average value). Traces (304A, 306A, and 308A) are relatively flat, indicating that there are no or minimal audible transients present during the switching event. Trace (310A) is the low-pass filter output for the digital microphone associated with a poor selection of the switching time moment (when the output of the digital microphone's integrator is at a maximum positive value or a maximum negative value). Trace (310A) shows a distinct peak, indicating that there are significant audible transients during the switching event.

[0027] FIG. 3b is a graph (302B) comparing the low-pass filter outputs for digital microphones with and without dynamic seamless switching during a switching event (for a zero modulator input). Traces (306B) are the low-pass filter outputs for the digital microphone associated with a good selection of the switching time moment (when the output of the digital microphone's integrator is at an average value). Trace (306B) is relatively flat, indicating that there are no or minimal audible transients present during the switching event. Trace (310B) is the low-pass filter outputs for the digital microphone associated with a poor selection of the switching time moment (e.g., when the output of the digital microphone's integrator is at a maximum positive value or a maximum negative value). Trace (310B) shows a distinct peak during the switching event, indicating that there are significant audible transients during the switching event.

[0028] FIG. 4a is a block diagram of a state detector and control block (400A) that can be used to monitor the output of an integrator in a digital microphone according to one embodiment. The state detection and control block (400A) includes digital signal processing elements for monitoring the output state of the integrator and determining whether the output state of the integrator is between a first threshold and a second threshold. If yes, the state detector and control block (400A) generates an appropriate output signal capable of switching a component within the digital microphone. For example, in the embodiments, the output signal may be used to switch a variable gain block as previously described, or to switch between switched capacitors of different values, or to switch between different clock frequencies. In some embodiments, the output of the state detector and control block (400A) may be one or more control signals. In other embodiments, the state detector and control block (400A) may include additional control circuits, such as switches and other control circuits.

[0029] FIG. 4b is a block diagram (400B) of a plurality of series-coupled integrators (127A and 127B) that can replace a single integrator of the digital microphone illustrated in FIG. 1d according to one embodiment. The first integrator (127A) includes a first summer (124A) and a first inverse Z-transform transfer function block (126A). The second integrator (127B) includes a second summer (124B) and a second inverse Z-transform transfer function block (126B). The input of the second summer (124B) is coupled to the output of the inverse Z-transform transfer function block (126A). Although only two integrator stages (127A and 127B) are illustrated, any number may be used. For example, up to five series-coupled integrators may be used in one embodiment. In some embodiments, the output of the last integrator among a plurality of series-coupled integrators is monitored by the state detection and control block (128) shown in FIG. 1d.

[0030] FIG. 4c is a block diagram of an integrator (400C) including a saturation block (402) that can be used for a single integrator of the digital microphone illustrated in FIG. 1d according to one embodiment. The integrator (400C) includes an adder (124C) and an inverse Z-transform transfer function block (126C) similar to those previously described, wherein the output of the inverse Z-transform transfer function block (126) is coupled to the input of the adder (124C) through a unity gain feedback path (404). The saturation block (402) is interposed between the adder (124C) and the inverse Z-transform transfer function block to ensure a more uniform distribution of the integrator stage output states, which may be required in some applications.

[0031] FIG. 5a is a generalized block diagram of a digital microphone (500A) having dynamic parameter changes in a digital modulator application example according to one embodiment. The digital microphone includes a package (102), a MEMS device (106), an ASIC (108), an ADC (110), a digital filter (112), a digital gain block (113), a digital modulator (116), and a single-bit output unit (118), all of which have been previously described. The digital microphone (500A) includes a state detection and parameter control block (502A) having an input unit coupled to the digital modulator (116) (at the output unit of one or more integrators) and an output unit for controlling one or more components (e.g., a variable gain block) with one or more control signals. For example, one or more control signals are the clock signal of the digital modulator (116) or the frequency F of another signal. s It may include a control signal (506A) for controlling, a control signal (508A) for controlling the loop gain of the digital modulator (116) or the gain value of a gain block within the digital modulator (116), or a control signal (510A) for controlling the values ​​of other components, such as the capacitance of one or more switched capacitors in the digital modulator (116). Typically, only one control signal is used, but other embodiments may use more than one control signal to dynamically change more than one parameter at the same time.

[0032] FIG. 5b is a generalized block diagram of a digital microphone (500B) having dynamic parameter changes in an ADC application example according to one embodiment. The digital microphone includes a package (102), a MEMS device (106), an ASIC (108), an ADC (110), a digital filter (112), a digital gain block (113), a digital modulator (116), and a single-bit output (118), all of which have been previously described. The digital microphone (500B) includes a state detection and parameter control block (502B) having an input coupled to the ADC (110) (at the output of one or more integrators) and an output for controlling one or more components (e.g., a variable gain block) with one or more control signals. For example, one or more control signals are the clock signal of the ADC (110) or the frequency F of another signal. s It may include a control signal (506B) for controlling, a control signal (508B) for controlling the loop gain of the ADC (110) or the gain value of a gain block within the ADC (110), or a control signal (510B) for controlling the values ​​of other components, such as the capacitance of one or more switched capacitors in the ADC (110). Typically, only one control signal is used, but other embodiments may use more than one control signal to dynamically change more than one parameter at the same time.

[0033] FIG. 6a is a block diagram of a seamless dynamic parameter changeable ADC (600A) that can be used in a digital microphone according to one embodiment. In some embodiments, the ADC (600A) is a sigma-delta ADC. The ADC (600A) includes a first summer (622A) having an input coupled to an ADC input (620A). A signal processing block (628A) including an integrator (627A) and a loop filter (630A) is coupled to the output of the first summer (622A). The integrator (627A) includes a second summer (624A) and an inverse Z-transform transfer function block (626A). The output of the inverse Z-transform transfer function block (626A) is coupled to the input of the second summer (624A). The loop filter (630A) may include a digital low-pass filter, wherein the coefficients of the filter may be changed in different operating modes. The output of the signal processing block (628A) is coupled to the input of the quantizer (632A), and the output of the quantizer is coupled to an ADC output (634A), which is a single-bit output in one embodiment. The digital-to-analog converter (636A) has an input coupled to the ADC output (634A) and an output coupled to the input of the first summer (622A).

[0034] In the ADC (600A) of FIG. 6a, seamless dynamic parameter change is achieved by adding a state detection and loop gain control block (638A), which has an input coupled to the output of the integrator (627A) and an output coupled to the control input of the loop filter (630A). The state detection and loop gain control block (638A) monitors the output of the integrator (627A) and determines whether the integrator (627A) is in an average integrator state or not. If it is in an average integrator state, the state detection and loop gain control block (638A) generates a control signal that signals to the loop filter (630A) that the coefficients of the filter can be safely changed without generating audible artifacts. If it is not in an average integrator state, the control signal is not generated or is switched to a level where the coefficients cannot be changed.

[0035] FIG. 6b is a block diagram of a switched capacitor sigma-delta ADC (600B) capable of seamless dynamic parameter change by changing the value of the sampling capacitance according to one embodiment. Specific components from the ADC (600A) are reproduced in FIG. 6a to show the location of the switched capacitor circuit, including the ADC input (620A), signal processing block (628A), quantizer (632A), ADC output (34A), and DAC (636A). The general location of the switched capacitor circuit is shown in the separated area (640A), and additional details of the switched capacitor circuit are shown in the lower part of FIG. 6b.

[0036] In some embodiments, the switched capacitor circuit may include a differential input signal comprising +vin and -vin single-ended inputs coupled to the first terminal of switch S1 and the first terminal of switch S2, respectively. Switches S1 and S2 are switched with two alternating phase signals p1 and p2. The second terminal of switch S1 and the second terminal of switch S2 are coupled together at node 641A. The first terminal of capacitor C1 and the first terminal of capacitor C2 are coupled to node 641A. The second node of capacitor C1 is coupled to the first terminal of switch S7. The second terminal of switch S7 and the second terminal of capacitor C2 are coupled together at node 643A. The control terminal of switch S7 is coupled to the state detection and loop gain control block (638A) shown in FIG. 6a. By closing switch S7, the sampling capacitance is changed and has a value determined by the parallel combination of capacitor C1 and capacitor C2. When switch S7 is open, the sampling capacitance has a value equal to that of capacitor C2. The DAC capacitor (CDAC) has a first terminal coupled to node 643A and a second terminal coupled to switches S5 and S6. The second terminal of switch S5 is coupled to a positive reference voltage +vref, and the second terminal of switch S6 is coupled to a negative reference voltage -vref. Switches S5 and S6 are switched with two alternating phase signals p1 and p2. In one embodiment, the integrator includes a differential operational amplifier (642A) having an input coupled to node 643A, and an integrating capacitor (C INT) is optionally coupled between the output of the differential operational amplifier (642A) and node 643A via switch S3. The same output is also optionally coupled to node 643A via switch S4. Switches S3 and S4 are switched with two alternating phase signals p1 and p2. In some embodiments, the differential operational amplifier (642A) is powered by a variable bias current source (644A) (i_bias).

[0037] Accordingly, FIG. 6b illustrates a switched capacitor sigma-delta ADC (600B) capable of dynamic parameter change (change of the capacitor value in the switched capacitor circuit) which can be performed in a manner that does not cause significant audio artifacts because the parameter change is performed when the output of the integrator in the ADC is in an average value state.

[0038] FIG. 6c is a block diagram of a digital modulator (600C) (noise shaper) capable of seamless dynamic parameter change, which can be used in a digital microphone according to one embodiment. The digital modulator (600C) includes a first summer (622B) having an input coupled to an nsh (noise shaper) input (620B). A signal processing block (628B) including an integrator (627B) and a loop filter (630B) is coupled to the output of the first summer (622B). The integrator (627B) includes a second summer (624B) and an inverse Z-transform transfer function block (626B). The output of the inverse Z-transform transfer function block (626B) is coupled to the input of the second summer (624B). The loop filter (630B) may include a digital low-pass filter, wherein the coefficients of the filter may be changed in different modes of operation. The output of the signal processing block (628B) is coupled to the input of the quantizer (632B), and the output of the quantizer is coupled to the digital modulator nsh (noise shaper) output (634B), which is a single-bit output in one embodiment.

[0039] In the digital modulator (600C) of FIG. 6b, seamless dynamic parameter change is achieved by adding a state detection and loop gain control block (638B), which has an input coupled to the output of an integrator (627B) and an output coupled to the control input of a loop filter (630B). The state detection and loop gain control block (638B) monitors the output of the integrator (627B) and determines whether the integrator (627B) is in an average integrator state or not. If it is in an average integrator state, the state detection and loop gain control block (638B) generates a control signal that signals to the loop filter (630B) that the coefficients of the filter can be safely changed without generating audible artifacts. If it is not in an average integrator state, the control signal is not generated or is switched to a level where the coefficients cannot be changed.

[0040] FIG. 6d is a block diagram of a digital modulator / ADC (600D) having the ability to dynamically change the sampling rate that can be used in a digital microphone according to one embodiment. In some embodiments, the digital modulator / ADC (600) includes a digital modulator or a sigma-delta ADC. The digital modulator / ADC (600D) includes a first summer (622C) having an input coupled to an input (620C). A signal processing block (628C) including an integrator (627C) and a loop filter (630C) is coupled to the output of the first summer (622C). The integrator (627C) includes a second summer (624C) and an inverse Z-transform transfer function block (626C). The output of the inverse Z-transform transfer function block (626C) is coupled to the input of the second summer (624C). The loop filter (630C) may include a digital low-pass filter. The output of the signal processing block (628C) is coupled to the input of the quantizer (632C), and the output of the quantizer is coupled to an output (634A), which is a single-bit output in one embodiment. In embodiments, some or all of the components of the digital modulator / ADC (600D) may be manufactured in an ASIC (602C).

[0041] In the digital modulator / ADC (600D) of FIG. 6d, seamless dynamic parameter change is achieved by adding a state detection and sampling rate control block (638C), which has an input coupled to the output of an integrator (627C), an input for receiving a system clock (654C) (clk), and an output (650C) (sampling rate Fs) coupled to any of the components in the ASIC (602C). The output (650C) includes a clock signal having the same frequency as the system clock in a first operating mode and a clock signal having a lower frequency than the system clock in a second operating mode. In some embodiments, the state detection and loop gain control block (638C) may include a frequency divider or other digital signal processing components for generating a signal in the output (650C). In some embodiments, the state detection and loop gain control block (638C) may include an additional output (652C) for distributing the signal at the output (650C) to any component within the digital microphone including the digital modulator / ADC (600D) of FIG. 6d. In some embodiments, the state detection and loop gain control block (638C) may include first and second clock signal inputs, and a switch for selecting between the first and second clock signal inputs to generate one or more of the output (650C) and the output (652C).

[0042] The state detection and loop gain control block (638C) monitors the output of the integrator (627C) and determines whether the integrator (627C) is in the average integrator state. If it is in the average integrator state, the state detection and loop gain control block (638C) safely changes the frequency of the clock signal at the output section (650C) and / or the output section (652C) without generating audible artifacts. If it is not in the average integrator state, the frequency of the clock signal at the output section (650C) and / or the output section (652C) remains constant and does not change.

[0043] FIG. 7 is a generalized block diagram (700) of a digital microphone (702) having seamless dynamic parameter changing capability. The digital microphone includes a MEMS device (704) coupled to an ASIC (712). The ASIC (712) includes at least one integrator (706) coupled to a detection and control component (708), which in turn is coupled to one or more other components (710) of the digital microphone. At least one of the other components (710) provides an output signal at an output section (714). As previously described, the detector and control component (708) monitors various output states of at least one integrator (706) and generates a control signal or other signal to change the parameters of at least one of the other components (710). For example, the detector and control component (708) may provide a control signal to change the value of the gain component, a control signal to change the value of the capacitor, or different frequency clock signals, or a control signal to a component to change the frequency of the clock signal, such as a frequency divider.

[0044] FIG. 8 is a block diagram of a method (800) for operating a digital microphone that implements seamless dynamic parameter change according to one embodiment. The method includes: a step of monitoring the state of an integrator of the digital microphone in step 802; a step of generating an output signal having a first level during a first state of the integrator and a second level during a second state of the integrator in step 804; and a step of controlling a parameter value of a signal processing component of the digital microphone with the output signal in step 806.

[0045] Exemplary embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entirety of the specification and claims submitted herein.

[0046] Example 1. According to one embodiment, a digital microphone comprises at least one integrator; a state detection and parameter control component directly coupled to the output of the integrator; and a signal processing component coupled to the output of the state detection and parameter control component, wherein the parameter of the signal processing component includes a first value in a first operation mode and a second value in a second operation mode different from the first operation mode.

[0047] Example 2. In Example 1, the state detection and parameter control component includes first and second thresholds, and the signal processing component includes a variable gain component configured to change gain values ​​when the output of the integrator is between the first threshold and the second threshold.

[0048] Example 3. In any of the above examples, the signal processing component comprises a digital microphone, the digital microphone, a digital modulator or an analog-to-digital converter (ADC).

[0049] Example 4. In any of the above examples, a digital microphone in which the parameters of the signal processing component include gain, frequency, or capacitance.

[0050] Example 5. In any of the above examples, a digital microphone configured such that a state detection and parameter control component generates a first output signal value when the state of the integrator is between a first threshold and a second threshold, and generates a second output signal value when the state of the integrator is not between the first threshold and the second threshold.

[0051] Example 6. In any of the above examples, at least one integrator comprises a plurality of series-coupled integrators, a digital microphone.

[0052] Example 7. In any of the above examples, at least one integrator, a state detection and parameter control component, and a signal processing component are manufactured in an application-specific integrated circuit (ASIC), in a digital microphone.

[0053] Example 8. In any of the above examples, a digital microphone further comprising a microelectromechanical system (MEMS) coupled to an ASIC, wherein the MEMS and the ASIC are manufactured in a semiconductor package.

[0054] Example 9. According to one embodiment, the digital modulator comprises: a summer; at least one integrator coupled to the summer; a quantizer coupled to the at least one integrator; a state detection and control component coupled to the output of the at least one integrator; and a variable gain block coupled between the state detection and control component and the summer.

[0055] Example 10. In Example 9, the state detection and control component is configured to generate a first output signal when the state of the integrator is between a first threshold and a second threshold, and to generate a second output signal when the state of the integrator is not between the first threshold and the second threshold.

[0056] Example 11. In any of the above examples, a digital modulator configured such that a variable gain block has a first gain value in response to a first output signal and a second gain value in response to a second output signal.

[0057] Example 12. In any of the above examples, a digital modulator in which an adder is configured to receive an "m" bit input signal, where "m" is an integer greater than 1, and a quantizer is configured to provide a single bit output signal.

[0058] Example 13. In any of the above examples, at least one integrator comprises a plurality of series-coupled integrators, a digital modulator.

[0059] Example 14. A digital modulator comprising, in any of the above examples, a loop filter interposed between at least one integrator and a quantizer.

[0060] Example 15. According to one embodiment, a method for operating a digital microphone comprises: monitoring the state of an integrator of the digital microphone; generating an output signal having a first level during a first state of the integrator and a second level during a second state of the integrator; controlling a parameter value of a signal processing component of the digital microphone with the output signal; and changing the operating mode of the digital microphone only during the first state of the integrator.

[0061] Example 16. A method of Example 15, further comprising the step of changing the loop gain of a digital microphone when the state of the integrator is within a predetermined range of values.

[0062] Example 17. In any of the above examples, the signal processing component comprises a digital modulator or an analog-to-digital converter (ADC) of a digital microphone.

[0063] Example 18. In any of the above examples, a method in which the parameter value of the signal processing component includes a gain value, a frequency value, or a capacitance value.

[0064] Example 19. In any of the above examples, a method wherein the parameter value includes a first value in a high signal-to-noise ratio (SNR) operating mode of the digital microphone and the parameter value includes a second value in a low SNR operating mode of the digital microphone.

[0065] Example 20. In any of the above examples, a method further comprising the step of generating a first level when the first state of the integrator is between a first threshold and a second threshold, and generating a second level when the second state of the integrator is not between a first threshold and a second threshold.

[0066] The digital components illustrated and described herein may be manufactured as digital circuit components in one or more integrated circuits. The digital components illustrated and described herein may also be implemented in a microprocessor that executes instructions to provide digital circuit component functions. Additionally, at least one of the digital components illustrated and described herein may be implemented as analog components. For example, an analog modulator may be used in some embodiments. Although a digital microphone has been described, the concepts of the embodiments may be implemented in an analog microphone having an integrator and a first (high-performance) operating mode and a second (low-power) operating mode, wherein dynamic switching is desired between the first operating mode and the second operating mode, or within one of the operating modes, without generating significant audio artifacts during switching events.

[0067] Although the present invention has been described with reference to exemplary embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of other embodiments of the invention, as well as the exemplary embodiments, will be apparent to those skilled in the art by referring to the description. Accordingly, the appended claims are intended to encompass any such modifications or embodiments.

Claims

Claim 1 As a digital microphone, at least one integrator; a state detection and parameter control component directly coupled to the output of the integrator; and includes a signal processing component coupled to the output of the state detection and parameter control component, wherein the parameter of the signal processing component includes a first output signal value in a first operating mode and a second output signal value in a second operating mode different from the first operating mode, and the parameter of the signal processing component includes a gain value, the state detection and parameter control component includes first and second thresholds, each of the first and second thresholds corresponds to an integrator output different from a digital or analog zero value, and the signal processing component includes a variable gain component configured to change gain values ​​when the output of the integrator is between the first threshold and the second threshold so that the parameter of the signal processing component of the digital microphone can be safely adjusted without causing audible artifacts, and the state detection and parameter control component generates the first output signal value when the output of the integrator is between the first threshold and the second threshold, and generates the second output signal value when the state of the integrator is not between the first threshold and the second threshold. Digital microphone configured. Claim 2 In claim 1, the signal processing component comprises a digital modulator or an analog-to-digital converter (ADC) of the digital microphone, a digital microphone. Claim 3 A digital microphone according to claim 1, wherein the parameters of the signal processing component further include the clock frequency of the digital microphone or the capacitance of one or more switched capacitors of the ADC. Claim 4 In claim 1, the digital microphone, wherein the at least one integrator comprises a plurality of series-coupled integrators. Claim 5 A digital microphone according to claim 1, wherein the at least one integrator, the state detection and parameter control component, and the signal processing component are manufactured in an application-specific integrated circuit (ASIC). Claim 6 In claim 5, a digital microphone further comprising a microelectromechanical system (MEMS) coupled to the ASIC, wherein the MEMS and the ASIC are manufactured in a semiconductor package. Claim 7 A digital modulator comprising: a summer; at least one integrator coupled to the summer; a quantizer coupled to the at least one integrator; a state detection and control component coupled to the output of the at least one integrator; and a variable gain block coupled between the state detection and control component and the summer, wherein the state detection and control component is configured to generate a first output signal when the output of the integrator is between a first threshold and a second threshold, and to generate a second output signal when the output of the integrator is not between the first threshold and the second threshold; and wherein the variable gain block is configured to have a first gain value in response to the first output signal and a second gain value in response to the second output signal. Claim 8 A digital modulator according to claim 7, wherein the summer is configured to receive an "m" bit input signal, "m" is an integer greater than 1, and the quantizer is configured to provide a single bit output signal. Claim 9 In claim 7, the digital modulator wherein the at least one integrator comprises a plurality of series-coupled integrators. Claim 10 A digital modulator according to claim 7, further comprising a loop filter interposed between at least one integrator and the quantizer. Claim 11 A method for operating a digital microphone, comprising: monitoring the state of an integrator of the digital microphone; generating an output signal having a first level during a first output of the integrator and a second level during a second output of the integrator; controlling a parameter value of a signal processing component of the digital microphone with the output signal, wherein the parameter of the signal processing component includes a gain value; and changing the operating mode of the digital microphone only during the first state of the integrator, and changing the loop gain of the digital microphone when the state of the integrator is within a predetermined range of values, wherein the loop gain change is achieved by adding a state detection and loop gain control block, wherein the state detection and loop gain control block has an input coupled to the output of the integrator and an output coupled to the control input of a loop filter. A method further comprising the step of generating the first level when the first output of the integrator is between the first threshold and the second threshold, and generating the second level when the second output of the integrator is not between the first threshold and the second threshold, so that the parameter of the signal processing component of the digital microphone can be safely adjusted without causing audible artifacts. Claim 12 In claim 11, the method wherein the signal processing component comprises a digital modulator or an analog-to-digital converter (ADC) of the digital microphone. Claim 13 In claim 11, the parameter value of the signal processing component further includes the clock frequency value of the digital microphone or the capacitance value of one or more switched capacitors of the ADC. Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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