Memory device and operating method thereof

Abstract

The present invention relates to an electronic device, and the memory device according to the present invention includes a precharge time information storage unit that stores information regarding a first precharge time for applying a bit line control signal determined according to the progress of a program operation and a second precharge time for applying a source line control signal, and a precharge voltage control unit that provides the bit line control signal and the source line control signal to page buffers and a source line driver during the longer precharge time between the first precharge time and the second precharge time during a program operation.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0002] A semiconductor device is a device that stores data by utilizing the characteristics of semiconductors. Semiconductor devices include memory systems that store data under the control of a host device, such as a computer or smartphone. A memory system may include a memory device where data is stored and a memory controller that controls the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

[0003] Non-volatile memory devices are memory devices in which data is not lost even when the power is cut off, and include ROM (Read Only Memory; ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and Flash Memory.

[0004] A non-volatile memory device performs a program operation to store data. The program operation can be performed by raising the voltages of the bit lines and source lines to target voltages and applying a program voltage to the word lines. If the number of bit lines to be raised to the target voltage is large or the magnitude of the target voltage to which the source lines must be raised is large, a large current is generated simultaneously within the non-volatile memory device; therefore, the time taken for the bit lines and source lines to rise to the target voltage can be adjusted to control the amount of current generated. The problem to be solved

[0005] An embodiment of the present invention provides a memory device capable of controlling the magnitude of the current generated during program operation and a method of operating the same. means of solving the problem

[0006] A memory device according to an embodiment of the present invention includes a precharge time information storage unit that stores information regarding a first precharge time for applying a bit line control signal determined according to the progress of a program operation and a second precharge time for applying a source line control signal, and a precharge voltage control unit that provides the bit line control signal and the source line control signal to page buffers and a source line driver during the longer precharge time between the first precharge time and the second precharge time during a program operation.

[0007] A memory device according to an embodiment of the present invention includes a precharge time information storage unit that stores information regarding a first precharge time during which the voltage of bit lines determined according to the progress of a program operation rises to a first precharge voltage and a second precharge time during which the voltage of a source line rises to the second precharge voltage, and a program operation control unit that controls the program operation such that during a precharge time among the first precharge time and the second precharge time, the voltage of the bit lines and the voltage of the source line rise to the first precharge voltage and the second precharge voltage, respectively.

[0008] A method of operating a memory device according to an embodiment of the present invention includes the steps of: storing information regarding a first precharge time during which the voltage of bit lines determined according to the progress of a program operation rises to a first precharge voltage and a second precharge time during which the voltage of a source line rises to the second precharge voltage; raising the voltage of the bit lines and the voltage of the source line to the first precharge voltage and the second precharge voltage, respectively, during a precharge time among the first precharge time and the second precharge time; and applying a program voltage to a word line connected to memory cells. Effects of the invention

[0009] According to the present technology, a memory device capable of controlling the magnitude of the current generated during program operation and a method of operating the same are provided. Brief explanation of the drawing

[0010] FIG. 1 is a drawing for explaining a memory system including a memory device according to an embodiment of the present invention. Figure 2 is a diagram illustrating the structure of the memory device of Figure 1. FIG. 3 is a diagram for explaining the structure of one of the multiple memory blocks (BLK1~BLKi) of FIG. 2. Figure 4 is a diagram illustrating the threshold voltage distribution of memory cells according to the program operation of a memory device. Figure 5 is a diagram illustrating the program operation of a memory device. Figure 6 is a diagram illustrating the program voltage application operation during the program operation of a memory device. FIG. 7 is a diagram illustrating a precharge section included in a program operation according to an embodiment of the present invention. FIG. 8 is a diagram illustrating the operation of bitline and source line linkage in a precharge section according to an embodiment of the present invention. FIG. 9 is a diagram illustrating another example of bitline and source line linkage operation in a precharge section according to an embodiment of the present invention. FIG. 10 is a diagram illustrating a program voltage application operation according to an embodiment of the present invention. FIG. 11 is a flowchart for explaining the program operation of a memory device according to an embodiment of the present invention. Specific details for implementing the invention

[0011] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0013] FIG. 1 is a drawing for explaining a memory system including a memory device according to an embodiment of the present invention.

[0014] Referring to FIG. 1, the memory system (50) may include a memory device (100) and a memory controller (200). The memory system (50) may be a device that stores data under the control of a host (300), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0015] The memory system (50) can be manufactured as any one of various types of storage devices according to the host interface, which is the method of communication with the host (300). For example, the memory system (50) can be configured as any one of various types of storage devices such as an SSD, MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD type secure digital card, USB (universal serial bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type storage device, PCI-E (PCI express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc.

[0016] The memory system (50) can be manufactured in any one of various types of package forms. For example, the memory system (50) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0017] The memory device (100) can store data. The memory device (100) operates in response to the control of the memory controller (200). The memory device (100) may include a memory cell array (not shown) comprising a plurality of memory cells that store data.

[0018] Memory cells can be configured as Single Level Cells (SLC) that store one bit of data, Multi Level Cells (MLC) that store two bits of data, Triple Level Cells (TLC) that store three bits of data, or Quad Level Cells (QLC) that can store four bits of data.

[0019] A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A single memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in a memory device (100) or reading data stored in a memory device (100). A memory block may be a unit for erasing data.

[0020] In the embodiment, the memory device (100) may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. For convenience of explanation, the present specification assumes that the memory device (100) is a NAND flash memory.

[0021] A memory device (100) receives a command and an address from a memory controller (200) and is configured to access an area selected by the address among memory cell arrays. The memory device (100) can perform operations instructed by the command on the area selected by the address. For example, the memory device (100) can perform a write operation (program operation), a read operation, and an erase operation. During a write operation, the memory device (100) will program data in the area selected by the address. During a read operation, the memory device (100) will read data from the area selected by the address. During an erase operation, the memory device (100) will erase data stored in the area selected by the address.

[0022] In an embodiment, the memory device (100) may include a precharge time information storage unit (140) and a program operation control unit (150).

[0023] The precharge time information storage unit (140) can store information regarding the time for applying a precharge voltage to the bit line and source line during a precharge operation. The precharge operation may be an operation included in the program operation. The precharge operation may be an operation that increases the voltage of the bit line and increases the voltage of the source line. The precharge time information storage unit (140) can store information regarding the time for applying a precharge voltage to the bit line and the time for applying a precharge voltage to the source line, determined according to the degree to which the program operation has progressed. In an embodiment, the degree to which the program operation has progressed may be the number of times a plurality of program loops have been performed. In another embodiment, the degree to which the program operation has progressed may be the number of memory cells programmed so that the memory cells have a threshold voltage corresponding to the target program state.

[0024] The program operation control unit (150) can control the program operation for memory cells. The program operation may be an operation of storing data in memory cells. Specifically, the program operation may be an operation of raising the threshold voltage of memory cells according to the data to be stored in the memory cells. When the program operation is performed, the memory cells may have a threshold voltage corresponding to any one of a plurality of program states. The plurality of program states may be determined according to the number of data bits stored in a single memory cell. For example, if a single memory cell is programmed as a Triple Level Cell (TLC) that stores three bits of data, the plurality of program states may mean an erase state and first to seventh program states. The threshold voltage of the memory cells after the program operation is performed may be determined according to the data to be stored in the memory cells. Each memory cell may have one of the plurality of program states as a target program state according to the data to be stored.

[0025] In an embodiment, the program operation may include a plurality of program loops. Each program loop may include a program voltage application operation and a verification operation. The program voltage application operation may be an operation of raising the threshold voltage of memory cells using a program voltage. The verification operation may be an operation of identifying whether the threshold voltage of memory cells has reached a threshold voltage corresponding to a target program state using a verification voltage.

[0026] The memory controller (200) can control the overall operation of the memory system (50).

[0027] When power is applied to the memory system (50), the memory controller (200) can execute firmware (FW). In an embodiment, the memory controller (200) can execute firmware to control communication between the host (300) and the memory device (100). In an embodiment, the memory controller (200) can convert the logical block address of the host to the physical block address of the memory device.

[0028] The memory controller (200) can control the memory device (100) to perform write operations, read operations, or erase operations, etc., according to a request from the host (300). When performing a write operation, the memory controller (200) can provide a write command, a physical block address, and data to the memory device (100). When performing a read operation, the memory controller (200) can provide a read command and a physical block address to the memory device (100). When performing an erase operation, the memory controller (200) can provide an erase command and a physical block address to the memory device (100).

[0029] In an embodiment, the memory controller (200) can independently generate commands, addresses, and data and transmit them to the memory device (100) regardless of a request from the host (300). For example, the memory controller (200) can provide commands, addresses, and data to the memory device (100) for performing read and write operations associated with performing wear leveling, read reclaim, garbage collection, etc.

[0030] In an embodiment, the memory controller (200) can control at least two memory devices (100). In this case, the memory controller (200) can control the memory devices (100) according to an interleaving method to improve operational performance. The interleaving method may be a method of controlling the operation of at least two memory devices (100) so that it overlaps.

[0031] The host (300) can communicate with the memory system (50) using at least one of various communication methods such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital) Card, MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0032] In an embodiment, the memory system (50) may include a buffer memory (not shown). For example, the buffer memory may temporarily store data received from the host (300) or data received from the memory device (100), or temporarily store metadata of the memory device (100) (e.g., a mapping table). The buffer memory may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0033] Figure 2 is a diagram illustrating the structure of the memory device of Figure 1.

[0034] Referring to FIG. 2, the memory device (100) may include a memory cell array (110), peripheral circuits (120), and control logic (130).

[0035] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKi). The plurality of memory blocks (BLK1 to BLKi) are connected to a row decoder (122) via local lines (LL). The plurality of memory blocks (BLK1 to BLKi) are connected to a page buffer group (123) via bit lines (BL1 to BLn). Each of the plurality of memory blocks (BLK1 to BLKi) includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells. A plurality of memory cells are defined as a single page if the memory cells connected to the same word line. That is, the memory cell array (110) is composed of a plurality of pages. According to an embodiment of the present invention, each of the plurality of memory blocks (BLK1 to BLKi) included in the memory cell array (110) may include a plurality of dummy cells. At least one dummy cell may be connected in series between the drain select transistor and the memory cells and between the source select transistor and the memory cells.

[0036] The memory cells of the memory device (100) may each be configured as a single-level cell (SLC) that stores one bit of data, a multi-level cell (MLC) that stores two bits of data, a triple-level cell (TLC) that stores three bits of data, or a quad-level cell (QLC) that can store four bits of data.

[0037] The peripheral circuit (120) drives the memory cell array (110). For example, the peripheral circuit (120) can drive the memory cell array (110) to perform program operations, read operations, and erase operations under the control of the control logic (130). As another example, the peripheral circuit (120) can apply various operating voltages to local lines (LL) and bit lines (BL1~BLn) or discharge the applied voltages under the control of the control logic (130).

[0038] Peripheral circuitry (120) may include a voltage generation circuit (121), a row decoder (122), a page buffer group (123), a column decoder (125), an input / output circuit (126), a pass / fail determination unit (127), and a source line driver (128). The row decoder (122) is connected to a memory cell array (110) via local lines (LL). Local lines (LL) may include drain select lines, word lines, and source select lines. According to an embodiment of the present invention, the word lines may include normal word lines and dummy word lines. According to an embodiment of the present invention, local lines (LL) may further include pipe select lines.

[0039] The row decoder (122) is configured to operate in response to the control of the control logic (130). The row decoder (122) receives address control signals (AD_signals) from the control logic (130).

[0040] The row decoder (122) is configured to decode a row address in response to an address control signal (AD_signals). The row decoder (122) can select at least one word line of a selected memory block by applying voltages provided from the voltage generation circuit (121) to at least one word line (WL) according to the decoded row address.

[0041] During program operation, the row decoder (122) will apply a program voltage to the selected word lines and a pass voltage of a level lower than the program voltage to the unselected word lines. During program verification operation, the row decoder (122) will apply a verification voltage to the selected word lines and a verification pass voltage of a level higher than the verification voltage to the unselected word lines.

[0042] During a read operation, the row decoder (122) will apply a read voltage to the selected word lines and apply a read pass voltage of a higher level than the read voltage to the unselected word lines.

[0043] The erase operation of the memory device (100) is performed in units of memory blocks. The address (ADD) input to the memory device (100) during the erase operation includes a block address. The row decoder (122) decodes the block address and can select one memory block according to the decoded block address.

[0044] The voltage generation circuit (121) is configured to generate multiple operating voltages (Vop) using an external power supply voltage supplied to the memory device (100). The voltage generation circuit (121) operates in response to the control of the control logic (130).

[0045] As an example, the voltage generation circuit (121) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generation circuit (121) is used as the operating voltage of the memory device (100).

[0046] As an example, the voltage generation circuit (121) can generate various operating voltages (Vop) used for program, read, and erase operations in response to an operation signal (OP_CMD). The voltage generation circuit (121) can generate multiple operating voltages (Vop) using an external power supply voltage or an internal power supply voltage. The voltage generation circuit (121) can be configured to generate various voltages required by the memory device (100). For example, the voltage generation circuit (121) can generate multiple erase voltages, multiple program voltages, multiple pass voltages, multiple select read voltages, and multiple non-select read voltages.

[0047] The voltage generation circuit (121) includes a plurality of pumping capacitors that receive an internal power supply voltage to generate a plurality of operating voltages (Vop) having various voltage levels, and will selectively activate the plurality of pumping capacitors in response to the control of the control logic (130) to generate a plurality of operating voltages (Vop).

[0048] The generated multiple operating voltages (Vop) can be supplied to the memory cell array (110) by the row decoder (122).

[0049] The page buffer group (123) includes first to n-th page buffers (PB1 to PBn). The first to n-th page buffers (PB1 to PBn) are each connected to a memory cell array (110) through first to n-th bit lines (BL1 to BLn). The first to n-th page buffers (PB1 to PBn) operate in response to the control of the control logic (130).

[0050] The first to nth page buffers (PB1 to PBn) communicate data (DATA) with the column decoder (125). During programming, the first to nth page buffers (PB1 to PBn) receive data (DATA) to be stored through the column decoder (125) and data lines (DL).

[0051] During a program operation, the first to n-th page buffers (PB1 to PBn) will transmit data (DATA) to be stored via the column decoder (125) to the selected memory cells via the bit lines (BL1 to BLn) when a program pulse is applied to a selected word line. The memory cells of the selected page are programmed according to the transmitted data (DATA). A memory cell connected to a bit line to which a program allow voltage (e.g., ground voltage) is applied will have an elevated threshold voltage. A memory cell connected to a bit line to which a program prohibit voltage (e.g., power supply voltage) is applied will have a maintained threshold voltage. During a program verification operation, the first to n-th page buffers (PB1 to PBn) read data (DATA) stored in the memory cells from the selected memory cells via the bit lines (BL1 to BLn).

[0052] When a read operation is performed, the page buffer group (123) can read data (DATA) from the memory cells of the selected page through bit lines (BL) and store the read data (DATA) in the first to nth page buffers (PB1~PBn).

[0053] During the erase operation, the page buffer group (123) can float bitlines (BL).

[0054] In an embodiment, while data stored in some of the page buffers among the plurality of page buffers included in the page buffer group (123) is programmed into the memory cell array (110), other page buffers can receive and store new data from the memory controller (200 of FIG. 1).

[0055] The column decoder (125) can transfer data between the input / output circuit (126) and the page buffer group (123) in response to a column address (CADD). For example, the column decoder (125) can exchange data with the page buffer group (123) via data lines (DL) or exchange data with the input / output circuit (126) via column lines (CL).

[0056] The input / output circuit (126) can transmit a command (CMD) and an address (ADD) received from the memory controller (200 in FIG. 1) to the control logic (130), or exchange data (DATA) with the column decoder (125).

[0057] The pass / fail determination unit (127) can generate a reference current in response to an allow bit (VRY_BIT<#>) signal generated by the control logic (130) during a read operation or a verification operation, and compare the sensing voltage (VPB) received from the page buffer group (123) with the reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic (130). For example, the pass / fail determination unit (127) can output a pass signal to the control logic (130) if the magnitude of the sensing voltage (VPB) is greater than the reference voltage. As another example, the pass / fail determination unit (127) can output a fail signal to the control logic (130) if the magnitude of the sensing voltage (VPB) is smaller than the reference voltage.

[0058] The source line driver (128) is connected to the memory cells included in the memory cell array (110) via the source line (SL) and can control the voltage applied to the source line (SL). In an embodiment, the source line driver (128) can generate a precharge voltage during a precharge operation and apply it to the source line (SL) of the memory cell array (110).

[0059] The source line driver (128) can receive a source line control signal (CTRL_SL) from the control logic (130) and can control the source line voltage applied to the source line (SL) based on the source line control signal (CTRL_SL).

[0060] The control logic (130) may be connected to a voltage generation circuit (121), a row decoder (122), a page buffer group (123), a column decoder (124), and a pass / fail determination unit (127). The control logic (130) may be configured to control the general operation of the memory device (100). The control logic (130) may operate in response to a command (CMD) transmitted from an external device.

[0061] The control logic (130) can control the peripheral circuit (120) by generating various signals in response to the command (CMD) and address (ADD). For example, the control logic (130) can generate an operation signal (OP_CMD), an address control signal (AD_signals), a page buffer control signal (PBSIGNALS), an allow bit (VRY_BIT<#>), and a source line control signal (CTRL_SL) in response to the command (CMD) and address (ADD). The control logic (130) can output the operation signal (OP_CMD) to the voltage generation circuit (121), the address control signal (AD_signals) to the row decoder (122), the page buffer control signal (PBSIGNALS) to the page buffer group (123), the allow bit (VRY_BIT<#>) to the pass / fail determination unit (127), and the source line control signal (CTRL_SL) to the source line driver (128). Additionally, the control logic (130) can determine whether the verification operation has passed or failed in response to the pass or fail signal (PASS / FAIL) output by the pass / fail determination unit (127).

[0062] The precharge time information storage unit (140) and program operation control unit (150) illustrated in FIG. 1 may be included in the control logic (130) of FIG. 2.

[0063] The program operation control unit (150) can control the peripheral circuit (120) to perform program operations on memory cells. The program operation control unit (150) can control the peripheral circuit (120) to apply operation voltages (Vop) to be used for program operations to row lines (RL) and bit lines (BL1~BLn). The program operation control unit (150) can determine the time to apply a page buffer control signal (PBSIGNALS) to the page buffer group (123) and the time to apply a source line control signal (CTRL_SL) to the source line driver (128) during a precharge operation based on information regarding the precharge time stored in the precharge time information storage unit (140).

[0064] FIG. 3 is a diagram for explaining the structure of one of the multiple memory blocks (BLK1~BLKi) of FIG. 2.

[0065] Memory block (BLKi) represents any one of the memory blocks (BLK1~BLKi) shown in FIG. 2.

[0066] Referring to FIG. 3, a plurality of word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. Here, the first selection line may be a source selection line (SSL), and the second selection line may be a drain selection line (DSL). More specifically, a memory block (BLKi) may include a plurality of strings (ST) connected between bit lines (BL1~BLn) and a source line (SL). Bit lines (BL1~BLn) may each be connected to the strings (ST), and the source line (SL) may be connected to the strings (ST) in common. Since the strings (ST) may be configured identically, the string (ST) connected to the first bit line (BL1) will be described specifically as an example.

[0067] A string (ST) may include a source select transistor (SST), a plurality of memory cells (MC1 to MC16), and a drain select transistor (DST) connected in series between a source line (SL) and a first bit line (BL1). A single string (ST) may include at least one source select transistor (SST) and one drain select transistor (DST), and may also include more memory cells (MC1 to MC16) than the number shown in the drawing.

[0068] The source of the source select transistor (SST) can be connected to the source line (SL), and the drain of the drain select transistor (DST) can be connected to the first bit line (BL1). Memory cells (MC1~MC16) can be connected in series between the source select transistor (SST) and the drain select transistor (DST). The gates of the source select transistors (SST) included in different strings (ST) can be connected to the source select line (SSL), the gates of the drain select transistors (DST) can be connected to the drain select line (DSL), and the gates of the memory cells (MC1~MC16) can be connected to multiple word lines (WL1~WL16). Among the memory cells included in different strings (ST), a group of memory cells connected to the same word line can be called a physical page (PG). Accordingly, the memory block (BLKi) may contain as many physical pages (PG) as there are word lines (WL1~WL16).

[0069] A single memory cell can store one bit of data. This is commonly referred to as a single-level cell (SLC). In this case, a single physical page (PG) can store one logical page (LPG) of data. One logical page (LPG) of data can contain as many data bits as the number of cells contained within a single physical page (PG).

[0070] A single memory cell can store two or more bits of data. In this case, a single physical page (PG) can store two or more logical pages (LPG) of data.

[0071] Figure 4 is a diagram illustrating the threshold voltage distribution of memory cells according to the program operation of a memory device.

[0072] In Figure 4, the horizontal axis of the graph represents the threshold voltage (Vth) of the memory cells, and the vertical axis of the graph represents the number of memory cells (# of cells).

[0073] Referring to Fig. 4, the threshold voltage distribution of memory cells can change from an initial state to a final program state depending on the program operation.

[0074] Figure 4 explains the case assuming that one memory cell is programmed as TLC to store three bits of data.

[0075] The initial state is a state where no program operation is performed, and the threshold voltage distribution of the memory cells may be in an erased state (E).

[0076] The final program state may be the threshold voltage distribution of the memory cells that performed the program operation. The threshold voltage of the memory cells that performed the program operation may have a threshold voltage corresponding to any one of the multiple program states. For example, if a single memory cell is programmed as a TLC storing three bits of data, the multiple program states may refer to an erase state (E) and first to seventh program states (PV1~PV7). In the embodiment, the threshold voltage of the memory cells that performed the program operation may have a threshold voltage corresponding to any one of the erase state (E) and first to seventh program states (PV1~PV7). The threshold voltage of the memory cells in the initial state may be raised through the program operation to a threshold voltage corresponding to any one of the erase state (E) and first to seventh program states (PV1~PV7).

[0077] Each memory cell may have an erase state (E) and one of the first to seventh program states (PV1~PV7) as a target program state. The target program state may be determined based on the data to be stored in the memory cell. Each memory cell may have a threshold voltage corresponding to the target program state among the final program states through a program operation.

[0078] Figure 5 is a diagram illustrating the program operation of a memory device.

[0079] In FIG. 5, the horizontal axis of the graph represents time, and the vertical axis of the graph represents the voltage (V) applied to the word line. The voltage (V) applied to the word line may include a program voltage (Vpgm) and a verification voltage (V_vfy).

[0080] Figure 5 describes the case where a single memory cell is programmed as a TLC to store three bits of data. However, the scope of the present invention is not limited thereto, and a single memory cell may be programmed to store two bits or less of data or four bits or more of data.

[0081] Referring to FIGS. 1 and FIGS. 5, the program operation of the memory device (100) may include a plurality of program loops (PL1 to PLn). The memory device (100) may perform a program operation by executing a plurality of program loops (PL1 to PLn) so that selected memory cells connected to selected word lines have a threshold voltage corresponding to any one of a plurality of program states. For example, when a memory cell is programmed as TLC, the memory device (100) may perform a program operation by executing a plurality of program loops (PL1 to PLn) so that it has a threshold voltage corresponding to an erase state (E) or any one of the first to seventh program states (PV1 to PV7).

[0082] Each of the multiple program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step).

[0083] The program voltage application operation (PGM Step) may be an operation of applying a program voltage to a selected word line connected to selected memory cells. For example, the memory device (100) may apply a first program voltage (Vpgm1) to a selected word line connected to selected memory cells in a first program loop (PL1). After the first program voltage (Vpgm1) is applied to the selected word line, the threshold voltage of each of the selected memory cells may have a threshold voltage corresponding to a target program state among a plurality of program states.

[0084] The Verify Step may be an operation of applying a verification voltage to a selected word line connected to selected memory cells. The Verify Step may be an operation of determining whether the threshold voltage of each of the selected memory cells has a threshold voltage corresponding to a target program state among a plurality of program states. The Verify Step may be an operation of applying a verification voltage corresponding to a target program state of each of the selected memory cells.

[0085] In an embodiment, the memory device (100) may apply first to seventh verification voltages (V_vfy1 to V_vfy7) after applying a first program voltage (Vpgm1) to a selected word line connected to selected memory cells in a first program loop (PL1). The memory device (100) may apply a verification voltage corresponding to the target program state of the memory cells among the first to seventh verification voltages (V_vfy1 to V_vfy7) to the selected word line. For example, the memory device (100) may perform a verification operation (Verify Step) for memory cells whose target program state is the first program state using the first verification voltage (V_vfy1). The magnitude of the verification voltages (V_vfy1 to V_vfy7) may increase as it goes from the first verification voltage (V_vfy1) to the seventh verification voltage (V_vfy7). Specifically, the magnitudes of the verification voltages (V_vfy1 to V_vfy7) may be such that the first verification voltage (V_vfy1) is the smallest and the seventh verification voltage (V_vfy7) is the largest. The number of verification voltages is not limited to this embodiment.

[0086] The threshold voltage of memory cells that have passed the Verify Step by each of the Verify voltages (V_vfy1~V_vfy7) can be determined to have a threshold voltage corresponding to the target program state. Memory cells that have passed the Verify Step can be programmed inhibited in the second program loop (PL2). A program inhibit voltage can be applied to the bit lines connected to the programmed memory cells.

[0087] The threshold voltage of memory cells for which the Verify Step failed by each of the verification voltages (V_vfy1~V_vfy7) can be determined to not have a threshold voltage corresponding to the target program state. Memory cells for which the Verify Step failed can perform the second program loop (PL2).

[0088] In the second program loop (PL2), the memory device (100) can apply a second program voltage (Vpgm2) that is higher than the first program voltage (Vpgm1) by a unit voltage (△Vpgm) to a selected word line connected to the selected memory cells. Afterward, the memory device (100) can perform the verification step of the second program loop (PL2) in the same way as the verification step of the first program loop (PL1).

[0089] Afterwards, the memory device (100) can perform the next program loop in the same way as the second program loop (PL2) a preset number of times.

[0090] In an embodiment, if the program operation is not completed within a preset number of program loops, the program operation may fail. If the program operation is completed within a preset number of program loops, the program operation may pass. Whether the program operation is completed may be determined by whether all verification steps for the selected memory cells have passed. If the verification steps for all selected memory cells have passed, the next program loop may not be executed.

[0091] In the embodiment, the program voltage can be determined according to the Incremental Step Pulse Programming (ISPP) method. The level of the program voltage can be increased or decreased stepwise as the program loops (PL1 to PLn) are repeated. The number of times the program voltages used in each program loop are applied, the voltage level, and the voltage application time can be determined in various forms according to the control of the memory controller (200).

[0092] Figure 6 is a diagram illustrating the program voltage application operation during the program operation of a memory device.

[0093] Referring to FIG. 6, the program operation may include a plurality of program loops (PL1 to PLn). Each of the plurality of program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step). The program voltage application operation (PGM Step) may include a precharge section (Precharge), a program pulse section (Pgm Pulse), and a discharge section (Discharge).

[0094] The interval t1 to t2 may be a precharge interval. The precharge interval may be a interval for precharging the voltage of the bit line (BL) and the voltage of the source line (SL). In the precharge interval, the voltage of the bit line connected to the memory cell having a threshold voltage corresponding to the target program state may rise to a first precharge voltage (Vpre1). The first precharge voltage (Vpre1) may be a program prohibition voltage. In an embodiment, the first precharge voltage (Vpre1) may be a voltage greater than the ground voltage (Gnd). In another embodiment, the first precharge voltage (Vpre1) may be a power supply voltage. In the precharge interval, the voltage of the bit line connected to the memory cell that does not have a threshold voltage corresponding to the target program state may maintain the ground voltage (Gnd). The ground voltage (Gnd) may be a program allowance voltage. The voltage of the bit line can rise to a first precharge voltage (Vpre1) in response to a page buffer control signal (PBSIGNALS) received from the control logic (130) shown in FIG. 2.

[0095] In the precharge period, the voltage of the source line (SL) can rise to a second precharge voltage (Vpre2). When the voltage of the source line rises to the second precharge voltage (Vpre2), the channel potential of the memory cells can rise. The voltage of the source line can rise to the second precharge voltage (Vpre2) in response to a source line control signal (CTRL_SL) received from the control logic (130) shown in FIG. 2. In an embodiment, the magnitude of the second precharge voltage (Vpre2) may be equal to the magnitude of the first precharge voltage (Vpre1). In another embodiment, the magnitude of the second precharge voltage (Vpre2) may be a voltage smaller than the first precharge voltage (Vpre1).

[0096] The interval t2~t3 may be a program pulse interval (Pgm Pulse). The program pulse interval (Pgm Pulse) may be an interval for raising the threshold voltage of selected memory cells among a plurality of memory cells. During the program pulse interval (Pgm Pulse), the memory device (100) may apply a program voltage (Vpgm) to the selected word line (Sel_WL). During the program pulse interval (Pgm Pulse), the memory device (100) may apply a pass voltage (Vpass) to the unselected word lines (Unsel_WL).

[0097] The t3~t4 interval may be a discharge interval. The discharge interval may be an interval for lowering the voltage of the selected word line (Sel_WL), unselected word lines (Unsel_WL), and source line (SL). During the discharge interval, the memory device (100) may apply a ground voltage (Gnd) to the selected word line (Sel_WL). During the discharge interval, the memory device (100) may apply a ground voltage (Gnd) to the unselected word lines (Unsel_WL). During the discharge interval, the voltage of the source line (SL) may be lowered to the ground voltage (Gnd).

[0098] FIG. 7 is a diagram illustrating a precharge section included in a program operation according to an embodiment of the present invention.

[0099] Referring to FIGS. 1 and FIGS. 7, the program operation may include a plurality of program loops (PL1 to PLn). Each of the plurality of program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step). The program voltage application operation (PGM Step) may include a precharge section (Precharge), a program pulse section (Pgm Pulse), and a discharge section (Discharge). In FIGS. 7, only the precharge section (Precharge) of the program voltage application operation (PGM Step) will be described.

[0100] The memory device (100) may apply a bitline control signal (PBSENSE) to the page buffer during the precharge period. The magnitude of the bitline control signal (PBSENSE) may rise at a constant slope during the precharge period. The bitline control signal (PBSENSE) may be a control signal that raises the voltage of a bitline connected to the page buffer. For example, the bitline control signal (PBSENSE) may be a control signal included in the page buffer control signal (PBSIGNALS) provided by the control logic (130) shown in FIG. 2. In an embodiment, the voltage of the bitline may rise to a first precharge voltage (Vpre1) in response to the bitline control signal (PBSENSE).

[0101] The memory device (100) can apply a source line control signal (CTRL_SL) to the source line driver during the precharge period. The source line control signal (CTRL_SL) may be a control signal that increases the voltage of the source line connected to the source line driver. In an embodiment, the voltage of the source line may increase to a second precharge voltage (Vpre2) in response to the source line control signal (CTRL_SL).

[0102] The t1~t2 interval may be the precharge interval of the first program loop (PL1).

[0103] Specifically, in the interval t1 to t11, the memory device (100) can apply a bitline control signal (PBSENSE) having a magnitude of a first bitline control voltage (Vp1) to the page buffer. In the interval t11 to t12, the memory device (100) can increase the magnitude of the bitline control signal (PBSENSE) from the first bitline control voltage (Vp1) to the second bitline control voltage (Vp2). In the interval t11 to t12, the slope of the increase from the first bitline control voltage (Vp1) to the second bitline control voltage (Vp2) may be the first slope (△S1). In the interval t12 to t2, the memory device (100) can apply a bitline control signal (PBSENSE) having a magnitude of the second bitline control voltage (Vp2) to the page buffer. A bitline control signal (PBSENSE) can be applied to the page buffer during a zero bitline precharge time (Pret_bl0) corresponding to the interval t1 to t2. During the interval t1 to t2, the voltage of the bitline can rise to a first precharge voltage (Vpre1) in response to the bitline control signal (PBSENSE).

[0104] During the interval t1 to t2, the memory device (100) may not apply a source line control signal (CTRL_SL) to the source line driver. For example, the memory device (100) may apply a source line control signal (CTRL_SL) having a magnitude of ground voltage (Gnd) to the source line driver. During the interval t1 to t2, the voltage of the source line may maintain the ground voltage (Gnd) in response to the source line control signal (CTRL_SL).

[0105] The interval t3~t4 may be the precharge interval of the i-th program loop (PLi).

[0106] Specifically, in the interval t3 to t31, the memory device (100) may apply a bitline control signal (PBSENSE) having a first bitline control voltage (Vp1) to the page buffer. In the interval t31 to t32, the memory device (100) may increase the magnitude of the bitline control signal (PBSENSE) from the first bitline control voltage (Vp1) to the second bitline control voltage (Vp2). In the interval t31 to t32, the slope of the bitline control signal (PBSENSE) rising from the first bitline control voltage (Vp1) to the second bitline control voltage (Vp2) may be a second slope (△S2). The second slope (△S2) may be smaller than the first slope (△S1). In the interval t32 to t4, the memory device (100) may apply a bitline control signal (PBSENSE) having a second bitline control voltage (Vp2) to the page buffer. The bitline control signal (PBSENSE) may be applied to the page buffer during a first bitline precharge time (Pret_bl1) corresponding to the interval t3 to t4. The first bitline precharge time (Pret_bl1) may be longer than the zero bitline precharge time (Pret_bl0). In the interval t3 to t4, the voltage of the bitline may rise to the first precharge voltage (Vpre1) in response to the bitline control signal (PBSENSE).

[0107] When a program is executed, among multiple program loops, there may be a program loop in which many memory cells rise to a threshold voltage corresponding to the target program state. In this case, a first precharge voltage (Vpre1) may need to be applied to the bit lines connected to the memory cells that have risen to the threshold voltage corresponding to the target program state. That is, as the number of memory cells that have risen to the threshold voltage corresponding to the target program state increases, the number of bit lines to which the first precharge voltage must be applied also increases, and thus a large current may be generated simultaneously in the bit lines. Accordingly, to control the amount of current generated, the slope of the rising bit line control signal (PBSENSE) can be adjusted.

[0108] In the interval t3 to t32, the memory device (100) may apply a source line control signal (CTRL_SL) having a magnitude of a first source line control voltage (Vc1) to the source line driver. In the interval t3 to t32, the voltage of the source line may rise to a second precharge voltage (Vpre2) in response to the source line control signal (CTRL_SL). The source line control signal (CTRL_SL) may be applied to the source line driver during a first source line precharge time (Pret_sl1) corresponding to the interval t3 to t32. The voltage of the source line may rise to a second precharge voltage (Vpre2) during the first source line precharge time (Pret_sl1).

[0109] In the precharge period of the i-th program loop (PLi), the first bitline precharge time (Pret_bl1) during which the bitline control signal (PBSENSE) is applied and the first source line precharge time (Pret_sl1) during which the source line control signal (CTRL_SL) is applied may be different. Specifically, the first bitline precharge time (Pret_bl1) may be longer than the first source line precharge time (Pret_sl1). Since the precharge period of the i-th program loop (PLi) extends until the t4 period during which the application of the bitline control signal (PBSENSE) ends, the source line control signal (CTRL_SL) may be applied until the t4 period, which is after the t32 period.

[0110] The interval t5~t6 may be the precharge interval of the nth program loop (PLn).

[0111] Specifically, in the interval t5 to t51, the memory device (100) may apply a bitline control signal (PBSENSE) having a first bitline control voltage (Vp1) to the page buffer. In the interval t51 to t52, the memory device (100) may increase the magnitude of the bitline control signal (PBSENSE) from the first bitline control voltage (Vp1) to the second bitline control voltage (Vp2). In the interval t51 to t52, the slope of the increase from the first bitline control voltage (Vp1) to the second bitline control voltage (Vp2) may be the first slope (△S1). In the interval t52 to t53, the memory device (100) may apply a bitline control signal (PBSENSE) having a second bitline control voltage (Vp2) to the page buffer. A bitline control signal (PBSENSE) may be applied to the page buffer during a zero bitline precharge time (Pret_bl0) corresponding to the interval t5 to t53. The time during which the bitline control signal is applied in the nth program loop (PLn) may be shorter than the time during which the bitline control signal is applied in the ith program loop (PLi). In the interval t5 to t53, the voltage of the bitline may rise to a first precharge voltage (Vpre1) in response to the bitline control signal (PBSENSE).

[0112] In the interval t5 to t6, the memory device (100) may apply a source line control signal (CTRL_SL) having a magnitude of a second source line control voltage (Vc2) to the source line driver. The magnitude of the second source line control voltage (Vc2) may be greater than the first source line control voltage (Vc1). In the interval t5 to t6, the voltage of the source line may rise to a third precharge voltage (Vpre3) in response to the source line control signal (CTRL_SL). The magnitude of the third precharge voltage (Vpre3) may be greater than the second precharge voltage (Vpre2). The source line control signal may be applied to the source line driver during a second source line precharge time (Pret_sl2) corresponding to the interval t5 to t6. The voltage of the source line may rise to the third precharge voltage (Vpre3) during the second source line precharge time (Pret_sl2). Since the magnitude of the voltage rise of the source line in the nth program loop (PLn) is greater than the magnitude of the voltage rise of the source line in the ith program loop (PLi), the source line precharge time in the nth program loop (PLn) may be longer than the source line precharge time in the ith program loop (PLi). The second source line precharge time (Pret_sl2) may be longer than the zero bit line precharge time (Pret_bl0). Since the precharge period of the nth program loop (PLn) is until the t6 period when the application of the source line control signal (CRTL_SL) ends, the bit line control signal (PBSENSE) may be applied until the t6 period, which is after the t53 period.

[0113] In one embodiment, the memory device (100) may determine the time for applying a bitline control signal according to the number of times a program loop is performed. In another embodiment, the memory device (100) may determine the time for applying a bitline control signal according to the number of memory cells having a threshold voltage corresponding to a target program state during a program operation. In yet another embodiment, the memory device (100) may determine the time for applying a bitline control signal according to the number of bitlines that need to rise to a first precharge voltage (Vpre1) during a program operation.

[0114] In an embodiment, the memory device (100) can determine the time for applying a source line control signal according to the magnitude of the rise in the voltage of the source line. For example, if the magnitude of the rise in the voltage of the source line is small, the time for applying the source line control signal may be short. As another example, if the magnitude of the rise in the voltage of the source line is large, the time for applying the source line control signal may be long.

[0115] The memory device (100) can store information regarding the time for applying a bitline control signal and the time for applying a source line control signal, determined according to the degree of program operation progress. For example, the degree of program operation progress may refer to the number of times multiple program loops have been executed. As another example, the degree of program operation progress may refer to the number of memory cells having a threshold voltage corresponding to a target program state. The memory device (100) can store information regarding the time for applying a bitline control signal and the time for applying a source line control signal in the precharge time information storage unit (140) shown in FIG. 1. As described through FIG. 7, the memory device (100) can apply a bitline control signal to the page buffer during a bitline precharge time determined according to the degree of program operation progress, and apply a source line control signal to the source line driver during a source line precharge time determined according to the degree of program operation progress.

[0116] Multiple program loops (PL1 to PLn) can be divided into an initial period, a middle period, and a final period. For example, as illustrated in FIG. 7, the initial period may be the first program loop (PL1), the middle period may be the i-th program loop (PLi), and the final period may be the n-th program loop (PLn). In the middle period, the bitline precharge time may be longer than the source line precharge time. In the final period, the source line precharge time may be longer than the bitline precharge time.

[0117] FIG. 8 is a diagram illustrating the operation of bitline and source line linkage in a precharge section according to an embodiment of the present invention.

[0118] In Fig. 8, details that overlap with Fig. 7 will be omitted. In Fig. 8, only the precharge section during the program voltage application operation (PGM Step) will be described.

[0119] Referring to FIGS. 1 and FIGS. 8, the interval t3 to t4 may be a precharge interval of the i-th program loop (PLi).

[0120] Specifically, in the interval t3 to t4, the memory device (100) can apply a bitline control signal (PBSENSE) to the page buffer. The bitline control signal (PBSENSE) can be applied to the page buffer during a first bitline precharge time (Pret_bl1) corresponding to the interval t3 to t4.

[0121] In the interval t3 to t4, the memory device (100) can apply a source line control signal (CTRL_SL) having a magnitude of the first source line control voltage (Vc1) to the source line driver. The source line control signal (CTRL_SL) can be applied to the source line driver during the first bit line precharge time (Pret_bl1) corresponding to the interval t3 to t4.

[0122] In the precharge period of the i-th program loop (PLi), the memory device (100) can compare the bitline precharge time and the source line precharge time. The memory device (100) can apply the bitline control signal (PBSENSE) and the source line control signal (CTRL_SL) to the page buffer and the source line driver, respectively, during the longer precharge time between the bitline precharge time and the source line precharge time. In an embodiment, as in the i-th program loop (PLi) of FIG. 7, if the bitline precharge time is longer than the source line precharge time, the memory device (100) can apply the bitline control signal (PBSENSE) and the source line control signal (CTRL_SL) to the page buffer and the source line driver during the first bitline precharge time (Pret_bl1) in the i-th program loop (PLi). The voltage of the bit line can rise to the first precharge voltage (Vpre1) during the first bit line precharge time (Pret_bl1). The voltage of the source line can rise to the second precharge voltage (Vpre2) during the first bit line precharge time (Pret_bl1).

[0123] The interval t5~t6 may be the precharge interval of the nth program loop (PLn).

[0124] Specifically, in the interval t5 to t6, the memory device (100) can apply a bitline control signal (PBSENSE) to the page buffer. The bitline control signal (PBSENSE) can be applied to the page buffer during a second source line precharge time (Pret_sl2) corresponding to the interval t5 to t6.

[0125] In the interval t5 to t6, the memory device (100) can apply a source line control signal (CTRL_SL) having a magnitude of the second source line control voltage (Vc2) to the source line driver. The source line control signal (CTRL_SL) can be applied to the source line driver during the second source line precharge time (Pret_sl2) corresponding to the interval t5 to t6.

[0126] In the precharge period of the nth program loop (PLn), the memory device (100) can compare the bitline precharge time and the source line precharge time. In an embodiment, if the source line precharge time is longer than the bitline precharge time, as in the nth program loop (PLn) of FIG. 7, the memory device (100) can apply a bitline control signal (PBSENSE) and a source line control signal (CTRL_SL) to the page buffer and the source line driver during the second source line precharge time (Pret_sl2) in the nth program loop (PLn). In the nth program loop (PLn), the bitline control signal can be applied to the page buffer during the second source line precharge time (Pret_sl2), which is longer than the zero bitline precharge time (Pret_bl0) described in FIG. 7. That is, the slope of the rising bitline control signal (PBSENSE) in the nth program loop (PLn) of Fig. 8 may be smaller than the slope of the rising bitline control signal (PBSENSE) in the nth program loop (PLn) of Fig. 7.

[0127] The voltage of the bit line can rise to the first precharge voltage (Vpre1) during the second source line precharge time (Pret_sl2). The voltage of the source line can rise to the third precharge voltage (Vpre3) during the second source line precharge time (Pret_sl2).

[0128] In an embodiment, the memory device (100) can compare the bitline precharge time and the source line precharge time in each of the plurality of program loops. The memory device (100) can apply the bitline control signal and the source line control signal to the page buffer and the source line driver during the longer precharge time between the bitline precharge time and the source line precharge time in each of the plurality of program loops.

[0129] FIG. 9 is a diagram illustrating another example of bitline and source line linkage operation in a precharge section according to an embodiment of the present invention.

[0130] In FIG. 9, content that overlaps with FIG. 7 and FIG. 8 will be omitted. In FIG. 9, only the precharge section during the program voltage application operation (PGM Step) will be described.

[0131] Referring to FIGS. 1 and FIGS. 9, the interval t3 to t4 may be a precharge interval of the i-th program loop (PLi).

[0132] Specifically, in the interval t3 to t4, the memory device (100) can apply a bitline control signal (PBSENSE) to the page buffer. The bitline control signal (PBSENSE) can be applied to the page buffer during the source line precharge time (Pret_sl) corresponding to the interval t3 to t4.

[0133] In the interval t3 to t4, the memory device (100) can apply a source line control signal (CTRL_SL) having a magnitude of the second source line control voltage (Vc2) to the source line driver. The source line control signal (CTRL_SL) can be applied to the source line driver during a source line precharge time (Pret_sl) corresponding to the interval t3 to t4.

[0134] In the embodiment, unlike the case where the bitline precharge time is longer than the source line precharge time in the i-th program loop (PLi) of FIG. 7, the source line precharge time may be longer than the bitline precharge time in the i-th program loop (PLi) of FIG. 9. At this time, the memory device (100) may apply a bitline control signal (PBSENSE) and a source line control signal (CTRL_SL) to the page buffer and the source line driver during the source line precharge time (Pret_sl) in the i-th program loop (PLi). The voltage of the bitline may rise to a first precharge voltage (Vpre1) during the source line precharge time (Pret_sl). The voltage of the source line may rise to a third precharge voltage (Vpre3) during the source line precharge time (Pret_sl).

[0135] The interval t5~t6 may be the precharge interval of the nth program loop (PLn).

[0136] Specifically, in the interval t5 to t6, the memory device (100) can apply a bitline control signal (PBSENSE) to the page buffer. The bitline control signal (PBSENSE) can be applied to the page buffer during the source line precharge time (Pret_sl) corresponding to the interval t5 to t6.

[0137] In the interval t5 to t6, the memory device (100) may apply a source line control signal (CTRL_SL) having a magnitude of the second source line control voltage (Vc2) to the source line driver. The source line control signal (CTRL_SL) may be applied to the source line driver during the source line precharge time (Pret_sl) corresponding to the interval t5 to t6. In the nth program loop (PLn), the memory device (100) may apply a bit line control signal (PBSENSE) and a source line control signal (CTRL_SL) to the page buffer and the source line driver during the source line precharge time (Pret_sl). The voltage of the bit line may rise to the first precharge voltage (Vpre1) during the source line precharge time (Pret_sl). The voltage of the source line may rise to the third precharge voltage (Vpre3) during the source line precharge time (Pret_sl).

[0138] FIG. 10 is a diagram illustrating a program voltage application operation according to an embodiment of the present invention.

[0139] The memory device (100) illustrated in FIG. 1 may include control logic (1000), a voltage generation unit (1100), a source line driver (1200), a page buffer (1300), and a memory cell array (1400).

[0140] The control logic (1000) can be implemented as a component of the control logic (130) shown in FIG. 2. The voltage generation unit (1100) may include the voltage generation circuit (121) and row decoder (122) shown in FIG. 2. The source line driver (1200) can be implemented as a component of the source line driver (128) shown in FIG. 2. The page buffer (1300) can be implemented as a component of the page buffer group (123) shown in FIG. 2.

[0141] The control logic (1000) may include a program operation control unit (1010) and a precharge time information storage unit (1020). The program operation control unit (1010) can control the program operation for the memory cell array (1400). The precharge time information storage unit (1020) can store information regarding the bitline precharge time and source line precharge time determined according to the progress of the program operation.

[0142] The program operation control unit (1010) may include a wordline voltage control unit (1011) and a precharge voltage control unit (1012). The wordline voltage control unit (1011) can control the voltage to be applied to the wordline connected to the memory cells. The wordline voltage control unit (1011) can provide a wordline voltage control signal (OP_CMD) to the voltage generation unit (1100) to generate a voltage (V_wl) to be applied to the wordline.

[0143] The precharge voltage control unit (1012) can provide a source line control signal (CTRL_SL) and a bit line control signal (PBSENSE) to the source line driver (1200) and the page buffer (1300) based on information regarding the precharge time (Pret_inf) received from the precharge time information storage unit (1020). The information regarding the precharge time (Pret_inf) may include information regarding the bit line precharge time and the source line precharge time.

[0144] In an embodiment, the precharge voltage control unit (1012) can provide a bitline control signal (PBSENSE) to the page buffer (1300) during the bitline precharge time in the first precharge mode, and provide a source line control signal (CTRL_SL) to the source line driver (1200) during the source line precharge time. That is, as described in FIG. 7, the precharge voltage control unit (1012) can provide the bitline control signal (PBSENSE) and the source line control signal (CTRL_SL) to the page buffer (1300) and the source line driver (1200), respectively, during the bitline precharge time and the source line precharge time determined according to the progress of the program operation.

[0145] In another embodiment, the precharge voltage control unit (1012) may provide a bitline control signal (PBSENSE) and a source line control signal (CTRL_SL) to the page buffer (1300) and the source line driver (1200) for the longer of the bitline precharge time and the source line precharge time determined according to the progress of the program operation in the second precharge mode as described in FIG. 8. The precharge voltage control unit (1012) may compare the bitline precharge time and the source line precharge time in each of the plurality of program loops. In an embodiment, the precharge voltage control unit (1012) may include a precharge time comparison unit that compares the bitline precharge time and the source line precharge time in each of the plurality of program loops. The precharge time comparison unit may determine the longer of the bitline precharge time and the source line precharge time as the precharge time.

[0146] The voltage generation unit (1100) can generate a voltage (V_wl) to be applied to a word line in response to a word line voltage control signal (OP_CMD) and provide it to the memory cell array (1400). The voltage (V_wl) to be applied to the word line may be a program voltage or a pass voltage.

[0147] The source line driver (1200) can provide a second precharge voltage (V_pre2) to the memory cell array (1400) in response to a source line control signal (CTRL_SL). The source line connected between the source line driver (1200) and the memory cell array (1400) can rise to the second precharge voltage (V_pre2) according to the source line control signal (CTRL_SL).

[0148] The page buffer (1300) can provide a first precharge voltage (V_pre1) to the memory cell array (1400) in response to a bitline control signal (PBSENSE). A bitline connected between the page buffer (1300) and the memory cell array (1400) can rise to the first precharge voltage (V_pre1) according to the bitline control signal (PBSENSE).

[0149] FIG. 11 is a flowchart for explaining the program operation of a memory device according to an embodiment of the present invention.

[0150] Referring to FIG. 11, in step S1101, the memory device (100) may store precharge information regarding a first precharge time and a second precharge time determined according to the progress of the program operation. The first precharge time may be a bitline precharge time. The second precharge time may be a source line precharge time.

[0151] In step S1103, the memory device (100) may compare a first precharge time and a second precharge time. If the first precharge time is longer than the first precharge time and the second precharge time, step S1105 may be performed. Alternatively, if the second precharge time is longer than the first precharge time and the second precharge time, step S1107 may be performed.

[0152] In step S1105, the memory device (100) may raise the voltage of the bit lines to a first precharge voltage and the voltage of the source line to a second precharge voltage during a first precharge time. In an embodiment, the memory device (100) may apply a bit line control signal and a source line control signal to a page buffer and a source line driver during the first precharge time.

[0153] In step S1107, the memory device (100) may raise the voltage of the bit lines to the first precharge voltage and the voltage of the source line to the second precharge voltage during the second precharge time. In an embodiment, the memory device (100) may apply a bit line control signal and a source line control signal to the page buffer and the source line driver during the second precharge time.

[0154] In step S1109, the memory device (100) can apply a program voltage to the word lines connected to the memory cells. Explanation of the symbols

[0155] 50: Memory System 100: Memory device 140: Precharge time information storage unit 150: Program operation control unit 200: Memory controller 300: Host

Claims

Claim 1 A memory device comprising: a precharge time information storage unit storing information regarding a first precharge time for applying a bit line control signal determined according to the progress of a program operation and a second precharge time for applying a source line control signal; and a precharge voltage control unit providing the bit line control signal and the source line control signal to page buffers and a source line driver during the longer precharge time between the first precharge time and the second precharge time during a program operation, wherein the progress of the program operation is the number of times a plurality of program loops included in the program operation have been performed. Claim 2 A memory device according to claim 1, further comprising: memory cells each connected between source lines and bit lines; and a word line control unit including a plurality of program loops and performing the program operation of storing data in the memory cells; wherein the page buffers provide voltage to the bit lines according to the bit line control signal, and the source line driver provides voltage to the source line according to the source line control signal. Claim 3 In claim 2, the magnitude of the bit line control signal is a memory device that rises at a constant slope during the longer precharge time. Claim 4 delete Claim 5 delete Claim 6 A memory device according to claim 1, wherein the precharge voltage control unit further comprises a precharge time comparison unit that determines the longer precharge time based on the result of comparing the first precharge time and the second precharge time. Claim 7 In claim 6, the plurality of program loops include an initial section, a middle section, and a final section distinguished according to the number of times the plurality of program loops are executed, and the precharge voltage control unit is a memory device that provides the source line control signal to the source line driver in the middle section and the final section. Claim 8 In claim 7, the precharge time comparison unit is a memory device that determines the longer precharge time as the second precharge time in the middle section and the end section. Claim 9 In claim 7, the size of the source line control signal is a memory device that increases based on the number of times the plurality of program loops are executed. Claim 10 In claim 9, the precharge time comparison unit determines the longer precharge time in the middle section as the first precharge time and determines the longer precharge time in the end section as the second precharge time. Claim 11 A memory device comprising: a precharge time information storage unit storing information regarding a first precharge time during which the voltage of bit lines determined according to the progress of a program operation rises to a first precharge voltage and a second precharge time during which the voltage of a source line rises to a second precharge voltage; and a program operation control unit controlling the program operation such that during a program operation, the voltage of the bit lines and the voltage of the source line rise to a first precharge voltage and a second precharge voltage, respectively, during a precharge time among the first precharge time and the second precharge time; wherein the progress of the program operation is the number of times a plurality of program loops included in the program operation have been performed. Claim 12 A memory device according to claim 11, further comprising: memory cells respectively connected to the source lines and bit lines; and peripheral circuits that perform the program operation of storing data in the memory cells. Claim 13 In claim 12, the program operation comprises a plurality of program loops, and the program operation control unit controls the peripheral circuit so that the voltage of the source line rises to the second precharge voltage from a predetermined program loop among the plurality of program loops. Claim 14 In claim 13, the program operation control unit controls the peripheral circuit so that the voltage of the bit lines and the voltage of the source line rise to the first precharge voltage and the second precharge voltage, respectively, during the second precharge time. Claim 15 In claim 13, the magnitude of the second precharge voltage is a memory device that increases based on the number of times the plurality of program loops are executed. Claim 16 In claim 15, the plurality of program loops include an initial section, a middle section, and a final section separated according to the number of executions of the plurality of program loops, and the program operation control unit controls the peripheral circuit such that in the middle section, the voltage of the bit lines and the voltage of the source line rise to the first precharge voltage and the second precharge voltage, respectively, during the first precharge time, and in the final section, the voltage of the bit lines and the voltage of the source line rise to the first precharge voltage and the second precharge voltage, respectively. Claim 17 A method of operating a memory device comprising: a step of storing information regarding a first precharge time during which the voltage of bit lines determined according to the progress of a program operation rises to a first precharge voltage and a second precharge time during which the voltage of a source line rises to a second precharge voltage; a step of causing the voltage of the bit lines and the voltage of the source line to rise to the first precharge voltage and the second precharge voltage, respectively, during a precharge time among the first precharge time and the second precharge time; and a step of applying a program voltage to a word line connected to memory cells; wherein the progress of the program operation is the number of times a plurality of program loops included in the program operation have been performed. Claim 18 delete Claim 19 A method of operation of a memory device according to claim 17, wherein during the second precharge time, the voltage of the bit lines and the voltage of the source line are each raised to the first precharge voltage and the second precharge voltage, respectively. Claim 20 In claim 17, the method of operation of a memory device in which the magnitude of the second precharge voltage increases based on the number of times the plurality of program loops are executed. Claim 21 In claim 20, the plurality of program loops include an initial section, a middle section, and a final section distinguished according to the number of times the plurality of program loops are executed, and the step of the voltage of the bit lines and the voltage of the source line rising to a first precharge voltage and a second precharge voltage, respectively, during any one of the precharge times, is a method of operation of a memory device in which the voltage of the bit lines and the voltage of the source line rise to a first precharge voltage and a second precharge voltage, respectively, during the first precharge time in the middle section, and the voltage of the bit lines and the voltage of the source line rise to a first precharge voltage and a second precharge voltage, respectively, during the second precharge time in the final section.

Images