Controller and operation method thereof

Abstract

A controller controls the operation of a semiconductor memory device based on a request received from a host. The controller includes a host interface, a first function block, a second function block, and an internal command cache. The host interface generates a first internal command in response to the request. The first function block generates a second internal command in response to the first internal command. The second function block operates in response to the second internal command. The internal command cache caches at least one internal command corresponding to a reference internal command.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a controller for controlling a semiconductor memory device and a method of operating the same. Background Technology

[0002] A semiconductor memory device may be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are stacked vertically on a semiconductor substrate. A three-dimensional semiconductor memory device is a memory device designed to overcome the integration density limitations of a two-dimensional semiconductor memory device and may include a plurality of memory cells stacked vertically on a semiconductor substrate.

[0003] The controller can control the operation of the semiconductor memory device. Specifically, in response to a request received from a host, the controller controls the semiconductor memory device to perform an operation corresponding to the request by transmitting a command to the semiconductor memory device. The problem to be solved

[0004] An embodiment of the present invention provides a controller with improved speed and a method of operation thereof. means of solving the problem

[0005] A controller according to one embodiment of the present invention controls the operation of a semiconductor memory device based on a request received from a host. The controller includes a host interface, a first function block, a second function block, and an internal command cache. The host interface generates a first internal command in response to the request. The first function block generates a second internal command in response to the first internal command. The second function block operates in response to the second internal command. The internal command cache caches at least one internal command corresponding to a reference internal command.

[0006] A controller according to another embodiment of the present invention controls the operation of a semiconductor memory device based on a request received from a host. The controller includes a host interface, a first function block, and an internal command cache. The host interface generates a first internal command in response to the request. The first function block generates a second internal command in response to the first internal command. The internal command cache caches at least one internal command corresponding to a reference request.

[0007] According to another embodiment of the present invention, the operation of a semiconductor memory device is controlled based on a request received from a host by a method of operation of a controller. The method of operation of the controller includes the step of fetching a first internal command generated in response to the request; the step of determining whether a second internal command corresponding to the first internal command is stored in an internal command cache; and the step of transmitting the second internal command to a lower layer based on the determination result.

[0008] According to another embodiment of the present invention, the operation of a semiconductor memory device is controlled based on a request received from a host by a method of operation of a controller. The method of operation of the controller includes the step of fetching the request, the step of determining whether an internal command corresponding to the request is stored in an internal command cache, and the step of transmitting the internal command corresponding to the request to a lower layer based on the determination result. Effects of the invention

[0009] This technology can provide a controller with improved speed and a method of operation thereof. Brief explanation of the drawing

[0010] Figure 1 is a block diagram showing a storage device and a host device. Figure 2 is a block diagram showing the semiconductor memory device of Figure 1. FIG. 3 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 1. Figure 4 is a block diagram showing an example of the controller of Figure 1. FIG. 5 is a diagram illustrating internal commands generated in each layer of the controller (200) of FIG. 4. Figure 6 is a block diagram showing another example of the controller of Figure 1. FIG. 7 is a diagram illustrating internal commands generated in each layer of the controller (201) of FIG. 6. FIG. 8 is a block diagram showing a controller according to one embodiment of the present invention. FIG. 9 is a block diagram showing an exemplary embodiment of the internal command cache illustrated in FIG. 8. FIGS. 10a and FIGS. 10b are block diagrams for explaining the operation of a controller according to an embodiment of the present invention. FIG. 11 is a diagram illustrating internal commands generated in each layer of the controller (205) of FIG. 8 or obtained from the cache upon a cache hit. FIG. 12 is a block diagram showing a controller according to another embodiment of the present invention. FIG. 13 is a block diagram showing an exemplary embodiment of the internal command cache illustrated in FIG. 12. FIG. 14 is a diagram illustrating internal commands generated in each layer of the controller (207) of FIG. 12 or obtained from the cache upon a cache hit. FIGS. 15a and FIGS. 15b are drawings for exemplarily illustrating the configuration of the internal command storage unit shown in FIGS. 9 and FIGS. 13, respectively. FIGS. 16a and FIGS. 16b are flowcharts illustrating the operation method of a controller according to exemplary embodiments of the present invention, respectively. FIG. 17 is a block diagram showing a storage device (1000) including a semiconductor memory device and a controller. Specific details for implementing the invention

[0011] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0013] Figure 1 is a block diagram showing a storage device and a host device.

[0014] Referring to FIG. 1, the storage device (10) includes a semiconductor memory device (100) and a controller (200). The storage device (10) also communicates with a host device (20). The controller (200) controls the general operation of the semiconductor memory device (100). Additionally, the controller (200) controls the operation of the semiconductor memory device (100) based on an operation request received from the host device (20).

[0015] The semiconductor memory device (100) operates in response to the control of the controller (200). The semiconductor memory device (100) includes a memory cell array having a plurality of memory blocks. As an example, the semiconductor memory device (100) may be a flash memory device.

[0016] The controller (200) can exchange user data (DATA_U) based on a request (RQ) from the host device (20). Specifically, the controller (200) can receive a write request, a read request, or a trim request, etc., from the host device (20), and control the semiconductor memory device (100) based on the received requests. More specifically, the controller (200) can generate commands (CMD) to control the operation of the semiconductor memory device (100) and transmit them to the semiconductor memory device (100). Meanwhile, the controller (200) can exchange data (DATA_N) with the semiconductor memory device (100).

[0017] A semiconductor memory device (100) receives a command and an address from a controller (200) and is configured to access an area selected by the address among memory cell arrays. That is, the semiconductor memory device (100) performs an internal operation corresponding to the command on the area selected by the address.

[0018] For example, the semiconductor memory device (100) can perform a program operation, a read operation, and an erase operation. During the program operation, the semiconductor memory device (100) will program data in an area selected by an address. During the read operation, the semiconductor memory device (100) will read data from an area selected by an address. During the erase operation, the semiconductor memory device (100) will erase data stored in an area selected by an address.

[0020] Figure 2 is a block diagram showing the semiconductor memory device of Figure 1.

[0021] Referring to FIG. 2, the semiconductor memory device (100) includes a memory cell array (110), an address decoder (120), a read and write circuit (130), control logic (140), and a voltage generation unit (150).

[0022] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) are connected to an address decoder (120) via word lines (WL). The plurality of memory blocks (BLK1 to BLKz) are connected to a read and write circuit (130) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. As an example, the plurality of memory cells are non-volatile memory cells and may be composed of non-volatile memory cells having a vertical channel structure. The memory cell array (110) may be composed of a memory cell array with a two-dimensional structure. According to an example, the memory cell array (110) may be composed of a memory cell array with a three-dimensional structure. Meanwhile, each of the plurality of memory cells included in the memory cell array may store at least 1 bit of data. In one embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a single-level cell (SLC) that stores 1 bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a multi-level cell (MLC) that stores 2 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a triple-level cell (TLC) that stores 3 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array (110) may be a quad-level cell (QLC) that stores 4 bits of data. According to an embodiment, the memory cell array (110) may include a plurality of memory cells that each store 5 bits or more of data.

[0023] The address decoder (120), the read and write circuit (130), the control logic (140), and the voltage generation unit (150) operate as peripheral circuits that drive the memory cell array (110). The address decoder (120) is connected to the memory cell array (110) through word lines (WL). The address decoder (120) is configured to operate in response to the control of the control logic (140). The address decoder (120) receives an address through an input / output buffer (not shown) inside the semiconductor memory device (100).

[0024] The address decoder (120) is configured to decode a block address among the received addresses. The address decoder (120) selects at least one memory block according to the decoded block address. Additionally, during a read operation, when a read voltage is applied, the address decoder (120) applies a read voltage (Vread) generated by the voltage generator (150) to the selected word line among the selected memory blocks, and applies a pass voltage (Vpass) to the remaining unselected word lines. Additionally, during a program verification operation, when a verification voltage generated by the voltage generator (150) is applied to the selected word line among the selected memory blocks, and applies a pass voltage (Vpass) to the remaining unselected word lines.

[0025] The address decoder (120) is configured to decode the column address among the received addresses. The address decoder (120) transmits the decoded column address to the read and write circuit (130).

[0026] The read operation and program operation of the semiconductor memory device (100) are performed in page units. The address received upon request for a read operation and program operation includes a block address, a row address, and a column address. The address decoder (120) selects one memory block and one word line according to the block address and row address. The column address is decoded by the address decoder (120) and provided to the read and write circuit (130).

[0027] The address decoder (120) may include a block decoder, a row decoder, a column decoder, and an address buffer, etc.

[0028] The read and write circuit (130) includes a plurality of page buffers (PB1 to PBm). The read and write circuit (130) can operate as a "read circuit" during a read operation of the memory cell array (110) and as a "write circuit" during a write operation. The plurality of page buffers (PB1 to PBm) are connected to the memory cell array (110) through bit lines (BL1 to BLm). The plurality of page buffers (PB1 to PBm) continuously supply sensing current to the bit lines connected to the memory cells to sense the threshold voltage of the memory cells during a read operation and a program verification operation, and detect through a sensing node that the amount of current flowing changes according to the program state of the corresponding memory cell, and latch it as sensing data. The read and write circuit (130) operates in response to page buffer control signals output from the control logic (140).

[0029] The read and write circuit (130) senses data in a memory cell during a read operation, temporarily stores the read data, and then outputs the data (DATA) to an input / output buffer (not shown) of a semiconductor memory device (100). As an exemplary embodiment, the read and write circuit (130) may include a column selection circuit, etc., in addition to page buffers (or page registers).

[0030] The control logic (140) is connected to the address decoder (120), the read and write circuit (130), and the voltage generation unit (150). The control logic (140) receives a command (CMD) and a control signal (CTRL) through an input / output buffer (not shown) of the semiconductor memory device (100). The control logic (140) is configured to control the general operation of the semiconductor memory device (100) in response to the control signal (CTRL). Additionally, the control logic (140) outputs a control signal to adjust the sensing node precharge potential level of a plurality of page buffers (PB1~PBm). The control logic (140) can control the read and write circuit (130) to perform a read operation of the memory cell array (110).

[0031] The voltage generation unit (150) generates a read voltage (Vread) and a pass voltage (Vpass) during a read operation in response to a control signal output from the control logic (140). To generate multiple voltages having various voltage levels, the voltage generation unit (150) includes multiple pumping capacitors that receive an internal power supply voltage, and will generate multiple voltages by selectively activating the multiple pumping capacitors in response to the control of the control logic (140).

[0032] The address decoder (120), the read and write circuit (130), and the voltage generation unit (150) can function as "peripheral circuits" that perform read, write, and erase operations on the memory cell array (110). The peripheral circuits perform read, write, and erase operations on the memory cell array (110) based on the control of the control logic (140).

[0033] Each of the plurality of memory blocks (BLK1~BLKz) included in the memory cell array (110) may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate.

[0035] FIG. 3 is a circuit diagram showing one of the memory blocks (BLKa) among the memory blocks (BLK1~BLKz) of FIG. 1.

[0036] Referring to FIG. 3, a memory block (BLKa) includes multiple cell strings (CS11–CS1m, CS21–CS2m). Within the memory block (BLKa), m cell strings are arranged in the row direction (i.e., +X direction). In FIG. 3, two cell strings are shown arranged in the column direction (i.e., +Y direction). However, this is for convenience of explanation, and it will be understood that three or more cell strings may be arranged in the column direction.

[0037] Each of the plurality of cell strings (CS11~CS1m, CS21~CS2m) includes at least one source select transistor (SST), first to n memory cells (MC1~MCn), and at least one drain select transistor (DST).

[0038] Each of the source select transistor (SST), drain select transistor (DST), and memory cells (MC1 to MCn) may have a similar structure. As an example, each of the source select transistor (SST), drain select transistor (DST), and memory cells (MC1 to MCn) may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an example, a pillar for providing a channel layer may be provided in each cell string. As an example, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each cell string.

[0039] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and the memory cells (MC1~MCn).

[0040] As an example, source select transistors of cell strings arranged in the same row are connected to a source select line extending in the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. In FIG. 3, source select transistors of cell strings (CS11–CS1m) of the first row are connected to a first source select line (SSL1). Source select transistors of cell strings (CS21–CS2m) of the second row are connected to a second source select line (SSL2).

[0041] As another embodiment, the source selection transistors of the cell strings (CS11~CS1m, CS21~CS2m) can be commonly connected to a single source selection line.

[0042] The first to nth memory cells (MC1 to MCn) of each cell string are connected in series between a source select transistor (SST) and a drain select transistor (DST). The gates of the first to nth memory cells (MC1 to MCn) are each connected to the first to nth word lines (WL1 to WLn).

[0043] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells (MC1 to MCn). The cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings of the first row (CS11 to CS1m) are connected to the first drain select line (DSL1). The drain select transistors of the cell strings of the second row (CS21 to CS2m) are connected to the second drain select line (DSL2).

[0044] Cell strings arranged in a column direction are connected to a bit line extending in a column direction. In FIG. 3, the cell strings of the first column (CS11, CS21) are connected to the first bit line (BL1). The cell strings of the m-th column (CS1m, CS2m) are connected to the m-th bit line (BLm).

[0045] Memory cells connected to the same word line within cell strings arranged in a row direction constitute one page. For example, among the cell strings (CS11–CS1m) of the first row, memory cells connected to the first word line (WL1) constitute one page. Among the cell strings (CS21–CS2m) of the second row, memory cells connected to the first word line (WL1) constitute another page. By selecting either of the drain selection lines (DSL1, DSL2), cell strings arranged in a row direction will be selected. By selecting any of the word lines (WL1–WLn), one page among the selected cell strings will be selected.

[0046] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m bit lines (BL1~BLm). And among the cell strings arranged in the row direction (CS11~CS1m or CS21~CS2m), the even-numbered cell strings may be connected to the even bit lines, and among the cell strings arranged in the row direction (CS11~CS1m or CS21~CS2m), the odd-numbered cell strings may be connected to the odd bit lines.

[0047] As an example, at least one of the first to nth memory cells (MC1 to MCn) may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor (SST) and the memory cells (MC1 to MCn). Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor (DST) and the memory cells (MC1 to MCn). As more dummy memory cells are provided, the reliability of operation for the memory block (BLKa) is improved, while the size of the memory block (BLKa) increases. As fewer dummy memory cells are provided, the size of the memory block (BLKa) decreases, while the reliability of operation for the memory block (BLKa) may decrease.

[0048] To efficiently control at least one dummy memory cell, each dummy memory cell may have a required threshold voltage. Program operations may be performed on all or some of the dummy memory cells before or after an erase operation on the memory block (BLKa). When an erase operation is performed after a program operation, the dummy memory cells may have a required threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0049] As illustrated in FIG. 3, the memory blocks (BLK1 to BLKz) of the semiconductor memory device (100) may be composed of memory blocks with a three-dimensional structure. However, the present invention is not limited thereto, and the memory blocks (BLK1 to BLKz) of the semiconductor memory device (100) may be composed of memory blocks with a two-dimensional structure.

[0051] Figure 4 is a block diagram showing an example of the controller of Figure 1.

[0052] Referring to FIG. 4, the controller (200) includes a host interface (Host I / F, 210), a first function block (230), a second function block (250), and a memory interface (Memory I / F, 270).

[0053] The first and second function blocks (230, 250) can control the general operations of the controller (200). As an example, each of the first and second function blocks (FB1; 230, FB2; 250) may be a processor. In this case, the first function block (230) may be a processor that runs the first firmware (FW1). Additionally, the second function block (250) may be a processor that runs the second firmware (FW2).

[0054] The host interface (210) can receive a request (RQ) from the host device (20) and, in response, generate a first internal command (ICMD1). The host interface (210) can transmit the generated first internal command (ICMD1) to the first function block (230).

[0055] By the first firmware (FW1), the first function block (230) can control the operation of receiving write data transmitted from the host device (20) through the host interface (210). Additionally, by the first firmware (FW1), the first function block (230) can transmit data read from the semiconductor memory device (100) to the host device (20) through the host interface (210).

[0056] Additionally, for example, the first firmware (FW1) driven by the first function block (230) may include a Flash Translation Layer (hereinafter referred to as 'FTL'). The FTL may provide an interface between an external device and the semiconductor memory device (100) so that the semiconductor memory device (100) can be used efficiently. For example, the FTL may perform the role of converting a logical address received from an external device, such as a host device (20), into a physical address used by the semiconductor memory device (100). The FTL may perform the address conversion operation described above through a mapping table. For example, the logical address points to a logical location of a storage area managed by the host device (20), and the physical address points to a physical location of the semiconductor memory device (100) managed by the controller (200).

[0057] FTL can perform operations such as wear-leveling and garbage collection (GC) so that the semiconductor memory device (100) can be used efficiently. For example, wear-leveling refers to an operation of managing the program / erase count of multiple memory blocks so that the program / erase count of multiple memory blocks included in the semiconductor memory device (100) becomes uniform. For example, garbage collection (GC) refers to an operation of moving the valid pages of some memory blocks among the multiple memory blocks included in the semiconductor memory device (100) to other memory blocks and then erasing some memory blocks. The erased some memory blocks can be used as free blocks. FTL can secure free blocks of the semiconductor memory device (100) by performing garbage collection.

[0058] To this end, the first function block (230) can generate a second internal command (ICMD2) in response to the first internal command (ICMD1). The first function block (230) can transmit the second internal command (ICMD2) to the second function block (250).

[0059] By means of the second firmware (FW2), the second function block (250) can convert write data to be transmitted to the semiconductor memory device (100). For example, the second function block (250) can encode the write data to be transmitted to the semiconductor memory device (100). The encoding operation can be performed for various purposes. For example, to perform an error correction operation on data read from the semiconductor memory device (100), the write data can be encoded for an error correction operation before being transmitted to the semiconductor memory device (100). Subsequently, during a read operation, the second function block (250) can perform an error correction operation on the read data.

[0060] As another example, the second function block (250) can render data to be transferred to the semiconductor memory device (100). Subsequently, during a read operation, the second function block (250) can perform a de-rendering operation on the read data.

[0061] In this case, the second function block (FB2; 250) can generate a third internal command (ICMD3) in response to the second internal command (ICMD2). The second function block (FB2; 250) can transmit the third internal command (ICMD3) to the memory interface (270).

[0062] The first function block (FB1; 230) and the second function block (FB2; 250) may be configured as different, separate processors, but may also be integrated into a single processor. When the first function block (FB1; 230) and the second function block (FB2; 250) are configured into a single processor, said single processor can drive the first firmware (FW1) and the second firmware (FW2).

[0063] The controller (200) can communicate with the semiconductor memory device (100) through the memory interface (270). For example, the memory interface (270) may include a NAND interface. The memory interface (270) can generate a command (CMD) that is directly transmitted to the semiconductor memory device (100) in response to a third internal command (ICMD3) received from the second function block (250).

[0064] In this way, to generate a command (CMD) to be transmitted to the semiconductor memory device (100) in response to a request (RQ) received from the host device (20), the controller (200) may internally generate a first internal command (ICMD1), a second internal command (ICMD2), and a third internal command (ICMD3). The first internal command (ICMD1), the second internal command (ICMD2), and the third internal command (ICMD3) may be generated for communication between layers within the controller (200).

[0065] For example, the host interface (210) can configure Layer 1. The first function block (230) can configure Layer 2. The second function block (250) can configure Layer 3. The memory interface (270) can configure Layer 4. Layer 1 can communicate with Layer 2 via the first internal command (ICMD1). Layer 2 can communicate with Layer 3 via the second internal command (ICMD2). Layer 3 can communicate with Layer 4 via the third internal command (ICMD3).

[0066] In FIG. 4, the controller (200) is shown as having four layers, but this is exemplary. For example, a controller (200) having five or more layers can also be configured, in which case the function blocks can also be three or more.

[0068] FIG. 5 is a diagram illustrating internal commands generated in each layer of the controller (200) of FIG. 4. The following description will be made with reference to FIG. 4 and FIG. 5 together.

[0069] Referring to FIG. 5, a host interface (210) corresponding to Layer 1 can generate a first internal command (ICMD1) in response to a request from a host device (20). The generated first internal command (ICMD1) is transmitted to Layer 2. A first function block (230) corresponding to Layer 2 can generate a second internal command (ICMD2) in response to the first internal command (ICMD1). The generated second internal command (ICMD2) is transmitted to Layer 3. A second function block (250) corresponding to Layer 3 can generate a third internal command (ICMD3) in response to the second internal command (ICMD2). The generated third internal command (ICMD3) is transmitted to Layer 4.

[0070] In this way, the first to third internal commands (ICMD1, ICMD2, ICMD3) are generated sequentially. According to the example with reference to FIGS. 4 and 5, the controller (200) generates the first to third internal commands (ICMD1, ICMD2, ICMD3) sequentially in response to a request (RQ) received from the host device (20), and finally generates a command (CMD) and transmits it to the semiconductor memory device (100). That is, time is consumed to sequentially generate the first to third internal commands (ICMD1, ICMD2, ICMD3) internally, and this causes the operation speed of the controller (200) and the storage device (10) including it to slow down.

[0072] FIG. 6 is a block diagram showing another example of the controller of FIG. 1. Referring to FIG. 6, the controller (201) includes a host interface (Host I / F, 210), a first function block (230), a second function block (250), a third function block (260), and a memory interface (Memory I / F, 270). Compared to the controller (200) of FIG. 4, the controller (201) of FIG. 6 further includes a third function block (260). Redundant descriptions will be omitted below.

[0073] The first function block (230) may generate a fourth internal command (ICMD4) in addition to the second internal command (ICMD2). The first function block (230) may transmit the fourth internal command (ICMD4) to the third function block (260). The third function block (260) may operate based on the fourth internal command (ICMD4). As illustrated in FIG. 6, the fourth internal command (ICMD4) is an internal command generated in response to a request (RQ) from the host device (20), but it may be an internal command unrelated to the generation of the command (CMD) transmitted to the semiconductor memory device (100). That is, the third function block (260) may perform other operations unrelated to the generation of the command (CMD) transmitted to the semiconductor memory device (100). In this case as well, the third function block (260) may be included in the third layer (Layer 3). In other words, a single layer can contain two or more function blocks.

[0075] FIG. 7 is a diagram illustrating internal commands generated at each layer of the controller (201) of FIG. 6. Referring to FIG. 7, a host interface (210) corresponding to the first layer (Layer 1) can generate a first internal command (ICMD1) in response to a request from a host device (20). The generated first internal command (ICMD1) is transmitted to the second layer (Layer 2). A first function block (230) corresponding to the second layer (Layer 2) can generate a second internal command (ICMD2) in response to the first internal command (ICMD1). The generated second internal command (ICMD2) is transmitted to the second function block of the third layer (Layer 3). Additionally, the first function block (230) can generate a fourth internal command (ICMD4) in response to the first internal command (ICMD1). The generated fourth internal command (ICMD4) is transmitted to the third function block of the third layer (Layer 3). The second function block (250) included in the third layer (Layer 3) can generate a third internal command (ICMD3) in response to the second internal command (ICMD2). The generated third internal command (ICMD3) is transmitted to the fourth layer (Layer 4). Additionally, the third function block (260) included in the third layer (Layer 3) can perform an operation unrelated to command (CMD) generation in response to the fourth internal command (ICMD4).

[0076] In this way, the first to fourth internal commands (ICMD1, ICMD2, ICMD3, ICMD4) are generated sequentially. According to the example with reference to FIGS. 6 and 7, the controller (200) generates the first and second internal commands (ICMD1, ICMD2) sequentially in response to a request (RQ) received from the host device (20), generates the third internal command (ICMD3) in response to the second internal command (ICMD2), and generates the fourth internal command (ICMD4) in response to the first internal command (ICMD1). That is, time is consumed to generate the first to fourth internal commands (ICMD1, ICMD2, ICMD3, ICMD4) internally, which causes the operation speed of the controller (201) and the storage device including it to slow down.

[0077] A controller according to one embodiment of the present invention includes an internal command cache that temporarily stores internal commands. Accordingly, internal commands stored in the internal command cache are output immediately without the need for sequential generation from an upper layer to a lower layer. Accordingly, the operating speed of the controller and the storage device including it is improved.

[0079] FIG. 8 is a block diagram showing a controller according to one embodiment of the present invention.

[0080] Referring to FIG. 8, the controller (205) includes a host interface (Host I / F, 215), a first function block (235), a second function block (255), an internal command cache (245), and a memory interface (Memory I / F, 275). The host interface (215), the first function block (235), the second function block (255), and the memory interface (275) shown in FIG. 8 may be substantially the same components as the host interface (210), the first function block (230), the second function block (250), and the memory interface (270) shown in FIG. 4, respectively. That is, compared to the controller (200) of FIG. 4, the controller (205) of FIG. 8 further includes an internal command cache (245). Redundant descriptions will be omitted below.

[0081] A first internal command (ICMD1) output from a host interface (215) can be transmitted to a first function block (FB1; 230) and an internal command cache (245). When the first internal command (ICMD1) and the corresponding internal commands of lower layers are stored in the internal command cache (245), the internal command cache (245) can transmit the stored internal commands to the lower layers. For example, when the second and third internal commands (ICMD2, ICMD3) corresponding to the first internal command (ICMD1) are stored in the internal command cache (245), that is, when a cache hit occurs, the internal command cache (245) transmits the second internal command (ICMD2) to the second function block (255) and transmits the third internal command (ICMD3) to the memory interface (275). In this case, the first function block (235) will not generate the second internal command (ICMD2). Also, the second function block (255) will not generate the third internal command (ICMD3).

[0082] Meanwhile, if the second and third internal commands (ICMD2, ICMD3) corresponding to the first internal command (ICMD1) are not stored in the internal command cache (245), that is, if a cache miss occurs, the first function block (235) will generate the second internal command (ICMD2) and transmit it to the second function block (255). Additionally, the second function block (255) will generate the third internal command (ICMD3) in response to the second internal command (ICMD2).

[0084] FIG. 9 is a block diagram showing an exemplary embodiment of the internal command cache illustrated in FIG. 8.

[0085] Referring to FIG. 9, the internal command cache (245) may include an internal command storage unit (247) and a cache management unit (249). The internal command storage unit (247) may store a reference internal command and internal commands of the corresponding lower layers.

[0086] The cache management unit (249) receives an internal command input into the internal command cache (245) and determines whether the internal command is stored in the internal command storage unit (247). If the received internal command is stored in the internal command storage unit (247), the cache management unit (249) controls the internal command storage unit (247) via a control signal (CTRL) to output internal commands of a lower layer corresponding to the received internal command.

[0087] For example, as illustrated in FIG. 9, when a first internal command (ICMD1) is input into the internal command cache (245), the cache management unit (249) determines whether the reference first internal command (ICMD1) is stored in the internal command storage unit (247). If the first internal command (ICMD1) is stored in the internal command storage unit (247), the cache management unit (249) controls the internal command storage unit (247) via a control signal (CTRL) to output second and third internal commands (ICMD2, ICMD3) corresponding to the received first internal command (ICMD1).

[0088] Additionally, the cache management unit (249) can replace internal commands stored in the internal command storage unit (247) as needed. Various replacement policies can be used to replace the internal commands stored in the internal command storage unit (247).

[0089] For example, the cache management unit (249) can replace internal commands stored in the internal command storage unit (247) according to the LFU (least frequently used) policy. In this case, the cache management unit (249) can control the internal command storage unit (247) to remove internal commands that have the lowest usage frequency among the stored internal commands.

[0090] As another example, the cache management unit (249) can replace internal commands stored in the internal command storage unit (247) according to the least recently used (LRU) policy. In this case, the cache management unit (249) can control the internal command storage unit (247) to remove internal commands that have not been used for the longest time among the stored internal commands.

[0091] As another example, the cache management unit (249) may manage to store internal commands in the internal command storage unit (247) preferentially, for which the ratio of the time required for internal command generation to the total operation time is high. Taking random read operations as an example, the time required for internal command generation is relatively long compared to the time required for the entire random read operation. On the other hand, in the case of sequential read operations, the time required for internal command generation is relatively short compared to the time required for the entire sequential read operation. The cache management unit (249) may manage the internal command storage unit (247) to store internal commands corresponding to random read operations rather than internal commands corresponding to sequential read operations.

[0093] FIGS. 10a and FIGS. 10b are block diagrams for explaining the operation of a controller according to an embodiment of the present invention.

[0094] As illustrated in FIG. 10a, when the first internal command (ICMD1) and the corresponding second and third internal commands (ICMD2, ICMD3) are stored in the internal command cache (245), that is, when a cache hit occurs, the internal command cache (245) transmits the second internal command (ICMD2) to the second function block (255) and transmits the third internal command (ICMD3) to the memory interface (275). In this case, the first function block (235) will not generate the second internal command (ICMD2). Also, the second function block (255) will not generate the third internal command (ICMD3).

[0095] On the other hand, as illustrated in FIG. 10b, if the second and third internal commands (ICMD2, ICMD3) corresponding to the first internal command (ICMD1) are not stored in the internal command cache (245), i.e., if a cache miss occurs, the first function block (235) will generate the second internal command (ICMD2) and pass it to the second function block (255). Additionally, the second function block (255) will generate the third internal command (ICMD3) in response to the second internal command (ICMD2). In this case, the internal command cache (245) may not perform any separate operation.

[0097] FIG. 11 is a diagram illustrating internal commands generated in each layer of the controller (205) of FIG. 8 or obtained from the cache upon a cache hit.

[0098] Referring to FIG. 11, a host interface (210) corresponding to Layer 1 can generate a first internal command (ICMD1) in response to a request from a host device (20). The generated first internal command (ICMD1) is transmitted to an internal command cache (245). The internal command cache (245) determines whether second and third internal commands (ICMD2, ICMD3) corresponding to the first internal command (ICMD1) are stored. If the second and third internal commands (ICMD2, ICMD3) are stored in the internal command cache (245), the second internal command (ICMD2) is transmitted to Layer 3, and at the same time, the third internal command (ICMD3) is transmitted to Layer 4.

[0099] Accordingly, according to the controller (205) in accordance with an embodiment of the present invention, the second and third internal commands (ICMD2, ICMD3) can be immediately transmitted to lower layers (Layer 3, Layer 4) without the need to sequentially generate the second and third internal commands (ICMD2, ICMD3) after generating the first internal command (ICMD1). Accordingly, the operating speed of the controller (205) and the storage device including it is improved.

[0101] FIG. 12 is a block diagram showing a controller according to another embodiment of the present invention.

[0102] Referring to FIG. 12, the controller (207) includes a host interface (Host I / F, 217), a first function block (237), a second function block (257), an internal command cache (280), and a memory interface (Memory I / F, 277). The host interface (217), the first function block (237), the second function block (257), and the memory interface (277) shown in FIG. 12 may be substantially the same components as the host interface (215), the first function block (235), the second function block (255), and the memory interface (275) shown in FIG. 8, respectively. Therefore, redundant descriptions are omitted.

[0103] The internal command cache (280) of FIG. 12 receives a request (RQ) from a host device (20) through a host interface (217). The internal command cache (280) determines whether first to third internal commands (ICMD1, ICMD2, ICMD3) corresponding to the request (RQ) are stored. If the first to third internal commands (ICMD1, ICMD2, ICMD3) corresponding to the request (RQ) from the host device (20) are stored in the internal command cache (280), the internal command cache (280) can transmit the stored first to third internal commands (ICMD1, ICMD2, ICMD3) to the first function block (237), the second function block (257), and the memory interface (277), respectively. In this case, the host interface (217) has not generated the first internal command (ICMD1). Additionally, the first function block (237) will not generate the second internal command (ICMD2). Meanwhile, the second function block (257) will not generate the third internal command (ICMD3).

[0104] Meanwhile, if the first to third internal commands (ICMD1, ICMD2, ICMD3) corresponding to the request (RQ) from the host device (20) are not stored in the internal command cache (280), i.e., if a cache miss occurs, the host interface (217) will generate the first internal command (ICMD1). The first function block (237) will generate the second internal command (ICMD2) in response to the first internal command (ICMD1) and transmit the second internal command (ICMD2) to the second function block (257). Additionally, the second function block (257) will generate the third internal command (ICMD3) in response to the second internal command (ICMD2).

[0106] FIG. 13 is a block diagram showing an exemplary embodiment of the internal command cache illustrated in FIG. 12.

[0107] Referring to FIG. 13, the internal command cache (280) may include an internal command storage unit (287) and a cache management unit (289). The internal command storage unit (287) may store a reference request (RQ) and internal commands of the corresponding lower layers.

[0108] The cache management unit (289) receives a request (RQ) input into the internal command cache (280) and determines whether internal commands corresponding to the request (RQ) are stored in the internal command storage unit (287). If internal commands corresponding to the received request (RQ) are stored in the internal command storage unit (287), the cache management unit (289) controls the internal command storage unit (287) via a control signal (CTRL) to output internal commands of a lower layer corresponding to the received request (RQ).

[0110] FIG. 14 is a diagram illustrating internal commands generated in each layer of the controller (207) of FIG. 12 or obtained from the cache upon a cache hit.

[0111] Referring to FIG. 14, when the internal command cache (280) receives a request (RQ) through the host interface (217), the internal command cache (280) determines whether internal commands (ICMD1, ICMD2, ICMD3) corresponding to the request (RQ) are stored. If internal commands (ICMD1, ICMD2, ICMD3) corresponding to the request (RQ) are stored, the internal command cache (280) will transmit the stored internal commands (ICMD1, ICMD2, ICMD3) to the second to fourth layers (Layer 2, Layer 3, Layer 4), respectively.

[0112] Accordingly, according to the controller (207) in accordance with an embodiment of the present invention, when internal commands (ICMD1, ICMD2, ICMD3) corresponding to a request (RQ) received from a host device (20) are cached, they can be immediately transmitted to corresponding lower layers (Layer 2, Layer 3, Layer 4) without the need to generate them sequentially. Accordingly, the operating speed of the controller (207) and the storage device including it is improved.

[0114] FIGS. 15a and FIGS. 15b are drawings for exemplarily illustrating the configuration of the internal command storage unit shown in FIGS. 9 and FIGS. 13, respectively.

[0115] Referring to FIG. 15a, internal commands stored in the internal command storage unit (247) of FIG. 9 are illustrated. For example, referring to the first row of FIG. 15a, it can be seen that the received internal command, i.e., the reference internal command, is the first internal command (ICMD1), and the set of internal commands of the corresponding lower layers are the second and third internal commands (ICMD2, ICMD3). That is, when the internal command cache (245) receives the first internal command (ICMD1), the internal command cache (245) outputs the second and third internal commands (ICMD2, ICMD3) to the lower layers.

[0116] Meanwhile, referring to the second row of FIG. 15a, it can be seen that the received internal command, i.e., the reference internal command, is the fourth internal command (ICMD4), and the set of internal commands of the corresponding lower layers is the fifth internal command (ICMD5). That is, when the internal command cache (245) receives the fourth internal command (ICMD4), the internal command cache (245) outputs the fifth internal command (ICMD5) to the lower layers.

[0117] In this way, the internal command storage unit (247) can store k entries. Each entry may include a reference internal command and sets of internal commands of the corresponding lower layers.

[0118] As described above, the cache management unit (249) can replace internal commands stored in the internal command storage unit (247) as needed. For example, the cache management unit (249) can remove one of the k entries stored in the internal command storage unit (247) and add a new entry. To do this, the cache management unit (249) can use various replacement policies.

[0119] For example, the cache management unit (249) can replace entries stored in the internal command storage unit (247) according to the least frequently used (LFU) policy. In this case, the cache management unit (249) can control the internal command storage unit (247) to remove the entry with the lowest usage frequency among the k entries stored.

[0120] As another example, the cache management unit (249) can replace entries stored in the internal command storage unit (247) according to the LRU (least recently used) policy. In this case, the cache management unit (249) can control the internal command storage unit (247) to remove the entry that has not been used for the longest time among the k entries stored.

[0121] As another example, the cache management unit (249) may manage to store entries for internal commands in the internal command storage unit (247) preferentially, such that the ratio of the time required for internal command generation to the total operation time is high. Taking random read operations as an example, the time required for internal command generation is relatively long compared to the time required for the entire random read operation. On the other hand, in the case of sequential read operations, the time required for internal command generation is relatively short compared to the time required for the entire sequential read operation. The cache management unit (249) may manage the internal command storage unit (247) to store entries corresponding to random read operations rather than entries corresponding to sequential read operations.

[0122] Referring to FIG. 15b, internal commands stored in the internal command storage unit (287) of FIG. 13 are illustrated. For example, referring to the first row of FIG. 15b, it can be seen that the received request, i.e., the reference request, is the first request (RQ1), and the set of internal commands of the corresponding lower layers is the first to third internal commands (ICMD1, ICMD2, ICMD3). That is, when the internal command cache (280) receives the first request (RQ1), the internal command cache (280) outputs the first to third internal commands (ICMD1, ICMD2, ICMD3) to the lower layers.

[0123] Meanwhile, referring to the second row of FIG. 15b, it can be seen that the received request, i.e., the reference request, is the second request (RQ2), and the internal command set of the corresponding lower layers is the fourth and fifth internal commands (ICMD4, ICMD5). That is, when the internal command cache (280) receives the second request (RQ2), the internal command cache (245) outputs the fourth and fifth internal commands (ICMD4, ICMD5) to the lower layers.

[0124] In this way, the internal command storage unit (287) can store k entries. Each entry may include a reference request (RQ) and a set of internal commands of the corresponding lower layers.

[0126] FIGS. 16a and FIGS. 16b are flowcharts illustrating the operation method of a controller according to exemplary embodiments of the present invention, respectively.

[0127] Referring to FIG. 16a, a method of operation of a controller according to exemplary embodiments of the present invention includes the steps of fetching a first internal command (ICMD1) (S110), searching for the first internal command in an internal command cache (S120), and determining whether the first internal command has been found (S130). Meanwhile, if the first internal command has been found (S130: yes), the method of operation of the controller further includes the steps of obtaining a second internal command corresponding to the first internal command from an internal command cache (S140) and transmitting the second internal command to a corresponding lower layer (S160).

[0128] In step (S110), a first internal command (ICMD1) may be output from the host interface (215) to the internal command cache (245) as illustrated in FIG. 8. In step (S120), the internal command cache (245) retrieves the first internal command (ICMD1) from the internal command storage unit (247). If the reference first internal command (ICMD1) is stored in the internal command storage unit (247) (S130: Yes), a second internal command (ICMD2) corresponding to the lower layer of the first internal command (ICMD1) will also be stored together. In this case, the internal command cache (245) obtains the stored second internal command (ICMD2) (S140). Subsequently, the internal command cache (245) transmits the second internal command (ICMD2) to the second function block (255) included in the third layer. At this time, step (S160) is performed by the internal command cache (245).

[0129] Meanwhile, the method of operation of the above controller further includes, when the first internal command is not found (S130: No), the step of generating a second internal command corresponding to the first internal command (S150) and the step of transmitting the second internal command to a corresponding lower layer (S160).

[0130] If the reference first internal command (ICMD1) is not stored in the internal command storage unit (247) (S130: No), the first function block (235) generates a second internal command (ICMD2) of the lower layer corresponding to the first internal command (ICMD1) (S150). Subsequently, the first function block (235) transmits the generated second internal command (ICMD2) to the second function block (255) included in the third layer. At this time, step (S160) is performed by the first function block (235).

[0131] Referring to FIG. 16b, a method of operation of a controller according to exemplary embodiments of the present invention includes the steps of fetching a request received from a host (S210), searching for the received request in an internal command cache (S220), determining whether the request has been found (S230), obtaining an internal command corresponding to the request from the internal command cache if the request has been found (S230: yes), generating an internal command corresponding to the request if the request has not been found (S230: no) (S250), and transmitting the internal command to a corresponding lower layer (S260).

[0132] The method illustrated in FIG. 16b is substantially the same as the method illustrated in FIG. 16a, except that it searches for internal command caching from a request from a host device rather than the first internal command. Therefore, redundant descriptions are omitted.

[0134] FIG. 17 is a block diagram showing a storage device (1000) including a semiconductor memory device and a controller.

[0135] The semiconductor memory device (1300) of FIG. 17 can be configured and operated in the same way as the semiconductor memory device (100) described with reference to FIG. 2. Redundant descriptions below are omitted.

[0136] The controller (1200) is connected to a host device (Host) and a semiconductor memory device (1300). In response to a request from the host device (Host), the controller (1200) is configured to access the semiconductor memory device (1300). For example, the controller (1200) is configured to control read, program, erase, and background operations of the semiconductor memory device (1300). The controller (1200) is configured to provide an interface between the semiconductor memory device (1300) and the host device (Host). The controller (1200) is configured to run firmware for controlling the semiconductor memory device (1300).

[0137] The controller (1200) includes RAM (1210, Random Access Memory), a processing unit (1220, processing unit), a host interface (1230, host interface), a memory interface (1240, memory interface), and an error correction block (1250).

[0138] The RAM (1210) is used as any one of the operating memory of the processing unit (1220), the cache memory between the semiconductor memory device (1300) and the host device (Host), and the buffer memory between the semiconductor memory device (1300) and the host device (Host).

[0139] The processing unit (1220) controls the general operations of the controller (1200). The processing unit (1220) is configured to control the read operation, program operation, erase operation, and background operation of the semiconductor memory device (1300). The processing unit (1220) is configured to run firmware for controlling the semiconductor memory device (1300). The processing unit (1220) can perform the function of a flash translation layer (FTL). The processing unit (1220) can convert a logical block address (LBA) provided by a host device into a physical block address (PBA) through the flash translation layer (FTL). The flash translation layer (FTL) can receive a logical block address (LBA) as input using a mapping table and convert it into a physical block address (PBA). There are various address mapping methods of the flash translation layer depending on the mapping unit. Representative address mapping methods include the page mapping method, the block mapping method, and the hybrid mapping method.

[0140] The host interface (1230) includes a protocol for performing data exchange between a host device (Host) and a controller (1200). As an exemplary embodiment, the controller (1200) is configured to communicate with the host device (Host) through at least one of various interface protocols, such as a USB (Universal Serial Bus) protocol, a MMC (multimedia card) protocol, a PCI (peripheral component interconnection) protocol, a PCI-E (PCI-express) protocol, an ATA (Advanced Technology Attachment) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a SCSI (small computer small interface) protocol, an ESDI (enhanced small disk interface) protocol, and an IDE (Integrated Drive Electronics) protocol, a private protocol, etc.

[0141] The memory interface (1240) interfaces with the semiconductor memory device (1300). For example, the memory interface (1240) includes a NAND interface or a NOR interface.

[0142] The error correction block (1250) is configured to detect and correct errors in data received from the semiconductor memory device (1300) using an error correction code (ECC). The error correction block (1250) can correct errors in the read page data using an error correction code. The error correction block (1250) can correct errors using coded modulations such as LDPC (low density parity check) code, BCH (Bose-Chaudhri-Hocquenghem) code, turbo code, Reed-Solomon code, convolution code, RSC (recursive systematic code), TCM (trellis-coded modulation), BCM (Block coded modulation), and Hamming code.

[0143] During a read operation, the error correction block (1250) can correct errors in the read page data. If the read page data contains error bits that exceed the number of correctable bits, the decode may fail. If the page data contains error bits that are equal to or less than the number of correctable bits, the decode may succeed. Success of the decode indicates that the corresponding read command has passed. Failure of the decode indicates that the corresponding read command has failed. When the decode is successful, the controller (1200) outputs the error-corrected page data to the host device.

[0144] The controller (1200) and the semiconductor memory device (1300) can be integrated into a single semiconductor device. As an exemplary embodiment, the controller (1200) and the semiconductor memory device (1300) can be integrated into a single semiconductor device to form a memory card. For example, the controller (1200) and the semiconductor memory device (1300) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash Card (CF), Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD Card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0145] The controller (1200) and the semiconductor memory device (1300) can be integrated into a single semiconductor device to form a solid-state drive (SSD). The solid-state drive (SSD) includes a storage device configured to store data in semiconductor memory. When the storage device is used as a solid-state drive (SSD), the operating speed of the host device connected to the storage device is dramatically improved.

[0146] As another example, the storage device (1000) is a computer, UMPC (Ultra Mobile PC), workstation, netbook, PDA (Personal Digital Assistants), portable computer, web tablet, wireless phone, mobile phone, smartphone, e-book, PMP (portable multimedia player), portable game console, navigation device, black box, digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network It is provided as one of the various components of an electronic device, such as an RFID device or one of the various components constituting a computing system.

[0147] As an exemplary embodiment, the semiconductor memory device (1300) or storage device may be mounted in various types of packages. For example, the semiconductor memory device (1300) or storage device may be mounted in a manner such as a Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip on Board (COB), Ceramic Dual Inline Package (CERDIP), Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-level Processed Stack Package (WSP), etc. Explanation of the symbols

[0148] 100: Semiconductor memory device 110: Memory cell array 120: Address decoder 130: Read and write circuit 140: Control logic 150: Voltage generation unit 200: Controller 1000: Storage device

Claims

Claim 1 A controller for controlling the operation of a semiconductor memory device based on a request received from a host, comprising: a host interface that generates a first internal command in response to the request; a first function block that generates a second internal command in response to the first internal command; a second function block that operates in response to the second internal command; and an internal command cache that caches at least one internal command determined based on the time required for generating the internal command among internal commands corresponding to a reference internal command. Claim 2 A controller according to claim 1, wherein if a second internal command corresponding to the first internal command is cached in the internal command cache, the internal command cache transmits the second internal command to the second function block. Claim 3 A controller according to claim 2, wherein if a second internal command corresponding to the first internal command is cached in the internal command cache, the first function block is configured not to generate the second internal command. Claim 4 A controller according to claim 1, wherein if a second internal command corresponding to the first internal command is not cached in the internal command cache, the first function block generates the second internal command and transmits the generated second internal command to the second function block. Claim 5 A controller according to claim 1, further comprising a memory interface that communicates with the semiconductor memory device. Claim 6 A controller for controlling the operation of a semiconductor memory device based on a request received from a host, comprising: a host interface that generates a first internal command in response to the request; a first function block that generates a second internal command in response to the first internal command; and an internal command cache that caches at least one internal command determined based on the time required for generating the internal command among internal commands corresponding to a reference request. Claim 7 A controller according to claim 6, wherein if a first internal command corresponding to the request is cached in the internal command cache, the internal command cache transmits the first internal command to the first function block. Claim 8 A controller according to claim 7, characterized in that when a first internal command corresponding to the request is cached in the internal command cache, the host interface is configured not to generate the first internal command. Claim 9 A controller according to claim 6, characterized in that if the first internal command corresponding to the request is not cached in the internal command cache, the host interface generates the first internal command and transmits the generated first internal command to the first function block. Claim 10 A controller according to claim 6, further comprising a second function block that operates in response to the second internal command, wherein if the second internal command corresponding to the request is cached in the internal command cache, the internal command cache transmits the second internal command to the second function block. Claim 11 A controller according to claim 6, further comprising a second function block that operates in response to the second internal command, wherein if the second internal command corresponding to the request is not cached in the internal command cache, the first function block generates the second internal command and transmits the generated second internal command to the second function block. Claim 12 A method of operation of a controller that controls the operation of a semiconductor memory device based on a request received from a host, comprising: storing in an internal command cache at least one internal command determined based on the time required for generating an internal command among internal commands corresponding to a previous request received prior to the request; fetching a first internal command generated in response to the request; determining whether a second internal command corresponding to the first internal command is stored in the internal command cache; and transmitting the second internal command to a lower layer based on the result of the determination. Claim 13 A method of operation of a controller according to claim 12, wherein the step of transmitting the second internal command to a lower layer based on the result of the above judgment comprises: a step of obtaining the second internal command from the internal command cache in response to a judgment that the second internal command is stored in the internal command cache; and a step of transmitting the obtained second internal command to the lower layer. Claim 14 A method of operation of a controller according to claim 12, wherein the step of transmitting the second internal command to a lower layer based on the above judgment result comprises: a step of generating the second internal command in response to a judgment that the second internal command is not stored in the internal command cache; and a step of transmitting the generated second internal command to the lower layer. Claim 15 A method of operation of a controller that controls a write operation of a semiconductor memory device based on a request received from a host, comprising: storing in an internal command cache at least one internal command determined based on the time required for generating an internal command among internal commands corresponding to a previous request received prior to the request; fetching the request; determining whether an internal command corresponding to the request is stored in the internal command cache; and transmitting the internal command corresponding to the request to a lower layer based on the determination result. Claim 16 A method of operation of a controller according to claim 15, wherein the step of transmitting an internal command corresponding to the request to a lower layer based on the result of the above judgment comprises: a step of obtaining the internal command from the internal command cache in response to a judgment that the internal command corresponding to the request is stored in the internal command cache; and a step of transmitting the obtained internal command to the lower layer. Claim 17 A method of operation of a controller according to claim 15, wherein the step of transmitting an internal command corresponding to the request to a lower layer based on the result of the above judgment comprises: a step of generating the internal command in response to a judgment that the internal command corresponding to the request is not stored in the internal command cache; and a step of transmitting the generated internal command to the lower layer.

Images