Page buffer, memory device including the page buffer and memory system including the memory device

Abstract

The present invention relates to an electronic device, wherein a memory device according to the present invention comprises first memory cells programmed to have a threshold voltage corresponding to one of a plurality of program states, data latches each storing a plurality of first logical page data to be stored in the first memory cells, and a pre-sensing latch storing data sensed by a pre-verification operation. The pre-sensing latch stores second logical page data to be stored in the second memory cells when a main verification operation for a critical program state among the plurality of program states is passed.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a page buffer, a memory device including a page buffer, and a memory system including a memory device. Background Technology

[0002] A memory system is a device that stores data under the control of a host device, such as a computer or smartphone. A memory system may include a memory device where data is stored and a memory controller that controls the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

[0003] Non-volatile memory devices are memory devices in which data is not lost even when the power is cut off, and include ROM (Read Only Memory; ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and Flash Memory.

[0004] A non-volatile memory device performs a programming operation to store data. The programming operation can be performed by varying the threshold voltage of the memory cells included in the non-volatile memory device. If the threshold voltage of the memory cells does not have a threshold voltage corresponding to the data to be stored, a failure of the programming operation may occur. If the programming operation fails, a reprogramming operation can be performed by reusing the data to be stored in the memory cells. To prepare for a failure of the programming operation, the data to be stored in the memory cells must not be lost until the programming operation is terminated. Until the programming operation is terminated, the data to be stored in the memory cells may remain in the memory controller or the non-volatile memory device. The problem to be solved

[0005] An embodiment of the present invention provides a page buffer capable of recovering data necessary for reprogramming in the event of a program operation failure, a memory device including the page buffer, and a memory system including the memory device. means of solving the problem

[0006] A memory device according to an embodiment of the present invention includes first memory cells programmed to have a threshold voltage corresponding to one of a plurality of program states, data latches each storing a plurality of first logical page data to be stored in the first memory cells, and a pre-sensing latch storing data sensed by a pre-verification operation. The pre-sensing latch stores second logical page data to be stored in the second memory cells when a main verification operation for a critical program state among the plurality of program states is passed.

[0007] A memory device according to an embodiment of the present invention includes a memory block comprising a first physical page and a second physical page, data latches each storing a plurality of first logical page data to be stored in the first physical page, and a cache latch storing second logical page data to be stored in the second physical page. If a program operation to store the plurality of first logical page data in the first physical page fails, any one of the data latches provides the logical page data of any one of the plurality of first logical page data to an external memory controller.

[0008] A memory system according to an embodiment of the present invention includes a memory device comprising a first physical page and a second physical page, and a memory controller that provides a plurality of first logical page data to be stored in the first physical page and a second logical page data to be stored in the second physical page, and then acquires any one of the plurality of first logical page data from the memory device in response to a failure of a program operation.

[0009] A page buffer according to an embodiment of the present invention includes data latches that each store a plurality of first logical page data to be stored in a first physical page, a main sensing latch that stores result information for a main verification operation, and a pre-sensing latch that stores result information for a pre-verification operation. In response to a program suspend command, any one of the data latches transmits one of the logical page data among the plurality of first logical page data to the pre-sensing latch, and the main sensing latch reflects the result information for the main verification operation in the plurality of first logical page data and stores the data sensed by the read operation. Effects of the invention

[0010] According to the present technology, a memory device capable of recovering data necessary for reprogramming in the event of a program operation failure and a memory system including the same are provided. Brief explanation of the drawing

[0011] FIG. 1 is a diagram for illustrating a memory system including a memory device and a memory controller. Figure 2 is a diagram illustrating the threshold voltage distribution of memory cells according to the program operation of a memory device. Figure 3 is a diagram illustrating the program operation of a memory device. Figure 4 is a diagram illustrating the threshold voltage distribution of memory cells storing at least one bit of data. Figure 5 is a diagram illustrating the structure of a memory block configured in three dimensions. FIG. 6 is a diagram for explaining some of the memory cell strings illustrated in FIG. 5. FIG. 7 is a diagram for explaining another part of the memory cell strings shown in FIG. 5. Figure 8 is a diagram illustrating the sequence of program operations of a memory device. FIG. 9 is a diagram illustrating the program operation and recovery operation of a memory device. Figure 10 is a diagram illustrating the page buffer of Figure 1. Figure 11 is a diagram illustrating the main verification operation and pre-verification operation of a memory device. FIG. 12 is a diagram illustrating the operation of a page buffer according to an embodiment of the present invention. FIG. 13 is a diagram illustrating the operation of a page buffer according to another embodiment of the present invention. FIG. 14 is a diagram illustrating the operation of a page buffer according to another embodiment of the present invention. FIG. 15 is a diagram illustrating the operation of a page buffer according to another embodiment of the present invention. FIG. 16 is a diagram illustrating the cache program operation and recovery operation of a memory device. FIG. 17 is a flowchart illustrating the intermediate program operation and final program operation of a memory device. FIG. 18 is a flowchart illustrating the program suspend, resume, and cache program operations of a memory device. FIG. 19 is a flowchart illustrating other embodiments of program suspend, resume operation, and cache program operation of a memory device. Specific details for implementing the invention

[0012] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0014] FIG. 1 is a diagram for illustrating a memory system including a memory device and a memory controller.

[0015] Referring to FIG. 1, the memory system (50) may include a memory device (100) and a memory controller (200). The memory system (50) may be a device that stores data under the control of a host (300), which is an external device, and is included in a mobile phone, a computer, or an in-vehicle infotainment system.

[0016] In an embodiment, the memory system (50) may be manufactured as any one of various types of storage devices according to the host interface, which is a method of communication with the host (300). In an embodiment, the memory system (50) may be manufactured as any one of various types of package forms.

[0017] The memory device (100) can store data. The memory device (100) can operate in response to the control of the memory controller (200). In an embodiment, the memory device (100) may be a volatile memory device or a non-volatile memory device.

[0018] A memory device (100) may be configured to receive a command (CMD) and an address (ADDR) from a memory controller (200) and to access an area selected by the address (ADDR). The memory device (100) may perform a program operation to write data to the area selected by the address (ADDR), a read operation to read data, or an erase operation to delete data.

[0019] The memory controller (200) can control the overall operation of the memory system (50).

[0020] When power is applied to the memory system (50), the memory controller (200) can execute firmware (FW). In an embodiment, the memory controller (200) can execute firmware to control communication between the host (300) and the memory device (100).

[0021] The memory controller (200) can control the memory device (100) to perform a program operation, a read operation, or an erase operation, etc., according to a request from the host (300). The memory controller (200) can provide a command (CMD), an address (ADDR), or data (DATA) to the memory device (100) according to the program operation, the read operation, or the erase operation.

[0022] In an embodiment, the memory controller (200) can independently generate commands, addresses, and data and transmit them to the memory device (100) regardless of a request from the host (300). For example, the memory controller (200) can provide commands, addresses, and data to the memory device (100) for performing read operations and program operations involved in performing wear leveling, read reclaim, garbage collection, etc.

[0023] In an embodiment, the memory controller (200) may include a buffer memory (210). The buffer memory (210) may temporarily store data provided from the host (300) or temporarily store data read from the memory device (100). In an embodiment, the buffer memory (210) may store metadata. The metadata may be data containing information used to operate the memory system (50). In an embodiment, the metadata may include map data indicating the correspondence between the logical address of the host (300) and the physical address of the memory device (100).

[0024] In an embodiment, the buffer memory (210) may be a volatile memory device. For example, the buffer memory (210) may be a static random access memory (SRAM). In an embodiment, the buffer memory (210) may be located outside the memory controller (200) or inside the memory controller (200). In another embodiment, the buffer memory (210) may be located outside the memory system (50).

[0025] In an embodiment, the buffer memory (210) may temporarily store data corresponding to a write request from the host (300). The memory device (100) may perform a program operation to receive data corresponding to the write request and store it in a memory cell. However, if the data corresponding to the write request is not properly stored in the memory cell, the program operation may fail. If the program operation fails, the memory device (100) may perform a reprogram operation to receive the data corresponding to the write request stored in the buffer memory (210) again and store it in the memory cell. The data corresponding to the write request may be stored in the buffer memory (210) until the program operation is terminated in preparation for the failure of the program operation. However, if the data corresponding to the write request is stored inside the memory device (100), the buffer memory (210) may not need to store the data corresponding to the write request. In other words, if the memory controller (200) has data corresponding to the write request stored inside the memory device (100), it can obtain the data corresponding to the write request from the memory device (100) even if the program operation fails. Accordingly, the buffer memory (210) can remove the data corresponding to the write request after providing the data corresponding to the write request to the memory device (100).

[0026] The host (300) can communicate with the memory system (50) using at least one of various communication methods.

[0027] In an embodiment, the memory device (100) may include a memory cell array (110), a peripheral circuit (120), and a control logic circuit (130).

[0028] The memory cell array (110) may include a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) may be connected to an address decoder (121) via row lines (RL). The plurality of memory blocks (BLK1 to BLKz) may be connected to a page buffer group (123) via bit lines (BL1 to BLm). Each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells.

[0029] Multiple memory cells may each be composed of a Single Level Cell (SLC) that stores one bit of data, a Multi Level Cell (MLC) that stores two bits of data, a Triple Level Cell (TLC) that stores three bits of data, a Quad Level Cell (QLC) that can store four bits of data, or memory cells that store five or more bits of data.

[0030] The peripheral circuit (120) can drive the memory cell array (110). For example, the peripheral circuit (120) can drive the memory cell array (110) to perform program operations, read operations, and erase operations under the control of the control logic circuit (130). As another example, the peripheral circuit (120) can apply various operating voltages to row lines (RL) and bit lines (BL1~BLm) or discharge the applied voltages under the control of the control logic circuit (130).

[0031] The peripheral circuit (120) may include an address decoder (121), a voltage generator (122), a page buffer group (123), a data input / output circuit (124), and a sensing circuit (125).

[0032] The address decoder (121) can be connected to the memory cell array (110) through row lines (RL). The row lines (RL) may include drain select lines, word lines, source select lines, and a common source line.

[0033] The address decoder (121) may be configured to operate in response to the control of the control logic circuit (130). The address decoder (121) may receive an address (ADDR) from the control logic circuit (130).

[0034] The address decoder (121) may be configured to decode a block address among the received addresses (ADDR). The address decoder (121) may select at least one memory block among the memory blocks (BLK1~BLKz) according to the decoded block address. The address decoder (121) may be configured to decode a row address among the received addresses (ADDR). The address decoder (121) may select at least one word line of the selected memory block by applying voltages provided by the voltage generation unit (122) to at least one word line (WL) according to the decoded row address.

[0035] During program operation, the address decoder (121) may apply a program voltage to selected word lines and a pass voltage of a level lower than the program voltage to unselected word lines. During program verification operation, the address decoder (121) may apply a verification voltage to selected word lines and a verification pass voltage of a level higher than the verification voltage to unselected word lines.

[0036] The address decoder (121) may be configured to decode the column address among the transmitted addresses (ADDR). The decoded column address may be transmitted to the page buffer group (123). For example, the address decoder (121) may include components such as a row decoder, a column decoder, an address buffer, etc.

[0037] The voltage generation unit (122) may be configured to generate a plurality of operating voltages (Vop) using an external power supply voltage supplied to the memory device (100). The voltage generation unit (122) may operate in response to the control of the control logic circuit (130).

[0038] As an example, the voltage generator (122) can generate various operating voltages (Vop) used for program, read, and erase operations in response to an operation signal (OPSIG). For example, the voltage generator (122) can generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

[0039] The generated multiple operating voltages (Vop) can be supplied to the memory cell array (110) by the address decoder (121).

[0040] The page buffer group (123) may include first to m page buffers (PB1 to PBm). The first to m page buffers (PB1 to PBm) may each be connected to a memory cell array (110) through first to m bit lines (BL1 to BLm). The first to m page buffers (PB1 to PBm) may operate in response to control by a control logic circuit (130).

[0041] The first to m-th page buffers (PB1 to PBm) can communicate data (DATA) with the data input / output circuit (124). During programming, the first to m-th page buffers (PB1 to PBm) can receive data (DATA) through the data input / output circuit (124) and data lines (DL).

[0042] During a program operation, the first to m-page buffers (PB1 to PBm) can transmit data (DATA) received through the data input / output circuit (124) to selected memory cells via bit lines (BL1 to BLm). The memory cells of the selected pages can be programmed according to the transmitted data (DATA). A memory cell connected to a bit line to which a program allow voltage (e.g., ground voltage) is applied may have an elevated threshold voltage. A memory cell connected to a bit line to which a program prohibit voltage (e.g., power supply voltage) is applied may have a maintained threshold voltage. During a verification operation, the first to m-page buffers (PB1 to PBm) can read data (DATA) stored in the memory cells from the selected memory cells via bit lines (BL1 to BLm).

[0043] In an embodiment, while data stored in some of the page buffers among the plurality of page buffers included in the page buffer group (123) is programmed into the memory cell array (110), other page buffers can receive and store new data from the memory controller (200).

[0044] The data input / output circuit (124) can be connected to the first to m page buffers (PB1 to PBm) through data lines (DL). The data input / output circuit (124) can operate in response to the control of the control logic circuit (130).

[0045] The data input / output circuit (124) may include a plurality of input / output buffers (not shown) for receiving input data (DATA). When a program is executed, the data input / output circuit (124) may receive data (DATA) to be stored from the memory controller (200).

[0046] The sensing circuit (125) can generate a reference current in response to an allow bit (VRYBIT) signal generated by the control logic circuit (130) during a verification operation, and output a pass signal or a fail signal to the control logic circuit (130) by comparing the sensing voltage (VPB) received from the page buffer group (123) with the reference voltage generated by the reference current. For example, the sensing circuit (125) can output a pass signal to the control logic circuit (130) if the magnitude of the sensing voltage (VPB) is greater than the reference voltage. As another example, the sensing circuit (125) can output a fail signal to the control logic circuit (130) if the magnitude of the sensing voltage (VPB) is smaller than the reference voltage.

[0047] The control logic circuit (130) may be connected to an address decoder (121), a voltage generator (122), a page buffer group (123), a data input / output circuit (124), and a sensing circuit (125). The control logic circuit (130) may be configured to control the general operation of the memory device (100). The control logic circuit (130) may operate in response to a command (CMD) transmitted from the memory controller (200).

[0048] The control logic circuit (130) can control the peripheral circuit (120) by generating various signals in response to the command (CMD) and address (ADDR). For example, the control logic circuit (130) can generate an operation signal (OPSIG), an address (ADDR), a page buffer control signal (PBSIG), and an allow bit (VRYBIT) in response to the command (CMD) and address (ADDR). The control logic circuit (130) can output the operation signal (OPSIG) to the voltage generation unit (122), output the address (ADDR) to the address decoder (121), output the page buffer control signal (PBSIG) to the page buffer group (123), and output the allow bit (VRYBIT) to the sensing circuit (125). Additionally, the control logic circuit (130) can determine whether the verification operation has passed or failed in response to a pass or fail signal (PASS / FAIL) output by the sensing circuit (125).

[0049] In an embodiment, the control logic circuit (130) can control the program operation for the memory cells. In an embodiment, the program operation may include an intermediate program operation and a final program operation. The control logic circuit (130) can control the peripheral circuit (120) to perform the intermediate program operation and the final program operation for the memory cells.

[0050] In an embodiment, each of the page buffers (PB1 to PBm) included in the page buffer group (123) may include a plurality of latches. The plurality of latches may temporarily store data and information used in program operations.

[0051] In an embodiment, a plurality of latches can store data to be stored in memory cells until the program operation ends in preparation for a program operation failure. For example, if the memory cells are programmed as TLC, the plurality of latches can store three bits of data until the program operation ends. In the event of a program failure, the plurality of latches can provide data to be stored in memory cells to the memory controller (200) for a reprogram operation.

[0052] Figure 2 is a diagram illustrating the threshold voltage distribution of memory cells according to the program operation of a memory device.

[0053] In Figure 2, the horizontal axis of the graph represents the threshold voltage (Vth) of the memory cells, and the vertical axis of the graph represents the number of memory cells (# of cells).

[0054] Referring to FIG. 2, the memory device (100) can perform a programming operation on memory cells. The programming operation may include an intermediate programming operation and a final programming operation. The threshold voltage distribution of the memory cells may change from an initial state to an intermediate programming state according to the intermediate programming operation, and change from an intermediate programming state to a final programming state according to the final programming operation. The intermediate programming operation may be an operation in which the threshold voltage of the memory cells has a threshold voltage corresponding to either an erase state (E) or an intermediate state (MID PV). The final programming operation may be an operation in which the threshold voltage of each memory cell has a threshold voltage corresponding to a target programming state.

[0055] The initial state is a state where no program operation is performed, and the threshold voltage distribution of the memory cells may be in an erased state (E).

[0056] The intermediate program state may be the program state of the memory cells that have performed the intermediate program operation. The threshold voltage of the memory cells may have a threshold voltage corresponding to either the erase state (E) or the intermediate state (MID PV) by the intermediate program operation. In the embodiment, the intermediate state (MID PV) may be a program state equal to or lower than the fourth program state (PV4).

[0057] In an embodiment, among the memory cells, memory cells having an erase state (E) and first to third program states (PV1~PV3) as target program states may have a threshold voltage corresponding to the erase state (E) by an intermediate program operation. In an embodiment, among the memory cells, memory cells having fourth to seventh program states (PV4~PV7) as target program states may have a threshold voltage corresponding to an intermediate state (MID PV) by an intermediate program operation.

[0058] The final program state may be the program state of the memory cells that have performed the intermediate program operation and the final program operation. The threshold voltage of the memory cells may have a threshold voltage corresponding to any one of the program states through the final program operation. In the embodiment, when the memory cells are programmed as TLC, the final program states may refer to the erase state (E) and the first to seventh program states (PV1~PV7).

[0059] Specifically, memory cells having a threshold voltage of the erase state (E) in an intermediate program state may have a threshold voltage corresponding to any one of the erase state (E) and the first to third program states (PV1~PV3) through a final program operation. Memory cells having a threshold voltage of the intermediate state (MID PV) in an intermediate program state may have a threshold voltage corresponding to any one of the fourth to seventh program states (PV4~PV7) through a final program operation.

[0060] Each memory cell may have a target program state among the final program states, such as an erase state (E) and the first to seventh program states (PV1 to PV7). The target program state may be determined according to the data to be stored in each memory cell. During an intermediate program operation, the threshold voltage of the memory cells may have a threshold voltage corresponding to either the erase state (E) or the intermediate state (MID PV), and during a final program operation, the threshold voltage of the memory cells may have a threshold voltage corresponding to either the erase state (E) or the first to seventh program states (PV1 to PV7).

[0061] Figure 3 is a diagram illustrating the program operation of a memory device.

[0062] In Fig. 3, the horizontal axis of the graph represents time, and the vertical axis of the graph represents the voltage (V) applied to the word line.

[0063] Figure 3 describes the case where a single memory cell is programmed as a TLC to store three bits of data. However, the scope of the present invention is not limited thereto, and a single memory cell may be programmed to store two bits or less of data or four bits or more of data.

[0064] Referring to FIG. 3, the program operation may include an intermediate program operation and a final program operation. The intermediate program operation may be an operation of applying an intermediate program voltage (Vpgm_m) to word lines connected to selected memory cells. In an embodiment, the intermediate program voltage (Vpgm_m) may be a voltage of a predetermined magnitude. During the intermediate program operation, a program allowance voltage or a program prohibition voltage may be applied to bit lines connected to each memory cell. Specifically, when the intermediate program voltage (Vpgm_m) is applied to the word line, a program prohibition voltage may be applied to the bit line connected to the memory cell having the erase state (E) and the first to third program states (PV1~PV3) as the target program state. And, when the intermediate program voltage (Vpgm_m) is applied to the word line, a program allowance voltage may be applied to the bit line connected to the memory cell having the fourth to seventh program states (PV4~PV7) as the target program state.

[0065] The memory device (100) can perform a final program operation after performing an intermediate program operation. The final program operation may include a plurality of program loops (PL1 to PLn). The memory device (100) can perform a plurality of program loops (PL1 to PLn) such that the threshold voltage of selected memory cells connected to a selected word line has a threshold voltage corresponding to any one of the final program states. Each of the selected memory cells may have any one of the final program states as a target program state. For example, when a memory cell is programmed as TLC, the memory device (100) can perform a final program operation including a plurality of program loops such that the threshold voltage of the selected memory cells has a threshold voltage corresponding to an erase state (E) or any one of the first to seventh program states (PV1 to PV7).

[0066] Each of the multiple program loops (PL1 to PLn) may include a program voltage application operation (PGM Step) and a verification operation (Verify Step).

[0067] The program voltage application operation (PGM Step) may be an operation of applying a program voltage to a selected word line connected to selected memory cells. For example, the memory device (100) may apply a first program voltage (Vpgm1) to a selected word line connected to selected memory cells in a first program loop (PL1). After the first program voltage (Vpgm1) is applied to the selected word line, the threshold voltage of each of the selected memory cells may have a threshold voltage corresponding to a target program state among the final program states.

[0068] The Verify Step may be an operation of applying a verification voltage to a selected word line connected to selected memory cells. The Verify Step may be an operation of determining whether the threshold voltage of each of the selected memory cells has a threshold voltage corresponding to a target program state among the final program states. The Verify Step may be an operation of applying a verification voltage corresponding to a target program state of each of the selected memory cells.

[0069] In an embodiment, the memory device (100) may apply first to seventh verification voltages (V_vfy1 to V_vfy7) after applying a first program voltage (Vpgm1) to a selected word line connected to selected memory cells in a first program loop (PL1). The memory device (100) may apply a verification voltage corresponding to the target program state of the memory cells among the first to seventh verification voltages (V_vfy1 to V_vfy7) to the selected word line. For example, the memory device (100) may perform a verification operation on memory cells whose target program state is the first program state using the first verification voltage (V_vfy1). The magnitude of the verification voltages (V_vfy1 to V_vfy7) may increase as it goes from the first verification voltage (V_vfy1) to the seventh verification voltage (V_vfy7). Specifically, the magnitudes of the verification voltages (V_vfy1 to V_vfy7) may be such that the first verification voltage (V_vfy1) is the smallest and the seventh verification voltage (V_vfy7) is the largest. The number of verification voltages is not limited to this embodiment.

[0070] The threshold voltage of the memory cells through which the verification step has been passed by each of the verification voltages (V_vfy1~V_vfy7) can be determined to have a threshold voltage corresponding to the target program state. A program prohibition voltage in the second program loop (PL2) can be applied to the bit line connected to the memory cells through which the verification step has been passed.

[0071] The threshold voltage of memory cells that failed the verification step by each of the verification voltages (V_vfy1~V_vfy7) can be determined to not have a threshold voltage corresponding to the target program state. Memory cells that failed the verification step can perform a second program loop (PL2). A program allowance voltage in the second program loop (PL2) can be applied to the bit line connected to the memory cells that failed the verification step.

[0072] In the second program loop (PL2), the memory device (100) can apply a second program voltage (Vpgm2) that is higher than the first program voltage (Vpgm1) by a unit voltage (△Vpgm) to a selected word line connected to the selected memory cells. Afterward, the memory device (100) can perform the verification step of the second program loop (PL2) in the same way as the verification step of the first program loop (PL1).

[0073] Afterwards, the memory device (100) can perform the next program loop in the same way as the second program loop (PL2) a preset number of times.

[0074] In an embodiment, if the program operation is not completed within a preset number of program loops, the program operation may fail. If the program operation is completed within a preset number of program loops, the program operation may pass. Whether the program operation is completed may be determined by whether all verification steps for the selected memory cells have passed. If verification steps for all selected memory cells have passed, the next program loop may not be executed.

[0075] In the embodiment, the program voltage can be determined according to the Incremental Step Pulse Programming (ISPP) method. The level of the program voltage can be increased or decreased stepwise as the program loops (PL1 to PLn) are repeated. The number of times the program voltages used in each program loop are applied, the voltage level, and the voltage application time can be determined in various forms according to the control of the memory controller (200).

[0076] Figure 4 is a diagram illustrating the threshold voltage distribution of memory cells storing at least one bit of data.

[0077] In Figure 4, the horizontal axis of the graph represents the threshold voltage (Vth) of the memory cells, and the vertical axis of the graph represents the number of memory cells (# of cells).

[0078] Referring to FIG. 4, the intermediate program state may be the program state of memory cells that have performed the intermediate program operation. The threshold voltage of the memory cells that have performed the intermediate program operation may have a threshold voltage corresponding to either the erase state (E) or the intermediate state (MID PV). In the intermediate program state, one memory cell may store one data bit. In an embodiment, after performing the intermediate program operation, data of 0 may be stored in a memory cell having a threshold voltage corresponding to the erase state. In an embodiment, after performing the intermediate program operation, data of 1 may be stored in a memory cell having a threshold voltage corresponding to the intermediate state. The data stored in the memory cell during the intermediate program operation may be LSB (Least Significant Bit) data.

[0079] The intermediate read voltage (Vr_m) may be a read voltage for distinguishing between the erase state (E) and the intermediate state of the memory cells in the intermediate program state. In an embodiment, the intermediate read voltage (Vr_m) may be a voltage for reading LSB data stored in the memory cells after performing the intermediate program operation.

[0080] The final program state may be the program state of the memory cells that performed the final program operation. During the final program operation, the threshold voltage of the memory cell may have a threshold voltage corresponding to any one of the erase state (E) and the first to seventh program states (PV1~PV7). In the final program state, a single memory cell may store multiple bits of data. In an embodiment, when programmed as TLC, a single memory cell may store three bits of data. The three bits of data may include LSB data, CSB (Central Significant Bit) data, and MSB (Most Significant Bit) data.

[0081] The data stored in the memory cell during the final program operation may be CSB data and LSB data. That is, the memory device (100) may store LSB data in the memory cell during the intermediate program operation, and store CSB data and MSB data in the memory cell during the final program operation.

[0082] The fourth lead voltage (Vr4) may be a voltage for distinguishing LSB data in the final program state. The first lead voltage (Vr1), the third lead voltage (Vr3), and the sixth lead voltage (Vr6) may be voltages for distinguishing CSB data. The second lead voltage (Vr2), the fifth lead voltage (Vr5), and the seventh lead voltage (Vr7) may be voltages for distinguishing MSB data.

[0083] In the final program state, the LSB data of the erase state (E) and the first to third program states (PV1~PV3) may be the same as 0, and the LSB data of the fourth to seventh program states (PV4~PV7) may be the same as 1. That is, although the LSB data is stored in the memory cell in the intermediate program state, since it is necessary to distinguish between the erase state (E), the first to third program states (PV1~PV3), and the fourth to seventh program states (PV4~PV7), all LSB data, CSB data, and MSB data may be used in the final program operation.

[0084] Figure 5 is a diagram illustrating the structure of a memory block configured in three dimensions.

[0085] Referring to FIG. 5, a memory block may include a plurality of memory cells (M1 to M36). The plurality of memory cells (M1 to M36) may be connected between bit lines (BL1 to BL3) and a common source line (CSL). A single word line may be commonly connected to four local word lines. For example, a first word line (WL1) may be commonly connected to 11th to 14th local word lines (LWL11 to LWL14). Memory cells may be connected to each of the local word lines. Memory cells connected to a single local word line may constitute a single physical page. For example, the first to third memory cells (M1 to M3) connected to the 11th local word line (LWL11) may constitute a first physical page (PG1). A single word line may include as many physical pages as there are commonly connected local word lines.

[0086] The number of local wordlines connected to a single wordline can be determined by the number of memory cell strings commonly connected to a single bitline. For example, if four memory cell strings are commonly connected to a single bitline, four local wordlines can be commonly connected to a single wordline. In this case, a single wordline can contain four physical pages.

[0087] A single memory cell string may include memory cells serially connected in the Z direction. For example, a first memory cell string (ST1) may include a first memory cell (M1), a 13th memory cell (M13), and a 25th memory cell (M25). Memory cell strings in the Y direction may be connected to a single bit line. For example, a first memory cell string (ST1), a fourth memory cell string (ST4), a seventh memory cell string (ST7), and a tenth memory cell string (ST10) may be connected to a first bit line (BL1).

[0088] In an embodiment, a plurality of logical page data may be stored in a single physical page. The number of logical page data to be stored in a single physical page may be determined according to the number of bit data stored in a single memory cell. For example, if a single memory cell stores 3 bits of data, the plurality of logical page data may include LSB page data, CSB page data, and MSB page data.

[0089] The number of word lines, local word lines, memory cell strings, bit lines, and memory cells shown in FIG. 5 is for convenience of explanation and may be less or more than the number shown in FIG. 5.

[0090] FIG. 6 is a diagram for explaining some of the memory cell strings illustrated in FIG. 5.

[0091] FIG. 6 will be described with reference to FIG. 5. Referring to FIG. 6, each of the first to third memory cell strings (ST1 to ST3) may be connected to the first to third bit lines (BL1 to BL3), respectively. Each of the first to third memory cell strings (ST1 to ST3) may each include drain select transistors (DST11, DST12, DST13) commonly connected to the first drain select line (DSL1). Each of the first to third memory cell strings (ST1 to ST3) may each include source select transistors (SST11, SST12, SST13) commonly connected to the first source select line (SSL1). Each memory cell string may include memory cells connected to different local word lines, respectively. For example, the second memory cell string (ST2) may include a second memory cell (M2), a 14th memory cell (M14), and a 26th memory cell (M26) connected to the 11th local word line (LWL11), the 21st local word line (LWL21), and the 31st local word line (LWL31), respectively.

[0092] FIG. 7 is a diagram for explaining another part of the memory cell strings shown in FIG. 5.

[0093] FIG. 7 is described with reference to FIG. 5 and FIG. 6. Referring to FIG. 7, the first memory cell string (ST1), the fourth memory cell string (ST4), the seventh memory cell string (ST7), and the tenth memory cell string (ST10) may be connected between the first bit line (BL1) and the common source line (CSL). Each memory cell string may be connected to different drain select lines and source select lines. For example, the first memory cell string (ST1) may be connected to the first drain select line (DSL1) and the first source select line (SSL1). The first drain select line (DSL1) and the first source select line (SSL1) may be commonly connected to the first to third memory cell strings (ST1 to ST3). The fourth memory cell string (ST4) may be connected to the second drain select line (DSL2) and the second source select line (SSL2). The second drain select line (DSL2) and the second source select line (SSL2) may be commonly connected to the fourth to sixth memory cell strings (ST4~ST6). The seventh memory cell string (ST7) may be connected to the third drain select line (DSL3) and the third source select line (SSL3). The third drain select line (DSL3) and the third source select line (SSL3) may be commonly connected to the seventh to ninth memory cell strings (ST7~ST9). The tenth memory cell string (ST10) may be connected to the fourth drain select line (DSL4) and the fourth source select line (SSL4). The fourth drain selection line (DSL4) and the fourth source selection line (SSL4) can be commonly connected to the 10th to 12th memory cell strings (ST10~ST12).

[0094] As another example, unlike as illustrated in FIG. 7, the first to sixth memory cell strings (ST1 to ST6) may be commonly connected to one source selection line, and the seventh to twelfth memory cell strings (ST7 to ST12) may be commonly connected to one source selection line.

[0095] Figure 8 is a diagram illustrating the sequence of program operations of a memory device.

[0096] FIG. 8 will be described with reference to FIGS. 5 through 7. A memory device (100) can perform an Inter Program Operation (Inter PGM) and a Final Program Operation (Final PGM) according to the order shown in FIG. 8. In FIG. 8, memory cells connected to a single Local Word Line (Local WL) can constitute a single physical page. For example, a second physical page (PG2) may include the fourth to sixth memory cells (M4~M6) shown in FIG. 5, and a twelfth physical page (PG12) may include the thirteenth to thirteenth memory cells (M34~M36) shown in FIG. 5.

[0097] First, the memory device (100) can sequentially perform an Inter Program Operation (Inter PGM) for the first to fourth physical pages (PG1 to PG4) included in the first word line (WL1). Subsequently, the memory device (100) can perform an Inter Program Operation (Inter PGM) and a Final Program Operation (Final PGM) as the second word line (WL2) and the first word line (WL1) are selected alternately. In an embodiment, the memory device (100) can perform an Inter Program Operation (Inter PGM) for the fifth physical page (PG5) and then perform a Final Program Operation (Final PGM) for the first physical page (PG1). That is, an Inter Program Operation (Inter PGM) for each of the fifth to eighth physical pages (PG5 to PG8) and a Final Program Operation (Final PGM) for each of the first to fourth physical pages (PG1 to PG4) can be performed alternately.

[0098] Likewise, the memory device (100) can perform an Inter Program Operation (Inter PGM) and a Final Program Operation (Final PGM) by alternately selecting the third word line (WL3) and the second word line (WL2). After performing an Inter Program Operation (Inter PGM) for the 12th physical page (PG12), a Final Program Operation (Final PGM) for the 8th physical page (PG8) can be performed. That is, an Inter Program Operation (Inter PGM) for each of the 9th to 12th physical pages (PG9~PG12) and a Final Program Operation (Final PGM) for each of the 5th to 9th physical pages (PG5~PG9) can be performed alternately.

[0099] Afterward, when an Inter Program Operation (Inter PGM) is performed for all physical pages, a Final Program Operation (Final PGM) for the 9th to 12th physical pages (PG9~PG12) included in the 3rd word line (WL3), which is the last word line, can be performed sequentially.

[0100] FIG. 9 is a diagram illustrating the program operation and recovery operation of a memory device.

[0101] Referring to FIGS. 1 and 9, an input / output line (I / O) and a ready / busy line (R / B) are illustrated. A memory device (100) may receive a command (CMD), an address (ADDR), and data from a memory controller (200) through the input / output line (I / O). The memory device (100) may output a status signal to the memory controller (200) through the ready / busy line (R / B). For example, the memory device (100) may output a busy status signal to the memory controller (200) while an internal operation is being performed. The busy status signal may be logic low. The memory device (100) may output a ready status signal to the memory controller (200) while no operation is being performed. The ready status signal may be logic high.

[0102] First, the memory device (100) can receive command, address, and LSB data through an input / output line (I / O). The memory device (100) can perform an intermediate program operation (Inter PGM) using the LSB data. The time required to perform the intermediate program operation may be a first program time (tPROG1). At this time, the memory device may output a busy state signal.

[0103] Subsequently, the memory device (100) can receive command (CMD), address (ADDR), and CSB data through an input / output line (I / O). Then, a first transfer time (tTran) may be required to store the CSB data. Specifically, the first transfer time (tTran) may be the time required to move data between latches included in the page buffer of the memory device (100). Next, the memory device (100) can receive command (CMD), address (ADDR), and MSB data through an input / output line. The memory device (100) can read LSB data from memory cells and perform a final program operation (Final PGM) using the LSB data, CSB data, and MSB data. The time required to perform the final program operation (Final PGM) may be a second program time (tPROG2). At this time, the memory device (100) may output a busy state signal.

[0104] Subsequently, the memory controller (200) may provide a Status Read command to the memory device (100) to check whether the final program operation has passed. At this time, if the final program operation (Final PGM) has failed, the memory device (100) may provide a signal to the memory controller (200) indicating that the final program operation (Final PGM) has failed. Subsequently, the memory controller (200) may provide a Recovery command to the memory device (100) requesting data necessary for reprogramming. If the data requested by the memory controller (200) is LSB data, the memory device (100) may provide LSB data to the memory controller (200).

[0105] Meanwhile, a program operation failure may mean that the threshold voltage distribution of the memory cells is not formed into a threshold voltage distribution that distinguishes each program state, such as the final program state in FIG. 4. Therefore, since logical page data cannot be read from the memory cells to reprogram when the program operation fails, the logical page data may need to be stored in the buffer memory (210) of the memory controller. Specifically, referring to FIG. 8, the memory device (100) alternately performs intermediate program operations and final program operations for each physical page; thus, when the final program operation for the first physical page (PG1) is being performed, the buffer memory (210) may need to store the LSB page data of each of the second to fourth physical pages (PG2~PG4) that have only performed intermediate program operations. Additionally, the buffer memory (210) may also need to store the LSB page data of the fifth physical page (PG5) to be used for cache program operations. That is, when alternately performing intermediate program operations and final program operations for each physical page, in preparation for program operation failure, and since there is a large amount of logical page data that the buffer memory (210) must store for cache program operations, it may be advantageous to store the logical page data inside the memory device (100).

[0106] Figure 10 is a diagram illustrating the page buffer of Figure 1.

[0107] The page buffer (1100) illustrated in FIG. 10 may be any one of the first to mth page buffers (PB1 to PBm) illustrated in FIG. 1.

[0108] Referring to FIG. 10, the page buffer (1100) may include a precharge circuit (1110), a main sensing latch (1120), a pre-sensing latch (1130), and a data latch (1140). The precharge circuit (1110), the main sensing latch (1120), the pre-sensing latch (1130), and the data latch (1140) may be connected between a bit line (BL) and a data line (DL). The bit line (BL) may be connected to a memory cell.

[0109] The precharge circuit (1110) may be a circuit that precharges the voltage of the bit line. The precharge circuit (1110) may raise the voltage of the bit line to a program allow voltage, a program prohibit voltage, or a precharge voltage depending on the threshold voltage of the memory cell during a program operation.

[0110] The main sensing latch (1120) may be a latch that stores data sensed by a main verification operation. The main verification operation may be an operation that identifies the threshold voltages of memory cells using a main verification voltage. The data stored in the main sensing latch (1120) may be data indicating whether the main verification operation is passed or failed. In an embodiment, the main sensing latch (1120) may store main verification result information indicating that the main verification operation has passed if the threshold voltage of the memory cell is higher than the main verification voltage. In an embodiment, the main sensing latch (1120) may store main verification result information indicating that the main verification operation has failed if the threshold voltage of the memory cell is lower than the main verification voltage.

[0111] The pre-sensing latch (1130) may be a latch that stores data sensed by a pre-verification operation. The pre-verification operation may be an operation that identifies the threshold voltage of a memory cell using a pre-verification voltage lower than the main verification voltage. The data stored in the pre-sensing latch (1130) may be data indicating whether the threshold voltage of the memory cell has a threshold voltage higher than the pre-verification voltage. The main verification operation and the pre-verification operation will be described later with reference to FIG. 11.

[0112] The data latch (1140) may be a latch that stores data to be stored in a memory cell. The data latch (1140) may receive data to be stored in the memory cell from the memory controller via a data line (DL). In an embodiment, the data latch (1140) may be composed of multiple data latches. In an embodiment, the data latch (1140) may be composed of three data latches that store LSB data, CSB data, and MSB data, respectively. In another embodiment, the data latch (1140) may be composed of four data latches that store LSB data, CSB data, MSB data, and LSB data of the next physical page to be programmed, respectively. If the data latch (1140) is composed of multiple data latches, any one of the multiple data latches may be a cache latch. The cache latch may store data to be output to the memory controller.

[0113] Figure 11 is a diagram illustrating the main verification operation and pre-verification operation of a memory device.

[0114] The program state (P) illustrated in FIG. 11 may be any one of the first to seventh program states illustrated in FIG. 2. The memory device (100) may perform a main verification operation using a main verification voltage (Vvfym) and a pre-verification operation using a pre-verification voltage (Vvfyp). The main verification voltage (Vvfym) may be a threshold voltage corresponding to the program state (P). The main verification voltage (Vvfym) may be a threshold voltage corresponding to the target program state of each memory cell. The main verification voltage (Vvfym) may be any one of the first to seventh verification voltages (V_vfy1 to V_vfy7) illustrated in FIG. 3. The pre-verification voltage (Vvfyp) may be a voltage lower than the main verification voltage (Vvfym).

[0115] In an embodiment, the threshold voltage of memory cells for which the program voltage application operation has ended in any one of the multiple program loops may have the threshold voltage of the first to third cells (Cell1 to Cell3). Subsequently, in a verification operation, the memory device can identify the degree to which the threshold voltage of the memory cells has risen using the main verification voltage (Vvfym) and the pre-verification voltage (Vvfyp).

[0116] In an embodiment, the first cell (Cell1) may have a threshold voltage smaller than the pre-verification voltage (Vvfyp) after the program voltage application operation of one program loop is terminated. The second cell (Cell2) may have a threshold voltage larger than the pre-verification voltage (Vvfyp) and smaller than the main verification voltage (Vvfym). The third cell (Cell3) may have a threshold voltage larger than the main verification voltage (Vvfym).

[0117] The threshold voltage of the first cell (Cell1) may be raised significantly to a threshold voltage corresponding to the programmed state (P) compared to the threshold voltage of the second cell (Cell2). At this time, the first cell (Cell1) may be the cell to be programmed (PGM Cell). When the programmed voltage is applied, a program allowable voltage may be applied to the bit line connected to the first cell (Cell1). In the embodiment, the program allowable voltage may be a ground voltage.

[0118] The threshold voltage of the second cell (Cell2) may rise less than the threshold voltage of the first cell (Cell1) to a threshold voltage corresponding to the program state (P). In this case, the second cell (Cell2) may be a DPGM cell. When the program voltage is applied, a precharge voltage may be applied to the bit line connected to the second cell (Cell2). In the embodiment, the precharge voltage may be a voltage greater than the ground voltage and less than the program prohibition voltage.

[0119] The threshold voltage of the third cell (Cell3) has a threshold voltage corresponding to the program state (P), so the threshold voltage may not rise further. In this case, the third cell (Cell3) may be an inhibit cell. When the program voltage is applied, a program prohibition voltage may be applied to the bit line connected to the third cell (Cell3). In the embodiment, the program prohibition voltage may be a power supply voltage.

[0120] In an embodiment, the pre-sensing latch (1130) of FIG. 10 can store data indicating whether the memory cell connected to the bit line is a programmed cell (PGM Cell) or a DPGM cell (DPGM Cell) in a pre-verification operation using a pre-verification voltage (Vvfyp). In an embodiment, the main sensing latch (1120) of FIG. 10 can store data indicating whether the memory cell connected to the bit line is a programmed cell (PGM Cell) and a DPGM cell (DPGM Cell) or an inhibit cell in a main verification operation using a main verification voltage (Vvfym).

[0121] FIG. 12 is a diagram illustrating the operation of a page buffer according to an embodiment of the present invention.

[0122] FIG. 12 describes the operation of a page buffer in the case where the data latch is composed of three parts. That is, the data latch (1140) illustrated in FIG. 10 may be composed of a first data latch (1141), a second data latch (1142), and a third data latch (1143). In an embodiment, any one of the first data latch (1141), the second data latch (1142), and the third data latch (1143) may be a cache latch.

[0123] In FIG. 12, with reference to FIG. 5, FIG. 8, and FIG. 10, an example of a case in which a final program operation for the second physical page is performed will be described. The final program operation for the second physical page may be performed after the intermediate program operation for the sixth physical page is completed. Then, when the final program operation for the second physical page is completed, the intermediate program operation for the seventh physical page may be performed. At this time, in order to perform a cache program operation, the LSB page data of the seventh physical page may be received before the final program operation for the second physical page is completed.

[0124] First, the page buffer (1100) of FIG. 10 can receive CSB data and MSB data to be stored in the second physical page from the memory controller. Specifically, the second data latch (1142) can store CSB data, and the third data latch (1143) can store MSB data. Subsequently, the page buffer (1100) can store LSB data read from the memory cell. Specifically, the first data latch (1141) can store LSB data. Subsequently, the final program operation can be performed using the LSB data, CSB data, and MSB data stored in the first to third data latches (1141 to 1143).

[0125] Meanwhile, the pre-verification operation may be performed only until the main verification operation for the 6th program state is passed. Since the 7th program state is the program state with the highest threshold voltage among the final program states, it may not need to form a narrower threshold voltage distribution than the 1st to 6th program states. That is, since the pre-verification operation for the 7th program state may not be performed, there may be no data to be stored in the pre-sensing latch (1130) when the main verification operation for the 6th program state is passed. Accordingly, the pre-sensing latch (1130) may store the LSB data (Next-LSB) of the next physical page when the main verification operation for the 6th program state is passed. For example, referring to FIGS. 5 and 8, since the LSB data, CSB data, and MSB data stored in the 1st to 3rd data latches are data used for the final program operation of the 2nd physical page, the LSB data (Next-LSB) of the next physical page may be data to be used for the intermediate program operation of the 7th physical page.

[0126] After the final program operation for the second physical page is completed, the page buffer (1100) may store the LSB data, CSB data, MSB data of the second physical page and the LSB data of the seventh physical page. That is, since the memory controller can obtain the LSB data, CSB data, and MSB data from the memory device even if the program operation fails, the buffer memory of the memory controller may not need to store data in preparation for a program operation failure. That is, after the LSB data, CSB data, and MSB data are provided to the memory device, the buffer memory of the memory controller may remove the LSB data, CSB data, and MSB data from the buffer memory. Additionally, since the page buffer (1100) also stores the LSB data (Next-LSB) of the next physical page, it may be possible to perform a cache program operation while preparing for a program operation failure.

[0127] FIG. 13 is a diagram illustrating the operation of a page buffer according to another embodiment of the present invention.

[0128] FIG. 13 describes the operation of a page buffer in the case where the data latch is composed of three parts. That is, the data latch (1140) illustrated in FIG. 10 may be composed of a first data latch (1141), a second data latch (1142), and a third data latch (1143). In an embodiment, the third data latch (1143) may be a cache latch.

[0129] In FIG. 13, with reference to FIG. 5, FIG. 8, and FIG. 10, an example of performing a final program operation for a second physical page is described. First, the page buffer (1100) of FIG. 10 can receive CSB data and MSB data to be stored in the second physical page from the memory controller. The CSB data and MSB data can be stored in the second and third data latches (1142 to 1143). Subsequently, the page buffer (1100) can store LSB data read from the memory cell. The LSB data can be stored in the first data latch (1141). Subsequently, a final program operation for the second physical page can be performed using the LSB data, CSB data, and MSB data.

[0130] Subsequently, when a program suspend command is input from the memory controller, the final program operation may be suspended. When the final program operation is suspended, the LSB data stored in the first data latch may be transferred to the pre-sensing latch (1130). Then, the main verification data (Main-verify), which represents the result of the main verification operation for the memory cell connected to the page buffer (1100), may be stored in the main sensing latch (1120). Since the main verification data (Main-verify) is data used when the final program operation is resumed, it may be data that the page buffer (1100) must store. Accordingly, the main verification data (Main-verify) may be reflected in the CSB data and MSB data stored in the first and second data latches (1141~1142). The first and second data latches (1141 to 1142) may store modified CSB data (Mod-CSB) and modified MSB data (Mod-MSB) with the main verification data (Main-verify) reflected therein.

[0131] After the final program operation is stopped, when a read command is input from the memory controller, the main sensing latch (1120) can store sensing data that has been sensed from the data stored in the memory cell. Subsequently, the sensing data can be output to the memory controller through the third data latch (1143).

[0132] After sensing data is output to the memory controller, when a program resume command is input, the modified MSB data (Mod-MSB) can be transferred to the third data latch (1143), the modified CSB data (Mod-CSB) can be transferred to the second data latch (1142), and the LSB data can be transferred to the first data latch (1141). Subsequently, the final program operation can be resumed using the LSB data, the modified CSB data (Mod-CSB), and the modified MSB data (Mod-MSB). Since the LSB data is stored in the first data latch (1141) without being modified, unlike the CSB data and MSB data, an additional data latch may not be required to store the LSB data in the page buffer rather than the buffer memory of the memory controller.

[0133] After the final program operation is resumed, the page buffer (1100) can store logical page data to be stored in the next physical page whenever the main verification operation for critical program states is passed. In an embodiment, when the main verification operation for the fifth program state among the final program states is passed, the first logical page data (Next-Page1) to be stored in the next physical page can be stored in the second data latch (1142). Referring to FIG. 4, since the sixth and seventh program states can be distinguished by only MSB data, the first logical page data (Next-Page1) to be stored in the next physical page can be stored in the second data latch (1142). The final program operation for the sixth and seventh program states can be performed using only MSB data.

[0134] In an embodiment, when the main verification operation for the seventh program state among the final program states passes, the second logical page data (Next-Page2) to be stored in the next physical page can be stored in the third data latch (1143).

[0135] When the final program operation is terminated, the page buffer (1100) may store LSB data, the first logical page data (Next-Page1) and the second logical page data (Next-Page2) of the next physical page. Accordingly, since the page buffer (1100) can provide LSB data to the memory controller even if the final program operation fails, the buffer memory of the memory controller may not need to store LSB data.

[0136] FIG. 14 is a diagram illustrating the operation of a page buffer according to another embodiment of the present invention.

[0137] FIG. 14 describes the operation of a page buffer in the case where the data latch is composed of four parts. That is, the data latch (1140) illustrated in FIG. 10 may be composed of a first data latch (1141), a second data latch (1142), a third data latch (1143), and a fourth data latch (1144). In an embodiment, the fourth data latch (1144) may be a cache latch.

[0138] In FIG. 14, a case in which a final program operation for a second physical page is performed is described as an example by referring to FIG. 5, FIG. 8, and FIG. 10, just as in FIG. 12. First, the page buffer (1100) of FIG. 11 can receive CSB data and MSB data to be stored in the second physical page from the memory controller. Specifically, the second data latch (1142) can store CSB data, and the third data latch (1143) can store MSB data. Subsequently, the page buffer (1100) can store LSB data read from the memory cell. Specifically, the first data latch (1141) can store LSB data. Then, the page buffer (1100) can receive LSB data (Next-LSB) of the next physical page from the memory controller. Specifically, the fourth data latch (1144) can store LSB data (Next-LSB) of the next physical page. Afterwards, the final program operation can be performed using the LSB data, CSB data, and MSB data stored in the first to third data latches (1141 to 1143).

[0139] In an embodiment, when a program operation fails, the page buffer (1100) may provide any one of the following data to the memory controller: LSB data, CSB data, MSB data, and LSB data of the next physical page (Next-LSB). For example, when a recovery command requesting LSB data from the memory controller is input, the LSB data of the next physical page (Next-LSB) stored in the fourth data latch (1144) may be stored in the pre-sensing latch (1130). Subsequently, the LSB data stored in the first data latch (1141) may be provided to the memory controller through the fourth data latch (1144).

[0140] After the final program operation for the second physical page is completed, the page buffer (1100) may store LSB data, CSB data, MSB data, and LSB data of the next physical page (Next-LSB). That is, by configuring the data latch to four, cache program operation is possible, and preparation for a program operation failure is possible. In addition, since LSB data, CSB data, and MSB data are stored in the page buffer (1100), the buffer memory of the memory controller may not need to store LSB data, CSB data, and MSB data in preparation for a program operation failure.

[0141] FIG. 15 is a diagram illustrating the operation of a page buffer according to another embodiment of the present invention.

[0142] FIG. 15 describes the operation of a page buffer in the case where the data latch is composed of four parts. That is, the data latch (1140) illustrated in FIG. 10 may be composed of a first data latch (1141), a second data latch (1142), a third data latch (1143), and a fourth data latch (1144). In an embodiment, the fourth data latch (1144) may be a cache latch.

[0143] In FIG. 15, a case in which a final program operation for a second physical page is performed is described as an example by referring to FIG. 5, FIG. 8, and FIG. 10, just as in FIG. 12. First, the page buffer (1100) of FIG. 10 can receive CSB data and MSB data to be stored in the second physical page from the memory controller. Subsequently, the page buffer (1100) can store LSB data read from the memory cell. Specifically, the first to third data latches (1141 to 1143) can store LSB data, CSB data, and MSB data, respectively. Subsequently, a final program operation for the second physical page can be performed using the LSB data, CSB data, and MSB data.

[0144] Subsequently, when a program suspend command is input, the final program operation may be stopped. When the final program operation is stopped, the LSB data stored in the first data latch (1141) may be transferred to the pre-sensing latch (1130). In the embodiment, if the main verification operation for the memory cell connected to the page buffer (1100) has passed, the main sensing latch (1120) may store main verification data (Main-verify) indicating that the program is prohibited. And, since the threshold voltage of the memory cell connected to the page buffer (1100) must not rise even after the final program operation is resumed, the main verification data (Main-verify) may be data that must be stored. And, if the main verification operation for the memory cell has passed, the LSB data, CSB data, and MSB data stored in the first to third data latches (1141 to 1143) may no longer be needed. Accordingly, the main verification data (Main-verify) can be reflected in the LSB data, CSB data, and MSB data stored in the first to third data latches (1141 to 1143). The first to third data latches (1141 to 1143) may store the modified LSB data (Mod-LSB), modified CSB data (Mod-CSB), and modified LSB data (Mod-MSB) in which the main verification data (Main-verify) is reflected. In another embodiment, if the main verification operation for the memory cell connected to the page buffer (1100) fails, the original data, namely the LSB data, CSB data, and MSB data, may be stored in the first to third data latches (1141 to 1143).

[0145] When a read command is input after the final program operation is stopped, the main sensing latch (1120) can store sensing data that has been sensed from the data stored in the memory cell. Afterwards, the sensing data can be output to the memory controller through the fourth data latch (1144).

[0146] After the sensing data is output to the memory controller, a program resume command may be received. When the program resume command is input, the LSB data stored in the pre-sensing latch (1130) may be stored in the fourth data latch (1144). Subsequently, the final program operation may be resumed.

[0147] In an embodiment, after the final program operation is resumed, the page buffer (1100) may store logical page data to be stored in the next physical page whenever the main verification operation for critical program states is passed. In an embodiment, when the main verification operation for the third program state among the final program states is passed, the first logical page data (Next-Page1) to be stored in the next physical page may be stored in the first data latch (1141). In an embodiment, the first logical page data (Next-Page1) may be LSB data. Referring to FIG. 4, since the LSB data of the fourth to seventh program states is the same as 1, the final program operation for the fourth to seventh program states may be performed using only CSB data and MSB data.

[0148] In an embodiment, when the main verification operation for the fifth program state among the final program states passes, the second logical page data (Next-Page2) to be stored in the next physical page can be stored in the first data latch (1141). In an embodiment, the second logical page data (Next-Page2) may be CSB data. Referring to FIG. 4, since the CSB data of the sixth and seventh program states is identical at 0, the final program operation for the sixth and seventh program states can be performed using only MSB data.

[0149] In an embodiment, when the main verification operation for the seventh program state among the final program states passes, the third logical page data (Next-Page3) to be stored in the next physical page can be stored in the first data latch (1141). In an embodiment, the third logical page data (Next-Page3) may be MSB data.

[0150] When the final program operation is terminated, the page buffer (1100) can store LSB data, the first logical page data (Next-Page1), the second logical page data (Next-Page2), and the third logical page data (Next-Page3) of the next physical page. Accordingly, even if the final program operation fails, the LSB data is stored in the page buffer (1100), so the buffer memory of the memory controller may not need to store the LSB data.

[0151] FIG. 16 is a diagram illustrating the cache program operation and recovery operation of a memory device.

[0152] In FIG. 16, the description of content that overlaps with FIG. 9 is omitted. In FIG. 16, the commands and addresses input from the memory controller are omitted for the convenience of explanation.

[0153] Referring to FIGS. 1 and FIGS. 16, the memory device (100) can receive CSB data and MSB data from the memory controller. Then, the memory device (100) can read LSB data from memory cells and perform a Final Program Operation (Final PGM) using the LSB data, CSB data, and MSB data. The memory device (100) can receive the first logical page data of the next physical page when the main verification operation for the third program state passes. The time during which the Final Program Operation is performed until the main verification operation for the third program state passes may be the 2-1 program time (tPROG2-1). The memory device (100) can receive the second logical page data of the next physical page when the main verification operation for the fifth program state passes. The time during which the Final Program Operation is performed until the main verification operation for the fifth program state passes may be the 2-2 program time (tPROG2-2). The memory device (100) can receive the third logical page data of the next physical page when the main verification operation for the seventh program state is passed. The time during which the final program operation is performed until the main verification operation for the seventh program state is passed may be the second-third program time (tPROG2-3). The second-fourth program time (tPROG2-4) may be the time during which the MSB data of the next physical page is stored in the third data latch.

[0154] Subsequently, the memory controller may provide a Status Read command to the memory device (100) to check whether the final program operation has passed. At this time, if the final program operation (Final PGM) has failed, the memory device (100) may provide a signal to the memory controller (200) indicating that the final program operation (Final PGM) has failed. Subsequently, the memory controller (200) may provide a Recovery command to the memory device (100) requesting LSB data required for reprogramming. The memory device (100) may provide LSB data to the memory controller (200) in response to the Recovery command.

[0155] FIG. 17 is a flowchart illustrating the intermediate program operation and final program operation of a memory device.

[0156] Referring to FIG. 17, in step S1701, the memory device (100) can perform an intermediate program operation using any one of the logical page data to be stored in the first physical page. Any one of the logical page data may be LSB page data.

[0157] In step S1703, the memory device (100) can perform a final program operation using a plurality of logical page data to be stored in the first physical page.

[0158] In step S1705, the memory device (100) may store any one of the logical page data to be stored in the second physical page when the main verification operation for the critical program state among the multiple program states passes. The critical program state may be the sixth program state. At this time, the memory device (100) may store LSB, CSB, and MSB page data to be stored in the first physical page and LSB page data to be stored in the second physical page. Since the memory device (100) stores the LSB, CSB, and MSB page data to be stored in the first physical page, it can prepare for the failure of the final program operation. Since the memory device (100) stores the LSB page data to be stored in the second physical page, it can perform a cache program operation.

[0159] In step S1707, the memory device (100) may perform an intermediate program operation using any one of the logical page data to be stored in the second physical page after the final program operation for the first physical page is terminated. Any one of the logical page data may be LSB page data.

[0160] FIG. 18 is a flowchart illustrating the program suspend, resume, and cache program operations of a memory device.

[0161] Referring to FIG. 18, in step S1801, the memory device (100) can perform a final program operation using a plurality of logical page data to be stored in the first physical page.

[0162] In step S1803, the memory device (100) may transfer any one of the logical page data to a pre-sensing latch in response to a program suspend command. Any one of the logical page data may be LSB page data to be stored in the first physical page.

[0163] In step S1805, the memory device (100) can transfer data of one logical page to the cache latch in response to a program resume.

[0164] In step S1807, the memory device (100) may store any one of the logical page data to be stored in the second physical page when the main verification operation for the third program state is passed. Any one of the logical pages may be LSB page data to be stored in the second physical page.

[0165] In step S1809, the memory device (100) may store one of the logical page data among the plurality of logical page data to be stored in the second physical page when the main verification operation for the fifth program state is passed. The other logical page data may be CSB page data to be stored in the second physical page.

[0166] In step S1811, the memory device (100) may store the remaining logical page data among the plurality of logical page data to be stored in the second physical page when the main verification operation for the seventh program state is passed. The remaining logical page data may be the MSB page data to be stored in the second physical page.

[0167] FIG. 19 is a flowchart illustrating other embodiments of program suspend, resume operation, and cache program operation of a memory device.

[0168] Referring to FIG. 19, in step S1901, the memory device (100) can perform a final program operation using a plurality of logical page data to be stored in the first physical page.

[0169] In step S1903, the memory device (100) may transfer any one of the logical page data of a plurality of logical page data to a pre-sensing latch in response to a program suspend. For example, the memory device (100) may transfer LSB data stored in a first data latch to a pre-sensing latch.

[0170] In step S1905, the memory device (100) may transfer any one logical page data to any one of the multiple data latches in response to a program resume. For example, the memory device (100) may transfer LSB data stored in a pre-sensing latch to a first data latch.

[0171] In step S1907, the memory device (100) may store first logical page data to be stored in the second physical page when the main verification operation for the fifth program state is passed. The second physical page may be a physical page to perform an intermediate program operation after the final program operation for the first physical page has been performed.

[0172] In step S1909, the memory device (100) can store second logical page data to be stored in the second physical page when the main verification operation for the seventh program state is passed.

[0173] In step S1911, the memory device (100) may provide data for one logical page to the memory controller in response to a recovery command. The recovery command may be a command received from the memory controller when the final program operation for the first physical page fails. Explanation of the symbols

[0174] 50: Memory System 100: Memory device 200: Memory controller 210: Buffer memory 300: Host

Claims

Claim 1 A memory device comprising: first memory cells programmed to have a threshold voltage corresponding to one of a plurality of program states; data latches each storing a plurality of first logical page data to be stored in the first memory cells; and a pre-sensing latch storing data sensed by a pre-verification operation; wherein the pre-sensing latch stores second logical page data to be stored in the second memory cells when a main verification operation for a critical program state among the plurality of program states is passed. Claim 2 A memory device further comprising, in claim 1, a main sensing latch that stores data sensed by the main verification operation. Claim 3 In claim 2, the main verification operation is a memory device in which the main verification operation identifies the threshold voltages of the first memory cells using a main verification voltage corresponding to any one of the program states. Claim 4 A memory device according to claim 1, wherein the pre-verification operation is an operation of identifying the threshold voltages of the first memory cells using a pre-verification voltage lower than the main verification voltage used in the main verification operation. Claim 5 A memory device according to claim 1, further comprising a control logic circuit that performs an intermediate program operation for the first memory cells using any one of the plurality of first logic page data, and then performs a final program operation for the first memory cells using the plurality of first logic page data. Claim 6 In claim 5, the control logic circuit is a memory device that performs the intermediate program operation for the second memory cells using the second logic page data after performing the final program operation for the first memory cells. Claim 7 In claim 5, the intermediate program operation is a memory device in which the threshold voltage of the first memory cells has a threshold voltage corresponding to either an erase state or an intermediate state. Claim 8 A memory device according to claim 1, wherein any one of the data latches provides any one of the logical page data among the plurality of first logical page data to an external memory controller in response to a failure of a final program operation that stores the remaining logical page data among the plurality of first logical page data in the first memory cells. Claim 9 A memory device according to claim 1, wherein the data latches acquire one of the plurality of first logical page data from the first memory cells and acquire the remaining logical page data among the plurality of first logical page data from an external memory controller. Claim 10 A memory device comprising: a memory block including a first physical page and a second physical page; data latches each storing a plurality of first logical page data to be stored in the first physical page; a cache latch storing second logical page data to be stored in the second physical page; and a pre-sensing latch storing data sensed by a pre-verification operation; wherein, when a program operation to store the plurality of first logical page data in the first physical page fails, any one of the data latches provides the logical page data of any one of the plurality of first logical page data to an external memory controller, and the cache latch transmits the second logical page data to the pre-sensing latch. Claim 11 A memory device according to claim 10, wherein the program operation comprises an intermediate program operation for storing any one of the logical page data in the first physical page and a final program operation for storing the remaining logical page data among the plurality of first logical page data in the first physical page. Claim 12 In claim 11, the intermediate program operation is a memory device in which the threshold voltages of the memory cells included in the first physical page have a threshold voltage corresponding to either an erase state or an intermediate state. Claim 13 In claim 11, the final program operation is a memory device in which the threshold voltage of each of the memory cells included in the first physical page rises to a threshold voltage corresponding to a target program state. Claim 14 delete Claim 15 In claim 11, the second logical page data is a memory device in which the second logical page data is data used for the intermediate program operation of the second physical page after the plurality of first logical page data are stored in the first physical page. Claim 16 A memory device comprising a first physical page, a second physical page, first latches storing a plurality of first logical page data to be stored in the first physical page, and a second latch storing second logical page data to be stored in the second physical page; and a memory controller that, after providing the plurality of first logical page data and the second logical page data, acquires any one of the plurality of first logical page data from the memory device in response to a failure of a program operation; wherein the second latch stores the second logical page data after a main verification operation for a critical program state among the target program states of memory cells included in the first physical page has been passed. Claim 17 In claim 16, the memory controller comprises a buffer memory for temporarily storing data to be provided to the memory device; and the plurality of first logical page data and the second logical page data provided to the memory device are removed from the buffer memory. Claim 18 In claim 16, the memory system comprises a program operation including an intermediate program operation that stores any one of the plurality of first logical page data in the first physical page, and a final program operation that stores the remaining logical page data among the plurality of first logical page data in the first physical page. Claim 19 delete Claim 20 delete Claim 21 A page buffer comprising: data latches each storing a plurality of first logical page data to be stored in a first physical page; a main sensing latch storing result information for a main verification operation; and a pre-sensing latch storing result information for a pre-verification operation; wherein, in response to a program suspend command, any one of the data latches transmits any one of the plurality of first logical page data to the pre-sensing latch, and the main sensing latch reflects the result information for the main verification operation to the plurality of first logical page data and stores data sensed by a read operation. Claim 22 A page buffer further comprising a cache latch that outputs the sensed data to an external memory controller in claim 21. Claim 23 In claim 22, the pre-sensing latch is a page buffer that transmits any one of the first logical page data to the cache latch in response to a program resume command. Claim 24 In claim 23, the cache latch is a page buffer that provides any one of the first logical page data to an external memory controller in response to a failure of a program operation that stores the plurality of first logical page data in the first physical page. Claim 25 In claim 23, the data latches are page buffers that store each of a plurality of second logical page data to be stored in a second physical page whenever the main verification operation for critical program states among the target program states of the memory cells included in the first physical page is passed. Claim 26 In claim 21, the pre-sensing latch is a page buffer that transmits any one of the first logical page data to any one of the data latches in response to a program resume command. Claim 27 In claim 26, the first logical page data stored in the data latches and the logical page data reflecting result information for the main verification operation is a page buffer that is used to resume a final program operation in which the threshold voltage of each of the memory cells included in the first physical page rises to a threshold voltage corresponding to a target program state in response to the program resume command. Claim 28 In claim 26, another data latch among the data latches is a page buffer that stores any one of a plurality of second logical page data to be stored in the second physical page when the main verification operation for a critical program state among the target program states of the memory cells included in the first physical page is passed. Claim 29 In claim 28, the program states having a threshold voltage higher than the critical program state among the target program states are page buffers that are program states programmed using another logical page data among the plurality of first logical page data. Claim 30 In claim 28, the threshold program state is a page buffer which is the target program state with the highest threshold voltage among the target program states.

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