Delay circuit of delay-locked loop circuit and delay-locked loop circuit

Abstract

The delay circuit of the delay-locked loop (DLL) circuit according to embodiments of the present invention includes a phase separator, a logic gate, and a delay line circuit. The phase separator separates the phase of a reference clock signal and outputs a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees. The logic gate delays the second reference clock signal and outputs a delayed reference clock signal. The delay line circuit includes a plurality of cascaded delay cells and delays the first reference clock signal and the delayed reference clock signal based on a control code set to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to the delay of one logic gate included in the delay cells.

Description

Technology Field

[0001] The present invention relates to the field of memory, and more specifically, to a delay circuit of a delay-locked loop circuit of a semiconductor memory device and a delay-locked loop circuit including the same. Background Technology

[0002] Semiconductor memory devices can be broadly classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices are memory devices in which stored data is lost when the power supply is cut off. Among volatile memory devices, dynamic random access memory (DRAM) is used in various fields, such as mobile systems, servers, and graphics devices.

[0003] Semiconductor memory devices can operate in synchronization with an externally applied clock. When an externally applied clock is used within the memory device, time delay (clock skew) may occur due to internal circuits. To compensate for this time delay, a Delay-Locked Loop (DLL) may be used. A Delay-Locked Loop is necessary for the memory device to synchronize with the external clock.

[0004] A delay locked loop can perform a locking operation to synchronize the phase of the input clock signal with the phase of the delayed output clock signal. The problem to be solved

[0005] The present invention provides a delay circuit of a delay fixed loop circuit capable of improving delay resolution.

[0006] One objective of the present invention is to provide a delay fixed-loop circuit having a delay circuit capable of improving delay resolution. means of solving the problem

[0007] A delay circuit of a delay-locked loop (DLL) circuit according to embodiments of the present invention for achieving the above-mentioned objective comprises a phase separator, a logic gate, and a delay line circuit. The phase separator separates the phase of a reference clock signal and outputs a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees. The logic gate delays the second reference clock signal and outputs a delayed reference clock signal. The delay line circuit comprises a plurality of cascaded delay cells and, based on a control code set, delays the first reference clock signal and the delayed reference clock signal to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to the delay of a logic gate included in the delay cells.

[0008] A delay-locked loop (DLL) circuit of a semiconductor memory device according to embodiments of the present invention for achieving the above-mentioned objective includes a first delay circuit, a second delay circuit, a clock pass circuit, a replica circuit, and a first delay controller. The first delay circuit generates a first delay clock signal and a second delay clock signal by delaying a reference clock signal based on a first control code set. The second delay circuit generates a first delay output clock signal by fine-tuning the delays of the first delay clock signal and the second delay clock signal based on a second control code set. The clock pass circuit delays the first delay output clock signal to provide an output clock signal having the same phase as the reference clock signal. The replica circuit generates a feedback clock signal by delaying the first delay output clock signal. The first delay controller adjusts the code value of the first control code set based on the first phase difference between the reference clock signal and the feedback clock signal detected during a first interval and provides the first control code set to the first delay circuit. The first delay circuit includes a phase splitter, a logic gate, and a delay line circuit. The phase splitter separates the phase of the reference clock signal and outputs a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees. The logic gate delays the second reference clock signal and outputs a delayed reference clock signal. The delay line circuit includes a plurality of cascaded delay cells and, based on the first control code set, adjusts the delay amount of the first reference clock signal and the delayed reference clock signal to output the first delayed clock signal and the second delayed clock signal having a delay amount corresponding to the delay of one logic gate included in the delay cells.

[0009] A delay circuit of a delay fixed loop circuit according to embodiments of the present invention for achieving the above-mentioned objective comprises a phase separator, a logic gate, and a delay line circuit. The phase separator separates the phase of a reference clock signal and outputs a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees. The logic gate delays the second reference clock signal and outputs a delay reference clock signal. The delay line circuit includes a plurality of cascaded delay cells and, based on a control code set, delays the first reference clock signal and the delay reference clock signal to output a first delay clock signal and a second delay clock signal having a delay amount corresponding to the delay of a logic gate included in the delay cells. The plurality of delay cells are cascaded sequentially and include first to k (k is a natural number greater than or equal to 2) delay cells configured identically. The first delay cell determines the sub-delay amount of the first reference clock signal and the delay reference clock signal and the transmission of the first reference clock signal and the delay reference clock signal to the second delay cell based on a first control bit among the control code set. Each of the first to kth delay cells includes a first to twelfth NAND gate, and based on the control code set, adjusts the delay amount between the first delay clock signal and the second delay clock signal to be equal to the delay amount of the first reference clock signal and the delay reference clock signal. Effects of the invention

[0010] According to embodiments of the present invention, a first reference clock signal and a delay reference clock signal are delayed based on a first control code set in a coarse delay line of a delay-locked loop circuit to generate a first delay clock signal and a second delay clock signal having a delay amount corresponding to the delay amount of one logic gate, thereby reducing the delay amount between the first delay clock signal and the second delay clock signal in the coarse delay line. Accordingly, bang-bang jitter that may occur after a coarse lock in the coarse delay line can be reduced. Brief explanation of the drawing

[0011] FIG. 1 is a block diagram showing a memory system according to embodiments of the present invention. FIG. 2 is a block diagram showing the configuration of a semiconductor memory device in the memory system of FIG. 1 according to embodiments of the present invention. FIG. 3 shows a first bank array in the semiconductor memory device of FIG. 2 according to embodiments of the present invention. FIG. 4 is a block diagram showing a delay-locked loop circuit in the semiconductor memory device of FIG. 2 according to embodiments of the present invention. FIG. 5 is a block diagram showing the configuration of a first delay circuit in the delay fixed loop circuit of FIG. 4 according to embodiments of the present invention. FIG. 6 is a circuit diagram showing the configuration of the first delay cell among the plurality of delay cells of FIG. 5. Figure 7 shows the delay path of the first reference clock signal and the second reference clock signal in the first delay circuit of Figure 5. Figure 8 is a waveform diagram showing various clock signals in the first delay circuit of Figure 5. FIG. 9 is a block diagram showing a second delay circuit in the delay-locked loop circuit of FIG. 4 according to embodiments of the present invention. FIG. 10 is a circuit diagram showing a delay clock generator in a second delay circuit according to embodiments of the present invention. FIG. 11 is a circuit diagram showing a phase interpolator block in a second delay circuit according to embodiments of the present invention. Figure 12 shows the operation of the phase interpolator block of Figure 11. Figure 13 shows the operation of the phase interpolator block of Figure 11. FIG. 14 shows the configuration of the first phase detector in the delay-locked loop circuit of FIG. 4 according to embodiments of the present invention. FIG. 15 shows a semiconductor memory device in the memory system of FIG. 1 according to embodiments of the present invention. FIG. 16 is a block diagram showing a delay-locked loop circuit in the semiconductor memory device of FIG. 15 according to embodiments of the present invention. FIG. 17 is a block diagram showing the multi-phase clock generator of FIG. 16 according to embodiments of the present invention. FIG. 18 is a block diagram showing the clock recovery circuit of FIG. 16 according to embodiments of the present invention. Figure 19 shows the operation of the clock recovery circuit of Figure 18. FIG. 20 is a flowchart illustrating the operation of the delay-locked loop circuit of FIG. 16 according to embodiments of the present invention. FIG. 21 is a flowchart illustrating the operation of the delay-locked loop circuit of FIG. 4 according to embodiments of the present invention. FIG. 22 is an exemplary block diagram showing a semiconductor memory device according to embodiments of the present invention. FIG. 23 is a structural diagram showing an example of a semiconductor package including a stacked memory device according to embodiments of the present invention. Specific details for implementing the invention

[0012] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0013] FIG. 1 is a block diagram showing a memory system according to embodiments of the present invention.

[0014] Referring to FIG. 1, the memory system (20) may include a memory controller (100) and a semiconductor memory device (200).

[0015] A memory controller (100) generally controls the operation of a memory system (20) and controls the overall data exchange between an external host and a semiconductor memory device (200). For example, the memory controller (100) controls the semiconductor memory device (200) to write data or read data in response to a request from the host.

[0016] Additionally, the memory controller (100) controls the operation of the semiconductor memory device (200) by applying operation commands to control the semiconductor memory device (200). According to an embodiment, the semiconductor memory device (200) may be a dynamic random access (DRAM) equipped with volatile memory cells, a double data rate 4 SDRAM (synchronous DRAM), an LPDDR4 SDRAM, or an LPDDR5 SDRAM.

[0017] The memory controller (100) transmits a clock signal (or clock, CLK), a command (CMD), and an address (ADDR) to the semiconductor memory device (200), and can exchange data (DQ) with the semiconductor memory device (200). The semiconductor memory device (200) may include a memory cell array (300) where data (DQ) is stored, a control logic circuit (210), and a delay-locked loop (DLL) circuit (400).

[0018] The delay-locked loop circuit (400) can generate a first delay clock signal and a second delay clock signal based on a reference clock signal based on a clock signal (CLK), and reduce the delay amount between the first delay clock signal and the second delay clock signal to generate an output clock signal having the same phase as the reference clock signal. The control logic circuit (210) can control access to the memory cell array (300) based on a command (CMD) and an address (ADDR), and control the operation of the delay-locked loop circuit (400).

[0019] FIG. 2 is a block diagram showing the configuration of a semiconductor memory device in the memory system of FIG. 1 according to embodiments of the present invention.

[0020] Referring to FIG. 2, the semiconductor memory device (200a) may include a control logic circuit (210), an address register (220), a bank control logic (230), a refresh counter (245), a row address multiplexer (240), a column address latch (250), a row decoder (260), a column decoder (270), a memory cell array (300), a sense amplifier section (285), an input / output gating circuit (290), an ECC engine (390), a clock buffer (225), a delay-locked loop circuit (400), and a data input / output buffer (295).

[0021] The memory cell array (300) may include first to eighth bank arrays (310 to 380). Additionally, the row decoder (260) may include first to eighth row decoders (260a to 260h) each connected to the first to eighth bank arrays (310 to 380), the column decoder (270) may include first to eighth column decoders (270a to 270h) each connected to the first to eighth bank arrays (310 to 380), and the sense amplifier unit (285) may include first to eighth sense amplifiers (285a to 285h) each connected to the first to eighth bank arrays (310 to 380).

[0022] The first to eighth bank arrays (310 to 380), the first to eighth sense amplifiers (285a to 285h), the first to eighth column decoders (270a to 270h), and the first to eighth row decoders (260a to 260h) may each constitute the first to eighth banks. Each of the first to eighth bank arrays (310 to 380) may include a plurality of word lines (WL), a plurality of bit lines (BTL), and a plurality of memory cells (MC) formed at the intersection of the word lines (WL) and the bit lines (BTL).

[0023] The address register (220) can receive an address (ADDR) including a bank address (BANK_ADDR), a row address (ROW_ADDR), and a column address (COL_ADDR) from the memory controller (100). The address register (220) can provide the received bank address (BANK_ADDR) to the bank control logic (230), provide the received row address (ROW_ADDR) to the row address multiplexer (240), and provide the received column address (COL_ADDR) to the column address latch (250).

[0024] The bank control logic (230) can generate bank control signals in response to the bank address (BANK_ADDR). In response to the bank control signals, a row decoder corresponding to the bank address (BANK_ADDR) among the first to eighth row decoders (260a to 260h) can be activated, and a column decoder corresponding to the bank address (BANK_ADDR) among the first to eighth column decoders (270a to 270h) can be activated.

[0025] The row address multiplexer (240) can receive a row address (ROW_ADDR) from the address register (220) and a refresh row address (REF_ADDR) from the refresh counter (245). The row address multiplexer (240) can optionally output the row address (ROW_ADDR) or the refresh row address (REF_ADDR) as a row address (RA). The row address (RA) output from the row address multiplexer (240) can be applied to the first to eighth bank decoders (260a to 260h), respectively.

[0026] The refresh counter (245) can sequentially increase or decrease the refresh row address (REF_ADDR) under the control of the control logic circuit (210).

[0027] Among the first to eighth bank row decoders (260a to 260h), the row decoder activated by the bank control logic (230) can decode the row address (RA) output from the row address multiplexer (240) and activate the word line corresponding to the row address. For example, the activated row decoder can apply a word line driving voltage to the word line corresponding to the row address.

[0028] The column address latch (250) receives a column address (COL_ADDR) from the address register (220) and can temporarily store the received column address (COL_ADDR). Additionally, the column address latch (250) can gradually increase the received column address (COL_ADDR) in burst mode. The column address latch (250) can apply the temporarily stored or gradually increased column address (COL_ADDR) to the first to eighth column decoders (270a to 270h), respectively.

[0029] Among the first to eighth column decoders (270a to 270h), the column decoder activated by the bank control logic (230) can activate a sense amplifier corresponding to the bank address (BANK_ADDR) and the column address (COL_ADDR) through the corresponding input / output gating circuit (290).

[0030] The input / output gating circuit (290) may include, together with circuits for gating input / output data, input data mask logic, read data latches for storing data output from the first to eighth bank arrays (310 to 380), and write drivers for writing data to the first to eighth bank arrays (310 to 380).

[0031] A codeword (CW) to be read from one of the first to eighth bank arrays (310 to 380) is detected by a sense amplifier corresponding to the one bank array and can be stored in the read data latches. The codeword (CW) stored in the read data latches can be provided to the memory controller (100) through a data input / output buffer (295) after ECC decoding is performed by the ECC engine (390).

[0032] Data (DQ) to be written to one of the first to eighth bank arrays (310 to 380) is provided to an ECC engine (390), the ECC engine (390) generates parity bits based on the data (DQ), and provides a codeword (CW) including the data (DQ) and the parity bits to an input / output gating circuit (290), and the input / output gating circuit (290) can write the codeword (CW) to a subpage of the one bank array through the write drivers.

[0033] The data input / output buffer (295) can provide data (DQ) to the ECC engine (390) based on the clock signal (CLK) during a write operation, and provide data (DQ) provided from the ECC engine (390) to the memory controller (100) based on the output clock signal (OCLK) provided by the phase-locked loop circuit (400) during a read operation. That is, the data input / output buffer (295) can output data (DQ) externally based on the output clock signal (OCLK) during a read operation.

[0034] The ECC engine (390) can perform ECC encoding and ECC decoding for data (DQ) based on a first control signal (CTL1) from the control logic circuit (210). The clock buffer (225) receives a clock signal (CLK) and provides it as a reference clock signal (REFCLK).

[0035] The delay-locked loop circuit (400) receives a reference clock signal (REFCLK), separates the phase of the reference clock signal (REFCLK) to generate a first delay reference clock signal and a second delay reference clock signal, delays the first reference clock signal and the second reference clock signal to generate a first delay clock signal and a second delay clock signal having a delay amount equal to the delay amount of one logic gate, finely adjusts the delay of the first delay clock signal and the second delay clock signal to generate an output clock signal (OCLK) having the same phase as the reference clock signal (REFCLK), and can provide the output clock signal (OCLK) to a data input / output buffer (295). The delay-locked loop circuit (400) can operate in response to a second control signal (CLT21) from the control logic circuit (210).

[0036] The control logic circuit (210) can control the operation of the semiconductor memory device (200). For example, the control logic circuit (210) can generate control signals to cause the semiconductor memory device (200) to perform a write operation or a read operation. The control logic circuit (210) may include a command decoder (211) that decodes a command (CMD) received from the memory controller (100) and a mode register (212) for setting the operation mode of the semiconductor memory device (200).

[0037] For example, the command decoder (211) can decode a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc., to generate the control signals corresponding to the command (CMD). In particular, the control logic circuit (210) can decode the command (CMD) to generate a first control signal (CTL1) that controls the ECC engine (390) and a second control signal (CTL21) that controls the delay locked loop circuit (400).

[0038] FIG. 3 shows a first bank array in the semiconductor memory device of FIG. 2 according to embodiments of the present invention.

[0039] Referring to FIG. 3, the first bank array (310) includes a plurality of word lines (WL1 to WLm, where m is an integer greater than or equal to 2), a plurality of bit lines (BL1 to BLn, where n is an integer greater than or equal to 2), and a plurality of memory cells (MCs) disposed at the intersection between the word lines (WL1 to WLm) and the bit lines (BL1 to BLn). Each of the memory cells (MCs) may include a cell transistor connected to each of the word lines (WL1 to WLm) and each of the bit lines (BL1 to BLn), and a cell capacitor connected to the cell transistor.

[0040] Word lines (WLs) to which memory cells (MCs) are connected can be defined as rows of the first bank array (310), and bit lines (BLs) to which memory cells (MCs) are connected can be defined as columns of the first bank array (310).

[0041] FIG. 4 is a block diagram showing a delay-locked loop circuit in the semiconductor memory device of FIG. 2 according to embodiments of the present invention.

[0042] Referring to FIG. 4, the delay fixed loop circuit (400) may include a coarse delay line (410), a fine delay line (450), a clock pass circuit (471), a replica circuit (472), a first phase detector (480a), a second phase detector (480b), a coarse delay controller (490), a fine delay controller (495), and DLL control logic (405).

[0043] The replica circuit (472) may include a clock path replica circuit (473) and a data path replica circuit (475). Hereinafter, the coarse delay line (410) is referred to as the first delay circuit, the fine delay line (450) is referred to as the second delay circuit, the coarse delay controller (490) is referred to as the first delay controller, and the fine delay controller (495) is referred to as the second delay controller.

[0044] The first delay circuit (410) delays the reference clock signal (REFCLK) based on the first control code set (CDCC) to generate the first delay clock signal (CLKS) and the second delay clock signal (CLKF). The second delay circuit (450) finely adjusts the delay amount of the first delay clock signal (CLKS) and the second delay clock signal (CLKF) based on the second control code set (FDCC) to generate the first delay output clock signal (CLKD1).

[0045] The clock pass circuit (471) delays the first delayed output clock signal (CLKD1) to generate an output clock signal (OCLK) having the same phase as the reference clock signal (REFCLK).

[0046] The replica circuit (472) delays the first delayed output clock signal (CLKD1) to generate a feedback clock signal (FBCLK). The clock path replica circuit (473) provides the same amount of delay as the clock buffer (225) to delay the first delayed output clock signal (CLKD1) and generate a second delayed output clock signal (CLKD2). The data path replica circuit (475) provides the same amount of delay as the data input / output buffer (295) and delays the second delayed output clock signal (CLKD2) to generate a feedback clock signal (FBCLK).

[0047] The first phase detector (480a) is activated during a first interval in response to a first enable signal (EN1), detects a first phase difference between a reference clock signal (REFCLK) and a feedback clock signal (FBCLK), and provides a first up / down (UP / DN1) signal corresponding to the first phase difference to the first delay controller (490). The first phase detector (480a) may also provide a termination signal (CEND) indicating the delay control operation of the first delay controller (490) to the DLL control logic (405) when a preset time has elapsed.

[0048] The second phase detector (480b) is activated during a second period different from the first period in response to the second enable signal (EN1), detects a second phase difference between the reference clock signal (REFCLK) and the feedback clock signal (FBCLK), and can provide a second up / down (UP / DN2) signal corresponding to the second phase difference to the second delay controller (495).

[0049] The first delay controller (490) outputs a first control code set (CDCC) to the first delay circuit (410) to coarsely adjust the delay amount of the first delay circuit (410) based on the first up / down (UP / DN1) signal. The second delay controller (495) outputs a second control code set (FDCC) to the second delay circuit (450) to finely adjust the delay amount of the second delay circuit (450) based on the second up / down (UP / DN2) signal.

[0050] The DLL control logic (405) can determine the logic levels of the first enable signal (EN1) and the second enable signal (EN2) in response to the initialization enable signal (INI_EN). When the initialization enable signal (INIT_EN) is activated, the DLL control logic (405) can activate the first enable signal (EN1) for a first period and deactivate the second enable signal (EN2). In response to the activation of the termination signal (CEND), the DLL control logic (405) can deactivate the first enable signal (EN1) and activate the second enable signal (EN2) for a second period. The initialization enable signal (INI_EN) may be included in the second control signal (CTL21) of FIG. 2.

[0051] FIG. 5 is a block diagram showing the configuration of a first delay circuit in the delay fixed loop circuit of FIG. 4 according to embodiments of the present invention.

[0052] Referring to FIG. 5, the first delay circuit (410) includes a phase separator (411), a logic gate (413), and a delay line circuit (415). The delay line circuit (415) may include a plurality of delay cells (420a, 420b, …, 420k, where k is a natural number greater than or equal to 3) that are cascaded sequentially. The plurality of delay cells (420a, 420b, …, 420k) may be referred to as the first to kth delay cells.

[0053] The phase splitter (411) receives a reference clock signal (REFCLK) and separates the phase of the reference clock signal (REFCLK) to generate a first reference clock signal (REFCLK0=INd) and a second reference clock signal (REFCLK180=INb) having a phase difference of 180 degrees.

[0054] The logic gate (413) is composed of a NAND gate and performs a NAND operation on the second reference clock signal (INb) and the power supply voltage (VDD) to output a delayed reference clock signal (IND).

[0055] A plurality of delay cells (420a, 420b, …, 420k) can delay a first reference clock signal (INd) and a delay reference clock signal (IND) based on a first control code set (CDCC) to output a first delay clock signal (CLKF) and a second delay clock signal (CLKS) having a delay amount corresponding to the delay amount of one logic gate included in each of the delay cells (420a, 420b, …, 420k).

[0056] The first delay cell (420a) can receive a first control code (CDCC1) including select control bits (SEL1) and forward control bits (ON1). The second delay cell (420b) can receive a second control code (CDCC2) including select control bits (SEL2) and forward control bits (ON2). The k-th delay cell (420k) can receive a k-th control code (CDCCk) including select control bits (SELk) and forward control bits (ONk).

[0057] FIG. 6 is a circuit diagram showing the configuration of the first delay cell among the plurality of delay cells of FIG. 5.

[0058] FIG. 6 shows the configuration of the first delay cell (420a), but the configuration of each of the delay cells (420b to 420k) may be the same as the configuration of the first delay cell (420a).

[0059] Referring to FIG. 6, the first delay cell (420a) may include first to twelfth NAND gates (421 to 428, 431 to 434).

[0060] In FIG. 6, the selection control bits (SEL1) may include first to fourth selection control bits (SEL11, SEL12, SEL13, SEL14), and the forward control bits (ON1) may include a first forward control bit (ON11) and a second forward control bit (ON12).

[0061] The first NAND gate (421) performs a NAND operation on the first reference clock signal (INd) and the first selection control bit (SEL11). The second NAND gate (422) performs a NAND operation on the first reference clock signal (INd) and the first transfer control bit (ON11). The third NAND gate (423) performs a NAND operation on the delayed reference clock signal (IND) and the first transfer control bit (ON11). The fourth NAND gate (424) performs a NAND operation on the delayed reference clock signal (IND) and the second selection control bit (SEL12).

[0062] The fifth NAND gate (425) performs a NAND operation on the output of the second NAND gate (422) and the third selection control bit (SEL13). The sixth NAND gate (426) performs a NAND operation on the output of the second NAND gate (422) and the second transfer control bit (ON12), and provides the result of the NAND operation to the second delay cell (420b). The seventh NAND gate (427) performs a NAND operation on the output of the third NAND gate (423) and the second transfer control bit (ON12), and provides the result of the NAND operation to the second delay cell (420b). The eighth NAND gate (428) performs a NAND operation on the output of the third NAND gate (423) and the fourth selection control bit (SEL14).

[0063] The ninth NAND gate (431) performs a NAND operation on the output of the fifth NAND gate (425) and the first transfer signal (TS11) from the second delay cell (420b). The tenth NAND gate (432) performs a NAND operation on the output of the eighth NAND gate (428) and the second transfer signal (TS12) from the second delay cell (420b).

[0064] The 11th NAND gate (433) performs a NAND operation on the output of the 1st NAND gate (421) and the output of the 9th NAND gate (431) to output a 1st delayed clock signal (CLKF). The 12th NAND gate (434) performs a NAND operation on the output of the 4th NAND gate (424) and the output of the 10th NAND gate (432) to output a 2nd delayed clock signal (CLKS).

[0065] The sub-delay amount of the first delay cell (420a) can be determined by the selection control bits (SEL11, SEL12, SEL13, SEL14) and the first transfer control bit (ON11). That is, if the first and second selection control bits (SEL11, SEL12) are at a high level and the first transfer control bit (ON11) is at a low level, the sub-delay amount of the first delay cell (420a) may correspond to the delay amount of two NAND gates. If the first and second selection control bits (SEL11, SEL12) are at a low level and the first transfer control bit (ON11) is at a high level, the third and fourth selection control bits (SEL13, SEL14) are at a high level and the second transfer control bit (ON12) is at a low level, the sub-delay amount of the first delay cell (420a) may correspond to the delay amount of four NAND gates.

[0066] The transmission of the delay reference clock signal (IND) and the first reference clock signal (INd) to the second delay cell (420b) can be determined by the second transmission control bit (ON12).

[0067] If the second transfer control bit (ON12) is at a high level, the sixth NAND gate (426) transfers the output of the second NAND gate (422) to the second delay cell (420b), and if the second transfer control bit (ON12) is at a low level, the sixth NAND gate (426) does not transfer the output of the second NAND gate (422) to the second delay cell (420b). Additionally, if the second transfer control bit (ON12) is at a high level, the seventh NAND gate (427) transfers the output of the third NAND gate (423) to the second delay cell (420b), and if the second transfer control bit (ON12) is at a low level, the seventh NAND gate (427) does not transfer the output of the third NAND gate (427) to the second delay cell (420b).

[0068] As described above, the first and second selection control bits (SEL11, SEL12) are enabled or disabled as a set, and the third and third selection control bits (SEL13, SEL14) are enabled or disabled.

[0069] Therefore, as the amount of delay to be controlled increases, the number of bits activated in the selection control bits (SEL1~SELk) of Fig. 5 increases by two, and only one bit can be activated in each of the transmission control bits (ON1~ONk).

[0070] Figure 7 shows the delay path of the first reference clock signal and the second reference clock signal in the first delay circuit of Figure 5.

[0071] In Fig. 7, it is assumed that the second transfer control bit (ON12) is at a low level.

[0072] Referring to FIGS. 5 through 7, when the first and second selection control bits (SEL11, SEL12) are at a high level and the first transfer control bit (ON11) is at a low level, the first reference clock signal (INd) is delayed through two NAND gates (421, 433) as indicated by reference number (443) and provided as the first delayed clock signal (CLKF), and the second reference clock signal (INb) is delayed through three NAND gates (413, 424, 434) as indicated by reference number (441) and provided as the second delayed clock signal (CLKS).

[0073] When the first and second selection control bits (SEL11, SEL12) are at a low level, the first transmission control bit (ON11) is at a high level, and the first and second selection control bits (SEL11, SEL12) are at a high level, the first reference clock signal (INd) is delayed through four NAND gates (422, 425, 431, 433) as indicated by reference number (444) and provided as a first delayed clock signal (CLKF), and the second reference clock signal (INb) is delayed through five NAND gates (413, 423, 428, 432, 434) as indicated by reference number (442) and provided as a second delayed clock signal (CLKS).

[0074] Therefore, the second reference clock signal (INb) can be delayed by the delay amount of one NAND gate with respect to the first reference clock signal (INd).

[0075] Figure 8 is a waveform diagram showing various clock signals in the first delay circuit of Figure 5.

[0076] Referring to FIGS. 5 to 8, a phase separator (411) separates the phase of a reference clock signal (REFCLK) to output a first reference clock signal (INd) and a second reference clock signal (INb) having a phase difference of 180 degrees. A NAND gate (413) inverts and delays the second reference clock signal (INb) to output a delayed reference clock signal (IND). Accordingly, the first reference clock signal (INd) and the delayed reference clock signal (IND) have a phase difference corresponding to a delay amount (445).

[0077] The delay cells (420a, 420b, …, 420k) delay the first reference clock signal (INd) and the delay reference clock signal (IND) to output the first delay clock signal (CLKF) and the second delay clock signal (CLKS). The first delay clock signal (CLKF) and the second delay clock signal (CLKS) have a phase difference corresponding to the delay amount (446).

[0078] As described with reference to FIGS. 6 and FIGS. 7, the delay amount (446) may be the same as the delay amount (445) and may correspond to the delay amount of one NAND gate.

[0079] FIG. 9 is a block diagram showing a second delay circuit in the delay-locked loop circuit of FIG. 4 according to embodiments of the present invention.

[0080] Referring to FIG. 9, the second delay circuit (450) includes a delay clock generator (450a) and a phase interpolator block (460).

[0081] The delay clock generator (450a) delays the first delay clock signal (CLKF) and the second delay clock signal (CLKS) to generate first to third sub-delay clock signals (CLKFD, CLKFS, CLKSD). The phase interpolator (460) outputs a first delay output clock signal (CLKD1) by fine-tuning the delay amount of the first to third sub-delay clock signals (CLKFD, CLKFS, CLKSD) in response to the second control code set (FDCC). The phase interpolator (460) can output a first delay output clock signal (CLKD1) by adjusting the slope (slew) of the first to third sub-delay clock signals (CLKFD, CLKFS, CLKSD) in response to the second control code set (FDCC).

[0082] FIG. 10 is a circuit diagram showing a delay clock generator in a second delay circuit according to embodiments of the present invention.

[0083] Referring to FIG. 10, the delay clock generator (450a) may include a plurality of inverters (451 to 459).

[0084] Inverters (451, 452, 453) invert the first delay clock signal (CLKF). Inverters (454, 455, 456) invert the second delay clock signal (CLKS). Inverter (457) inverts the outputs of inverters (451, 452) to output the first sub-delay clock signal (CLKFD). Inverter (458) inverts the outputs of inverters (453, 454) to output the second sub-delay clock signal (CLKFS). Inverter (459) inverts the outputs of inverters (455, 456) to output the third sub-delay clock signal (CLKSD).

[0085] Accordingly, the first sub-delay clock signal (CLKFD) is delayed by the delay amount of two inverters compared to the first delay clock signal (CLKF), the second sub-delay clock signal (CLKFS) is delayed by the sum of the delay amount of two inverters compared to the first delay clock signal (CLKF) and the delay amount between the first delay clock signal (CLKF) and the second delay clock signal (CLKS), and the third sub-delay clock signal (CLKSD) can be delayed by the delay amount of two inverters compared to the second delay clock signal (CLKS).

[0086] FIG. 11 is a circuit diagram showing a phase interpolator block in a second delay circuit according to embodiments of the present invention.

[0087] Referring to FIG. 11, the phase interpolator block (460) may include a plurality of phase interpolators (460a, 460b, 460c, 460d) and an inverter (469).

[0088] The phase interpolator (460a) may include PMOS transistors (461a–464a) and NMOS transistors (465a–468a). PMOS transistors (461a, 463a) and NMOS transistors (465a, 467a) are connected in a cascode form between the power supply voltage (VDD) and the ground voltage (VSS), and PMOS transistors (462a, 464a) and NMOS transistors (466a, 468a) are connected in a cascode form between the power supply voltage (VDD) and the ground voltage (VSS).

[0089] The gates of the PMOS transistor (461a) and the gate of the NMOS transistor (467a) receive a first sub-delay clock signal (CLKFD), the gates of the PMOS transistor (462a) and the gate of the NMOS transistor (468a) receive a second sub-delay clock signal (CLKFS), the gates of the PMOS transistor (463a) and the gate of the NMOS transistor (466a) receive a second control bit (FDCC2) of a second control code set (FDCC), and the gates of the PMOS transistor (464a) and the gate of the NMOS transistor (465a) receive a first control bit (FDCC1) of a second control code set (FDCC). The PMOS transistor (464a) and the NMOS transistor (466a) are connected at node (N11).

[0090] The configuration of the phase interpolator (460b) may be the same as the configuration of the phase interpolator (460a).

[0091] The phase interpolator (460c) may include PMOS transistors (461c–464c) and NMOS transistors (465c–468c). PMOS transistors (461c, 463c) and NMOS transistors (465c, 467c) are connected in a cascode form between the power supply voltage (VDD) and the ground voltage (VSS), and PMOS transistors (462c, 464c) and NMOS transistors (466c, 468c) are connected in a cascode form between the power supply voltage (VDD) and the ground voltage (VSS).

[0092] The gates of the PMOS transistor (461c) and the gate of the NMOS transistor (467c) receive a third sub-delay clock signal (CLKSD), the gates of the PMOS transistor (462c) and the gate of the NMOS transistor (468c) receive a second sub-delay clock signal (CLKFS), the gates of the PMOS transistor (463c) and the gate of the NMOS transistor (466c) receive a second control bit (FDCC2), and the gates of the PMOS transistor (464c) and the gate of the NMOS transistor (465c) receive a first control bit (FDCC1). The PMOS transistor (464c) and the NMOS transistor (466c) are connected at node (N21).

[0093] The configuration of the phase interpolator (460d) may be the same as the configuration of the phase interpolator (460c).

[0094] Node (N11) and Node (N21) are connected to each other, and the inverter (469) averages the voltage levels of Node (N11) and Node (N21) to provide a first delayed output clock signal (CLKD1).

[0095] Phase interpolators (460a, 460b, 460c, 460d) can output a first delayed output clock signal (CLKD1) by adjusting the slope of each edge of the first to third sub-delay clock signals (CLKFD, CLKFS, CLKSD) based on the second control code (FDCC).

[0096] Figure 12 shows the operation of the phase interpolator block of Figure 11.

[0097] Referring to FIG. 12, as described with reference to FIG. 11, phase interpolators (460a, 460b, 460c, 460d) can subdivide the phase of the first sub-delay clock signal (CLKFD) in response to the second control code (FDCC) (469a) and interpolate the subdivided phases to provide the first first delay output clock signal (CLKD1).

[0098] Figure 13 shows the operation of the phase interpolator block of Figure 11.

[0099] Referring to FIG. 13, as described with reference to FIG. 11, phase interpolators (460a, 460b, 460c, 460d) can subdivide the phase of the third sub-delay clock signal (CLKFS) in response to the second control code (FDCC) (469a) and interpolate the subdivided phases to provide the first delay output clock signal (CLKD1).

[0100] FIG. 14 shows the configuration of the first phase detector in the delay-locked loop circuit of FIG. 4 according to embodiments of the present invention.

[0101] Referring to FIG. 14, the first phase detector (480a) may include a first flip-flop (481), a second flip-flop (482), and an AND gate (483).

[0102] The first flip-flop (481) can be synchronized with the reference clock signal (REFCLK), and the second flip-flop (4822) can be synchronized with the feedback clock signal (FBCLK). In each of the first and second flip-flops (481, 482), the data input (D) can be connected to the power supply voltage (VDD). That is, the data input (D) can be connected to logic '1'. The first flip-flop (481) can output an output (Q) of logic '1' on the rising edge of the reference clock signal (REFCLK). The second flip-flop (482) can output an output (Q) of logic '1' on the rising edge of the feedback clock signal (FBCLK). The output (Q) of the first flip-flop (481) can be the first up signal (UP1), and the output (Q) of the second flip-flop (482) can be the first down signal (DN1).

[0103] The AND gate (483) can perform an AND operation on the output (Q) of the first flip-flop (481) and the output (Q) of the second flip-flop (482) and output a reset signal (RST). The reset signal (RST) can be transmitted to the first and second flip-flops (481, 482).

[0104] When the phase of the reference clock signal (REFCLK) is ahead of the phase of the feedback clock signal (FBCLK), the first up signal (UP1) from the rising edge of the reference clock signal (REFCLK) can be logic '1', and the first up signal (UP1) from the rising edge of the feedback clock signal (FBCLK) can be logic '0'. Similarly, when the phase of the feedback clock signal (FBCLK) is ahead of the phase of the reference clock signal (REFCLK), the first down signal (DN1) from the rising edge of the feedback clock signal (FBCLK) can be logic '1', and the first down signal (DN1) from the rising edge of the reference clock signal (REFCLK) can be logic '0'.

[0105] In summary, the first up signal (UP1) can be a logic '1' only in the interval between the rising edge of the reference clock signal (REFCLK) and the rising edge of the feedback clock signal (FBCLK) when the phase of the reference clock signal (REFCLK) is ahead of the phase of the feedback clock signal (FBCLK). The first down signal (DN1) can be a logic '1' only in the interval between the rising edge of the feedback clock signal (FBCLK) and the rising edge of the reference clock signal (REFCLK) when the phase of the feedback clock signal (FBCLK) is ahead of the phase of the reference clock signal (REFCLK).

[0106] In the delay fixed loop circuit (400) according to embodiments of the present invention, the first reference clock signal (INd) and the delay reference clock signal (IND) are delayed based on the first control code set (CDCC) in the first delay circuit (410) to generate a first delay clock signal (CLKF) and a second delay clock signal (CLKS) having a delay amount corresponding to the delay amount of one logic gate, thereby reducing the delay amount between the first delay clock signal (CLKF) and the second delay clock signal (CLKS) in the first delay circuit (410). Accordingly, bang-bang jitter that may occur after a coarse lock in the first delay circuit (410) can be reduced.

[0107] FIG. 15 shows a semiconductor memory device in the memory system of FIG. 1 according to embodiments of the present invention.

[0108] Referring to FIG. 15, the semiconductor memory device (200b) may include a control logic circuit (210), an address register (220), a bank control logic (230), a refresh counter (245), a row address multiplexer (240), a column address latch (250), a row decoder (260), a column decoder (270), a memory cell array (300), a sense amplifier section (285), an input / output gating circuit (290), an ECC engine (390), a clock buffer (225), a delay-locked loop circuit (500), and a data input / output buffer (295).

[0109] The semiconductor memory device (200b) of FIG. 15 differs from the semiconductor memory device (200a) of FIG. 2 in that it includes a delay-locked loop circuit (500) and the delay-locked loop circuit (500) is controlled in response to a second control signal (CTL22).

[0110] FIG. 16 is a block diagram showing a delay-locked loop circuit in the semiconductor memory device of FIG. 15 according to embodiments of the present invention.

[0111] Referring to FIG. 16, the delay-locked loop circuit (500) may include a multi-phase clock generator (510), a first duty cycle corrector (520), a delay line (545), a second duty cycle corrector (550), a clock tree (580), a clock recovery circuit (610), a clock multiplexer (640), a timing controller (650), a first duty cycle detector (660), and a second duty cycle detector (680). The delay-locked loop circuit (500) may further include a data replica path (585), a clock replica path (590), and a phase detector (595).

[0112] A multi-phase clock generator (510) receives a reference clock signal (REFCLK) and can generate first to fourth divided clock signals (MCLK0, MCLK90, MCLK180, MCLK270) having a phase difference of 90 degrees from each other by dividing the frequency of the reference clock signal (REFCLK). The multi-phase clock generator (510) can average the first to fourth divided clock signals (MCLK0, MCLK90, MCLK180, MCLK270) to provide an average divided clock signal (MMCLK) to a phase detector (595). The frequency of each of the first to fourth divided clock signals (MCLK0, MCLK90, MCLK180, MCLK270) may be half of the reference clock signal (REFCLK).

[0113] The first duty cycle corrector (520) corrects at least some of the duty errors of the first to fourth divided clock signals (MCLK0, MCLK90, MCLK180, MCLK270) in response to the first correction codes (CRCD0, CRCD90, CRCD180, CRCD270) and provides the first to fourth correction clock signals (FCLK0, FCLK90, FCLK180, FCLK270).

[0114] The delay line (545) delays at least a portion of the first to fourth correction clock signals (FCLK0, FCLK90, FCLK180, FCLK270) to provide the first to fourth delay clock signals (DCLK0, DCLK90, DCLK180, DCLK270). The delay line (545) may employ the first delay circuit (410) of FIG. 5. That is, the delay line (545) may delay at least a portion of the first to fourth correction clock signals (FCLK0, FCLK90, FCLK180, FCLK270) by the delay amount of one logic gate to provide the first to fourth delay clock signals (DCLK0, DCLK90, DCLK180, DCLK270).

[0115] The second duty cycle corrector (550) provides the first to fourth source clock signals (SCLK0, SCLK90, SCLK180, SCLK270) by adjusting the delay of at least some of the second to fourth delay clock signals (DCLK90, DCLK180, DCLK270) among the first to fourth delay clock signals (DCLK0, DCLK90, DCLK180, DCLK270) in response to the second correction code (QEC).

[0116] The clock tree (580) provides the first to fourth source clock signals (SCLK0, SCLK90, SCLK180, SCLK270) to the first to fourth propagating clock signals (PCLK0, PCLK90, PCLK180, PCLK270) into the semiconductor memory device (200) through internal paths.

[0117] The data replica path (585) can provide substantially the same amount of delay as the data input / output buffer (295). The clock replica path (590) can provide substantially the same amount of delay as the clock buffer (225). The data replica path (585) and the clock replica path (590) can delay the average propagation clock signal (MPCLK) provided from the clock tree (580) to provide the feedback clock signal (FBCLK) to the phase detector (595). The phase detector (595) detects the phase difference between the average divided clock signal (MMCLK) and the average propagation clock signal (MPCLK), and can adjust the amount of delay of the delay line (545) according to the detected phase difference.

[0118] The clock recovery circuit (610) receives first to fourth propagation clock signals (PCLK0, PCLK90, PCLK180, PCLK270), generates a first recovery clock signal (RCLK0) and a second recovery clock signal (RCLK180) based on the first to fourth propagation clock signals (PCLK0, PCLK90, PCLK180, PCLK270), and can output one of the first recovery clock signal (RCLK0) and the second recovery clock signal (RCLK180) as an output clock signal (OCLK).

[0119] The clock multiplexer (640) can select a pair of the first recovery clock (RCLK0) and the second recovery clock (RCLK180) or the first propagation clock signal (PCLK0) and the third propagation clock signal (PCLK180) according to the control of the timing controller (650), and output the selected pair to the first duty cycle detector (660).

[0120] The first duty cycle detector (660) can detect the duty error of the first propagation clock signal (PCLK0) and the third propagation clock signal (PCLK180), generate the first sub-correction code (CRCD0) and the third sub-correction code (CRCD180) based on the detected duty error, and generate the second correction code (QEC) by detecting the duty error of the first restoration clock signal (RCLK0) and the second restoration clock signal (RCLK180). The first duty cycle detector (660) can provide the first sub-correction code (CRCD0) and the third sub-correction code (CRCD180) to the first duty cycle corrector (520) and provide the second correction code (QEC) to the second duty cycle corrector (550).

[0121] The second duty cycle detector (680) can detect the duty error of the second propagation clock signal (PCLK90) and the fourth propagation clock signal (PCLK270), and generate the second sub-correction code (CRCD90) and the fourth sub-correction code (CRCD270) based on the detected duty error. The second duty cycle detector (680) can provide the second sub-correction code (CRCD90) and the fourth sub-correction code (CRCD270) to the first duty cycle corrector (520).

[0122] The timing controller (650) can control the operation timing of the first duty cycle detector (660), the second duty cycle detector (680), and the clock multiplexer (640).

[0123] FIG. 17 is a block diagram showing the multi-phase clock generator of FIG. 16 according to embodiments of the present invention.

[0124] Referring to FIG. 17, the multi-phase clock generator (510) may include a phase splitter (511) and a clock divider (513).

[0125] The phase splitter (511) separates the phase of the reference clock signal (REFCLK) and outputs a first reference clock signal (REFCLK0) and a second reference clock signal (REFCLK1810) having a phase difference of 180 degrees. The clock divider (513) divides the first reference clock signal (REFCLK0) and the second reference clock signal (REFCLK1810) by 2 each to output first to fourth divided clock signals (MCLK0, MCLK90, MCLK180, MCLK270).

[0126] FIG. 18 is a block diagram showing the clock recovery circuit of FIG. 16 according to embodiments of the present invention.

[0127] Figure 19 shows the operation of the clock recovery circuit of Figure 18.

[0128] Referring to FIGS. 18 and 19, the clock recovery circuit (610) may include multiplexers (611–615), an inverter (616), and a buffer (617).

[0129] Multiplexers (611–614) may be DDR multiplexers, and multiplexer (615) may be a balanced multiplexer. Each of the multiplexers (611–614) may output first to fourth selection clock signals (SSCLK1–SSCLK4) that are activated during one-fourth cycle of each of the first to fourth propagation clock signals (PCLK0, PCLK90, PCLK180, PCLK270) in response to selection signals (SS11–SS14).

[0130] The multiplexer (615) receives the first to fourth selection clock signals (SSCLK1 to SSCLK4) and, in response to the selection signal (SS15), alternately selects the first selection clock signal (SSCLK1) and the third selection clock signal (SSCLK3) to output the first recovery clock signal (RCLK0). The inverter (616) inverts the first recovery clock signal (RCLK0) to output the second recovery clock signal (RCLK180). The buffer (617) buffers the first recovery clock signal (RCLK0) to output the output clock signal (OCLK). The selection signals (SS11 to SS15) may be included in the second control signal (CTL22) of FIG. 15.

[0131] FIG. 20 is a flowchart illustrating the operation of the delay-locked loop circuit of FIG. 16 according to embodiments of the present invention.

[0132] Referring to FIGS. 16 to 20, the delay-locked loop circuit (500) is first activated (S210). The delay-locked loop circuit (500) is reset (S220). That is, the first correction codes (CRCD) and the second correction code (QEC) are reset.

[0133] The duty error of the input clock signals (MCLK0, MCLK90, MCLK180, MCLK270) is corrected in response to the first correction codes (CRCD) generated based on the duty error of the first to fourth propagation clock signals (PCLK0, PCLK90, PCLK180, PCLK270) (S230). The duty error of the output clock signals (DCLK0, DCLK90, DCLK180, DCLK270) is corrected in response to the second correction code (QEC) generated based on the duty error of the restoration clock signals (RCLK0, RCLK180) (S240). A coarse lock may be performed between steps (S230, S240).

[0134] FIG. 21 is a flowchart illustrating the operation of the delay-locked loop circuit of FIG. 4 according to embodiments of the present invention.

[0135] Referring to FIGS. 4 to 15 and FIG. 21, in the operation method of the delay-locked loop circuit (400), a phase splitter (411) generates a first reference clock signal (REFCLK0=INd) and a second reference clock signal (REFCLK180=INb) with a phase difference of 180 degrees from each other based on a reference clock signal (REFCLK) (S310).

[0136] A second reference clock signal (INb) is delayed and inverted at a logic gate (413) of a first delay circuit (410) to generate a delayed reference clock signal (IND), and a first reference clock signal (INd) and a delayed reference clock signal (IND) are delayed at a plurality of delay cells (420a, 420b, …, 420k) based on a first control code set (CDCC) to generate a first delayed clock signal (CLKF) and a second delayed clock signal (CLKS) having a delay amount corresponding to the delay amount of one logic gate (S320).

[0137] In the second delay circuit (450), the delay amount of the first delay clock signal (CLKF) and the second delay clock signal (CLKS) is finely adjusted based on the second control code set (FDCC) to generate the first delay output clock signal (CKLD1) (S330).

[0138] The clock pass circuit (471) delays the first delayed output clock signal (CKLD1) to generate an output clock signal (OCLK) having the same phase as the reference clock signal (REFCLK) and provides the output clock signal (OCLK) to the data input / output buffer (295). The data input / output buffer (295) outputs data (DQ) to the memory controller (100) based on the output clock signal (OCLK) (S340).

[0139] In the method of operation of the delay fixed loop circuit (400) according to embodiments of the present invention, the first reference clock signal (INd) and the delay reference clock signal (IND) are delayed based on the first control code set (CDCC) in the first delay circuit (410) to generate a first delay clock signal (CLKF) and a second delay clock signal (CLKS) having a delay amount corresponding to the delay amount of one logic gate, thereby reducing the delay amount between the first delay clock signal (CLKF) and the second delay clock signal (CLKS) in the first delay circuit (410). Accordingly, bang-bang jitter that may occur after a coarse lock in the first delay circuit (410) can be reduced.

[0140] That is, in the operation method of the delay fixed loop circuit (500) according to the embodiments of the present invention, the duty of the first propagation clock signal (PCLK0) and the second propagation clock signal (PCLK90) is detected to adjust the slope of the edge of the first divided clock signal (MCLK0) and the second divided clock signal (MCLK90) to compensate for the skew between the first divided clock and the third divided clock having a phase difference of 180 degrees, and the duty of the restored clock signal (RCLK0) is detected to adjust the delay amount of the second delayed clock signal (DCLK90) to compensate for the skew between the first divided clock and the second divided clock having a phase difference of 90 degrees.

[0141] FIG. 22 is an exemplary block diagram showing a semiconductor memory device according to embodiments of the present invention.

[0142] Referring to FIG. 22, a semiconductor memory device (700) may include at least one buffer die (710) and a plurality of memory dies (720-1, 720-2, ..., 720-p, where p is a natural number greater than or equal to 3) to provide a function for analyzing and rescuing soft data failure in a stacked chip structure.

[0143] Multiple memory dies (720-1, 720-2, ..., 720-p) are sequentially stacked on the top surface of the buffer die (710) and can communicate data through multiple through silicon via (hereinafter TSV) lines.

[0144] At least one of the plurality of memory dies (720-1, 720-2, ..., 720-p) may include a first type ECC engine (722) that generates transmission parity bits using transmission data transmitted to a cell core (721) that stores data and a buffer die (710). Here, since the first type ECC engine (722) is a circuit installed on the memory die, it may be referred to as a cell core ECC engine. The cell core (721) may include a plurality of memory cells having a DRAM cell structure.

[0145] The buffer die (710) may include a second type ECC engine (712) that generates error-corrected data by correcting the transmission error using transmission parity bits when a transmission error occurs in the transmission data received through the plurality of TSV lines. Here, the second type ECC engine (712) may be referred to as a via ECC engine since it is a circuit for correcting a transmission path failure.

[0146] The buffer die (710) may also include a delay-locked loop circuit (714) and a data input / output buffer (716). The delay-locked loop circuit (714) may employ the delay-locked loop circuit (400) of FIG. 4. The delay-locked loop circuit (714) may receive a clock signal (CLK) and provide an output clock signal (OCLK) having the same phase as the clock signal (CLK) to the data input / output buffer (716). The data input / output buffer (716) may output data (DQ) provided from the second type ECC engine (712) externally in synchronization with the output clock signal (OCLK).

[0147] The semiconductor memory device (700) may be a stacked chip type memory device or a stacked memory device that communicates the data and control signals through the TSV lines. The TSV lines may also be referred to as through-silicon electrodes.

[0148] The first type ECC engine (722) can also perform error correction on the data output from the memory die (720-p) before the transmission data is transmitted.

[0149] Transmission errors occurring in the transmitted data may be generated due to noise occurring in the TSV lines. Data failures generated due to noise occurring in the TSV lines may be soft data failures, as they are distinct from data failures caused by the memory die itself. Since such soft data failures are caused by transmission path failures, they can be detected and recovered by implementing ECC operations.

[0150] A data TSV line group (732) formed on a single memory die (720-p) may be composed of TSV lines (L1 to Lp), and a parity TSV line group (734) may be composed of TSV lines (L10 to Lq). The TSV lines (L1 to Lp) of the data TSV line group (732) and the TSV lines (L10 to Lq) of the parity TSV line group (734) may be connected to microbumps (MCBs) correspondingly formed between a plurality of memory dies (720-1 to 720-p).

[0151] The semiconductor memory device (700) may have a 3D chip structure or a 2.5D chip structure to communicate with an external memory controller via a data bus (B10). The buffer die (710) may be connected to the memory controller via the data bus (B10).

[0152] The first type ECC engine (722), which is a cell core ECC engine, outputs transmission data through the data TSV line group (732). Additionally, the first type ECC engine (722) outputs transmission parity bits through the parity TSV line group (734). The output transmission data may be data that has been error-corrected by the first type ECC engine (732).

[0153] The second type ECC engine (712), which is a via ECC engine, checks whether a transmission error has occurred in the transmission data received through the data TSV line group (732) using transmission parity bits received through the parity TSV line group (734). If a transmission error occurs, the second type ECC engine (712) corrects the transmission error in the transmission data using the transmission parity bits. If the number of bits of the transmission error cannot be corrected, the second type ECC engine (712) can output information indicating that a data error has occurred.

[0154] In the event that an error occurs in data read from high bandwidth memory (HBM) or a stacked chip structure, it must be distinguished for the analysis of the type of failure whether the error originated from the memory die itself or was caused by noise when the data was transmitted through silicon vias.

[0155] In embodiments of the present invention, as shown in FIG. 22, a cell core ECC engine is installed on the memory die and a via ECC engine is installed on the buffer die to verify the detection and correction of soft data failures. Soft data failures may include transmission errors caused by noise when data is transmitted through silicon via lines.

[0156] FIG. 23 is a structural diagram showing an example of a semiconductor package including a stacked memory device according to embodiments of the present invention.

[0157] Referring to FIG. 23, a semiconductor package (900) may include one or more stacked memory devices (910) and a graphic processing unit (GPU) (920). The stacked memory devices (910) and the GPU (920) are mounted on an interposer (930), and the interposer (930) on which the stacked memory devices (910) and the GPU (920) are mounted may be mounted on a package substrate (940). The GPU (920) may include a semiconductor device capable of performing memory control functions, and as an example, the GPU (920) may be implemented as an application processor (AP).

[0158] The stacked memory device (910) can be implemented in various forms, and according to one embodiment, the stacked memory device (910) may be a memory device in the form of High Bandwidth Memory (HBM) in which a plurality of layers are stacked. Accordingly, the stacked memory device (910) includes a buffer die and a plurality of memory dies, and the buffer die may include a delay-locked loop circuit.

[0159] A plurality of stacked memory devices (910) may be mounted on the interposer (930), and the GPU (920) may communicate with the plurality of stacked memory devices (910). As an example, each of the stacked memory devices (910) and the GPU (920) may include a physical (PHY) region, and communication between the stacked memory devices (910) and the GPU (920) may be performed through the physical (PHY) region. Meanwhile, if the stacked memory device (910) includes a direct access region, a test signal may be provided into the stacked memory device (910) through a conductive means (e.g., a solder ball (950)) mounted on the lower part of the package substrate (940) and the direct access region. Industrial applicability

[0160] The present invention can be applied to various systems using a semiconductor memory device employing a plurality of dynamic memory cells and a delay-locked loop circuit. That is, the present invention can be applied to various systems that use a semiconductor memory device as operating memory, such as smartphones, navigation systems, laptop computers, desktop computers, and game consoles.

[0161] As described above, although the present invention has been explained with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the following claims.

Claims

Claim 1 A delay circuit of a delay-locked loop (DLL) circuit comprising: a phase separator that separates the phase of a reference clock signal and outputs a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate that delays the second reference clock signal and outputs a delay reference clock signal; and a delay line circuit comprising a plurality of cascade-connected delay cells, and based on a control code set, delays the first reference clock signal and the delay reference clock signal to output a first delay clock signal and a second delay clock signal having a delay amount corresponding to the delay of one logic gate included in the delay cells. Claim 2 In claim 1, the plurality of delay cells are sequentially cascaded and include first to k (k is a natural number greater than or equal to 2) delay cells configured identically, and the first delay cell is a delay circuit of a delay fixed loop circuit that determines the sub-delay amount of the first reference clock signal and the delay reference clock signal and the transmission of the first reference clock signal and the delay reference clock signal to the second delay cell based on the first control code among the control code sets. Claim 3 In paragraph 2, the first delay cell comprises first to twelfth NAND gates, the first NAND gate performs a NAND operation on the first reference clock signal and the first selection control bit of the first control code, the second NAND gate performs a NAND operation on the first reference clock signal and the first transfer control bit of the first control code, the third NAND gate performs a NAND operation on the delay reference clock signal and the first transfer control bit, the fourth NAND gate performs a NAND operation on the delay reference clock signal and the second selection control bit of the first control code, the fifth NAND gate performs a NAND operation on the output of the second NAND gate and the third selection control bit of the first control code, the sixth NAND gate performs a NAND operation on the output of the second NAND gate and the second transfer control bit of the first control code, provides the result of the NAND operation to the second delay cell, and the seventh NAND gate is of the third NAND gate A NAND operation is performed on the output and the second transfer control bit, and the result of the NAND operation is provided to the second delay cell; the eighth NAND gate performs a NAND operation on the output of the third NAND gate and the fourth selection control bit of the first control code; the ninth NAND gate performs a NAND operation on the output of the fifth NAND gate and the first transfer signal from the second delay cell; the tenth NAND gate performs a NAND operation on the output of the eighth NAND gate and the second transfer signal from the second delay cell; and the eleventh NAND gate performs a NAND operation on the output of the first NAND gate and the output of the ninth NAND gate to output the first delay clock signal.The above 12th NAND gate is a delay circuit of a delay-locked loop circuit that performs NAND operations on the output of the 4th NAND gate and the output of the 10th NAND gate to output the 2nd delay clock signal. Claim 4 In paragraph 3, the first NAND gate, the fourth NAND gate, the fifth NAND gate, and the eighth NAND gate are delay circuits of a delay fixed loop circuit that determine the sub-delay amount in response to the first to fourth selection control bits. Claim 5 In paragraph 3, the delay circuit of the delay fixed loop, wherein the sixth NAND gate and the seventh NAND gate selectively transmit the first reference clock signal and the delay reference clock signal to the second delay cell in response to the second transfer control bit. Claim 6 In claim 1, the delay circuit of a delay fixed loop including a NAND gate that performs a NAND operation on the power supply voltage and the second reference clock signal and outputs the delay reference clock signal. Claim 7 A delay circuit of a delay fixed loop according to claim 1, wherein the delay amount between the first delay clock signal and the second delay clock signal is the same as the delay amount between the first reference clock signal and the delay reference clock signal, and the phase of the second delay clock signal is delayed by the delay amount compared to the phase of the first delay clock signal. Claim 8 A delay-locked loop (DLL) circuit of a semiconductor memory device comprises: a first delay circuit that delays a reference clock signal based on a first control code set to generate a first delay clock signal and a second delay clock signal; a second delay circuit that finely adjusts the delay of the first delay clock signal and the second delay clock signal based on a second control code set to generate a first delay output clock signal; a clock pass circuit that delays the first delay output clock signal to provide an output clock signal having the same phase as the reference clock signal; a replica circuit that delays the first delay output clock signal to generate a feedback clock signal; and a first delay controller that adjusts the code value of the first control code set based on a first phase difference between the reference clock signal and the feedback clock signal detected during a first interval and provides the first control code set to the first delay circuit, wherein the first delay circuit comprises: a phase separator that separates the phase of the reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; and a logic gate that delays the second reference clock signal to output a delayed reference clock signal. A delay fixed loop circuit comprising a delay line circuit that includes a plurality of cascade-connected delay cells, and outputs a first delay clock signal and a second delay clock signal having a delay amount corresponding to the delay of a logic gate included in the delay cells by adjusting the delay amount of the first reference clock signal and the delay reference clock signal based on the first control code set. Claim 9 In claim 8, the plurality of delay cells are sequentially cascaded and include first to k (k is a natural number greater than or equal to 2) delay cells configured identically, the first delay cell determines the sub-delay amount of the first reference clock signal and the delay reference clock signal and the transmission of the first reference clock signal and the delay reference clock signal to the second delay cell based on the first control code among the first control code sets, the first delay cell includes first to twelfth NAND gates, the first NAND gate performs a NAND operation on the first reference clock signal and the first selection control bit of the first control code, the second NAND gate performs a NAND operation on the first reference clock signal and the first transmission control bit of the first control code, the third NAND gate performs a NAND operation on the delay reference clock signal and the first transmission control bit, the fourth NAND gate performs a NAND operation on the delay reference clock signal and the second selection control bit of the first control code, and the The fifth NAND gate performs a NAND operation on the output of the second NAND gate and the third selection control bit of the first control code, the sixth NAND gate performs a NAND operation on the output of the second NAND gate and the second transfer control bit of the first control code, and provides the result of the NAND operation to the second delay cell, the seventh NAND gate performs a NAND operation on the output of the third NAND gate and the second transfer control bit, and provides the result of the NAND operation to the second delay cell, the eighth NAND gate performs a NAND operation on the output of the third NAND gate and the fourth selection control bit of the first control code, and the ninth NAND gate performs a NAND operation on the output of the fifth NAND gate and the first transfer signal from the second delay cell,A delay-locked loop circuit wherein the 10th NAND gate performs a NAND operation on the output of the 8th NAND gate and a second transfer signal from the second delay cell, the 11th NAND gate performs a NAND operation on the output of the 1st NAND gate and the output of the 9th NAND gate to output the first delay clock signal, and the 12th NAND gate performs a NAND operation on the output of the 4th NAND gate and the output of the 10th NAND gate to output the second delay clock signal. Claim 10 In claim 8, the second delay circuit comprises: a delay clock generator that delays the first delay clock signal and the second delay clock signal to generate first to third sub-delay clock signals; and a delay fixed loop circuit including a phase interpolator block that outputs the first delay output clock signal by finely adjusting the delay amount of the first to third sub-delay clock signals in response to the second control code set.

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