Memory controller and memory system

Abstract

A memory controller of a memory system comprising a memory device and a memory controller comprises a buffer memory including memory banks, one or more host access units that perform access to the buffer memory for a host, one or more memory access units that perform access to the buffer memory for a memory device, and a processor that controls the operation of the memory controller. The processor divides the memory banks into an external memory bank group for external operations related to the host and an internal memory bank group for internal operations within the memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform external operations and access the internal memory bank group to perform internal operations. Accordingly, bank conflicts in which the host and memory access units access the same memory bank in the memory system are prevented, and the utilization of the buffer memory can be improved.

Description

Technology Field

[0001] The present invention relates to a semiconductor integrated circuit, and more specifically to a memory controller and a memory system. Background Technology

[0002] Semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices depending on whether stored data is lost when the power supply is interrupted. Volatile memory devices offer fast read and write speeds but have the disadvantage that stored content is lost when the power supply is cut off. On the other hand, nonvolatile memory devices preserve their contents even when the power supply is interrupted. Therefore, nonvolatile memory devices are used to store content that needs to be preserved regardless of whether power is supplied.

[0003] A semiconductor memory device is controlled by a memory controller. The memory controller can temporarily store data received from a host in a buffer memory and write the data stored in the buffer memory to the semiconductor memory device. Additionally, the memory controller can temporarily store data read from the semiconductor memory device in the buffer memory and transmit the data stored in the buffer memory to the host. Furthermore, the memory controller can utilize the buffer memory to temporarily store data from the semiconductor memory device in order to perform internal operations such as garbage collection. The problem to be solved

[0004] One objective of the present invention is to provide a memory controller capable of preventing or reducing bank conflicts for buffer memory.

[0005] Another objective of the present invention is to provide a memory system including the memory controller. means of solving the problem

[0006] To achieve the above objective, the memory controller of a memory system including a memory device and a memory controller according to embodiments of the present invention comprises a buffer memory including memory banks, one or more host access units that perform access to the buffer memory for a host, one or more memory access units that perform access to the buffer memory for the memory device, and a processor that controls the operation of the memory controller. The processor divides the memory banks into an external memory bank group for external operations related to the host and an internal memory bank group for internal operations within the memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operations and access the internal memory bank group to perform the internal operations.

[0007] To achieve the other objectives mentioned above, a memory system according to embodiments of the present invention includes a memory device and a memory controller that controls the operation of the memory device. The memory controller includes a buffer memory comprising memory banks, one or more host access units that perform access to the buffer memory for a host, one or more memory access units that perform access to the buffer memory for the memory device, and a processor that controls the operation of the memory controller. The processor divides the memory banks into an external memory bank group for external operations related to the host and an internal memory bank group for internal operations within the memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operations and access the internal memory bank group to perform the internal operations. Effects of the invention

[0008] In a memory controller and memory system according to embodiments of the present invention as described above, the processor of the memory controller divides the memory banks of the buffer memory into an external memory bank group for external operations and an internal memory bank group for internal operations, and host access units access the external memory bank group, and memory access units access the external memory bank group to perform the external operations and access the internal memory bank group to perform the internal operations. Accordingly, bank conflicts in which the host and memory access units access the same memory bank in the memory system are prevented, and the utilization of the buffer memory can be improved. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing a memory system having a memory controller according to embodiments of the present invention and an electronic system including the same. Figure 2 is a diagram illustrating an example of memory bank allocation for buffer memory by the memory controller shown in Figure 1. FIG. 3 is a block diagram showing a memory controller according to one embodiment of the present invention. FIG. 4 is a flowchart illustrating an example of a buffer index request operation of a host access manager or memory access manager included in a memory controller. Figure 5 is a flowchart illustrating an example of the operation of a buffer allocator included in a memory controller. FIG. 6 is a diagram illustrating an example in which a memory controller according to an embodiment of the present invention changes external and internal memory bank groups according to the traffic volumes of internal and external operations. FIG. 7 is a block diagram showing a memory controller according to another embodiment of the present invention. FIG. 8 is a flowchart illustrating an example of a buffer indexing operation of a host access manager included in a memory controller. FIG. 9 is a flowchart illustrating an example of a buffer indexing operation of a memory access manager included in a memory controller. FIG. 10 is a diagram illustrating an example of memory bank allocation for buffer memory by the memory controller shown in FIG. 7. FIG. 11 is a block diagram showing a memory controller according to another embodiment of the present invention. FIG. 12 is a block diagram showing a memory controller according to another embodiment of the present invention. FIG. 13 is a block diagram showing a memory controller according to another embodiment of the present invention. FIG. 14 is a block diagram showing an electronic system according to embodiments of the present invention. FIG. 15 is a block diagram showing a memory system according to embodiments of the present invention. FIG. 16 is a block diagram showing an example of a memory device included in a memory system according to embodiments of the present invention. FIG. 17 is a perspective view showing an example of a memory block included in a memory cell array of the memory device of FIG. 16. Figure 18 is a circuit diagram showing the equivalent circuit of a memory block described with reference to Figure 17. FIG. 19 is a cross-sectional view showing an example of a memory device included in a memory system according to embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0011] FIG. 1 is a block diagram showing a memory system having a memory controller according to embodiments of the present invention and an electronic system including the same, and FIG. 2 is a diagram for explaining an example of memory bank allocation for a buffer memory by the memory controller shown in FIG. 1.

[0012] The electronic system (100) of FIG. 1 may be any computing system such as a PC (Personal Computer), server computer, data center, workstation, digital TV, set-top box, etc. in one embodiment, but is not limited thereto. In another embodiment, the electronic system (100) may be any mobile system such as a mobile phone, smartphone, tablet PC (Personal Computer), laptop computer, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), digital camera, camcorder, portable game console, music player, video player, navigation device, wearable device, IoT (Internet of Things) device, e-book, VR (Virtual Reality) device, AR (Augmented Reality) device, drone, etc.

[0013] Referring to FIG. 1, the electronic system (100) may include a host (120) and a memory system (140). The host (120) may write data (WD) (hereinafter, written data (WD)) to the memory system (140) and read data (RD) (hereinafter, read data (RD)) from the memory system (140).

[0014] The memory system (140) may include a memory device (160) and a memory controller (200) that controls the memory device (160). In one embodiment, the memory system (140) may be a storage device. For example, the memory system (140) may be a Solid State Drive (SSD), Universal Flash Storage (UFS), Multi Media Card (MMC), or embedded MMC (eMMC). If the memory system (140) is an SSD, the memory system (140) may be a device that follows the non-volatile memory express (NVMe) standard, but is not limited thereto. In another example, the memory system (140) may be implemented in the form of a Secure Digital (SD) card, a micro SD card, a memory stick, a chip card, a Universal Serial Bus (USB) card, a smart card, a Compact Flash (CF) card, or a similar form.

[0015] The memory device (160) can store write data (WD) received from the host (120). Additionally, data (RD) read from the memory device (160) can be provided to the host (120). In one embodiment, the memory device (160) may include one or more non-volatile memory devices. For example, the memory device (160) may include NAND flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory), or similar memory.

[0016] The memory controller (200) may include a buffer memory (210), at least one host access unit (220), at least one memory access unit (230), and a processor (240). In one embodiment, the memory controller (200) may further include a host interface, a memory interface, a Flash Translation Layer (FTL), an error correction code (ECC) engine, an advanced encryption standard (AES) engine, a working memory, etc.

[0017] The buffer memory (210) can temporarily store write data (WD) received from the host (120). The write data (WD) stored in the buffer memory (210) can be written to the semiconductor memory device (160). Additionally, the buffer memory (210) can temporarily store read data (RD) read from the semiconductor memory device (160). The read data (RD) stored in the buffer memory (210) can be transmitted to the host (120). Furthermore, to perform internal operations such as garbage collection, the buffer memory (210) can temporarily store data (MD) (hereinafter referred to as memory data (MD)) of the semiconductor memory device.

[0018] In one embodiment, the buffer memory (210) may be implemented as a volatile memory device such as Dynamic Random Access Memory (DRAM), but is not limited thereto. Additionally, the buffer memory (210) may include a plurality of memory banks (MB). Each memory bank (MB) may include a plurality of buffers. Each buffer may refer to memory cells of one row of a memory bank (MB), but is not limited thereto. Each data (WD, RD, MD) may be stored in each buffer of the buffer memory (210). Meanwhile, buffers within the same memory bank (MB) cannot perform data write / read operations simultaneously, but buffers within different memory banks (MB) can perform the data write / read operations substantially simultaneously.

[0019] A host access unit (220) can perform access to a buffer memory (210) for a host (120). For example, the host access unit (220) can access the buffer memory (210) to store write data (WD) received from the host (120) in the buffer memory (210). Additionally, the host access unit (220) can access the buffer memory (210) to read read data (WD) to be provided to the host (120) from the buffer memory (210). In one embodiment, the host access unit (220) can directly access the buffer memory (210), and the host access unit (220) may be called Host Direct Memory Access (HDMA).

[0020] The memory access unit (230) can perform access to the buffer memory (210) for the memory device (160). For example, the memory access unit (230) can access the buffer memory (210) to store read data (RD) read from the memory device (160) in the buffer memory (210). Additionally, the memory access unit (230) can access the buffer memory (210) to read write data (WD) to be written to the memory device (160) from the buffer memory (210). Additionally, the memory access unit (230) can access the buffer memory (210) to perform internal operations on memory data (MD) that is not transmitted to or received from the host (120) within the memory system (140). In one embodiment, the memory access unit (230) can directly access the buffer memory (210), and the memory device (160) may include at least one flash memory, and the memory access unit (230) may be called Flash Direct Memory Access (FDMA).

[0021] The processor (240) can control the operation of the memory controller (200) in response to a command received from the host (120). In one embodiment, the processor (240) may be a CPU (central processing unit), but is not limited thereto.

[0022] In a memory controller (200) according to embodiments of the present invention, the processor (240) may divide the memory banks (MB) of the buffer memory (210) into an external memory bank group (EMBG) for external operations related to the host (120) and an internal memory bank group (IMBG) for internal operations within the memory system (140). Here, the external operations may be operations on data (WD, RD) transmitted and received between the host (120) and the memory system (140). In one embodiment, the external operations may include a data writing operation for writing write data (WD) received from the host (120) to the memory device (160), and a data reading operation for providing read data (RD) read from the memory device (160) to the host (120). Additionally, the internal operations may be operations on memory data (MD) that is not transmitted or received to the host (120). In one embodiment, the internal operation may include a garbage collection operation that copies memory data (MD) of one block of the memory device (160) to another block and erases the one block to secure a free block. In another embodiment, the internal operation may further include a data migration operation that moves memory data (MD) of a region to another region when a region of the memory device (160) is set to be unused. In yet another embodiment, the internal operation may further include an on-chip buffer operation that moves memory data (MD) from a Single Level Cell (SLC) region of the memory device (160) to a Multi-Level Cell (MLC) region of the memory device (160).

[0023] To perform the above external operation, the host access unit (220) accesses the external memory bank group (EMBG) of the buffer memory (210), and the memory access unit (230) can access the external memory bank group (EMBG) of the buffer memory (210). For example, the host access unit (220) can write write data (WD) from the host (120) to memory banks (MB) within the external memory bank group (EMBG), and the memory access unit (230) can read the write data (WD) from memory banks (MB) within the external memory bank group (EMBG). Additionally, the memory access unit (230) can write read data (RD) from the memory device (160) to memory banks (MB) within the external memory bank group (EMBG), and the host access unit (220) can read the read data (RD) from memory banks (MB) within the external memory bank group (EMBG).

[0024] Additionally, to perform the above internal operation, the memory access unit (230) can access the internal memory bank group (IMBG) of the buffer memory (210). For example, the host access unit (220) can write memory data (MD) from one area of ​​the memory device (160) to memory banks (MB) within the internal memory bank group (IMBG). Additionally, to write memory data (MD) stored in the buffer memory (210) to another area of ​​the memory device (160), the host access unit (220) can read memory data (MD) from memory banks (MB) within the internal memory bank group (IMBG).

[0025] Meanwhile, in a conventional memory system, as illustrated in FIG. 2, a host access unit (or HDMA) and a memory access unit (or FDMA) can access the same memory bank of the buffer memory. As such, in a conventional memory system, a bank conflict may occur where different access units access the same memory bank. In this case, since the memory bank cannot simultaneously perform operations for the HDMA and operations for the FDMA, the utilization of the buffer memory in the conventional memory system may be reduced.

[0026] However, in the memory system (140) according to embodiments of the present invention, the memory banks (MB) of the buffer memory (210) are divided into an external memory bank group (EMBG) for the external operation and an internal memory bank group (IMBG) for the internal operation, and the host access unit (220) performing the external operation and the memory access unit (230) performing the internal operation can access different memory banks (MB). In this case, the bank conflict can be prevented or reduced, the external operation and the internal operation can be performed substantially simultaneously, and the utilization rate of the buffer memory (210) can be improved.

[0027] FIG. 3 is a block diagram showing a memory controller according to one embodiment of the present invention.

[0028] Referring to FIG. 3, the memory controller (200a) may include a buffer memory (210a), at least one host access unit (220a), at least one memory access unit (230a), and a processor (240a). In one embodiment, the processor (240a) may include a host access manager (250a), a memory access manager (260a), and a buffer allocator (270a).

[0029] The buffer memory (210a) may include a plurality of memory buffers (MB1 to MB8). FIG. 3 illustrates an example in which the buffer memory (210a) includes first to eighth memory buffers (MB1 to MB8). However, the number of memory buffers (MB1 to MB8) of the buffer memory (210a) is not limited to the example in FIG. 3. The first to eighth memory buffers (MB1 to MB) may be divided into an external memory bank group (EMBG) and an internal memory bank group (IMBG). For example, the first to fourth memory buffers (MB1 to MB4) may be grouped into an external memory bank group (EMBG), and the fifth to eighth memory buffers (MB5 to MB) may be grouped into an internal memory bank group (IMBG).

[0030] At least one host access unit (220a) can perform access to the buffer memory (210a) for the host. FIG. 3 illustrates an example in which the memory controller (200a) includes first and second host access units (HDMA1, HDMA2). However, the number of host access units (HDMA1, HDMA2) is not limited to the example of FIG. 3.

[0031] At least one memory access unit (230a) can perform access to the buffer memory (210a) for the memory device. FIG. 3 illustrates an example in which the memory controller (200a) includes first to fourth memory access units (FDMA1 to FDMA4). However, the number of memory access units (FDMA1 to FDMA4) is not limited to the example of FIG. 3.

[0032] In one embodiment, the memory controller (200a) is connected to the memory device through a plurality of channels, and the memory access units (FDMA1 to FDMA4) may be assigned to different channels. For example, if the memory controller (200a) is connected to the memory device through the first to eighth channels and includes the first to fourth memory access units (FDMA1 to FDMA4), the first memory access unit (FDMA1) may perform access for data transmitted and received through the first and second channels, the second memory access unit (FDMA2) may perform access for data transmitted and received through the third and fourth channels, the third memory access unit (FDMA3) may perform access for data transmitted and received through the fifth and sixth channels, and the fourth memory access unit (FDMA4) may perform access for data transmitted and received through the seventh and eighth channels. However, the number of channels and the number of memory access units (FDMA1 to FDMA4) are not limited to the example described above.

[0033] The host access manager (250a) can control the host access units (HDMA1, HDMA2). Additionally, the host access manager (250a) can manage external bank index pools (EBIP1, EBIP2, EBIP3, EBIP4) for each of the memory banks (MB1, MB2, MB3, MB4) within the external memory bank group (EMBG). For example, as illustrated in FIG. 3, an external memory bank group (EMBG) includes first, second, third, and fourth memory banks (MB1, MB2, MB3, MB4), and a host access manager (250a) may manage a first external bank index pool (EBIP1) for the first memory bank (MB1), a second external bank index pool (EBIP2) for the second memory bank (MB2), a third external bank index pool (EBIP3) for the third memory bank (MB3), and a fourth external bank index pool (EBIP4) for the fourth memory bank (MB4). Each external bank index pool (e.g., EBIP1) may store buffer indices of available buffers (or free buffers) of the corresponding memory bank (e.g., MB1).

[0034] To perform external operations, the host access manager (250a) provides the host access units (HDMA1, HDMA2) with buffer indices (BI3, BI4) within external bank index pools (EBIP1 to EBIP4), and the host access units (HDMA1, HDMA2) can access memory banks (MB1 to MB4) of an external memory bank group (EMBG) based on the buffer indices (BI3, BI4). Meanwhile, when the host access manager (250a) provides the buffer indices (BI3, BI4) to the host access units (HDMA1, HDMA2), the host access manager (250a) can delete the provided buffer indices (BI3, BI4) from the external bank index pools (EBIP1 to EBIP4).

[0035] In one embodiment, the host access manager (250a) may transmit a buffer index request (BI_REQ) to the buffer allocator (270a) when the number of buffer indexes stored in each external bank index pool (EBIP1 to EBIP4) is less than the reference number, as described below with reference to FIG. 4, so that each external bank index pool (EBIP1 to EBIP4) maintains a reference number of buffer indexes. For example, the maximum number of buffer indexes in each external bank index pool (EBIP1 to EBIP4) may be set by registers within the memory controller (200a), and the reference number may correspond to about 50% of the maximum number of buffer indexes, but is not limited thereto. Additionally, for example, the host access manager (250a) may send a buffer index request (BI_REQ) to the buffer allocator (270a) from when the number of buffer indexes in each external bank index pool (e.g., EBIP1) is about 50% of the maximum number of buffer indexes, i.e., less than the reference number, until the number of buffer indexes in the external bank index pool (e.g., EBIP1) becomes about 80% of the maximum number of buffer indexes.

[0036] When transmitting a buffer index request (BI_REQ), the host access manager (250a) may transmit to the buffer allocator (270a) a bank address (BA1) for a buffer memory corresponding to an external bank index pool where the number of buffer indices is less than the reference number. For example, if the number of buffer indices in the first external bank index pool (EBIP1) is less than the reference number, the host access manager (250a) may transmit to the buffer allocator (270a) a buffer index request (BI_REQ) containing the bank address (BA1) of the first memory bank (MB1) corresponding to the first external bank index pool (EBIP1). Additionally, the host access manager (250a) may receive a buffer index (BI1) of an available buffer (or free buffer) among the buffers of the first memory bank (MB1) from the buffer allocator (270a) and add the buffer index (BI1) to the first external bank index pool (EBIP1).

[0037] The memory access manager (260a) can control memory access units (FDMA1 to FDMA4). Additionally, the memory access manager (260a) can manage internal bank index pools (IBIP1, IBIP2, IBIP3, IBIP4) for each of the memory banks (MB5, MB6, MB7, MB8) within the internal memory bank group (IMBG). For example, as illustrated in FIG. 3, an internal memory bank group (IMBG) includes fifth, sixth, seventh, and eighth memory banks (MB5, MB6, MB7, MB8), and a memory access manager (260a) may manage a first internal bank index pool (IBIP1) for the fifth memory bank (MB5), a second internal bank index pool (IBIP2) for the sixth memory bank (MB6), a third internal bank index pool (IBIP3) for the seventh memory bank (MB7), and a fourth internal bank index pool (IBIP4) for the eighth memory bank (MB8). Each internal bank index pool (e.g., IBIP1) may store buffer indices of available buffers (or free buffers) of the corresponding memory bank (e.g., MB5).

[0038] To perform external operations, the memory access manager (260a) may receive buffer indices (BI3, BI4) from the host access manager (250a) and provide the buffer indices (BI3, BI4) to memory access units (FDMA1 to FDMA4). The memory access units (FDMA1 to FDMA4) may access memory banks (MB1 to MB4) of an external memory bank group (EMBG) based on the buffer indices (BI3, BI4) received from the host access manager (250a) through the memory access manager (260a).

[0039] To perform internal operations, the memory access manager (260a) provides the memory access units (FDMA1 to FDMA4) with a buffer index (BI5) within the internal bank index pools (IBIP1 to IBIP4), and the memory access units (FDMA1 to FDMA4) can access the memory banks (MB5 to MB8) of the internal memory bank group (IMBG) based on the buffer index (BI5). Meanwhile, when the memory access manager (260a) provides the buffer index (BI5) to the memory access units (FDMA1 to FDMA4), the memory access manager (260a) can delete the provided buffer index (BI5) from the internal bank index pools (IBIP1 to IBIP4).

[0040] In one embodiment, the memory access manager (260a) may transmit a buffer index request (BI_REQ) to the buffer allocator (270a) when the number of buffer indices stored in each internal bank index pool (IBIP1 to IBIP4) is less than the reference number, as described below with reference to FIG. 4, so that each internal bank index pool (IBIP1 to IBIP4) maintains a reference number of buffer indices. For example, the maximum number of buffer indices in each internal bank index pool (IBIP1 to IBIP4) may be set by registers within the memory controller (200a), and the reference number may correspond to about 50% of the maximum number of buffer indices, but is not limited thereto. Additionally, for example, the memory access manager (260a) may send a buffer index request (BI_REQ) to the buffer allocator (270a) from when the number of buffer indexes in each internal bank index pool (e.g., IBIP1) is about 50% of the maximum number of buffer indexes, i.e., less than the reference number, until the number of buffer indexes in the internal bank index pool (e.g., IBIP1) becomes about 80% of the maximum number of buffer indexes.

[0041] When transmitting a buffer index request (BI_REQ), the memory access manager (260a) may transmit to the buffer allocator (270a) a bank address (BA2) for a buffer memory corresponding to an internal bank index pool where the number of buffer indices is less than the reference number. For example, if the number of buffer indices in the first internal bank index pool (IBIP1) is less than the reference number, the memory access manager (260a) may transmit to the buffer allocator (270a) a buffer index request (BI_REQ) containing the bank address (BA2) of the fifth memory bank (MB5) corresponding to the first internal bank index pool (IBIP1). Additionally, the memory access manager (260a) may receive a buffer index (BI2) of an available buffer (or free buffer) among the buffers of the fifth memory bank (MB5) from the buffer allocator (270a) and add the buffer index (BI2) to the first external bank index pool (IBIP1).

[0042] The buffer allocator (270a) stores buffer indices of buffers in memory banks (MB1 to MB8) of the buffer memory (210a) and can manage whether each of the buffers in the memory banks (MB1 to MB8) is available or is a free buffer. Here, each buffer index may be the address of a corresponding buffer (e.g., memory cells of a row within a memory bank) or a value derived from the buffer address. The buffer allocator (270a) receives a buffer index request (BI_REQ) containing a bank address (BA1) of one of the memory buffers (MB1 to MB4) in an external memory bank group (EMBG) from the host access manager (250a), as described below with reference to FIG. 5, identifies a memory bank having the bank address (BA1) in response to the buffer index request (BI_REQ) containing the bank address (BA1), and transmits the buffer index (BI1) of an available buffer among the buffers of the identified memory bank to the host access manager (250a). Additionally, the buffer allocator (270a) may receive a buffer index request (BI_REQ) containing a bank address (BA2) of one of the memory buffers (MB5 to MB8) in the internal memory bank group (IMBG) from the memory access manager (260a), as described below with reference to FIG. 5, identify the memory bank having the bank address (BA2) in response to the buffer index request (BI_REQ) containing the bank address (BA2), and transmit the buffer index (BI2) of an available buffer among the buffers of the identified memory bank to the memory access manager (260a).

[0043] In a memory controller (200a) according to one embodiment of the present invention, an external memory bank group (EMBG) of the buffer memory (210a) may be used to perform the external operation, and an internal memory bank group (IMBG) of the buffer memory (210a) may be used to perform the internal operation.

[0044] For example, when a data write operation is performed as the above external operation, the host access manager (250a) provides the buffer index (BI3) of the first external bank index pool (EBIP1) to the first host access unit (HDMA1), and the first host access unit (HDMA1) can write write data (WD) to the buffer (BUF1) of the first memory bank (MB1) within the external memory bank group (EMBG) based on the buffer index (BI3). Additionally, the memory access manager (260a) can receive the buffer index (BI3) from the host access manager (250a) and provide the buffer index (BI3) to the third memory access unit (FDMA3). The third memory access unit (FDMA3) can read the write data (WD) from the buffer (BUF1) of the first memory bank (MB1) within the external memory bank group (EMBG) based on the buffer index (BI3) and provide the write data (WD) to the memory device.

[0045] In another example, when a data read operation is performed as the external operation, the host access manager (250a) may provide the buffer index (BI4) of the second external bank index pool (EBIP2) to the memory access manager (260a), and the memory access manager (260a) may provide the buffer index (BI4) to the fourth memory access unit (FDMA4). The fourth memory access unit (FDMA4) may write read data (RD) received from the memory device to the buffer (BUF2) of the second memory bank (MB2) within the external memory bank group (EMBG) based on the buffer index (BI4). Additionally, the host access manager (250a) may provide the buffer index (BI4) to the second host access unit (HDMA2). The second host access unit (HDMA2) can read data (RD) from the buffer (BUF2) of the second memory bank (MB2) in the external memory bank group (EMBG) based on the buffer index (BI4) and provide the read data (RD) to the host.

[0046] Additionally, for example, when the internal operation is performed in which memory data (MD) is copied or moved from a first area of ​​the memory device connected to a channel assigned to the first memory access unit (FDMA1) to a second area of ​​the memory device connected to a channel assigned to the second memory access unit (FDMA2), the memory access manager (260a) provides the first memory access unit (FDMA1) with a buffer index (BI5) of the second internal bank index pool (IBIP2), and the first memory access unit (FDMA1) can write memory data (MD) to a buffer (BUF3) of the sixth memory bank (MB6) within the internal memory bank group (IMBG) based on the buffer index (BI5). Additionally, the memory access manager (260a) provides the buffer index (BI5) to the second memory access unit (FDMA2), and the second memory access unit (FDMA2) reads memory data (MD) from the buffer (BUF3) of the sixth memory bank (MB6) based on the buffer index (BI5) and can provide the memory data (MD) to the memory device.

[0047] As described above, in the memory controller (200a) according to embodiments of the present invention, memory banks (MB1 to MB4) for external operation and memory banks (MB5 to MB8) for internal operation can be distinguished. Accordingly, bank conflicts in which the host and memory access units (220a, 230a) access the same memory bank are prevented, and the utilization rate of the buffer memory (210a) can be improved.

[0048] FIG. 4 is a flowchart illustrating an example of a buffer index request operation of a host access manager or memory access manager included in a memory controller.

[0049] Referring to FIGS. 3 and 4, the host access manager (250a) can compare the number of buffer indices of each external bank index pool (EBIP1 to EBIP4) with a first reference number, and the memory access manager (260a) can compare the number of buffer indices of each internal bank index pool (IBIP1 to IBIP4) with a second reference number (S410). According to embodiments, the first reference number and the second reference number may be the same or different from each other. For example, the first maximum number of buffer indices of each external bank index pool (EBIP1 to EBIP4) and the second maximum number of buffer indices of each internal bank index pool (IBIP1 to IBIP4) may be set by registers within the memory controller (200a), the first reference number may correspond to about 50% of the first maximum number of buffer indices, and the second reference number may correspond to about 50% of the second maximum number of buffer indices, but are not limited thereto. If the number of buffer indexes in each external bank index pool (EBIP1 to EBIP4) is greater than or equal to the first reference number (S410: NO), the host access manager (250a) may not output a buffer index request (BI_REQ). Additionally, if the number of buffer indexes in each internal bank index pool (IBIP1 to IBIP4) is greater than or equal to the second reference number (S410: NO), the memory access manager (260a) may not output a buffer index request (BI_REQ).

[0050] If the number of buffer indices of the first external bank index pool (EBIP1) is less than the first reference number (S410: YES), the host access manager (250a) may transmit a buffer index request (BI_REQ) to the buffer allocator (270a) containing the bank address (BA1) of the first memory bank (MB1) corresponding to the first external bank index pool (EBIP1) (S420). Additionally, if the number of buffer indices of the first internal bank index pool (IBIP1) is less than the second reference number (S410: YES), the memory access manager (260a) may transmit a buffer index request (BI_REQ) to the buffer allocator (270a) containing the bank address (BA2) of the fifth memory bank (MB5) corresponding to the first internal bank index pool (IBIP1) (S420).

[0051] If the host access manager (250a) or the memory access manager (260a) fails to receive the buffer index (BI1, BI2) from the buffer allocator (270a) and receives a failure response from the buffer allocator (270a) (S430: NO), the host access manager (250a) or the memory access manager (260a) may wait for a certain amount of time (S440) and resend the buffer index request (BI_REQ) (S420).

[0052] When the host access manager (250a) receives a buffer index (BI1) from the buffer allocator (270a) (S430: YES), the host access manager (250a) can update the first external bank index pool (EBIP1) by adding the buffer index (BI1) to the first external bank index pool (EBIP1) (S450). Additionally, when the memory access manager (260a) receives a buffer index (BI2) from the buffer allocator (270a) (S430: YES), the memory access manager (260a) can update the first internal bank index pool (IBIP1) by adding the buffer index (BI2) to the first internal bank index pool (IBIP1) (S450).

[0053] Figure 5 is a flowchart illustrating an example of the operation of a buffer allocator included in a memory controller.

[0054] Referring to FIGS. 3 and 5, the buffer allocator (270a) may receive a buffer index request (BI_REQ) containing bank addresses (BA1, BA2) from the host access manager (250a) or the memory access manager (260a) (S510).

[0055] The buffer allocator (270a) identifies a memory bank having bank addresses (BA1, BA2) of a buffer index request (BI_REQ) and can search for available buffers or free buffers among the buffers of the identified memory bank (S520). If the free buffer does not exist in the identified memory bank (S530: NO), the buffer allocator (270a) can send a failure response to the host access manager (250a) or the memory access manager (260a) (S540).

[0056] If the free buffer exists in the identified memory bank (S530: YES), the buffer allocator (270a) may transmit the buffer index (BI1, BI2) of the free buffer to the host access manager (250a) or the memory access manager (260a) (S550).

[0057] FIG. 6 is a diagram illustrating an example in which a memory controller according to an embodiment of the present invention changes external and internal memory bank groups according to the traffic volumes of internal and external operations.

[0058] Referring to FIGS. 3 and 6, the processor (240a) may group the first to fourth memory banks (MB1 to MB4) of the buffer memory (210a) into an external memory bank group (EMBG) for external operation, and group the fifth to eighth memory banks (MB5 to MB8) of the buffer memory (210a) into an internal memory bank group (IMBG) for internal operation.

[0059] In one embodiment, the processor (240a) can dynamically set an external memory bank group (EMBG) and an internal memory bank group (IMBG). The processor (240a) can compare a first traffic amount (TA1) of the external operation with a second traffic amount (TA2) of the internal operation. Additionally, if the difference between the first traffic amount (TA1) and the second traffic amount (TA2) is greater than or equal to a reference traffic amount, the number of memory banks in one of the external memory bank group (EMBG) and the internal memory bank group (IMBG) can be increased, and the number of memory banks in the other of the external memory bank group (EMBG) and the internal memory bank group (IMBG) can be decreased.

[0060] For example, if the first traffic amount (TA1) of the external operation is greater than the second traffic amount (TA2) of the internal operation, the processor (240a) can change one memory bank (MB5) from the internal memory bank group (IMBG) to the external memory bank group (EMBG), so that the external memory bank group (EMBG') has five memory banks (MB1 to MB5) and the internal memory bank group (IMBG') has three memory banks (MB6 to MB8).

[0061] FIG. 7 is a block diagram showing a memory controller according to another embodiment of the present invention, FIG. 8 is a flowchart for explaining an example of a buffer index designation operation of a host access manager included in the memory controller, FIG. 9 is a flowchart for explaining an example of a buffer index designation operation of a memory access manager included in the memory controller, and FIG. 10 is a diagram for explaining an example of memory bank allocation for a buffer memory by the memory controller shown in FIG. 7.

[0062] Referring to FIG. 7, the memory controller (200b) may include a buffer memory (210b), at least one host access unit (220b), at least one memory access unit (230b), and a processor (240b). The processor (240b) may include a host access manager (250b), a memory access manager (260b), and a buffer allocator (270b). The memory controller (200b) of FIG. 7 may have a configuration and operation similar to the memory controller (200a) of FIG. 3, except that the external memory bank group (EMBG) is further divided into external memory bank sub-groups (EMBSG1, EMBSG2) for each of the host access units (HDMA1, HDMA2).

[0063] The processor (240b) may divide the external memory bank group (EMBG) for external operation into a first external memory bank sub-group (EMBSG1) for a first host access unit (HDMA1) and a second external memory bank sub-group (EMBSG2) for a second host access unit (HDMA2). The first host access unit (HDMA1) may access at least one memory bank (MB1, MB2) within the first external memory bank sub-group (EMBSG1), and the second host access unit (HDMA2) may access at least one memory bank (MB3, MB4) within the second external memory bank sub-group (EMBSG2).

[0064] To enable each host access unit to access a corresponding external memory bank sub-group, the host access manager (250b) may assign a buffer index corresponding to each host access unit. For example, as illustrated in FIG. 8, when a command requesting an external operation is received from a host, the host access manager (250b) may determine the host access units (HDMA1, HDMA2) to perform access to the buffer memory (210b) for the external operation (S610). For example, the host access manager (250b) may alternately select the first and second host access units (HDMA1, HDMA2), but is not limited thereto. If the first host access unit (HDMA1) is selected as the host access manager to perform memory access for the external operation, the host access manager (250b) may determine the first external memory bank sub-group (EMBSG1) corresponding to the first host access unit (HDMA1) (S620). In this case, the host access manager (250b) can extract a buffer index from the first and second external bank index pools (EBIP1, EBIP2) for the first and second memory banks (MB1, MB2) within the first external memory bank sub-group (EMBSG1) (S630) and transmit the buffer index to the first host access unit (HDMA1) (S640). Accordingly, the first host access unit (HDMA1) can access the first and second memory banks (MB1, MB2) within the first external memory bank sub-group (EMBSG1) based on the buffer index.

[0065] In one embodiment, memory banks (MB5, MB6, MB7, MB8) within an internal memory bank group (IMBG) may be used sequentially or in a round-robin manner to perform internal operations. For example, to perform the internal operations, a memory access manager (260b) may select one of the internal bank index pools (IBIP1, IBIP2, IBIP3, IBIP4) for each of the memory banks (MB5, MB6, MB7, MB8) within the internal memory bank group (IMBG) in the round-robin manner and transmit the buffer index of the selected internal bank index pool to memory access units (FDMA1 to FDMA4).

[0066] As illustrated in FIG. 9, when the internal operation is performed, a memory access unit may be determined according to the channel associated with the internal operation (S710). For example, when an internal operation is performed in which memory data received through a channel assigned to the first memory access unit (FDMA1) is stored in a buffer memory (210b), the first memory access unit (FDMA1) may be determined as the memory access unit performing the memory access operation for the internal operation. The memory access manager (260b) may select a memory bank to be used for the internal operation within the internal memory bank group (IMBG) in the round-robin manner (S720), and may extract a buffer index from an internal bank index pool corresponding to the selected memory bank (S730). The memory access manager (260b) transmits the extracted buffer index to the first memory access unit (FDMA1) (S740), and the first memory access unit (FDMA1) may access the selected memory bank within the internal memory bank group (IMBG) based on the buffer index.

[0067] Meanwhile, in a conventional memory system, as illustrated in FIG. 10, a bank conflict may occur in which host access units (HDMA1, HDMA2) and memory access units (FDMA1, FDMA2, FDMA3, FDMA4) access the same memory bank of the buffer memory. However, in the memory controller (200b) according to the embodiments of the present invention, the memory banks (MB) of the buffer memory (210b) are divided into an external memory bank group (EMBG) and an internal memory bank group (IMBG), so that the host access units (HDMA1, HDMA2) performing the external operation and the memory access units (FDMA1, FDMA2, FDMA3, FDMA4) performing the internal operation can access different memory banks. Additionally, by further subdividing the external memory bank group (EMBG) into external memory bank sub-groups (EMBSG1, EMBSG2), the first and second host access units (HDMA1, HDMA2) can access different memory banks. Furthermore, by the memory access manager (260b) selecting memory banks (MB5, MB6, MB7, MB8) within the internal memory bank group (IMBG) in a round-robin manner, the memory access units (FDMA1, FDMA2, FDMA3, FDMA4) performing the internal operation can access different memory banks. Accordingly, bank collisions can be prevented or reduced, and the utilization rate of the buffer memory (210b) can be improved.

[0068] FIG. 11 is a block diagram showing a memory controller according to another embodiment of the present invention.

[0069] Referring to FIG. 11, the memory controller (200c) may include a buffer memory (210c), at least one host access unit (220c), at least one memory access unit (230c), and a processor (240c). The processor (240c) may include a host access manager (250c), a memory access manager (260c), and a buffer allocator (270c). The memory controller (200c) of FIG. 11 may have a configuration and operation similar to the memory controller (200b) of FIG. 7, except that the internal memory bank group (IMBG) is further divided into internal memory bank sub-groups (IMBSG1, IMBSG2, IMBSG3, IMBSG4) for each of the memory access units (FDMA1, FDMA2, FDMA3, FDMA4).

[0070] The processor (240c) may divide the internal memory bank group (IMBG) for internal operation into a first internal memory bank sub-group (IMBSG1) for the first memory access unit (FDMA1), a second internal memory bank sub-group (IMBSG2) for the second memory access unit (FDMA2), a third internal memory bank sub-group (IMBSG3) for the third memory access unit (FDMA3), and a fourth internal memory bank sub-group (IMBSG4) for the fourth memory access unit (FDMA4). When the first memory access unit (FDMA1) performs a memory access operation for the internal operation, the memory access manager (260c) provides the first memory access unit (FDMA1) with a buffer index of the first internal bank index pool (IBIP1), and the first memory access unit (FDMA1) can access the fifth memory bank (MB5) of the first internal memory bank sub-group (IMBSG1) based on the buffer index. When the second memory access unit (FDMA2) performs a memory access operation for the internal operation, the memory access manager (260c) provides the second memory access unit (FDMA2) with a buffer index of the second internal bank index pool (IBIP2), and the second memory access unit (FDMA2) can access the sixth memory bank (MB6) of the second internal memory bank sub-group (IMBSG2) based on the buffer index. When the third memory access unit (FDMA3) performs a memory access operation for the internal operation, the memory access manager (260c) provides the third memory access unit (FDMA3) with a buffer index of the third internal bank index pool (IBIP3), and the third memory access unit (FDMA3) can access the seventh memory bank (MB7) of the third internal memory bank sub-group (IMBSG3) based on the buffer index.When the fourth memory access unit (FDMA4) performs a memory access operation for the internal operation, the memory access manager (260c) provides the fourth memory access unit (FDMA4) with a buffer index of the fourth internal bank index pool (IBIP4), and the fourth memory access unit (FDMA4) can access the eighth memory bank (MB8) of the fourth internal memory bank sub-group (IMBSG4) based on the buffer index. Accordingly, bank collisions can be further prevented or reduced.

[0071] FIG. 12 is a block diagram showing a memory controller according to another embodiment of the present invention.

[0072] Referring to FIG. 12, the memory controller (200d) may include a buffer memory (210d), at least one host access unit (220d), at least one memory access unit (230d), and a processor (240d). The processor (240d) may include a host access manager (250d), a memory access manager (260d), and a buffer allocator (270d). The memory controller (200d) of FIG. 12 may have a configuration and operation similar to the memory controller (200c) of FIG. 11, except that each host access unit (e.g., HDMA1) alternately accesses memory banks (e.g., MB1, MB2) within the external memory bank sub-group (e.g., EMBSG1).

[0073] The first host access unit (HDMA1) can alternately access the first and second memory banks (MB1, MB2) within the first external memory bank sub-group (EMBSG1). For example, when a first host command requesting the writing of first write data (WD1) and a second host command requesting the writing of second write data (WD2) are received sequentially, the first host access unit (HDMA1) can write the first write data (WD1) to the first memory bank (MB1) within the first external memory bank sub-group (EMBSG1), and then write the second write data (WD2) to the second memory bank (MB2) within the first external memory bank sub-group (EMBSG1). Meanwhile, when the next write data is received, the first host access unit (HDMA1) can access the first memory bank (MB1) again.

[0074] FIG. 13 is a block diagram showing a memory controller according to another embodiment of the present invention.

[0075] Referring to FIG. 13, the memory controller (200e) may include a buffer memory (210e), at least one host access unit (220e), at least one memory access unit (230e), and a processor (240e). The processor (240e) may include a host access manager (250e), a memory access manager (260e), and a buffer allocator (270e). The memory controller (200e) of FIG. 13 may have a configuration and operation similar to the memory controller (200c) of FIG. 11, except that the external memory bank group (EMBG) is further divided into multiple external memory bank function groups (EMBF1, EMBF2) for each of the multiple function IDs (FID1, FID2).

[0076] A memory system including a memory controller (200e) may provide storage spaces corresponding to a plurality of function IDs (FID1, FID2) respectively to support multi-function, that is, to support virtualization of the memory system. In this case, the memory controller (200e) may receive a host command from a host that includes one of the function IDs (FID1, FID2). In response to the host command, host access units (HDMA1, HDMA2) may access an external memory bank function group corresponding to the one function ID of the host command among a plurality of external memory bank function groups (EMBF1, EMBF2).

[0077] In one embodiment, each external memory bank function group (EMBF1, EMBF2) may be further divided into external memory bank sub-groups (EMBSG1, EMBSG2, EMBSG3, EMBSG4) for each of the host access units (HDMA1, HDMA2). For example, a first external memory bank function group (EMBF1) corresponding to a first function ID (FID1) may be divided into a first external memory bank sub-group (EMBSG1) for a first host access unit (HDMA1) and a second external memory bank sub-group (EMBSG2) for a second host access unit (HDMA2), and a second external memory bank function group (EMBF2) corresponding to a second function ID (FID2) may be divided into a third external memory bank sub-group (EMBSG3) for a first host access unit (HDMA1) and a fourth external memory bank sub-group (EMBSG4) for a second host access unit (HDMA2).

[0078] For example, if a first host command (HCMD1) requesting to write the first write data (WD1) has a first function ID (FID1), the first host access unit (HDMA1) can write the first write data (WD1) to the first memory bank (MB1) of the first external memory bank sub-group (EMBSG1) corresponding to the first host access unit (HDMA1) within the first external memory bank function group (EMBF1) corresponding to the first function ID (FID1). In addition, if a second host command (HCMD2) requesting to write the second write data (WD2) has a second function ID (FID2), the second host access unit (HDMA2) can write the second write data (WD2) to the fourth memory bank (MB4) of the fourth external memory bank sub-group (EMBSG4) corresponding to the second host access unit (HDMA2) within the second external memory bank function group (EMBF2) corresponding to the second function ID (FID2).

[0079] FIG. 14 is a block diagram showing an electronic system according to embodiments of the present invention.

[0080] Referring to FIG. 14, the electronic system (100) may include a host (120) and a memory system (140). Additionally, the memory system (140) may include a memory controller (200) and a memory device (160). In one embodiment, the memory device (160) may be a non-volatile memory device (NVM). Additionally, according to an exemplary embodiment of the present invention, the host (120) may include a host controller (122) and a host memory (124). The host memory (124) may function as a buffer memory for temporarily storing data to be transmitted to the memory system (140) or data transmitted from the memory system (140).

[0081] When the memory device (160) of the memory system (140) includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the memory system (140) may include various other types of non-volatile memory. For example, the memory system (140) may include Magnetic RAM (MRAM), Spin-Transfer Torque MRAM, Conductive Bridging RAM (CBRAM), Ferroelectric RAM (FeRAM), Phase RAM (PRAM), Resistive RAM, and various other types of memory.

[0082] According to one embodiment, the host controller (122) and the host memory (124) may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller (122) and the host memory (124) may be integrated on the same semiconductor chip. As an example, the host controller (122) may be any one of a plurality of modules provided in an application processor, and the application processor may be implemented as a System on Chip (SoC). Additionally, the host memory (124) may be an embedded memory provided within the application processor, or a non-volatile memory or memory module placed outside the application processor.

[0083] The host controller (122) can manage the operation of storing data (e.g., write data) of the buffer area of ​​the host memory (124) in the memory device (160) or storing data (e.g., read data) of the memory device (160) in the buffer area.

[0084] The memory controller (200) may include a host interface (202), a memory interface (204), a buffer memory (210), a host access unit (220), a memory access unit (230), and a processor (240). In one embodiment, the processor (240) may be a central processing unit (CPU). Additionally, the memory controller (200) may further include a Flash Translation Layer (FTL) (280), a packet manager (290), an error correction code (ECC) engine, an advanced encryption standard (AES) engine, etc. The memory controller (200) may further include a working memory (not shown) on which the Flash Translation Layer (280) is loaded, and data writing and reading operations for the memory device (160) may be controlled by the CPU (240) executing the Flash Translation Layer.

[0085] The host interface (202) can transmit and receive packets with the host (120). The packet transmitted from the host (120) to the host interface (202) may include a command or data to be written to the memory device (160), and the packet transmitted from the host interface (202) to the host (120) may include a response to the command or data read from the memory device (160). The memory interface (204) can transmit data to be written to the memory device (160) to the memory device (160) or receive data read from the memory device (160). This memory interface (204) may be implemented to comply with standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0086] The flash conversion layer (280) can perform various functions such as address mapping, wear-leveling, and garbage collection. Address mapping is an operation that converts a logical address received from the host (120) into a physical address used to actually store data within the memory device (160). Wear-leveling is a technique to prevent excessive degradation of a specific block by ensuring that blocks within the memory device (160) are used uniformly, and can be implemented, for example, through firmware technology that balances the erase counts of physical blocks. Garbage collection is a technique to secure usable capacity within the memory device (160) by copying the valid data of a block to a new block and then erasing the existing block.

[0087] The packet manager (290) can generate a packet according to the protocol of the interface agreed upon with the host (120) or parse various information from a packet received from the host (120). Additionally, the buffer memory (210) can temporarily store data to be written to the memory device (160) or data to be read from the memory device (160). The buffer memory (210) may be a configuration provided within the memory controller (200), but it may also be placed outside the memory controller (200).

[0088] The ECC engine can perform error detection and correction functions for readout data read from the memory device (160). More specifically, the ECC engine can generate parity bits for write data to be written to the memory device (160), and the parity bits thus generated can be stored in the memory device (160) together with the write data. When reading data from the memory device (160), the ECC engine can correct errors in the readout data using the parity bits read from the memory device (160) together with the readout data, and output the readout data with the errors corrected.

[0089] The AES engine can perform at least one of the encryption and decryption operations on data input to the memory controller (200) using a symmetric-key algorithm.

[0090] FIG. 15 is a block diagram showing a memory system according to embodiments of the present invention.

[0091] Referring to FIG. 15, the memory system (140) may include a memory controller (200) and a memory device (160). The memory system (140) may support a plurality of channels (CH1, CH2, ..., CHm), and the memory controller (200) and the memory device (160) may be connected through the plurality of channels (CH1~CHm). For example, the memory system (140) may be implemented as a storage device such as an SSD.

[0092] The memory device (160) may include a plurality of non-volatile memory devices (NVM11, NVM12, ..., NVM1n, NVM21, NVM22, ..., NVM2n, NVMm1, NVMm2, ..., NVMmn). Each of the non-volatile memory devices (NVM11~NVMmn) may be connected to one of a plurality of channels (CH1~CHm) through a corresponding way. For example, non-volatile memory devices (NVM11–NVM1n) may be connected to a first channel (CH1) via ways (W11, W12, ..., W1n), non-volatile memory devices (NVM21–NVM2n) may be connected to a second channel (CH2) via ways (W21, W22, ..., W2n), and non-volatile memory devices (NVMm1–NVMmn) may be connected to a second channel (CHm) via ways (Wm1, Wm2, ..., Wmn). In one embodiment, each of the non-volatile memory devices (NVM11–NVMmn) may be implemented as any memory unit capable of operating according to individual commands from a memory controller (200). For example, each of the non-volatile memory devices (NVM11–NVMmn) may be implemented as a chip or a die, but the present invention is not limited thereto.

[0093] The memory controller (200) can transmit and receive signals to and from the memory device (160) through multiple channels (CH1~CHm). For example, the memory controller (200) can transmit commands (CMDa, CMDb, ..., CMDm), addresses (ADDRa, ADDRb, ..., ADDRm), and data (DATAa, DATAb, ..., DATAm) to the memory device (160) through the channels (CH1~CHm), or receive data (DATAa~DATAm) from the memory device (160).

[0094] The memory controller (200) can select one of the non-volatile memory devices connected to the corresponding channel through each channel and transmit and receive signals with the selected non-volatile memory device. For example, the memory controller (200) can select a non-volatile memory device (NVM11) among the non-volatile memory devices (NVM11~NVM1n) connected to the first channel (CH1). The memory controller (200) can transmit a command (CMDa), an address (ADDRa), and data (DATAa) to the selected non-volatile memory device (NVM11) through the first channel (CH1), or receive data (DATAa) from the selected non-volatile memory device (NVM11).

[0095] The memory controller (200) can transmit and receive signals to and from the memory device (160) in parallel through different channels. For example, the memory controller (200) can transmit a command (CMDb) to the memory device (160) through a second channel (CH2) while transmitting a command (CMDa) to the memory device (160) through a first channel (CH1). For example, the memory controller (200) can receive data (DATAb) from the memory device (160) through a second channel (CH2) while receiving data (DATAa) from the memory device (160) through a first channel (CH1).

[0096] The memory controller (200) can control the overall operation of the memory device (160). The memory controller (200) can control each of the non-volatile memory devices (NVM11~NVMmn) connected to the channels (CH1~CHm) by transmitting signals to the channels (CH1~CHm). For example, the memory controller (200) can control one of the selected non-volatile memory devices (NVM11~NVM1n) by transmitting a command (CMDa) and an address (ADDRa) to the first channel (CH1).

[0097] Each of the non-volatile memory devices (NVM11 to NVMmn) can operate under the control of the memory controller (200). For example, the non-volatile memory device (NVM11) can program data (DATAa) according to a command (CMDa), an address (ADDRa), and data (DATAa) provided through the first channel (CH1). For example, the non-volatile memory device (NVM21) can read data (DATAb) according to a command (CMDb) and an address (ADDRb) provided through the second channel (CH2), and transmit the read data (DATAb) to the memory controller (200).

[0098] The memory controller (200) includes L memory access units (FDMA1 to FDMAL) (L is an integer greater than or equal to 1), and the L memory access units (FDMA1 to FDMAL) may be assigned to different channels. For example, the first memory access unit (FDMA1) may perform access to the buffer memory of the memory controller (200) for data (DATAa, DATAb) of the first and second channels (CH1, CH2), and the L memory access unit (FDMAL) may perform access to the buffer memory for data (DATAm) of the m-1 and m channels (CHm-1, CHm) which are different from the first and second channels (CH1, CH2).

[0099] In FIG. 15, the memory device (160) communicates with the memory controller (200) through m channels, and the memory device (160) is shown as including n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to one channel can be varied. Also, FIG. 15 shows an example in which the memory device (160) includes non-volatile memory devices (NVM11~NVMmn), but the memory device (160) can be implemented as any memory device.

[0100] FIG. 16 is a block diagram showing an example of a memory device included in a memory system according to embodiments of the present invention.

[0101] Referring to FIG. 16, the memory device (300) may include a memory cell array (330) and a control circuit that performs operations on the memory cell array (330). The control circuit may include a control logic circuit (320), a page buffer circuit (340), a voltage generator (350), and a row decoder (360). Although not shown in FIG. 16, the memory device (300) may further include an interface circuit (310) and may also further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0102] The control logic circuit (320) can control various operations within the memory device (300) overall. The control logic circuit (320) can output various control signals in response to a command (CMD) and / or an address (ADDR) from the interface circuit (310). For example, the control logic circuit (320) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

[0103] The memory cell array (330) may include a plurality of memory blocks (BLK1 to BLKz) (z is a positive integer), and each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. The memory cell array (330) may be connected to a page buffer circuit (340) through bit lines (BL) and may be connected to a row decoder (360) through word lines (WL), string select lines (SSL), and ground select lines (GSL).

[0104] In an exemplary embodiment, the memory cell array (330) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array (330) may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0105] The page buffer circuit (340) may include a plurality of page buffers (PB1 to PBm) (m is an integer greater than or equal to 3), and the plurality of page buffers (PB1 to PBm) may each be connected to memory cells through a plurality of bit lines (BL). The page buffer circuit (340) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer circuit (340) may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer circuit (340) may apply a bit line voltage corresponding to the data to be programmed with the selected bit line. During a read operation, the page buffer circuit (340) may detect the current or voltage of the selected bit line to detect the data stored in the memory cell.

[0106] The voltage generator (350) can generate various types of voltages to perform program, readout, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generator (350) can generate a program voltage, a readout voltage, a program verification voltage, an erase voltage, etc. as a word line voltage (VWL).

[0107] The row decoder (360) can select one of a plurality of word lines (WL) and one of a plurality of string selection lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (360) can apply a program voltage and a program verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0108] FIG. 17 is a perspective view showing an example of a memory block included in a memory cell array of the memory device of FIG. 16.

[0109] Referring to FIG. 17, the memory block (BLKi) includes NAND strings formed in a three-dimensional structure or a vertical structure. The memory block (BLKi) includes structures extended along a plurality of directions (D1, D2, D3).

[0110] To form a memory block (BLKi), a substrate (111) is first provided. For example, the substrate (111) may be formed into a P-well formed by injecting a group 3 element such as boron (B). Alternatively, the substrate (111) may be formed into a pocket P-well provided within an N-well. Hereinafter, it is assumed that the substrate (111) is a P-well. However, the substrate (111) is not limited to a P-well.

[0111] On the substrate (111), a plurality of doping regions (311, 312, 313, 314) are formed along a second direction (D2). For example, the plurality of doping regions (311 to 314) may be formed of an N-type conductor different from the substrate (111). Hereinafter, it is assumed that the plurality of doping regions (311 to 314) have an N-type. However, the plurality of doping regions (311 to 314) are not limited only to having an N-type.

[0112] On a substrate (111) between doping regions (311, 312), a plurality of insulating materials (112) extending along a first direction (D1) are sequentially provided along a third direction (D3). For example, the plurality of insulating materials (112) may be formed spaced apart by a specific distance along the third direction (D3). For example, the plurality of insulating materials (112) may include an insulating material such as silicon oxide.

[0113] On a substrate (111) between doping regions (311, 312), a plurality of pillars (113) are formed sequentially along a first direction (D1) and penetrate a plurality of insulating materials (112) along a third direction (D3). For example, the plurality of pillars (113) can penetrate the plurality of insulating materials (112) and be connected to the substrate (111). Additionally, the plurality of pillars (113) are formed on the substrate between doping regions (312, 313) and also on the substrate between doping regions (313, 314).

[0114] In one embodiment, each pillar (113) may be composed of a plurality of materials. For example, the surface layer (114) of each pillar (113) may include a silicon material having a first type and may function as a region where a channel of a NAND string is formed. For example, the surface layer (114) of each pillar (113) may include a silicon material having the same type as the substrate (111). Hereinafter, it is assumed that the surface layer (114) of each pillar (113) includes P-type silicon. However, the surface layer (114) of each pillar (113) is not limited to including P-type silicon.

[0115] The inner layer (115) of each pillar (113) is composed of an insulating material. For example, the inner layer (115) of each pillar (113) may include an insulating material such as silicon oxide. For example, the inner layer (115) of each pillar (113) may include an air gap.

[0116] In the region between the doping regions (311, 312), a plurality of insulating materials (112), a plurality of pillars (113), and an insulating film (116) are provided along the exposed surface of the substrate (111). For example, the insulating film (116) provided on the exposed surface of the last insulating material (112) in the third direction (D3) along the third direction (D3) can be removed.

[0117] In the region between the doping regions (311, 312), a plurality of first conductive materials (211, 221, 231, 241, 251, 261, 271, 281, 291) are provided on the exposed surface of the insulating film (116). For example, a first conductive material (211) extending along a first direction (D1) may be provided between the insulating material (112) adjacent to the substrate (111) and the substrate (111). Specifically, a first conductive material (211) extending in a first direction (D1) may be provided between the insulating film (116) on the lower surface of the insulating material (112) adjacent to the substrate (111) and the substrate (111).

[0118] A first conductive material extending along a first direction (D1) is provided between an insulating film (116) on the upper surface of a specific insulating material among the insulating materials (112) and an insulating film (116) on the lower surface of an insulating material disposed on top of the specific insulating material. For example, first conductive materials (221–281) extending in the first direction (D1) may be provided between the insulating materials (112). For example, the first conductive materials (211–291) may be metal materials. For example, the first conductive materials (211–291) may be conductive materials such as polysilicon.

[0119] In the region between the doping regions (312, 313) and in the region between the doping regions (313, 314), a structure identical to the structure on the region between the doping regions (311, 312) may be provided.

[0120] A plurality of drains (321) are provided on each of the plurality of pillars (113). On the drains (321), a plurality of second conductive materials (331, 332, 333) extended in a second direction (D2) are provided. The second conductive materials (331–333) are arranged sequentially along a first direction (D1). Each of the second conductive materials (331–333) is connected to the drain (321) in the corresponding area. For example, the drains (321) and the second conductive materials (331–333) extended in the second direction (D2) can each be connected via contact plugs. For example, the second conductive materials (331–333) may be metal materials. For example, the second conductive materials (331–333) may be conductive materials such as polysilicon.

[0121] In the example of FIG. 17, the first conductive materials (211–291) can form word lines (WL), string select lines (SSL), and ground select lines (GSL). The second conductive materials (331–333) can form bit lines (BL). Also, in the example of FIG. 17, the number of layers of the first conductive materials (211–291) is merely exemplary.

[0122] Figure 18 is a circuit diagram showing the equivalent circuit of a memory block described with reference to Figure 17.

[0123] The memory block (BLKi) illustrated in FIG. 18 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block (BLKi) may be formed in a direction perpendicular to the substrate.

[0124] Referring to FIG. 18, a memory block (BLKi) may include a plurality of memory NAND strings (NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, NS33) connected between bit lines (BL1, BL2, BL3) and a common source line (CSL). Each of the plurality of memory NAND strings (NS11~NS33) may include a string select transistor (SST), a plurality of memory cells (MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8), and a ground select transistor (GST). The bit lines (BL1~BL3) may correspond to the second conductive materials (331~333) of FIG. 17, and the doping regions (311~314) of FIG. 17 may be connected to each other to form a common source line (CSL).

[0125] A string select transistor (SST) can be connected to corresponding string select lines (SSL1, SSL2, SSL3). Multiple memory cells (MC1 to MC8) can each be connected to corresponding word lines (WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8). A ground select transistor (GST) can be connected to corresponding ground select lines (GSL1, GSL2, GSL3). A string select transistor (SST) is connected to corresponding bit lines (BL1, BL2, BL3), and a ground select transistor (GST) can be connected to a common source line (CSL).

[0126] Cell strings commonly connected to one bit line form one column, and cell strings connected to one string selection line form one row. For example, cell strings (NS11, NS21, NS31) connected to the first bit line (BL1) form the first column, and cell strings (NS11, NS12, NS13) connected to the first string selection line (SSL1) can form the first row.

[0127] Word lines (e.g., WL1) of the same layer may be connected in common, and ground select lines (GSL1–GSL3) and string select lines (SSL1–SSL3) may be separated. Memory cells of the same semiconductor layer may share word lines, cell strings of the same row may share string select lines, and a common source line (CSL) may be connected in common to all cell strings.

[0128] In the example of FIG. 18, the number of word lines (WL1–WL8), bit lines (BL1–BL3) and memory cells (MC1–MC8) is merely exemplary.

[0129] Meanwhile, although a memory cell array and a memory block included in a memory device according to embodiments of the present invention have been described based on a NAND flash memory device, the memory device according to embodiments of the present invention may be any volatile memory device such as DRAM, SRAM, etc., or any non-volatile memory device such as PRAM, RRAM, MRAM, FRAM, NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), etc.

[0130] FIG. 19 is a cross-sectional view showing an example of a memory device included in a memory system according to embodiments of the present invention.

[0131] Referring to FIG. 19, the memory device (2000) may have a C2C (chip-to-chip) structure. A C2C structure may mean fabricating an upper chip containing a cell region (CELL) on a first wafer, fabricating a lower chip containing a peripheral circuit region (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For instance, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0132] Each of the peripheral circuit region (PERI) and cell region (CELL) of the memory device (2000) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA).

[0133] The peripheral circuit region (PERI) may include a first substrate (2210), an interlayer insulating layer (2215), a plurality of circuit elements (2220a, 2220b, 2220c) formed on the first substrate (2210), a first metal layer (2230a, 2230b, 2230c) connected to each of the plurality of circuit elements (2220a, 2220b, 2220c), and a second metal layer (2240a, 2240b, 2240c) formed on the first metal layer (2230a, 2230b, 2230c). In one embodiment, the first metal layer (2230a, 2230b, 2230c) may be formed of tungsten, which has relatively high electrical resistivity, and the second metal layer (2240a, 2240b, 2240c) may be formed of copper, which has relatively low electrical resistivity.

[0134] In this specification, only the first metal layer (2230a, 2230b, 2230c) and the second metal layer (2240a, 2240b, 2240c) are illustrated and described, but are not limited thereto, and at least one additional metal layer may be formed on the second metal layer (2240a, 2240b, 2240c). At least some of the one or more metal layers formed on the upper part of the second metal layer (2240a, 2240b, 2240c) may be formed of aluminum or the like, having an electrical resistivity lower than that of copper forming the second metal layer (2240a, 2240b, 2240c).

[0135] The interlayer insulating layer (2215) is disposed on a first substrate (2210) to cover a plurality of circuit elements (2220a, 2220b, 2220c), a first metal layer (2230a, 2230b, 2230c), and a second metal layer (2240a, 2240b, 2240c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0136] A lower bonding metal (2271b, 2272b) may be formed on the second metal layer (2240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (2271b, 2272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (2371b, 2372b) of the cell region (CELL) by a bonding method, and the lower bonding metal (2271b, 2272b) and the upper bonding metal (2371b, 2372b) may be formed of aluminum, copper, or tungsten, etc.

[0137] A cell region (CELL) may provide at least one memory block. The cell region (CELL) may include a second substrate (2310) and a common source line (2320). On the second substrate (2310), a plurality of word lines (2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338; 2330) may be stacked along a third direction (D3) perpendicular to the upper surface of the second substrate (2310). String selection lines and ground selection lines may be disposed on the upper and lower portions of the word lines (2330), respectively, and a plurality of word lines (2330) may be disposed between the string selection lines and the ground selection lines.

[0138] In the bitline bonding region (BLBA), the channel structure (CH) may extend in a third direction (D3) (i.e., Z-axis direction) perpendicular to the upper surface of the second substrate (2310) and penetrate wordlines (2330), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer (2350c) and a second metal layer (2360c). For example, the first metal layer (2350c) may be a bitline contact, and the second metal layer (2360c) may be a bitline. In one embodiment, the bitline (2360c) may extend along a second direction (D2) (i.e., Y-axis direction) parallel to the upper surface of the second substrate (2310).

[0139] In the example of FIG. 19, the area where the channel structure (CH) and bit line (2360c), etc. are placed may be defined as a bit line bonding area (BLBA). The bit line (2360c) may be electrically connected to circuit elements (2220c) that provide a page buffer (2393) in the peripheral circuit area (PERI) in the bit line bonding area (BLBA). For example, the bit line (2360c) may be connected to an upper bonding metal (2371c, 2372c) in the peripheral circuit area (PERI), and the upper bonding metal (2371c, 2372c) may be connected to a lower bonding metal (2271c, 2272c) that is connected to the circuit elements (2220c) of the page buffer (2393).

[0140] In the wordline bonding area (WLBA), wordlines (2330) may extend along a first direction (D1) (i.e., X-axis direction) perpendicular to the second direction (D2) and parallel to the upper surface of the second substrate (2310), and may be connected to a plurality of cell contact plugs (2341, 2342, 2343, 2344, 2345, 2346, 3347; 3340). The wordlines (2330) and the cell contact plugs (2340) may be connected to each other at pads provided by extending at least some of the wordlines (2330) along the first direction (D1) to different lengths. A first metal layer (2350b) and a second metal layer (2360b) may be connected in sequence to the upper portion of the cell contact plugs (2340) connected to the word lines (2330). The cell contact plugs (2340) may be connected to the peripheral circuit area (PERI) through the upper bonding metal (2371b, 2372b) of the cell area (CELL) and the lower bonding metal (2271b, 2272b) of the peripheral circuit area (PERI) in the word line bonding area (WLBA).

[0141] Cell contact plugs (2340) may be electrically connected to circuit elements (2220b) forming an address decoder or a row decoder (2394) in a peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (2220b) forming the row decoder (2394) may be different from the operating voltage of the circuit elements (2220c) forming the page buffer (2393). For example, the operating voltage of the circuit elements (2220c) forming the page buffer (2393) may be greater than the operating voltage of the circuit elements (2220b) forming the row decoder (2394).

[0142] A common source line contact plug (2380) may be disposed in the external pad bonding area (PA). The common source line contact plug (2380) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to a common source line (2320). A first metal layer (2350a) and a second metal layer (2360a) may be sequentially laminated on top of the common source line contact plug (2380). For example, the area where the common source line contact plug (2380), the first metal layer (2350a), and the second metal layer (2360a) are disposed may be defined as the external pad bonding area (PA).

[0143] Meanwhile, input / output pads (2205, 2305) may be disposed in the external pad bonding area (PA). A lower insulating film (2201) covering the lower surface of the first substrate (2210) may be formed on the lower surface of the first substrate (2210), and a first input / output pad (2205) may be formed on the lower insulating film (2201). The first input / output pad (2205) is connected to at least one of a plurality of circuit elements (2220a, 2220b, 2220c) disposed in the peripheral circuit area (PERI) through the first input / output contact plug (2203), and may be separated from the first substrate (2210) by the lower insulating film (2201). Additionally, a side insulating film is disposed between the first input / output contact plug (2203) and the first substrate (2210) to electrically separate the first input / output contact plug (2203) and the first substrate (2210).

[0144] An upper insulating film (2301) covering the upper surface of the second substrate (2310) may be formed on the upper surface of the second substrate (2310), and a second input / output pad (2305) may be disposed on the upper insulating film (2301). The second input / output pad (2305) may be connected to at least one of a plurality of circuit elements (2220a, 2220b, 2220c) disposed in the peripheral circuit region (PERI) through a second input / output contact plug (2303). In one embodiment, the second input / output pad (2305) may be electrically connected to the circuit element (2220a).

[0145] According to the embodiment, the second substrate (2310) and common source line (2320), etc., may not be placed in the area where the second input / output contact plug (2303) is placed. Additionally, the second input / output pad (2305) may not overlap with the word lines (2380) in the third direction (D3). The second input / output contact plug (2303) is separated from the second substrate (2310) in a direction parallel to the upper surface of the second substrate (2310) and may be connected to the second input / output pad (2305) by penetrating the interlayer insulating layer (2315) of the cell area (CELL).

[0146] According to the embodiment, the first input / output pad (2205) and the second input / output pad (2305) may be formed optionally. For example, the memory device (2000) may include only the first input / output pad (2205) disposed on the upper part of the first substrate (2201), or only the second input / output pad (2305) disposed on the upper part of the second substrate (2301). Alternatively, the memory device (2000) may include both the first input / output pad (2205) and the second input / output pad (2305).

[0147] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell region (CELL) and peripheral circuit region (PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0148] The memory device (2000) may form a lower metal pattern (2273a) of the same shape as the upper metal pattern (2372a) of the cell region (CELL) on the upper metal layer of the peripheral circuit region (PERI) in the external pad bonding region (PA), corresponding to the upper metal pattern (2372a) formed on the upper metal layer of the cell region (CELL). The lower metal pattern (2273a) formed on the upper metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, the memory device may form an upper metal pattern (2372a) of the same shape as the lower metal pattern (2273a) of the peripheral circuit region (PERI) on the upper metal layer of the cell region (CELL) in the external pad bonding region (PA), corresponding to the lower metal pattern (2273a) formed on the upper metal layer of the peripheral circuit region (PERI).

[0149] A lower bonding metal (2271b, 2272b) may be formed on the second metal layer (2240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (2271b, 2272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (2371b, 2372b) of the cell region (CELL) by a bonding method.

[0150] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (2392) of the same shape as the lower metal pattern (2252) of the peripheral circuit area (PERI) can be formed on the upper metal layer of the cell area (CELL) in correspondence with the lower metal pattern (2252) formed on the upper metal layer of the peripheral circuit area (PERI). A contact may not be formed on the upper metal pattern (2392) formed on the upper metal layer of the cell area (CELL). Industrial applicability

[0151] Embodiments of the present invention may be usefully applied to any electronic device and system including a memory device and a memory system. For example, embodiments of the present invention may be more usefully applied to electronic systems such as a PC (Personal Computer), server computer, data center, workstation, laptop, cellular phone, smartphone, MP3 player, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), digital TV, digital camera, portable game console, navigation device, wearable device, IoT (Internet of Things) device, IoE (Internet of Everything) device, e-book, VR (Virtual Reality) device, AR (Augmented Reality) device, drone, etc.

[0152] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

Claim 1 A memory controller of a memory system comprising a memory device and a memory controller, the memory controller comprising: a buffer memory comprising memory banks; one or more host access units performing access to the buffer memory for a host; one or more memory access units performing access to the buffer memory for the memory device; and a processor controlling the operation of the memory controller, wherein the processor divides the memory banks into an external memory bank group for external operations related to the host and an internal memory bank group for internal operations within the memory system, and wherein the host access units access the external memory bank group, and the memory access units access the external memory bank group to perform the external operations and access the internal memory bank group to perform the internal operations. Claim 2 A memory controller according to claim 1, wherein the external operation includes a data write operation for writing write data received from the host to the memory device, and a data read operation for providing read data read from the memory device to the host, and the internal operation includes a garbage collection operation for the memory device. Claim 3 A memory controller according to claim 1, wherein the processor comprises: a host access manager for controlling the host access units; and a memory access manager for controlling the memory access units, wherein the host access manager manages external bank index pools for each of the memory banks in the external memory bank group, and the memory access manager manages internal bank index pools for each of the memory banks in the internal memory bank group, and the host access units access the external memory bank group based on a first buffer index in the external bank index pools received from the host access manager, and the memory access units access the external memory bank group based on the first buffer index received from the host access manager through the memory access manager to perform the external operation, and access the internal memory bank group based on a second buffer index in the internal bank index pools received from the memory access manager to perform the internal operation. Claim 4 A memory controller according to claim 1, wherein the processor compares a first traffic amount of the external operation with a second traffic amount of the internal operation, and if the difference between the first traffic amount and the second traffic amount is greater than or equal to a reference traffic amount, increases the number of memory banks included in one of the external memory bank group and the internal memory bank group, and decreases the number of memory banks included in the other of the external memory bank group and the internal memory bank group. Claim 5 A memory controller according to claim 1, characterized in that the processor further divides the external memory bank group into external memory bank sub-groups for each of the host access units. Claim 6 A memory controller according to claim 1, wherein the processor includes a memory access manager that manages internal bank index pools for each of the memory banks within the internal memory bank group, and when the internal operation is performed, the memory access manager selects one internal bank index pool among the internal bank index pools in a round-robin manner and transmits the buffer index of the selected one internal bank index pool to the memory access units. Claim 7 A memory controller according to claim 1, characterized in that the processor further divides the internal memory bank group into internal memory bank sub-groups for each of the memory access units. Claim 8 A memory controller according to claim 1, wherein the processor further divides the external memory bank group into external memory bank sub-groups for each of the host access units, wherein the first external memory bank sub-group among the external memory bank sub-groups includes the first and second memory banks among the memory banks, and the first host access unit corresponding to the first external memory bank sub-group among the host access units alternately accesses the first memory bank and the second memory bank. Claim 9 A memory controller according to claim 1, wherein the processor further divides the external memory bank group into a plurality of external memory bank function groups for each of a plurality of function IDs, the memory controller receives a host command from the host including a function ID among the plurality of function IDs, and the host access units access an external memory bank function group corresponding to the one function ID among the plurality of external memory bank function groups in response to the host command. Claim 10 A memory system comprising: a memory device; and a memory controller for controlling the operation of the memory device, wherein the memory controller comprises: a buffer memory including memory banks; one or more host access units for accessing the buffer memory for a host; one or more memory access units for accessing the buffer memory for the memory device; and a processor for controlling the operation of the memory controller, wherein the processor divides the memory banks into an external memory bank group for external operations related to the host and an internal memory bank group for internal operations within the memory system, wherein the host access units access the external memory bank group, and the memory access units access the external memory bank group to perform the external operations and access the internal memory bank group to perform the internal operations.

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