Chip on film package and display apparatus including the same

Abstract

The technical concept of the present invention provides a chip-on-film package comprising: a base film having a chip mounting area, a main line pattern extended on the base film, and a branch line pattern extended on the base film and connected to the main line pattern; a semiconductor chip mounted on the film substrate so as to overlap with the chip mounting area; a first bump structure disposed between the semiconductor chip and the film substrate and connected to the main line pattern; and a second bump structure disposed between the semiconductor chip and the film substrate, connected to the branch line pattern, and spaced apart from the first bump structure in a first direction parallel to the first edge of the chip mounting area; wherein the branch line pattern is extended so as not to overlap with the first edge of the first bump structure facing the first edge of the chip mounting area and the first edge of the second bump structure facing the first edge of the chip mounting area.

Description

Technology Field

[0001] The technical concept of the present invention relates to a chip-on-film package and a display device including the same. Background Technology

[0002] A Chip-on-Film (COF) package includes a semiconductor chip, such as a display driver chip, mounted on a film substrate. In a Chip-on-Film package, the semiconductor chip can be electrically connected to the leads of the film substrate through bump structures. With the recent miniaturization of display devices, there is a demand for technology that allows the leads of the film substrate to be arranged at a fine pitch while suppressing damage to the leads caused by external stress. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a chip-on-film package with improved reliability.

[0004] Another problem that the technical concept of the present invention aims to solve is to provide a display device including the chip-on-film package. means of solving the problem

[0005] To solve the above-mentioned problem, the technical concept of the present invention provides a chip-on-film package comprising: a base film having a chip mounting area, a main line pattern extended on the base film, and a branch line pattern extended on the base film and connected to the main line pattern; a semiconductor chip mounted on the film substrate so as to overlap with the chip mounting area; a first bump structure disposed between the semiconductor chip and the film substrate and connected to the main line pattern; and a second bump structure disposed between the semiconductor chip and the film substrate, connected to the branch line pattern, and spaced apart from the first bump structure in a first direction parallel to the first edge of the chip mounting area; wherein the branch line pattern is extended so as not to overlap with the first edge of the first bump structure facing the first edge of the chip mounting area and the first edge of the second bump structure facing the first edge of the chip mounting area.

[0006] To solve the above-mentioned problem, the technical concept of the present invention comprises: a film substrate; a semiconductor chip mounted on the film substrate; a plurality of bump structures disposed between the film substrate and the semiconductor chip; an underfill material layer filling the gap between the semiconductor chip and the film substrate; and a heat dissipation resin layer covering the semiconductor chip on the film substrate; wherein the plurality of bump structures includes a first bump structure and a second bump structure, and the film substrate has a chip mounting area and an outer area outside the chip mounting area, wherein the chip mounting area is vertically superimposed with the semiconductor chip, a base film; a main line pattern extending on the chip mounting area of ​​the base film and including a first pad coupled to the first bump structure and a first extension pattern connected to the first pad; and a second pad coupled to the second bump structure and spaced from the first pad in a first direction parallel to the first edge of the chip mounting area. A chip-on-film package is provided, comprising: a branch line pattern extending between the main line pattern and the second pad and electrically connecting the first bump structure and the second bump structure; wherein the first pad extends from one edge of the first bump structure to another edge in a second direction perpendicular to the first direction, and the second pad extends from one edge of the first bump structure to another edge in the second direction, and the branch line pattern is spaced apart from the first side of the first pad closest to the first edge of the chip mounting area and the first side of the second pad closest to the first edge of the chip mounting area.

[0007] To solve the above-mentioned problem, the technical concept of the present invention comprises: a chip-on-film package including a film substrate, a plurality of bump structures on the film substrate, and a display driving chip on the plurality of bump structures; a display panel connected to the film substrate; and a driving printed circuit board connected to the film substrate; wherein the plurality of bump structures includes a first bump structure and a second bump structure, and the film substrate has a chip mounting area and an outer area outside the chip mounting area, wherein the chip mounting area is vertically superimposed with the display driving chip, a base film; a main line pattern extending on the chip mounting area of ​​the base film and including a first pad coupled to the first bump structure and a first extension pattern connected to the first pad; and a second pad coupled to the second bump structure and spaced from the first pad in a first direction parallel to the first edge of the chip mounting area. A display device is provided that includes a branch line pattern extending between the main line pattern and the second pad and electrically connecting the first bump structure and the second bump structure, wherein the first pad extends from one edge of the first bump structure to another edge in a second direction perpendicular to the first direction, and the second pad extends from one edge of the first bump structure to another edge in the second direction, and the branch line pattern is spaced apart from the first side of the first pad closest to the first edge of the chip mounting area and the first side of the second pad closest to the first edge of the chip mounting area. Effects of the invention

[0008] According to exemplary embodiments of the present invention, the reliability of a chip-on-film package can be improved by eliminating electrical failure issues caused by thermal deformation. Brief explanation of the drawing

[0009] FIG. 1 is a cross-sectional view showing a chip-on-film package according to exemplary embodiments of the present invention. FIG. 2 is a plan view showing a partial configuration of a chip-on-film package according to exemplary embodiments of the present invention. FIG. 3a is a plan view showing a chip-on-film package according to exemplary embodiments of the present invention. Figure 3b is a cross-sectional view of a chip-on-film package taken along the line 3B-3B' of Figure 3a. FIG. 4a is a plan view showing a chip-on-film package according to a comparative example. FIG. 4b is a cross-sectional view of a chip-on-film package according to a comparative example taken along the line 4B-4B' of FIG. 4a. FIG. 5 is a plan view showing a chip-on-film package according to exemplary embodiments of the present invention. FIG. 6 is a plan view showing a chip-on-film package according to exemplary embodiments of the invention. FIG. 7 is a plan view showing a chip-on-film package according to exemplary embodiments of the invention. FIG. 8 is a perspective view showing a display device according to exemplary embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0011] FIG. 1 is a cross-sectional view showing a chip-on-film package (10) according to exemplary embodiments of the present invention. FIG. 2 is a plan view showing a part of the configuration of a chip-on-film package (10) according to exemplary embodiments of the present invention.

[0012] Referring to FIGS. 1 and 2, a chip on film package (10) may include a film substrate (100), a semiconductor chip (200), and a plurality of bump structures (300).

[0013] The film substrate (100) may include a base film (110) and a conductive wiring pattern extending on the base film (110).

[0014] The base film (110) may be made of an insulating material. The base film (110) may be a flexible film having flexibility. For example, the base film (110) may include a resin-based material such as polyimide. For example, the base film (110) may include at least one of an epoxy resin, acrylic, polyether nitrile, polyether sulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0015] The base film (110) may include a circuit area (117) and a perforation (PF) area (112). The circuit area (117) may include a chip mounting area (RA) on which a semiconductor chip (200) is mounted, and an external area (RB) located outside the chip mounting area (RA). When viewed in a planar view, the chip mounting area (RA) may overlap vertically with the semiconductor chip (200) and may have the same shape as the semiconductor chip (200). The external area (RB) may be the remaining area of ​​the circuit area (117) excluding the chip mounting area (RA). The chip mounting area (RA) and the external area (RB) may be areas on the upper surface of the base film (110) facing the semiconductor chip (200). The PF area (119) may be placed on both sides of the base film (110). The above PF region (119) may include a plurality of PF holes (114). Since the pitch of the PF holes (114) is constant, the length of the base film (110) may be determined by the number of PF holes (114). The above PF region (119) may be cut and removed before the chip-on-film package (10) is placed on a display device.

[0016] In the following, a direction parallel to the upper surface of the base film (110) is defined as a horizontal direction (e.g., X direction and / or Y direction), and a direction perpendicular to the upper surface of the base film (110) is defined as a vertical direction (e.g., Z direction).

[0017] A conductive wiring pattern may be placed on the upper surface of a base film (110) and may extend along the upper surface of the base film (110). Of course, not limited thereto, a conductive wiring pattern may be placed on the lower surface of the base film (110) and may extend along the lower surface of the base film (110). The conductive wiring pattern may include copper (Cu), aluminum (Al), tin (Sn), gold (Au), nickel (Ni), lead (Pb), palladium (Pd), solder, or a combination thereof. For example, the conductive wiring pattern may be formed from aluminum foil or copper foil. For example, the conductive wiring pattern may be formed by patterning on a metal layer formed on the base film (110) by a casting, laminating, or electroplating method. For example, the line width of the conductive wiring pattern may be between 5 μm and 15 μm.

[0018] The conductive wiring pattern may include one or more input / output wiring patterns (120) extending from one or more edges of the base film (110) to the chip mounting area (RA), and one or more inner wiring patterns (130) extending within the chip mounting area (RA). The input / output wiring pattern (120) may be configured to transmit an input signal provided from the outside and input to the semiconductor chip (200) and / or an output signal output from the semiconductor chip (200). For example, the input / output wiring pattern (120) may be configured to transmit an input / output data signal, a control signal, a power signal (e.g., Vdd voltage, Vss voltage, ground voltage, etc.).

[0019] The film substrate (100) may further include a protective layer provided on the base film (110). The protective layer may cover a portion of the conductive wiring pattern and the base film (110). The protective layer may cover the conductive wiring pattern, but may not cover the portions of the conductive wiring pattern that are in contact with the plurality of bump structures (300). Direct contact between the conductive wiring pattern and the heat dissipation resin layer (420) may be blocked by the protective layer. In exemplary embodiments, the protective layer may include a solder resist or a dry film resist.

[0020] A semiconductor chip (200) may be mounted on a film substrate (100). A semiconductor chip (200) may be placed on a chip mounting area (RA) of a base film (110). The semiconductor chip (200) may include a display driver IC (DDI) used to drive a display device. In this case, the chip-on-film package (10) may correspond to a DDI package including the DDI. Of course, the type of semiconductor chip (200) is not limited thereto, and the semiconductor chip (200) may include a memory chip and / or a logic chip. Also, in FIGS. 1 and 2, the chip-on-film package (10) is illustrated as including one semiconductor chip (200), but the number of semiconductor chips (200) is not limited thereto. For example, the chip-on-film package (10) may include a plurality of semiconductor chips (200) spaced apart in a horizontal direction (e.g., X direction and / or Y direction) on a film substrate (100).

[0021] The semiconductor chip (200) may have a rectangular shape when viewed in a plane. For example, when viewed in a plane, the semiconductor chip (200) may have a short side extended in a first horizontal direction (e.g., Y direction) and a long side extended in a second horizontal direction (e.g., X direction) perpendicular to the first horizontal direction (e.g., Y direction). In exemplary embodiments, the length of the long side of the semiconductor chip (200) may be at least about 1.5 times the length of the short side.

[0022] When viewed in a planar view, the chip mounting area (RA) of the film substrate (100) may have the same shape and dimensions as the semiconductor chip (200). That is, the chip mounting area (RA) may have a rectangular shape that completely overlaps with the semiconductor chip (200), and the length along the first horizontal direction (e.g., Y direction) and the length along the second horizontal direction (e.g., X direction) of the chip mounting area (RA) may be the same as the length along the first horizontal direction (e.g., Y direction) and the length along the second horizontal direction (e.g., X direction), respectively. The chip mounting area (RA) may have a pair of first edges (SE) extended in a first horizontal direction (e.g., Y direction) and a pair of second edges (LE) extended in a second horizontal direction (e.g., X direction), wherein the first edge (SE) of the chip mounting area (RA) may be the short side of the chip mounting area (RA) and the second edge (LE) of the chip mounting area (RA) may be the long side of the chip mounting area (RA). The length of the second edge (LE) of the chip mounting area (RA) may be at least about 1.5 times the length of the first edge of the chip mounting area (RA).

[0023] The semiconductor chip (200) may include a substrate (210) and a plurality of chip pads (220).

[0024] The substrate (210) may be a semiconductor substrate and may include opposite lower and upper surfaces. The lower surface of the substrate (210) may be the active surface of the substrate (210) as a surface facing the film substrate (100). The upper surface of the substrate (210) may be the inactive surface of the substrate (210). The substrate (210) may be a silicon (Si) wafer comprising crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the substrate (210) may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). A plurality of chip pads (220) of the semiconductor chip (200) may be disposed on the lower surface of the semiconductor chip (200) and may be made of a conductive material.

[0025] A plurality of bump structures (300) may be disposed between a semiconductor chip (200) and a film substrate (100). Each of the plurality of bump structures (300) may have a pillar shape extending in a vertical direction (e.g., Z direction) between the semiconductor chip (200) and the film substrate (100). The plurality of bump structures (300) may physically and electrically connect the semiconductor chip (200) and the film substrate (100). The semiconductor chip (200) may be mounted on the film substrate (100) in a flip-chip manner through the plurality of semiconductor chips (200). Each of the plurality of bump structures (300) may be coupled to a corresponding chip pad (220) of the semiconductor chip (200) and a corresponding pad portion of the conductive wiring pattern.

[0026] For example, the bump structure (300) may comprise chromium (Cr), tungsten (W), titanium (Ti), copper (Cu), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or a combination thereof. For example, the bump structure (300) may be formed through an electroplating process. In exemplary embodiments, the material of the bump structure (300) may be different from the material of the conductive wiring pattern. In exemplary embodiments, the bump structure (300) may be formed of gold (Au), and the conductive wiring pattern may be formed of copper.

[0027] A plurality of bump structures (300) may include bump structures (300) arranged along the first edge (SE) of the chip mounting area (RA) or the short side of the semiconductor chip (200) and adjacent to the first edge (SE) of the chip mounting area (RA) or the short side of the semiconductor chip (200), and bump structures (300) arranged along the second edge (LE) of the chip mounting area (RA) or the long side of the semiconductor chip (200) and adjacent to the second edge (LE) of the chip mounting area (RA) or the long side of the semiconductor chip (200). The bump structures (300) arranged along the long side of the semiconductor chip (200) may be connected to input / output wiring patterns (120). In some exemplary embodiments, a bump structure (300) near the first edge (SE) of the chip mounting area (RA) and a bump structure (300) near the second edge (LE) of the chip mounting area (RA) can be electrically connected to each other through an inner wiring pattern (130).

[0028] For example, a plurality of bump structures (300) may each have a rectangular shape when viewed in a plane, and a plurality of bump structures (300) may each have a long side and a short side. In each of the plurality of bump structures (300), the length of the long side may be between 10 μm and 20 μm, the length of the short side may be between 30 μm and 50 μm, and the height (i.e., length along the vertical direction (e.g., Z direction)) may be between 10 μm and 20 μm. Additionally, the bump structures (300) may have a first pitch spacing (i.e., the distance between the centers of adjacent bump structures (300)) between 40 μm and 80 μm.

[0029] In each of the plurality of bump structures (300), the direction in which the long side is extended (i.e., the long axis) may be perpendicular to the edge of the adjacent chip mounting area (RA). For example, in the case of bump structures (300) arranged along the first edge (SE) of the chip mounting area (RA), the direction in which the long side of the bump structures (300) is extended may be perpendicular to the first edge (SE) of the chip mounting area (RA). For example, in the case of bump structures (300) arranged along the second edge (LE) of the chip mounting area (RA), the direction in which the long side of the bump structures (300) is extended may be perpendicular to the second edge (LE) of the chip mounting area (RA).

[0030] In exemplary embodiments of the present invention, the conductive wiring pattern of the film substrate (100) may include a branch line pattern (160) extending between bump structures (300) arranged along a first edge (SE) of a chip mounting area (RA). The branch line pattern (160) is connected to an inner wiring pattern (130), and the bump structures (300) connected through the branch line pattern (160) may be configured to receive a common signal through the inner wiring pattern (130) and the branch line pattern (160). For example, the bump structures (300) connected through the branch line pattern (160) may be configured to receive the same power signal (e.g., any one of Vdd voltage, Vss voltage, and ground voltage).

[0031] A chip-on-film package (10) may include an underfill material layer (410) that fills the gap between the semiconductor chip (200) and the film substrate (100) and at least partially covers the sidewalls of the semiconductor chip (200). The underfill material layer (410) may cover the sidewalls of the bump structures (300) between the semiconductor chip (200) and the film substrate (100) and cover the conductive wiring pattern. The underfill material may be made of an insulating material. The underfill material layer (410) may be formed, for example, from an epoxy resin. For example, the underfill material layer (410) may be formed by a capillary underfill process.

[0032] A chip-on-film package (10) may include a heat dissipation resin layer (420) covering a semiconductor chip (200) on a film substrate (100). The heat dissipation resin layer (420) may seal the semiconductor chip (200) and cover a portion of the film substrate (100) surrounding the surface of the underfill resin layer (420) and the semiconductor chip (200). The heat dissipation resin layer (420) may be formed from a resin material containing a filler. In exemplary embodiments, the filler contained in the heat dissipation resin layer (420) may include a thermally conductive filler (e.g., a metal filler) made of a material with high thermal conductivity.

[0033] FIGS. 3a and 3b are drawings showing a chip-on-film package according to exemplary embodiments of the present invention, where FIG. 3a is a plan view showing the chip-on-film package and FIG. 3b is a cross-sectional view of the chip-on-film package taken along the line 3B-3B' of FIG. 3a.

[0034] Referring to FIGS. 1, FIGS. 3a, and FIGS. 3b, bump structures (i.e., a first bump structure (310) and second bump structures (320)) may be arranged along a first edge (SE) of a chip mounting area (RA), and a film substrate (100) may include bump pads that are positioned below the bump structures and coupled with the bump structures. Each bump pad may have a roughly rectangular shape. Each bump pad may have a rectangular shape with a long side and a short side when viewed in a plane. Each bump pad may extend along the long axis direction of the corresponding bump structure (i.e., a second horizontal direction (e.g., X direction)) and may extend linearly from one edge to the other edge of the bump structure. For example, a plurality of bump pads may be arranged along the first edge (SE) of a chip mounting area (RA) that extends parallel to a first horizontal direction (e.g., Y direction) on a base film (110), and when viewed in a plane, the plurality of bump pads may have a rectangular shape in which the length along the second horizontal direction (e.g., X direction) is greater than the length along the first horizontal direction (e.g., Y direction).

[0035] In exemplary embodiments, a conductive cover layer may be disposed on the outer surface of the bump pads to enhance adhesion between the bump pads and the bump structures. The conductive cover layer may comprise, for example, at least one of tin (Sn), nickel (Ni), lead (Pb), palladium (Pd), and solder.

[0036] A film substrate (100) may include a main line pattern (140) and a branch line pattern (161) that extend and are interconnected on a base film (110). The main line pattern (140) may be connected to a first bump structure (310) which is one of the bump structures, and the branch line pattern (161) may extend from one point of the main line pattern (140) toward a second bump structure (320) which is one of the bump structures. In exemplary embodiments, the branch line pattern (161) may be in contact with the first extension pattern (141) of the main line pattern (140). The main line pattern (140) may be extended only within the chip mounting area (RA) of the base film (110). The branch line pattern (161) may be placed within the chip mounting area (RA) and / or the outer area (RB) of the base film (110). The branch line pattern (161) may be entirely within the chip mounting area (RA) of the base film (110), or may extend across both the chip mounting area (RA) and the outer area (RB).

[0037] The main line pattern (140) may include a first pad (143) coupled to the first bump structure (310) and a first extension pattern (141) extending along the surface of the base film (110) from one side of the first pad (143). One end of the branch line pattern (161) may be connected to the first extension pattern (141) of the main line pattern (140), and the other end of the branch line pattern (161) may be connected to one side of the second pad (151) coupled to the second bump structure (320). The first pad (143) and the second pad (151) may each be one of the aforementioned bump pads. The first pad (143) may be extended linearly in a second horizontal direction (e.g., X direction) from the first edge (311) of the first bump structure (310) to the other edge, and the second pad (151) may be extended linearly in a second horizontal direction (e.g., X direction) from the first edge (321) of the second bump structure (330) to the other edge.

[0038] When the first edge (311) of the first bump structure (310) is defined as the edge facing the first edge (SE) of the chip mounting area (RA) or the edge closest to the first edge (SE) of the chip mounting area (RA), and the first edge (321) of the second bump structure (320) is defined as the edge facing the first edge (SE) of the chip mounting area (RA) or the edge closest to the first edge (SE) of the chip mounting area (RA), the branch line pattern (161) does not overlap with the first edge (311) of the first bump structure (310) and the first edge (321) of the second bump structure (320). In other words, when the first side (1431) of the first pad (143) is defined as the side facing the first edge (SE) of the chip mounting area (RA) or the side closest to the first edge (SE) of the chip mounting area (RA), and the first side (1511) of the second pad (151) is defined as the side facing the first edge (SE) of the chip mounting area (RA) or the side closest to the first edge (SE) of the chip mounting area (RA), the branch line pattern (161) is not connected to the first side (1431) of the first pad (143) and the first side (1511) of the second pad (151).

[0039] FIGS. 4a and 4b are drawings showing a chip-on-film package according to a comparative example, where FIG. 4a is a plan view showing a chip-on-film package according to a comparative example, and FIG. 4b is a cross-sectional view of a chip-on-film package according to a comparative example taken along the line 4B-4B' of FIG. 4a.

[0040] Referring to FIGS. 4a and 4b, a chip-on-film package according to a comparative example includes a conductive pattern (910) extended on a base film (110) to connect between a first bump structure (310) and a second bump structure (320). The conductive pattern (910) extends between a first side (1431) of a first pad (143) and a first side (1511) of a second pad (151). When thermal deformation occurs in the chip-on-film package according to the comparison, deformation such as bending occurs in the film substrate (100), and stress is concentrated at the connection portion between the conductive pattern (910) and the first pad (143) and at the connection portion between the conductive pattern (910) and the second pad (151). In particular, when the chip-on-film package includes a heat dissipation resin layer (420), the thermal deformation tends to be more severe. These stress concentrations cause cracks in the connection area (CP) between the conduction pattern (910) and the first pad (143) and in the connection area between the conduction pattern (910) and the second pad (151), and these cracks short-circuit the wiring, causing electrical failures in the chip-on-film package.

[0041] However, in a chip-on-film package according to exemplary embodiments of the present invention, a branch line pattern (161) configured to electrically connect between bump structures is designed to extend by bypassing a region where stress is likely to concentrate during thermal deformation of the chip-on-film package. For example, one end of the branch line pattern (161) contacts a first extension pattern (141) of a main line pattern (140), and the other end of the branch line pattern (161) contacts a third side of the second pad (151) opposite to a first side (1511) of the second pad (151). The branch line pattern (161) is spaced apart from the first side (1431) of the first pad (143) closest to the first edge (SE) of the chip mounting area (RA) and the first side (1511) of the second pad (151) closest to the first edge (SE) of the chip mounting area (RA), and can be extended by bypassing the area between the first edge (SE) of the chip mounting area (RA) and the first side (1431) of the first pad (143) and the area between the first edge (SE) of the chip mounting area (RA) and the first side (1511) of the second pad (151). When viewed in a planar view, the wiring extends along a path that does not overlap the first edge (311) of the first bump structure (310) and the first edge (321) of the second bump structure (320), thereby electrically connecting the first bump structure (310) and the second bump structure (320). Since the wiring (e.g., branch line pattern (161)) is not placed in areas prone to stress concentration during thermal deformation of the chip-on-film package, electrical failure issues resulting from thermal deformation of the chip-on-film package can be eliminated.Accordingly, according to the chip-on-film package according to exemplary embodiments, the conductive wiring pattern of the film substrate (100) can directly transmit a power signal to bump structures near the short side of the semiconductor chip (200) to prevent voltage drop, and can also improve the reliability of the chip-on-film package by eliminating electrical failure issues caused by thermal deformation of the chip-on-film package.

[0042] FIGS. 5 to 7 are plan views showing chip-on-film packages according to exemplary embodiments of the present invention.

[0043] Referring to FIG. 5 together with FIG. 1, the film substrate (100) may include branch line patterns (i.e., first branch line patterns (162) and second branch line patterns (163)) configured to electrically connect between bump structures (i.e., first bump structures (310) and second bump structures (320)) arranged along the first edge (SE) of the chip mounting area (RA).

[0044] The first branch line pattern (162) may extend between the first pad (143) and the second pad (151) of the main line pattern (140). That is, one end of the first branch line pattern (162) may be connected to the first pad (143), and the other end of the first branch line pattern (162) may be connected to the second pad (151). When the second side of the first pad (143) is defined as the side connected to the first side (1431) of the first pad (143) and the second side of the second pad (151) is defined as the side connected to the first side (1511) of the second pad (151), the first branch line pattern (162) may extend between the second side of the first pad (143) and the second side of the second pad (151) facing each other in the first horizontal direction (e.g., Y direction). The first branch line pattern (162) extends by bypassing the area where stress is likely to concentrate during thermal deformation of the chip-on-film package (i.e., the area overlapping the first edge (311) of the first bump structure (310) and the first edge (321) of the second bump structure (320), thereby eliminating electrical failure issues caused by thermal deformation of the chip-on-film package.

[0045] Additionally, the second branch line pattern (163) may extend between adjacent second pads (151) in the first horizontal direction (e.g., Y direction). That is, one end of the second branch line pattern (163) may be connected to the second pad (151), and the other end of the second branch line pattern (163) may be connected to another second pad (151). The second branch line pattern (163) may extend between the second side of the second pad (151) and the second side of the other second pad (151) facing each other in the first horizontal direction (e.g., Y direction). Since the second branch line pattern (163) extends bypassing the area where stress is likely to concentrate during thermal deformation of the chip-on-film package (i.e., the area overlapping the first edge (321) of the second bump structure (320)), electrical failure issues due to thermal deformation of the chip-on-film package can be eliminated.

[0046] Referring to FIG. 6 together with FIG. 1, the film substrate (100) may include a branch line pattern (164) configured to electrically connect a first bump structure (310) and a second bump structure (320) that are spaced apart from each other along a first edge (SE) of a chip mounting area (RA). The first bump structure (310) and the second bump structure (320) may be spaced apart in a first horizontal direction (e.g., Y direction) with one or more third bump structures (330) in between. The third bump structure (330) is placed on a third pad (153), and the third pad (153) may be connected to a wiring pattern (132) that extends on the base film (110).

[0047] The branch line pattern (164) extends from the main line pattern (140) to the second pad (151) to which the second bump structure (320) is attached, and may pass through the outer region (RB) of the base film (110). The branch line pattern (164) may extend along a path passing through the outer region (RB) of the base film (110) so as not to interfere with the wiring pattern (132). Part of the branch line pattern (164) is covered by the semiconductor chip (200), and other part of the branch line pattern (164) is not covered by the semiconductor chip (200). That is, when viewed from a plane, part of the branch line pattern (164) within the chip mounting area (RA) is covered by the semiconductor chip (200), and other part of the branch line pattern (164) within the outer region (RB) is not covered by the semiconductor chip (200).

[0048] One end of the branch line pattern (164) contacts the first extension pattern (141) of the main line pattern (140), and the other end of the branch line pattern (164) contacts the third side of the second pad (151) opposite to the first side (1511) of the second pad (151). The branch line pattern (164) extends along a path that bypasses the first edge (311) of the first bump structure (310) and the first edge (321) of the second bump structure (320) to electrically connect the first bump structure (310) and the second bump structure (320). The branch line pattern (164) extends by bypassing the area where stress is likely to concentrate during thermal deformation of the chip-on-film package (i.e., the area overlapping the first edge (311) of the first bump structure (310) and the first edge (321) of the second bump structure (320), thereby eliminating electrical failure issues caused by thermal deformation of the chip-on-film package.

[0049] Referring to FIG. 7 together with FIG. 1, the film substrate (100) may include a branch line pattern (165) configured to electrically connect a first bump structure (310) and a second bump structure (320) that are mutually spaced apart in a first horizontal direction (e.g., Y direction) with a third bump structure in between. The branch line pattern (165) may extend from the main line pattern (140) to a second pad (151) to which the second bump structure (320) is attached, passing through an outer region (RB) of the base film (110). One end of the branch line pattern (165) may be connected to a second side of the first pad (143), and the other end of the branch line pattern (165) may be connected to a second side of the second pad (151). The branch line pattern (165) extends along a path that bypasses the first edge (311) of the first bump structure (310) and the first edge (321) of the second bump structure (320), thereby electrically connecting the first bump structure (310) and the second bump structure (320). Since the branch line pattern (165) extends by bypassing the area where stress is likely to concentrate during thermal deformation of the chip-on-film package (i.e., the area overlapping the first edge (311) of the first bump structure (310) and the first edge (321) of the second bump structure (320)), electrical failure issues caused by thermal deformation of the chip-on-film package can be eliminated.

[0050] FIG. 8 is a perspective view showing a display device (1000) according to exemplary embodiments of the present invention.

[0051] Referring to FIG. 8, the display device (1000) may include at least one chip-on-film package (10), a driving printed circuit board (600), and a display panel (500).

[0052] The chip-on-film package (10) may correspond to any one of the chip-on-film packages described above with reference to FIGS. 1 to 3b and FIGS. 5 to 7.

[0053] A chip-on-film package (10) may include a film substrate (100) and a semiconductor chip (200) mounted on the film substrate (100). In exemplary embodiments, a chip-on-film package (10) may include a single semiconductor chip (200). In exemplary embodiments, a chip-on-film package (10) may include a plurality of semiconductor chips (200) of different types. For example, the chip-on-film package (10) may include a semiconductor chip (200) configured to perform the function of a gate driver by being connected to the gate lines of a display panel (500) and / or a semiconductor chip (200) configured to perform the function of a source driver by being connected to the source lines of a display panel (500).

[0054] The chip-on-film package (10) is located between the driving printed circuit board and the display panel and can be connected to each of the driving printed circuit board (600) and the display panel (500). The chip-on-film package (10) receives a signal output from the driving printed circuit board (600) and can transmit the signal to the display panel (500).

[0055] One or more driving circuit chips (610) capable of simultaneously or sequentially applying power and signals to the chip-on-film package (10) may be mounted on the driving printed circuit board (600).

[0056] The display panel (500) may be, for example, an LCD (liquid crystal display) panel, an LED (light emitting diode) panel, an OLED (organic LED) panel, or a plasma display panel (PDP).

[0057] The chip-on-film package (10) can be electrically connected to the driving connection wiring (630) of the driving printed circuit board (600) and the panel connection wiring (530) of the display panel (500), respectively.

[0058] In exemplary embodiments, a single chip-on-film package (10) may be connected between the driving printed circuit board (600) and the display panel (500). For example, if the display panel (500) is intended to provide a small-area screen, such as a mobile phone, or supports a relatively low resolution, the display device (1000) may include a single chip-on-film package (10). In exemplary embodiments, a plurality of chip-on-film packages (10) may be connected between the driving printed circuit board (600) and the display panel (500). For example, if the display panel (500) is intended to provide a large-area screen, such as a television, or supports a relatively high resolution, the display device (1000) may include a plurality of chip-on-film packages (10).

[0059] A chip-on-film package (10) may be connected to at least one side of a display panel (500). For example, one or more chip-on-film packages (10) may be connected to only one of the four side walls of the display panel (500), and the chip-on-film packages (10) may not be connected to the other three side walls of the display panel (500). Alternatively, one or more chip-on-film packages (10) may be connected to each of two or more side walls of the display panel (500). For example, one or more chip-on-film packages (10) may be connected to each of two interconnected side walls of the display panel (500).

[0060] The display panel (500) may include a transparent substrate (510), an image area (520) formed on the transparent substrate (510), and panel connection wiring (530). The transparent substrate (510) may be, for example, a glass substrate or a flexible substrate. A plurality of pixels having the image area (520) are connected to a plurality of corresponding panel connection wirings (530) and may be operated according to a signal provided by the semiconductor chip (200) mounted on the chip-on-film package (10).

[0061] A chip-on-film package (10) may have an input pad formed at one end and an output pad formed at the other end. Each of the input pad and the output pad may be connected to the driving connection wiring (630) of the driving printed circuit board (600) and the panel connection wiring (530) of the display panel (500), respectively, by an anisotropic conductive layer (650). The anisotropic conductive layer (650) may be, for example, an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive layer (650) may have a structure in which conductive particles are dispersed within an insulating adhesive layer. The anisotropic conductive layer (650) may have anisotropic electrical characteristics that allow current to flow only in the vertical direction and are insulated in the horizontal direction.

[0062] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0063] 10: Chip-on-film package 100: Film substrate 110: Base film 120: Input / output wiring pattern 130: Main Line Pattern 160: Branch Line Pattern 300: Bump structure 410: Underfill material layer 420: Heat dissipation resin layer

Claims

Claim 1 A film substrate comprising a base film having a chip mounting area, a main line pattern extending on the base film, and a branch line pattern extending on the base film and connected to the main line pattern; a semiconductor chip mounted on the film substrate so as to overlap the chip mounting area; and a first bump structure disposed between the semiconductor chip and the film substrate and connected to the main line pattern. A chip-on-film package comprising: a second bump structure disposed between the semiconductor chip and the film substrate, connected to the branch line pattern, and spaced apart from the first bump structure in a first direction parallel to the first edge of the chip mounting area; wherein the branch line pattern is extended so as not to overlap the first edge of the first bump structure facing the first edge of the chip mounting area and the first edge of the second bump structure facing the first edge of the chip mounting area; the film substrate further comprises a second pad coupled to the second bump structure; and the branch line pattern extends from the main line pattern to the second pad via an outer region of the base film outside the chip mounting area. Claim 2 A chip-on-film package according to claim 1, wherein the chip mounting area has a rectangular shape when viewed in a planar view, and the length of the first edge of the chip mounting area is smaller than the length of the second edge of the chip mounting area extended in a second direction perpendicular to the first direction. Claim 3 A chip-on-film package according to claim 1, characterized in that the main line pattern and the branch line pattern are configured to transmit the same power signal. Claim 4 A chip-on-film package according to claim 1, wherein the main line pattern comprises a first pad coupled to the first bump structure and a first extension pattern extending from one side of the first pad, the first pad extending from one edge of the first bump structure to the other edge along a second direction perpendicular to the first direction, and the second pad extending from one edge of the second bump structure to the other edge along the second direction. Claim 5 A chip-on-film package according to claim 4, characterized in that one end of the branch line pattern is connected to the first extension pattern and the other end of the branch line pattern is connected to one side of the second pad. Claim 6 A chip-on-film package according to claim 4, characterized in that the branch line pattern extends from one side of the first pad facing the first direction to one side of the second pad. Claim 7 delete Claim 8 A chip-on-film package according to claim 4, wherein the film substrate further comprises a third pad located between the first pad and the second pad in the first direction, and the chip-on-film package further comprises a third bump structure disposed between the third pad and the semiconductor chip. Claim 9 A chip-on-film package according to claim 1, further comprising a heat dissipation resin layer covering the semiconductor chip on the film substrate, wherein the heat dissipation resin layer comprises a resin material containing a metal filler. Claim 10 A film substrate; a semiconductor chip mounted on the film substrate; a plurality of bump structures disposed between the film substrate and the semiconductor chip; an underfill material layer filling the gap between the semiconductor chip and the film substrate; and a heat dissipation resin layer covering the semiconductor chip on the film substrate; wherein the plurality of bump structures includes a first bump structure and a second bump structure, and the film substrate has a chip mounting area and an outer area outside the chip mounting area, wherein the chip mounting area is vertically superimposed with the semiconductor chip, a base film; a main line pattern extending on the chip mounting area of ​​the base film and including a first pad coupled to the first bump structure and a first extension pattern connected to the first pad; and a second pad coupled to the second bump structure and spaced from the first pad in a first direction parallel to the first edge of the chip mounting area. A chip-on-film package comprising: a branch line pattern extending between the main line pattern and the second pad and electrically connecting the first bump structure and the second bump structure; a third pad located between the first pad and the second pad in the first direction; and a wiring pattern extending on the chip mounting area of ​​the base film and connected to the third pad; wherein the first pad extends from one edge of the first bump structure to the other edge in a second direction perpendicular to the first direction, and the second pad extends from one edge of the second bump structure to the other edge in the second direction, and the branch line pattern is spaced apart from the first side of the first pad closest to the first edge of the chip mounting area and the first side of the second pad closest to the first edge of the chip mounting area, and the branch line pattern is spaced apart from the third pad and the wiring pattern and does not interfere with the wiring pattern.

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