Semiconductor device

Abstract

A semiconductor device with improved electrical characteristics by improving stability is provided. The semiconductor device comprises a base substrate, an insulating film on the base substrate, and an upper substrate on the insulating film, wherein the insulating film comprises a crystalline insulating material, the thickness of the insulating film is 1 to 1000 nm, and the thickness of the upper substrate is 1 to 100 nm.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0002] To meet the superior performance and low prices demanded by consumers, it is necessary to increase the integration density of semiconductor devices. Since integration density is a critical factor in determining product prices for semiconductor devices, particularly increased integration density is required.

[0003] Recently, due to process miniaturization, the impact of leakage current at the bottom of semiconductor devices is becoming severe. As an alternative, SOI (silicon on insulator) wafers are attracting attention.

[0004] Conventional SOI wafers consume two wafers during manufacturing, and the manufacturing cost is high due to the complex process. Accordingly, attempts to form SOI structures through heteroepitaxial growth have been proposed. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics by enhancing stability.

[0006] The problems that the present invention aims to solve are not limited to the technical problems mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to some embodiments of the present invention for achieving the above objectives comprises a base substrate, an insulating film on the base substrate, and an upper substrate on the insulating film, wherein the insulating film comprises a crystalline insulating material, the thickness of the insulating film is 1 to 1000 nm, and the thickness of the upper substrate is 1 to 100 nm.

[0008] A semiconductor device according to some embodiments of the present invention for solving the above problem comprises a base substrate, a first insulating film on the base substrate, a first upper substrate on the first insulating film, a second insulating film on the first upper substrate, and a second upper substrate on the second insulating film, wherein the first insulating film and the second insulating film comprise a crystalline insulating material, the thickness of the first insulating film and the second insulating film is each 1 to 1000 nm, and the thickness of the first upper substrate and the second upper substrate is each 1 to 100 nm.

[0009] A semiconductor device according to some embodiments of the present invention for solving the above problem comprises a substrate having a lower pattern extending in a first direction, a first insulating film disposed within the substrate, a sheet pattern disposed on the lower pattern spaced apart from the lower pattern, and a gate electrode on the lower pattern extending in a second direction different from the first direction and surrounding the sheet pattern, wherein the lower pattern is disposed on the first insulating film, the first insulating film comprises a crystalline insulating material, the thickness of the first insulating film is 1 to 1000 nm, and the thickness of the lower pattern is 1 to 100 nm.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIGS. 1 to 3 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIGS. 4 to 7 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIG. 8 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 9 to 11 are drawings for explaining a semiconductor device according to some embodiments. FIG. 12 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 13 and FIGS. 14 are exemplary cross-sectional views for illustrating a semiconductor device according to some embodiments by cutting along AA and BB of FIG. 12, respectively. FIGS. 15 to 17 are exemplary cross-sectional views for illustrating a semiconductor device according to some embodiments. FIG. 18 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 19 and FIGS. 20 are exemplary cross-sectional views for illustrating a semiconductor device according to some embodiments by cutting along AA and BB of FIG. 18, respectively. FIGS. 21 to 23 are exemplary cross-sectional views for illustrating a semiconductor device according to some embodiments. FIG. 24 is a diagram for explaining the meaning of a lattice constant in a semiconductor device according to some embodiments. Specific details for implementing the invention

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0013] FIGS. 1 to 3 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments.

[0014] Referring to FIGS. 1 to 3, a base substrate (100) may be provided.

[0015] The base substrate (100) may include a semiconductor material. For example, the base substrate (100) may include silicon (Si).

[0016] The upper surface of the base substrate (100) may have a crystal plane (100).

[0017] A first insulating film (110) may be formed on a base substrate (100). The first insulating film (110) may be formed on a crystal plane (100) of the base substrate (100). The first insulating film (110) may extend along the upper surface of the base substrate (100). The first insulating film (110) may be in contact with the upper surface of the base substrate (100).

[0018] The first insulating film (110) may include a crystalline insulating material.

[0019] The crystalline insulating material may have a small lattice mismatch with the base substrate (100). The crystalline insulating material may be a material that exhibits suitable electrical insulation and interfacial stability.

[0020] Specifically, a crystalline insulating material may be a material with a calculated bandgap energy of 4.0 eV or higher. The bandgap energy of a crystalline insulating material can be calculated using Density Functional Theory (DFT) utilizing Heyd-Scuseria-Ernzerhof (HSE) and Generalized Gradient Approximation (GGA). Alternatively, the bandgap energy of a crystalline insulating material can be obtained through optical measurement methods.

[0021] For example, the first insulating film (110) may include at least one of fluoride, oxide, and oxyfluoride.

[0022] Specifically, the fluoride is aluminum fluoride (AlF₆) x ; provided that x is a positive number less than or equal to 3), calcium fluoride (CaF x ; provided that x is a positive number less than or equal to 2), strontium fluoride (SrF x; provided that x is a positive number less than or equal to 2), Yttrium fluoride (YF x ; provided that x is a positive number less than or equal to 3) and zirconium fluoride (ZrF x ; provided that x may include at least one of the following (a positive number less than or equal to 4).

[0023] The oxide is aluminum oxide (Al2O2). x , provided that x is a positive number less than or equal to 3), Beryllium oxide (BeO₂) x ; provided that x is a positive number less than or equal to 1), calcium zirconium oxide (Ca x Zr (1-x) O y ; where x is a positive number between 0 and 1 inclusive, and y is a positive number less than or equal to 2), hafnium oxide (HfO₂ x ; provided that x is a positive number less than or equal to 2) and yttrium oxide (Y2O x ; provided that x may include at least one of the following (a positive number less than or equal to 3).

[0024] The fluoride is lanthanum oxyfluoride (LaO₂). x F y ; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1), Lutetium oxyfluoride (LuO₂) x F y ; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1) and yttrium oxyfluoride (YO x F y ; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1) at least one of these may be included.

[0025] The thickness of the first insulating film (110) may be 1 to 1000 nm.

[0026] The first insulating film (110) can be formed by depositing a crystalline insulating material through physical vapor deposition or chemical vapor deposition.

[0027] However, the method of forming the first insulating film (110) is merely an example, and the technical concept of the present invention is not limited thereto. For example, the first insulating film (110) may be physically deposited through molecular beam epitaxy (MBE). As another example, the first insulating film (110) may be chemically deposited through chemical vapor deposition (CVD).

[0028] The difference between the lattice constant of the semiconductor material of the base substrate (100) and the lattice constant of the crystalline insulating material of the first insulating film (110) may be less than 7%. A detailed explanation of the difference between the lattice constant of the semiconductor material of the base substrate (100) and the lattice constant of the crystalline insulating material of the first insulating film (110) will be described later using FIG. 24.

[0029] A first upper substrate (120) may be formed on a first insulating film (110). The first upper substrate (120) may extend along the upper surface of the first insulating film (110). The first upper substrate (120) may be in contact with the upper surface of the first insulating film (110).

[0030] The first upper substrate (120) may include a semiconductor material. For example, the first upper substrate (120) may include silicon (Si).

[0031] The thickness of the first upper substrate (120) may be 1 to 100 nm.

[0032] The base substrate (100) and the first insulating film (110) are in contact, and the first insulating film (110) and the first upper substrate (120) may be in contact. That is, a mixed layer may not be formed between the base substrate (100) and the first insulating film (110), and between the first insulating film (110) and the first upper substrate (120), due to a difference in reactivity between the film materials.

[0033] FIGS. 4 to 7 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments.

[0034] For the convenience of explanation, the explanation will focus on the differences from the explanation using FIGS. 1 to 3.

[0035] Referring to FIGS. 4 to 7, a base substrate (100) may be provided.

[0036] An amorphous layer (110p) can be deposited on a base substrate (100). Then, the amorphous layer (110p) can be crystallized through a subsequent heat treatment (S100) to form a first insulating film (110).

[0037] The subsequent heat treatment (S100) may include annealing at a high temperature. However, this is merely an example, and the technical concept of the present invention is not limited thereto. For example, the subsequent heat treatment (S100) may be performed using ultraviolet (UV) light.

[0038] After that, a first upper substrate (120) can be formed on the first insulating film (110).

[0039] FIG. 8 is a drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those explained using FIG. 1 to 7 are simplified or omitted.

[0040] Referring to FIG. 8, a semiconductor device according to some embodiments may include a base substrate (100) and a first insulating film (110), a first upper substrate (120), a second insulating film (111) and a second upper substrate (121) stacked sequentially on the base substrate (100).

[0041] A first insulating film (110) may be formed on a base substrate (100). The first insulating film (110) may extend along the upper surface of the base substrate (100). The first insulating film (110) may be in contact with the upper surface of the base substrate (100).

[0042] The first insulating film (110) may include a crystalline insulating material. For example, the first insulating film (110) may include at least one of fluoride, oxide, and oxyfluoride.

[0043] The thickness of the first insulating film (110) may be 1 to 1000 nm.

[0044] The difference between the lattice constant of the semiconductor material of the base substrate (100) and the lattice constant of the crystalline insulating material of the first insulating film (110) may be less than 7%.

[0045] A first upper substrate (120) may be formed on a first insulating film (110). The first upper substrate (120) may extend along the upper surface of the first insulating film (110). The first upper substrate (120) may be in contact with the upper surface of the first insulating film (110).

[0046] The first upper substrate (120) may include a semiconductor material. For example, the first upper substrate (120) may include silicon (Si).

[0047] The thickness of the first upper substrate (120) may be 1 to 100 nm.

[0048] A second insulating film (111) may be formed on the first upper substrate (120). The second insulating film (111) may extend along the upper surface of the first upper substrate (120). The second insulating film (111) may be in contact with the upper surface of the first upper substrate (120).

[0049] The second insulating film (111) may include a crystalline insulating material. For example, the second insulating film (111) may include at least one of fluoride, oxide, and oxyfluoride.

[0050] The thickness of the second insulating film (111) may be 1 to 1000 nm.

[0051] The difference between the lattice constant of the semiconductor material of the first upper substrate (120) and the lattice constant of the crystalline insulating material of the second insulating film (111) may be less than 7%.

[0052] A second upper substrate (121) may be formed on the second insulating film (111). The second upper substrate (121) may extend along the upper surface of the second insulating film (111). The second upper substrate (121) may come into contact with the upper surface of the second insulating film (111).

[0053] The second upper substrate (121) may include a semiconductor material. For example, the second upper substrate (121) may include silicon (Si).

[0054] The thickness of the second upper substrate (121) may be 1 to 100 nm.

[0055] FIGS. 9 to 11 are drawings for explaining a semiconductor device according to some embodiments.

[0056] For the convenience of explanation, the explanation will focus on the differences from the explanation using FIGS. 1 to 3.

[0057] Referring to FIG. 9, a semiconductor device according to some embodiments may further include a gate structure (240) and a source / drain region (230).

[0058] A gate structure (240) may be disposed on a base substrate (200), a first insulating film (210), and a first upper substrate (220). The gate structure (240) may include a gate insulating film (241), a gate electrode (242), a gate capping film (243), and a gate spacer (244).

[0059] A gate insulating film (241) may be formed on a first upper substrate (220). The gate insulating film (241) may extend along the upper surface of the first upper substrate (220). The gate insulating film (241) may extend along the lower surface of the gate electrode (242).

[0060] The shape of the gate insulating film (241) is merely an example, and the technical concept of the present invention is not limited thereto. For example, the gate insulating film (241) may extend along the sidewall and bottom surface of the gate electrode (242).

[0061] The gate insulating film (241) is shown as a single layer, but this is merely an example and the technical concept of the present invention is not limited thereto. For example, the gate insulating film (241) may have a multilayer structure.

[0062] The gate insulating film (241) may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide.

[0063] The gate electrode (242) can be formed on the first upper substrate (220). Specifically, the gate electrode (242) can be formed on the gate insulating film (241).

[0064] The gate electrode (242) may include a conductive material. For example, the gate electrode (242) is titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum It may include at least one of nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but is not limited thereto.

[0065] The gate capping film (243) can be placed on the gate electrode (242). The gate capping film (243) can be placed between the gate spacers (244).

[0066] However, the arrangement of the gate capping film (243) is merely an example, and the technical concept of the present invention is not limited thereto. For example, the gate capping film (243) may be placed on the gate electrode (242) and the gate spacer (244).

[0067] The gate capping film (243) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN) and combinations thereof.

[0068] A gate spacer (244) may be placed on the sidewalls of the gate insulating film (241), the gate electrode (242), and the gate capping film (243). A pair of gate spacers (244) may wrap both sidewalls of the gate insulating film (241), the gate electrode (242), and the gate capping film (243).

[0069] The gate spacer (244) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0070] A source / drain region (230) may be formed within the first upper substrate (220). The source / drain region (230) may be formed within the first upper substrate (220) exposed by a gate structure (240). Specifically, the source / drain region (230) may be formed within the first upper substrate (220) exposed by a gate electrode (242).

[0071] However, the arrangement of the source / drain region (230) is merely an example, and the technical concept of the present invention is not limited thereto. For example, unlike as shown in FIG. 9, the source / drain region (230) may be formed within the first upper substrate (220) exposed by the gate electrode (242) and the gate spacer (244).

[0072] The source / drain region (230) may contain p-type impurities or n-type impurities.

[0073] Referring to FIG. 9, the source / drain region (230) may not come into contact with the first insulating film (210). That is, a semiconductor device according to some embodiments may have a partially depleted silicon on insulator (PDSOI) structure.

[0074] However, this is merely an example, and the technical concept of the present invention is not limited thereto. For example, as shown in FIG. 10, the source / drain region (230) may be in contact with the first insulating film (210). That is, a semiconductor device according to some embodiments may have a fully depleted silicon on insulator (FDSOI) structure.

[0075] For reference, FIG. 11 illustrates an embodiment of a semiconductor device including the SOI structure of FIG. 8. For convenience of explanation, parts that overlap with those described using FIG. 8 and FIG. 10 are simplified or omitted.

[0076] Referring to FIG. 11, a semiconductor device according to some embodiments may further include a second insulating film (211) and a second upper substrate (221).

[0077] The second insulating film (211) and the second upper substrate (221) can be stacked sequentially on the first upper substrate (220).

[0078] A source / drain region (230) may be formed within the second upper substrate (221). The source / drain region (230) may be formed within the second upper substrate (221) exposed by the gate structure (240). Specifically, the source / drain region (230) may be formed within the second upper substrate (221) exposed by the gate electrode (242).

[0079] The source / drain region (230) may be in contact with the second insulating film (211). That is, a semiconductor device according to some embodiments may have a fully depleted silicon on insulator (FDSOI) structure.

[0080] However, this is merely an example, and the technical concept of the present invention is not limited thereto. For example, although not illustrated, the source / drain region (230) may not come into contact with the second insulating film (211). That is, a semiconductor device according to some embodiments may have a partially depleted silicon on insulator (PDSOI) structure.

[0081] FIG. 12 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 13 and FIG. 14 are exemplary cross-sectional views for illustrating a semiconductor device according to some embodiments, each cut along AA and BB of FIG. 12. FIG. 15 to 17 are exemplary cross-sectional views for illustrating a semiconductor device according to some embodiments.

[0082] For reference, FIG. 15 is a cross-sectional view taken along AA of FIG. 12, and FIG. 16 and FIG. 17 are cross-sectional views taken along BB of FIG. 12.

[0083] Referring to FIGS. 12 to 17, a semiconductor device according to some embodiments may include a substrate (300), a first insulating film (310), an active pattern (AP1), a plurality of gate structures (GS1), and an epitaxial pattern (350).

[0084] The substrate (300) may include a low-voltage operating region and a high-voltage operating region. More specifically, the low-voltage operating region may include, for example, a logic region or an SRAM region, but is not limited thereto. The high-voltage operating region may include, for example, an I / O region, but is not limited thereto.

[0085] The substrate (300) may be a silicon-on-insulator (SOI). The substrate (300) may include a semiconductor material.

[0086] For example, the substrate (300) may include silicon (Si). The upper surface of the substrate (300) may have a crystal plane (100).

[0087] The substrate (300) may include a lower substrate (314) and a lower pattern (315).

[0088] The lower substrate (314) may be in the form of a plate extending in the first direction (X) and the second direction (Y).

[0089] A lower pattern (315) may be formed on a lower substrate (314). The lower pattern (315) may be extended in a first direction (X). The lower pattern (315) may be spaced apart in a second direction (Y). The lower pattern (315) may protrude from the upper surface of the lower substrate (314).

[0090] The lower pattern (315) can be separated by a pin trench (FT1) extending in the first direction (X).

[0091] The lower pattern (315) may include side walls facing each other. The side walls of the lower pattern (315) may extend in a first direction (X). The side walls of the lower pattern (315) may be defined by a pin trench (FT1).

[0092] The thickness of the lower pattern (315) can be 1 to 100 nm.

[0093] The first insulating film (310) may be disposed within the substrate (300). The first insulating film (310) may correspond to the first insulating film (110) of FIG. 3.

[0094] The first insulating film (310) may include a crystalline insulating material. For example, the first insulating film (310) may include at least one of fluoride, oxide, and oxyfluoride.

[0095] Specifically, the fluoride is aluminum fluoride (AlF₆) x; provided that x is a positive number less than or equal to 3), calcium fluoride (CaF x ; provided that x is a positive number less than or equal to 2), strontium fluoride (SrF x ; provided that x is a positive number less than or equal to 2), Yttrium fluoride (YF x ; provided that x is a positive number less than or equal to 3) and zirconium fluoride (ZrF x ; provided that x may include at least one of the following (a positive number less than or equal to 4).

[0096] The oxide is aluminum oxide (Al2O2). x , provided that x is a positive number less than or equal to 3), Beryllium oxide (BeO₂) x ; provided that x is a positive number less than or equal to 1), calcium zirconium oxide (Ca x Zr (1-x) O y ; where x is a positive number between 0 and 1 inclusive, and y is a positive number less than or equal to 2), hafnium oxide (HfO₂ x ; provided that x is a positive number less than or equal to 2) and yttrium oxide (Y2O x ; provided that x may include at least one of the following (a positive number less than or equal to 3).

[0097] The fluoride is lanthanum oxyfluoride (LaO₂). x F y ; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1), Lutetium oxyfluoride (LuO₂) x F y ; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1) and yttrium oxyfluoride (YO x F y; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1) at least one of these may be included.

[0098] The thickness of the first insulating film (310) may be 1 to 1000 nm.

[0099] The difference between the lattice constant of the semiconductor material of the substrate (300) and the lattice constant of the crystalline insulating material of the first insulating film (310) may be less than 7%.

[0100] The lower pattern (315) can be placed on the first insulating film (310).

[0101] Specifically, as illustrated in FIG. 13, the first insulating film (310) may be placed within the lower pattern (315). However, the placement of the first insulating film (310) is merely an example, and the technical concept of the present invention is not limited thereto.

[0102] For example, as illustrated in FIG. 15, the first insulating film (310) may be placed within the lower substrate (314) below the lower pattern (315). Accordingly, the first insulating film (310) may be extended in the second direction (Y).

[0103] Additionally, as shown in FIG. 14, the first insulating film (310) may not come into contact with the epitaxial pattern (350). That is, a semiconductor device according to some embodiments may have a partially depleted silicon on insulator (PDSOI) structure.

[0104] However, this is merely an example, and the technical concept of the present invention is not limited thereto. For example, as shown in FIG. 16, the first insulating film (310) may come into contact with an epitaxial pattern (350). That is, a semiconductor device according to some embodiments may have a fully depleted silicon on insulator (FDSOI) structure.

[0105] The number of first insulating films (310) is shown as one in FIGS. 13 to 16, but this is merely an example and the technical concept of the present invention is not limited thereto.

[0106] For example, as illustrated in FIG. 17, a semiconductor device according to some embodiments may further include a second insulating film (311).

[0107] The second insulating film (311) may be disposed within the substrate (300). The second insulating film (311) may be disposed spaced apart from the first insulating film (310).

[0108] The second insulating film (311) may correspond to the second insulating film (111) shown in FIG. 8.

[0109] The second insulating film (311) may include a crystalline insulating material. For example, the second insulating film (311) may include at least one of fluoride, oxide, and oxyfluoride.

[0110] The thickness of the second insulating film (311) may be 1 to 1000 nm.

[0111] The second insulating film (311) can come into contact with the epitaxial pattern (350). That is, a semiconductor device according to some embodiments may have a fully depleted silicon on insulator (FDSOI) structure.

[0112] However, this is merely an example, and the technical concept of the present invention is not limited thereto. For example, although not illustrated, the second insulating film (311) may not come into contact with the epitaxial pattern (350).

[0113] An active pattern (AP1) may be placed on a substrate (300). The active pattern (AP1) may be extended in a first direction (X). Although not illustrated, the active pattern (AP1) may be spaced apart in a second direction (Y) that intersects the first direction (X).

[0114] For example, the active pattern (AP1) may be an area where an NMOS is formed, and for another example, the active pattern (AP1) may be an area where a PMOS is formed.

[0115] The active pattern (AP1) may include a plurality of sheet patterns (NS).

[0116] The sheet pattern (NS) can be placed on the substrate (300). The sheet pattern (NS) can be placed spaced apart from the substrate (300).

[0117] A plurality of sheet patterns (NS) may be placed on the lower pattern (315). The plurality of sheet patterns (NS) may be spaced apart from the lower pattern (315) in a third direction (Z) that intersects the first direction (X) and the second direction (Y). The plurality of sheet patterns (NS) may be spaced apart from each other in the third direction (Z). The plurality of sheet patterns (NS) spaced apart from each other may be arranged in the first direction (X) along the upper surface of the lower pattern (315).

[0118] A field insulating film (305) can be formed on a substrate (300). The field insulating film (305) can fill at least a portion of the pin trench (FT1).

[0119] The field insulating film (305) may cover at least a portion of the sidewall of the lower pattern (315). The lower pattern (315) may be defined by the field insulating film (305).

[0120] The field insulating film (305) may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0121] A plurality of gate structures (GS1) may be disposed on a substrate (300). Each gate structure (GS1) may extend in a second direction (Y). Adjacent gate structures (GS1) may be spaced apart in a first direction (X).

[0122] A gate structure (GS1) can be placed on an active pattern (AP1). The gate structure (GS1) can intersect with the active pattern (AP1). The gate structure (GS1) can wrap around a sheet pattern (NS).

[0123] The gate structure (GS1) may include, for example, a gate electrode (320), a gate insulating film (330), an outer spacer (341), and a gate capping pattern (345).

[0124] A plurality of gate electrodes (320) may be disposed on the substrate (300). The gate electrodes (320) may be disposed on the lower pattern (315).

[0125] Each gate electrode (320) may extend in a second direction (Y) that intersects the first direction (X). Each gate electrode (320) may be spaced apart in the first direction (X).

[0126] The gate electrode (320) can be placed on the gate insulating film (330) described later. Each gate electrode (320) can intersect with the active pattern (AP1). Each gate electrode (320) can wrap around each sheet pattern (NS).

[0127] The gate electrode (320) may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The gate electrode (320) is, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum It may include at least one of nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but is not limited thereto. Conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the materials described above, but are not limited thereto.

[0128] The number of gate electrodes (320) is shown as two, but this is for convenience only and is not limited thereto. The number of gate electrodes (320) may be more or fewer than two.

[0129] The gate insulating film (330) can wrap around the perimeter of the sheet pattern (NS).

[0130] A gate insulating film (330) may be disposed on a substrate (300). The gate insulating film (330) may extend along the upper surface of the lower pattern (315) and the upper surface of the field insulating film (305). The gate insulating film (330) may wrap each sheet pattern (NS). The gate insulating film (330) may wrap the gate electrode (320).

[0131] The gate insulating film (330) can be positioned along the upper surface of the sheet pattern (NS) located at the top and the inner wall of the outer spacer (341).

[0132] The gate insulating film (330) may include an insulating material, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide.

[0133] The outer spacer (341) may be disposed on the side wall of the gate electrode (320). The outer spacer (341) may extend in a second direction (Y). A pair of outer spacers (341) may be formed on the side wall of the gate electrode (320).

[0134] The outer spacer (341) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0135] Although not illustrated in FIGS. 12 to 17, a semiconductor device according to some embodiments may further include an inner spacer. This does not limit the technical scope of the invention.

[0136] The inner spacer may extend along the side of the gate insulating film (330). The inner spacer may be placed between adjacent sheet patterns (NS) in the third direction (Z).

[0137] The inner spacer may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0138] The gate capping pattern (345) can be placed on the gate electrode (320), the gate insulating film (330), and the outer spacer (341).

[0139] The gate capping pattern (345) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN) and combinations thereof.

[0140] Multiple epitaxial patterns (350) may be included in the source / drain of a transistor using a sheet pattern (NS) as a channel region.

[0141] A plurality of epitaxial patterns (350) may be disposed on a lower pattern (315). A plurality of epitaxial patterns (350) may be disposed between gate electrodes (320) adjacent in a first direction (X). Each epitaxial pattern (350) may be connected to a sheet pattern (NS) adjacent in the first direction (X). The epitaxial pattern (350) may be formed adjacent to one side of the sheet pattern (NS) and the other side of the sheet pattern (NS).

[0142] Although not shown, source / drain contacts may be disposed on a plurality of epitaxial patterns (350). Additionally, a metal silicide film may be further disposed between the source / drain contacts and the epitaxial patterns (350).

[0143] The first interlayer insulating film (391) can cover the sidewalls of the outer spacer (341) and the gate capping pattern (345). The first interlayer insulating film (391) can be placed on the epitaxial pattern (350).

[0144] The second interlayer insulating film (392) can be placed on the first interlayer insulating film (391) and the gate capping pattern (345).

[0145] The first interlayer insulating film (391) and the second interlayer insulating film (392) may each include, for example, silicon oxide, silicon nitride, silicon oxynitride, FOX (Flowable Oxide), TOSZ (Tonen SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, or a combination thereof, but are not limited thereto.

[0146] FIG. 18 is a layout diagram illustrating a semiconductor device according to some embodiments. FIG. 19 and FIG. 20 are exemplary cross-sectional views illustrating a semiconductor device according to some embodiments, cut along AA and BB of FIG. 18, respectively. FIG. 21 to 23 are exemplary cross-sectional views illustrating a semiconductor device according to some embodiments.

[0147] For reference, FIG. 21 is a cross-sectional view taken along AA of FIG. 18, and FIG. 22 and FIG. 23 are cross-sectional views taken along BB of FIG. 18.

[0148] Referring to FIGS. 18 to 23, a semiconductor device according to some embodiments may include a substrate (400), a first insulating film (410), a pin-shaped pattern (F), a plurality of gate structures (GS2) and an epitaxial pattern (450).

[0149] The substrate (400) may include a low-voltage operating region and a high-voltage operating region. More specifically, the low-voltage operating region may be, for example, a logic region or an SRAM region, but is not limited thereto. The high-voltage operating region may be, for example, an I / O region, but is not limited thereto.

[0150] The substrate (400) may be a silicon-on-insulator (SOI). The substrate (400) may include a semiconductor material.

[0151] For example, the substrate (400) may include silicon (Si). The upper surface of the substrate (400) may have a crystal plane (100).

[0152] A pin-shaped pattern (F) can be placed on the substrate (400).

[0153] The pin-shaped pattern (F) may be extended in a first direction (X). The pin-shaped pattern (F) may be spaced apart in a second direction (Y). The pin-shaped pattern (F) may protrude from the upper surface of the substrate (400).

[0154] The pin-shaped pattern (F) can be separated by a pin trench (FT2) extending in the first direction (X).

[0155] The pin-shaped pattern (F) may include side walls facing each other. The side walls of the pin-shaped pattern (F) may extend in a first direction (X). The side walls of the pin-shaped pattern (F) may be defined by pin trenches (FT2).

[0156] The first insulating film (410) may be placed within a pin-shaped pattern (F) or a substrate (400). For example, as shown in FIG. 19, the first insulating film (410) may be placed within a pin-shaped pattern (F). As another example, as shown in FIG. 21, the first insulating film (410) may be placed within a substrate (400).

[0157] The first insulating film (410) can correspond to the first insulating film (110) of FIG. 3.

[0158] The first insulating film (410) may include a crystalline insulating material. For example, the first insulating film (410) may include at least one of fluoride, oxide, and oxyfluoride.

[0159] Specifically, the fluoride is aluminum fluoride (AlF₆) x ; provided that x is a positive number less than or equal to 3), calcium fluoride (CaF x ; provided that x is a positive number less than or equal to 2), strontium fluoride (SrF x ; provided that x is a positive number less than or equal to 2), Yttrium fluoride (YF x ; provided that x is a positive number less than or equal to 3) and zirconium fluoride (ZrF x ; provided that x may include at least one of the following (a positive number less than or equal to 4).

[0160] The oxide is aluminum oxide (Al2O2). x , provided that x is a positive number less than or equal to 3), Beryllium oxide (BeO₂) x ; provided that x is a positive number less than or equal to 1), calcium zirconium oxide (Ca x Zr (1-x) O y; where x is a positive number between 0 and 1 inclusive, and y is a positive number less than or equal to 2), hafnium oxide (HfO₂ x ; provided that x is a positive number less than or equal to 2) and yttrium oxide (Y2O x ; provided that x may include at least one of the following (a positive number less than or equal to 3).

[0161] The fluoride is lanthanum oxyfluoride (LaO₂). x F y ; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1), Lutetium oxyfluoride (LuO₂) x F y ; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1) and yttrium oxyfluoride (YO x F y ; provided that x is a positive number less than or equal to 1, and y is a positive number less than or equal to 1) at least one of these may be included.

[0162] The thickness of the first insulating film (410) may be 1 to 1000 nm.

[0163] The difference between the lattice constant of the semiconductor material of the substrate (400) and the lattice constant of the crystalline insulating material of the first insulating film (410) may be less than 7%.

[0164] The thickness of the pin-shaped pattern (F) on the first insulating film (410) can be 1 to 100 nm.

[0165] As illustrated in FIG. 20, the first insulating film (410) may not come into contact with the epitaxial pattern (450). That is, a semiconductor device according to some embodiments may have a partially depleted silicon on insulator (PDSOI) structure.

[0166] However, this is merely an example, and the technical concept of the present invention is not limited thereto. For example, as shown in FIG. 22, the first insulating film (410) may come into contact with an epitaxial pattern (450). That is, a semiconductor device according to some embodiments may have a fully depleted silicon on insulator (FDSOI) structure.

[0167] The number of first insulating films (410) is shown as one in FIGS. 19 to 22, but this is merely an example and the technical concept of the present invention is not limited thereto.

[0168] For example, as illustrated in FIG. 23, a semiconductor device according to some embodiments may further include a second insulating film (411).

[0169] The second insulating film (411) can be placed within the pin-shaped pattern (F). The second insulating film (411) can be placed spaced apart from the first insulating film (410).

[0170] The second insulating film (411) may correspond to the second insulating film (111) shown in FIG. 8.

[0171] The second insulating film (411) may include a crystalline insulating material. For example, the second insulating film (411) may include at least one of fluoride, oxide, and oxyfluoride.

[0172] The thickness of the second insulating film (411) may be 1 to 1000 nm.

[0173] The second insulating film (411) can come into contact with the epitaxial pattern (450). That is, a semiconductor device according to some embodiments may have a fully depleted silicon on insulator (FDSOI) structure.

[0174] However, this is merely an example, and the technical concept of the present invention is not limited thereto. For example, although not illustrated, the second insulating film (411) may not come into contact with the epitaxial pattern (450).

[0175] A field insulating film (405) can be formed on a substrate (400). The field insulating film (405) can fill at least a portion of the pin trench (FT2).

[0176] The field insulating film (405) can cover at least a portion of the sidewall of the pin-shaped pattern (F). The pin-shaped pattern (F) can be defined by the field insulating film (405).

[0177] The field insulating film (405) may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0178] A plurality of gate structures (GS2) may be disposed on a substrate (400). Each gate structure (GS2) may extend in a second direction (Y). Adjacent gate structures (GS2) may be spaced apart in a first direction (X).

[0179] The gate structure (GS2) can be placed on the pin-shaped pattern (F). The gate structure (GS2) can intersect with the pin-shaped pattern (F). The gate structure (GS2) can wrap around the pin-shaped pattern (F).

[0180] The gate structure (GS2) may include, for example, a gate electrode (420), a gate insulating film (430), an outer spacer (441), and a gate capping pattern (445).

[0181] A plurality of gate electrodes (420) may be disposed on a substrate (400). The gate electrodes (420) may be disposed on a pin-shaped pattern (F).

[0182] Each gate electrode (420) may extend in a second direction (Y) that intersects the first direction (X). Each gate electrode (420) may be spaced apart in the first direction (X).

[0183] The gate electrode (420) can be placed on the gate insulating film (430) described later. Each gate electrode (420) can intersect with the pin-shaped pattern (F). Each gate electrode (420) can wrap around the pin-shaped pattern (F).

[0184] The gate electrode (420) may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The gate electrode (420) is, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum It may include at least one of nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but is not limited thereto. Conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the materials described above, but are not limited thereto.

[0185] The number of gate electrodes (420) is shown as two, but this is for convenience only and is not limited thereto. The number of gate electrodes (420) may be more or fewer than two.

[0186] The gate insulating film (430) can cover a portion of the sidewall of the pin-shaped pattern (F).

[0187] The gate insulating film (430) may be disposed on the substrate (400). The gate insulating film (430) may extend along the upper surface of the pin-shaped pattern (F) and the upper surface of the field insulating film (405). The gate insulating film (430) may wrap the gate electrode (420).

[0188] The gate insulating film (430) can be placed along the upper surface of the pin-shaped pattern (F) and the inner wall of the outer spacer (441).

[0189] The gate insulating film (430) may include an insulating material, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide.

[0190] The outer spacer (441) may be disposed on the side wall of the gate electrode (420). The outer spacer (441) may extend in a second direction (Y). A pair of outer spacers (441) may be formed on the side wall of the gate electrode (420).

[0191] The outer spacer (441) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0192] The gate capping pattern (445) can be placed on the gate electrode (420), the gate insulating film (430), and the outer spacer (441).

[0193] The gate capping pattern (445) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN) and combinations thereof.

[0194] Multiple epitaxial patterns (450) may be included in the source / drain of a transistor using a pin-shaped pattern (F) as a channel region.

[0195] A plurality of epitaxial patterns (450) may be disposed between pin-shaped patterns (F). A plurality of epitaxial patterns (450) may be disposed between gate electrodes (420) adjacent in a first direction (X). Each epitaxial pattern (450) may be connected to a pin-shaped pattern (F) adjacent in the first direction (X). The epitaxial pattern (450) may be formed adjacent to one side of the pin-shaped pattern (F) and the other side of the pin-shaped pattern (F).

[0196] Although not shown, source / drain contacts may be disposed on a plurality of epitaxial patterns (450). Additionally, a metal silicide film may be further disposed between the source / drain contacts and the epitaxial patterns (450).

[0197] The first interlayer insulating film (491) can cover the sidewalls of the outer spacer (441) and the gate capping pattern (445). The first interlayer insulating film (491) can be placed on the epitaxial pattern (450).

[0198] The second interlayer insulating film (492) can be placed on the first interlayer insulating film (491) and the gate capping pattern (445).

[0199] The first interlayer insulating film (491) and the second interlayer insulating film (492) may each include, for example, silicon oxide, silicon nitride, silicon oxynitride, FOX (Flowable Oxide), TOSZ (Tonen SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, or a combination thereof, but are not limited thereto.

[0200] FIG. 24 is a diagram for explaining the meaning of a lattice constant in a semiconductor device according to some embodiments.

[0201] For reference, FIG. 24 illustrates an example of a possible reference grid within the plane (100) of silicon. Specifically, silicon may be a component of the base substrate (100, 200) of FIG. 3, FIG. 7, FIG. 8, FIG. 9 to FIG. 11, and the substrate (300, 400) of FIG. 13 to FIG. 17, FIG. 19 to FIG. 23.

[0202] Referring to FIGS. 3 and 24, the base substrate (100) may include a semiconductor material, and the insulating film (110) may include a crystalline insulating material. For example, the base substrate (100) may include silicon.

[0203] The lattice constant along the (100) plane of silicon can be the first distance (D1). The first distance can be about 5.43 Å.

[0204] In a semiconductor device according to some embodiments, the difference between the lattice constant of silicon and the lattice constant of a crystalline insulating material may be less than 7%. That is, the difference between the first distance (D1) and the lattice constant of a crystalline insulating material may be less than 7%.

[0205] However, the meaning of the lattice constant is merely illustrative, and the technical concept of the present invention is not limited thereto. In the present invention, the meaning of the lattice constant may be interpreted in an expanded manner.

[0206] For example, on a silicon plane (100), the lattice constant can be measured differently depending on the direction. Specifically, the lattice constant can be measured in the directions of the second, third, and fifth distances (D2, D3, D5) differently from the direction of the first distance (D1).

[0207] As another example, in the (100) plane of silicon, the lattice constant can be measured differently depending on the multiple. Specifically, the first distance (D1) is the shortest distance from one particle to the next adjacent particle in the direction of the first distance (D1). In contrast, the third distance and the fifth distance (D3, D5) are the shortest distances from one particle to the second adjacent particle in each direction. Also, the fourth distance (D4) is half the shortest distance from one particle to the next adjacent particle in the direction of the fourth distance (D4).

[0208] Accordingly, the lattice constant along the (100) plane of silicon may be the second to fifth distance (D2 to D5).

[0209] In a semiconductor device according to some embodiments, the difference between the lattice constant of silicon and the lattice constant of a crystalline insulating material may be less than 7%. That is, the difference between one of the second to fifth distances (D2 to D5) and the lattice constant of the crystalline insulating material may be less than 7%.

[0210] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0211] 100: Base substrate 110: First insulating film 111: Second insulating film 120: First upper substrate 121: Second upper substrate

Claims

Claim 1 A semiconductor device comprising: a base substrate; an insulating film on the base substrate; and an upper substrate on the insulating film, wherein the insulating film comprises a crystalline insulating material, the thickness of the insulating film is 1 to 1000 nm, the thickness of the upper substrate is 1 to 100 nm, the base substrate comprises a semiconductor material, and the difference between the lattice constant of the semiconductor material and the lattice constant of the crystalline insulating material is less than 7%. Claim 2 A semiconductor device according to claim 1, wherein the insulating film comprises at least one of fluoride, oxide, and oxyfluoride. Claim 3 delete Claim 4 A semiconductor device according to claim 1, wherein the insulating film is in contact with the upper surface of the base substrate, and the upper surface of the base substrate has a (100) crystal plane. Claim 5 A semiconductor device according to claim 1, wherein the base substrate and the insulating film are in contact, and the insulating film and the upper substrate are in contact. Claim 6 A semiconductor device according to claim 1, further comprising: a gate electrode formed on the upper substrate; spacers formed on both side walls of the gate electrode; and a source / drain region formed within the upper substrate exposed by the gate electrode, wherein the source / drain region is in contact with the insulating film. Claim 7 A semiconductor device comprising: a base substrate; a first insulating film on the base substrate; a first upper substrate on the first insulating film; a second insulating film on the first upper substrate; and a second upper substrate on the second insulating film, wherein the first insulating film and the second insulating film comprise a crystalline insulating material, the thickness of the first insulating film and the second insulating film is each 1 to 1000 nm, the thickness of the first upper substrate and the second upper substrate is each 1 to 100 nm, the base substrate comprises a semiconductor material, and the difference between the lattice constant of the semiconductor material and the lattice constant of the crystalline insulating material is less than 7%. Claim 8 A semiconductor device comprising: a substrate including a lower substrate and a lower pattern extending in a first direction parallel to the upper surface of the lower substrate on the lower substrate; a first insulating film disposed within the lower pattern; a sheet pattern disposed on the lower pattern spaced apart from the lower pattern; and a gate electrode extending in a second direction intersecting the first direction and surrounding the sheet pattern on the lower pattern, wherein the first insulating film comprises a crystalline insulating material, the thickness of the first insulating film is 1 to 1000 nm, and the thickness of the lower pattern is 1 to 100 nm. Claim 9 In claim 8, the semiconductor device wherein the first insulating film comprises at least one of fluoride, oxide, and oxyfluoride. Claim 10 A semiconductor device according to claim 8, further comprising an epitaxial pattern disposed between gate electrodes adjacent in the first direction on the lower pattern, wherein the epitaxial pattern is in contact with the first insulating film.

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