semiconductor device and method for partial EMI shielding

Abstract

A semiconductor device includes a substrate. An electrical component is disposed on the substrate. An encapsulant is deposited on the electrical component. A vertical interconnect structure is disposed within the encapsulant. A shielding layer is formed on the encapsulant and the vertical interconnect structure. A groove is formed within the shielding layer around the vertical interconnect structure. A portion of the shielding layer remains on the vertical interconnect structure as a contact pad.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and in particular to a semiconductor device for partial electromagnetic interference (EMI) shielding and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, electromagnetic signal transmission and reception, electronic device control, optoelectronics, and the generation of visual images for television displays. Semiconductor devices are used in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. They can also be found in military applications, aviation, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices are often susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or other inter-device interference such as capacitive, inductive, or conductive coupling (also known as crosstalk), which can disrupt operation. High-speed analog or digital circuits, such as radio frequency (RF) filters, also cause interference.

[0004] A conductive layer is typically formed on a semiconductor package to shield electronic components within the package from EMI and other interference. The shielding layer absorbs EMI before signals reach the semiconductor dies and individual components within the package, which could otherwise cause device malfunction. Additionally, the shielding layer is formed on packages containing components expected to generate EMI to protect peripheral devices. The problem to be solved

[0005] One problem with conventional methods of semiconductor package shielding is that the shielding can block desirable electromagnetic waves, such as those from an antenna within the package or from transmission and reception therefrom. Partial EMI shielding, in which a shielding layer is absent in a portion of the semiconductor package, can be used. Partial EMI shielding protects a portion of the package while leaving another portion exposed. The portion of the package kept exposed from the shielding layer may contain an antenna, physical terminals, or connectors, and electrical conductors may be physically attached for wired communication.

[0006] Masking using metal or plastic tape is generally used to leave parts of a semiconductor package without a shielding layer. However, partial shielding using masks causes many manufacturing problems. For example, it is difficult to apply tapes due to strict design rules. Therefore, there is a need for improved semiconductor devices and manufacturing methods for partial EMI shielding. Brief explanation of the drawing

[0007] FIGS. 1a-1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by top street. FIGS. 2a-2g are drawings illustrating that a conductor extends through an opening in the shield to form an EMI shield; FIGS. 3a-3d are diagrams illustrating an optional process flow using metal cans for vertical interconnection; FIGS. 4a and 4b are drawings illustrating the use of PCB units for vertical interconnection; Figures 5a and 5b are drawings illustrating the use of a connector; Figures 6a-6c are drawings illustrating the stacking of semiconductor packages. Figures 7a and 7b illustrate an electronic device having a stacked semiconductor package. Specific details for implementing the invention

[0008] The present invention is described in the following description by one or more embodiments with reference to drawings in which the same or similar elements are represented. Although the present invention is described in the best form for achieving the purpose of the invention, those skilled in the art will understand that it is intended to include alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and the equivalents supported by the following detailed description and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and multiple semiconductor devices. "Semiconductor die" and "die" are used interchangeably.

[0009] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, function to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current necessary to perform the electrical circuit function.

[0010] Back-end manufacturing refers to the process of cutting or singulating a finished wafer into individual semiconductor dies and packaging the dies for structural support, electrical interconnection, and environmental isolation. To singulate semiconductor dies, the wafer is scored and cut along non-functional areas of the wafer known as saw streets or scribes. The wafer is individualized using laser cutting tools or saw blades. After singulation, the individual semiconductor dies are mounted on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, or wire bonds. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical insulation. The finished package is then inserted into an electrical system, allowing the functions of the semiconductor device to be utilized by other system components.

[0011] FIG. 1a illustrates a semiconductor wafer (100) having a base substrate material (102), such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials, for structural support. A plurality of semiconductor dies or components (104) are formed on the wafer (100) separated by a wafer area between inactive dies or a saw street (106). The saw street (106) provides a cutting area for singulating the semiconductor wafer (100) into individual semiconductor dies (104). In one embodiment, the semiconductor wafer (100) has a width or diameter of 100 to 450 millimeters (mm).

[0012] FIG. 1b illustrates a cross-sectional view of a portion of a semiconductor wafer (100). Each semiconductor die (104) has a back or inactive surface (108) and an active surface (110) for implementing analog and digital circuits, which are implemented by active components, passive components, conductive layers, and dielectric layers formed inside the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit includes one or more transistors, diodes, and other circuit elements formed within the active surface (110) to implement analog or digital circuits, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuits. The semiconductor die (104) may also include IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0013] An electrically conductive layer (112) is formed on an active surface (110) using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer (112) may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials. The conductive layer (112) acts as a contact pad electrically connected to a circuit on the active surface (110).

[0014] An electrically conductive bump material is deposited on a conductive layer (112) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, having an optional flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (112) using a suitable attachment or bonding process. In one embodiment, the bump material may be reflowed by heating the material above its melting point to form a ball or bump (114). In one embodiment, the bump (114) is formed on an underlying bump metallization (UBM) having optionally a wetting layer, a barrier layer, and an adhesive layer. The bump (114) may also be compression bonded or heat-pressed bonded to the conductive layer (112). The bump (114) represents one type of interconnect structure that can be formed on the conductive layer (112). The interconnect structure may also use bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0015] In FIG. 1c, the semiconductor wafer (100) is singulated into individual semiconductor dies (104) through the saw street (106) using a saw blade or laser cutting tool (118). After singulation, the individual semiconductor dies (104) can be inspected and electrically tested to identify known well-functioning dies or known well-functioning units (KGD / KGU).

[0017] FIGS. 2a-2g illustrate a process for forming a shielded semiconductor package (150) having a conductive path routed through shielding. In some embodiments, the package (150) is a system-in-package (SiP) module. FIG. 2a illustrates a partial cross-sectional view of a substrate (152). Although only one substrate (152) is shown, typically hundreds or thousands of substrates are processed on a common carrier that uses the same steps as described herein for a single unit but is performed in batches. The substrate (152) may also start as one large substrate for multiple units that are separated from each other during or after the manufacturing process.

[0018] The substrate (152) comprises one or more insulating layers (154) and one or more conductive layers (156) interleaved therewith. In one embodiment, the insulating layer (154) is a core insulating substrate, and the conductive layer (156) is patterned on the upper and lower surfaces, such as, for example, a copper-clad laminated substrate. The conductive layers (156) also include conductive vias electrically coupled through the insulating layers (154). The substrate (152) may comprise any number of conductive and insulating layers interleaved with one another. A solder mask or passivation layer may be formed on both sides of the substrate (152). Any suitable type of substrate or lead frame is used for the substrate (152) in other embodiments.

[0019] The semiconductor package (150) of FIG. 2a mounts two semiconductor dies (104a-104b) and individual components (160), as well as other individual active or passive components, semiconductor dies, or other components desired for the intended function of the package. Solder bumps (114) are reflowed between the conductive layer (156) and the semiconductor die (104) to mechanically and electrically connect the die to the substrate (152). Any type and number of components may be mounted on the top surface, bottom surface, or both of the substrate (152) as shown in FIG. 2a, and may also be embedded within the substrate in any appropriate order and configuration. The semiconductor dies (104) and individual components (160) shown in the drawings are merely exemplary. Any appropriate type, number, and configuration of components may be used.

[0020] After mounting the semiconductor die (104), individual components (160), and any other desired electrical components onto the substrate (152), the components are encapsulated by the encapsulant or molding compound (170) of FIG. 2B. The encapsulant (170) is deposited onto the substrate (152), the semiconductor die (104), and the individual components (160) using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant (170) may be a polymer composite material such as an epoxy resin, an epoxy acrylate, or a polymer with or without fillers. The encapsulant (170) is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. The encapsulant (170) completely covers the top and side surfaces of the semiconductor die (104) and the individual components (160). The encapsulant (170) fills all gaps between the substrate (152) and the semiconductor die (104) or discrete component (160) unless a separate underfill is used. The encapsulant (170) is back-grinded to reduce the thickness of the encapsulant if desired.

[0021] In FIG. 2c, a mechanical drill, chemical etching, or laser (172) is used to form an opening (174) through the encapsulant (170). In other embodiments, any suitable through-hole forming method is used. The opening (174) is fully formed through the encapsulant (170) to expose the contact pad (176) of the conductive layer (156). In some embodiments, one or more additional conductive layers are formed on the substrate (152), wherein the opening (174) acts as an etching stop layer and is formed before the encapsulant (170) is deposited to improve electrical contact with subsequently formed conductive vias.

[0022] In FIG. 2d, a conductive material is deposited on the opening (174) and the contact pad (176) to form a vertical interconnect structure or a conductive via (178). The conductive via (178) is formed using any suitable metal deposition technique, such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, dispensing, or plating. The sputtered material may be copper, steel, aluminum, gold, a combination thereof, or other suitable material. The conductive material may be overfilled for the opening (174), and the conductive material may be deposited on top of the encapsulant (170) and then removed by grinding, etching, or other suitable means. The top surface of the conductive via (178) is generally made coplanar with the top surface of the encapsulant (170). The conductive via (178) provides an electrical connection from the top of the encapsulant (170) to the substrate (152).

[0023] In FIG. 2e, the shielding layer (180) is formed on the package (150) using any suitable metal deposition technique such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material may be copper, steel, aluminum, gold, a combination thereof, or other suitable material. The shielding layer (180) completely covers the exposed surfaces of the encapsulant (170), the substrate (152), and the conductive via (178). If the semiconductor package (150) is formed as a unit strip, the strip is optionally singulated before forming the shielding layer (180) so that the shielding layer can be deposited below the side surface of the package. The conductive layer (156) is exposed on the side of the substrate (152) to allow the shielding layer (180) to be connected to ground through the substrate. The shielding layer (180) is formed directly on the conductive via (178) and is in physical contact with it.

[0024] In FIG. 2f, a laser (182) is used to form a groove (184) through a shielding layer (180) around the footprint of a conductive via (178). The laser (182) may be the same as or different from the laser (172) used to form the opening (174). Chemical etching, mechanical etching, or other suitable processes are used in other embodiments. The groove (184) is formed completely through the shielding layer (180), exposing the encapsulant (170) and leaving a portion of the shielding layer isolated as a contact pad (186). The contact pad (186) is electrically coupled to the conductive layer (156) of the substrate (152) with a portion of the shielding layer (180) remaining on the conductive via (178).

[0025] FIG. 2g is a plan view illustrating that a plurality of contact pads (186) are formed to allow electrical communication from the upper surface of the package (150) to the components within the package. The package (150) exposes the contact pads (186) for subsequent electrical connection of additional components without partial molding or partial shielding of the package. The package (150) satisfies the primary purpose of partial molding and partial shielding, that is, a method of exposing the contact pads from the top of the package without the need to mask the molding or shielding step. The package (150) remains almost entirely shielded except for the area of ​​the groove (184), while allowing electrical connection through the shielding layer (180). FIG. 2g illustrates a single row of five contact pads (186), but a suitable layout (e.g., multiple rows or square contact pads) may be used depending on the intended use. The package (150) can be used as a package-on-package lower package by mounting another semiconductor package on the upper surface of the package (150) and electrically coupling the package to the contact pad (186).

[0026] FIGS. 3a-3d illustrate optional alternative embodiments in which a semiconductor package (190) is formed. In FIG. 3-a, a conductive pillar (192) is mounted on a substrate (152) together with a semiconductor die (104) and individual components (160). The conductive pillar (192) is pre-formed from aluminum, copper, steel, titanium, gold, other metals, or a combination or alloy thereof. The conductive pillar (192) is formed individually and then selected and placed on the substrate (152). The conductive pillar (192) may be formed by molding, cutting a sheet or block of material into a desired size and shape, or by other suitable means. In other embodiments, the conductive pillar (192) is formed directly on the substrate (152) using a photoresist layer as a mask to be removed. In some embodiments, the conductive pillar (192) is a metal can.

[0027] The encapsulant (170) is deposited on the substrate (150) in FIG. 3b as described above. The encapsulant (170) completely covers the conductive pillar (192). In other embodiments, a forming method (e.g., film-assisted forming) is used to expose the upper surface of the conductive pillar (192) from the encapsulant (170). A mechanical grinder (194), chemical etching, chemical-mechanical flattening, or other suitable means is used in FIG. 3c to reduce the thickness of the encapsulant (170) and expose the upper surface of the conductive pillar (192). In some embodiments, the upper portion of the conductive pillar (192) is also removed.

[0028] The shielding layer (180), groove (184), and contact pad (186) are formed in FIG. 3 as described above. The conductive pillar (192) provides an electrical connection from the conductive layer (156) of the substrate (152) to the contact pad (186) on the upper surface of the package (190).

[0029] FIGS. 4A and 4B illustrate a similar embodiment in which a semiconductor package (200) has an electronic bar (e-bar) or PCB unit (202) for vertical interconnection. The PCB unit (202) is a small printed circuit board structured similarly to the substrate (152) and includes at least an insulating base material, contact pads on the upper and lower surfaces, and conductive vias penetrating the insulating base material that connect the upper and lower contact pads to each other. In FIG. 4A, the PCB unit (202) is mounted on the substrate (152) using solder paste, solder bumps, conductive adhesive, or other suitable means. The PCB unit (202) may have multiple rows of conductive vias and contact pads for additional signal paths. In other embodiments, multiple PCB units (202) are used per package. In FIG. 4B, the encapsulant (170), shielding layer (180), groove (184), and contact pad (186) are formed as described above. The contact pad (186) can be optionally completely removed, and the upper contact pad of the PCB unit (202) is used for subsequent electrical connection.

[0030] FIGS. 5A and 5B illustrate an embodiment in which a semiconductor package (210) has a board-to-board (B2B) or other type of connector (212) mounted on a substrate (152) in FIG. 5A. An encapsulant (170) and a shielding layer (180) are formed in FIG. 5B as described above. An opening (214) is formed to completely remove the shielding layer (180) on the connector (212). Since the opening (214) extends around the connector in a plan view, it can be considered as a groove around the connector (212). The connector (212) exposed from the package (210) allows another corresponding connector to remain as a contact pad, for example by snapping into the connector (212), without needing to leave a portion of the shielding layer (180) as a contact pad.

[0031] FIGS. 6a-6c illustrate forming a package-on-package (PoP) system by stacking an upper package on top of a package (150). Although the package (150) is specifically illustrated, any of the packages described above may function as the lower package of the PoP. In FIG. 6a, the upper package (222) is mounted onto the lower package (150) using an adhesive standoff (226) or other suitable means. The upper package (222) is structured similarly to the lower package (150) by including a similar substrate (152). In other embodiments, any type of semiconductor package or device is mounted on the package (150) and coupled to a contact pad (186).

[0032] The upper package (222) includes a spring pin (224) mounted on the bottom of the package to electrically connect the components within the package (222) to the package (150). The spring pin (224) is formed of an electrically conductive material and applies mechanical force to the contact pad (186) to establish a reliable electrical connection between the packages. A plurality of spring pins (224) are used to electrically connect the upper package (222) to a plurality of contact pads (186) and to allow electrical communication between the two packages.

[0033] A PoP (220) having a contact pad (186) formed by forming a groove in the shielding layer (180) provides the primary function of partial shielding, namely, to shield some components while ensuring that other components are not shielded. By using an upper package (222) without a shielding layer, components that should not be shielded can be placed on the lower package (150), and the lower package (150) can be kept in a nearly completely shielded state. Components that should remain unshielded, such as an antenna, can be placed on the shielding layer (180) within the upper package (222). The shielding layer (180) exists between the upper package (222) and the lower package (150) to protect the two packages from EMI emitted by the two packages to each other.

[0034] FIG. 6b illustrates a PoP (230) having an upper package (232) coupled to a contact pad (186) by a solder bump (234). Similar to a spring pin (224), the solder bump (234) functions to allow electrical communication between components of the package (150, 232). However, the solder bump (234) allows reflow between the package (232) and the contact pad (186) to establish a more secure mechanical and electrical connection. Multiple rows of conductive vias (178), contact pads (186), and solder bumps (234) are used to mount the upper package (232) within an existing ball grid array.

[0035] FIG. 6c illustrates a stacked package (240) configured similarly to a semiconductor package (150) but having a lower package (242) having two rows of conductive pillars (178a and 178b) and two rows of corresponding contact pads (186a and 186b). A bare semiconductor die (104c) is mounted directly on the contact pads (186). Multiple rows of vias (178) and contact pads (186) may be formed further apart so that a larger die or package can be mounted on the lower package (242).

[0036] FIGS. 7a and 7b illustrate the integration of the semiconductor package described above, such as a PoP (220), into a larger electronic device (340), for example. FIG. 7a illustrates a partial cross-section of the PoP (220) mounted on a printed circuit board (PCB) or another substrate (342) as part of the electronic device (340). A bump (346) is formed in any desired manufacturing step similar to the description of the bump (114) described above and is reflowed onto the conductive layer (344) of the PCB (342) to physically attach and electrically connect the semiconductor package (150) to the PCB. In other embodiments, thermal compression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the PoP (220) and the PCB (342). The semiconductor dies (104) from the upper package (222) and the lower package (150) are each electrically coupled to the conductive layer (344) through the bump (346).

[0037] FIG. 7b illustrates an electronic device (340) comprising a PCB (342), wherein a plurality of semiconductor packages are mounted on the surface of the PCB comprising a PoP (220). Depending on the application, the electronic device (340) may have one type of semiconductor package or various types of semiconductor packages. The electronic device (340) may be a standalone system that uses semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device (340) may be a sub-component of a larger system. For example, the electronic device (340) may be part of a tablet, a computer, a cellular phone, a digital camera, a communication system, or other electronic device. The electronic device (340) may also be a graphics card, a network interface card, or another signal processing card inserted into a computer. The semiconductor packages may include a microprocessor, memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, individual active or passive devices, or other semiconductor dies or electrical components.

[0038] In FIG. 7b, the PCB (342) provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces (344) are formed on the surface of or within a layer of the PCB (342) using deposition, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces (344) provide electrical communication between the semiconductor package, the mounted components, and other external systems or components. The traces (344) also provide power and ground connections to the semiconductor package as needed.

[0039] In some embodiments, the semiconductor device has two packaging levels. The first stage packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second stage packaging includes mechanically and electrically attaching the intermediate substrate to a PCB (342). In other embodiments, the semiconductor device may have only the first stage packaging in which the die is directly mechanically and electrically mounted to the PCB (342).

[0040] For the purpose of explanation, various types of first-stage packaging, including bond wire packages (346) and flip chips (348), are shown on the PCB (342). Additionally, a ball grid array (BGA) (350), a bump chip carrier (BCC) (352), a land grid array (LGA) (356), a multichip module (MCM), a SIP module (358), a quad flat lead-free package (QFN) (360), a quad flat package (362), and an embedded wafer-level ball grid array (eWLB) (364) are shown mounted on the PCB (342) together with the PoP (220). Conductive traces (344) electrically connect the various packages and components placed on the PCB (342) to the PoP (220), allowing components within the PoP (220) to be used by other components on the PCB.

[0041] Depending on system requirements, any combination of semiconductor packages composed of any combination of first and second stage packaging styles and other electronic components may be connected to the PCB (342). In some embodiments, the electronic device (340) comprises a single attached semiconductor package, whereas other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, the manufacturer can integrate prefabricated components into the electronic device and system. Because the semiconductor package contains sophisticated functions, the electronic device can be manufactured using inexpensive components and a simplified manufacturing process. As a result, the device is less likely to fail and has lower manufacturing costs, leading to reduced consumer costs.

[0042] Although one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will understand that modifications and changes to these embodiments may be made without departing from the scope of the present invention as described in the following claims.

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: providing a substrate (152); placing an electrical component on the substrate (152); depositing an encapsulant (170) on the electrical component; placing a vertical interconnect structure (178) within the encapsulant; forming a shielding layer (180) over the encapsulant and the vertical interconnect structure; forming a groove (184) within the shielding layer around the vertical interconnect structure, wherein a portion of the shielding layer remains on the vertical interconnect structure as a contact pad (186); and mounting a semiconductor package to the shielding layer using an adhesive standoff (226) so that a spring pin (224) of the semiconductor package contacts the contact pad, wherein the adhesive standoff (226) extends from the semiconductor package (222) to the shielding layer (180), and the spring pin (224) applies mechanical force to the contact pad (186). Claim 2 delete Claim 3 A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: forming an opening through an encapsulant; and forming a vertical interconnect structure by depositing a conductive material on the opening. Claim 4 A method for manufacturing a semiconductor device according to claim 1, further comprising the step of placing the vertical interconnect structure on a substrate before depositing the encapsulant. Claim 5 A method for manufacturing a semiconductor device according to claim 4, wherein the vertical interconnection structure is a PCB unit. Claim 6 A method for manufacturing a semiconductor device according to claim 1, further comprising singulating the substrate and the encapsulant before forming a shielding layer. Claim 7 A method for manufacturing a semiconductor device, comprising: providing a first semiconductor package including a substrate (152), a vertical interconnect structure (178) disposed on the substrate, and an encapsulant (170) deposited on the substrate; forming a shielding layer (180) on the encapsulant (170) and the vertical interconnect structure (178); forming a groove (184) within the shielding layer (180) around the vertical interconnect structure (178) - the groove (184) extends continuously around a first portion of the shielding layer over the vertical interconnect structure - and mounting the semiconductor package to the shielding layer using an adhesive so that a spring pin (224) of the semiconductor package contacts a first portion of the shielding layer (180) - the adhesive extends from the semiconductor package (222) to the shielding layer (180), and the spring pin (224) applies mechanical force to the first portion of the shielding layer (180). Claim 8 delete Claim 9 A method for manufacturing a semiconductor device according to claim 7, wherein the vertical interconnect structure extends from the substrate to the shielding layer. Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 In claim 7, the vertical interconnect structure is a conductive via or a conductive filament, a method for manufacturing a semiconductor device. Claim 17 A method for manufacturing a semiconductor device, wherein, in claim 7, the vertical interconnect structure is a PCB unit. Claim 18 A method for manufacturing a semiconductor device, wherein, in claim 7, the vertical interconnect structure is a connector. Claim 19 A method for manufacturing a semiconductor device, comprising the steps of: providing a first semiconductor package comprising a substrate (152), a vertical interconnect structure (178) disposed on the substrate, an encapsulant (170) deposited on the substrate, and a shielding layer (180) formed on the encapsulant; forming a groove (184) within the shielding layer (180) around the vertical interconnect structure (178)—the groove extending continuously around a first portion of the shielding layer over the vertical interconnect structure—; and placing a second semiconductor package on the first semiconductor package such that a spring pin (224) of the second semiconductor package contacts a first portion of the shielding layer (180)—the spring pin (224) applies mechanical force to the first portion of the shielding layer (180). Claim 20 A method for manufacturing a semiconductor device, wherein, in paragraph 19, the vertical interconnect structure is a connector. Claim 21 A method for manufacturing a semiconductor device according to claim 19, wherein the vertical interconnect structure extends from the substrate to the shielding layer. Claim 22 A method for manufacturing a semiconductor device, comprising the steps of: providing a substrate (152); placing a vertical interconnect structure (178) on the substrate (152); depositing an encapsulant (170) on the substrate; forming a shielding layer (180) on the encapsulant (170) - the shielding layer includes a groove (184) around the vertical interconnect structure (178); placing a semiconductor package (222) on the shielding layer (180), such that a spring pin (224) of the semiconductor package contacts a contact pad (186) within the groove (184); and placing an adhesive standoff (226) located between the semiconductor package (222) and the shielding layer (180) apart from the spring pin (224). Claim 23 A method for manufacturing a semiconductor device, wherein, in paragraph 22, the vertical interconnect structure is a connector. Claim 24 A method for manufacturing a semiconductor device according to claim 22, wherein the vertical interconnect structure extends from a substrate to a shielding layer. Claim 25 A method for manufacturing a semiconductor device according to claim 22, wherein the groove extends completely around a vertical interconnect structure when viewed in a planar view.

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