Semiconductor device and method for fabricating the same

Abstract

A semiconductor device including a multi-bridge channel and a method for manufacturing the same are provided. A semiconductor device comprises a substrate including a first region and a second region; a plurality of first bridge patterns sequentially stacked on the first region and spaced apart from each other and each extending in a first direction; a first gate structure extending in a second direction intersecting the first direction and penetrating by the plurality of first bridge patterns; a first epitaxial pattern on a side of the first gate structure connected to the plurality of first bridge patterns and including a first impurity having a first conductivity type; a first silicide pattern on the first epitaxial pattern that overlaps with the plurality of first bridge patterns in a first direction; a plurality of second bridge patterns sequentially stacked on the second region and spaced apart from each other and each extending in a third direction; a second gate structure extending in a fourth direction intersecting the third direction and penetrating by the plurality of second bridge patterns; a second epitaxial pattern on a side of the second gate structure connected to the plurality of second bridge patterns and including a second impurity having a second conductivity type different from the first conductivity type; and a plurality of second bridges on the second epitaxial pattern in a third direction It includes a second silicide pattern that overlaps with the patterns, wherein the first silicide pattern and the second silicide pattern have different stress characteristics.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device comprising a multi-bridge channel and a method for manufacturing the same. Background Technology

[0002] As one of the scaling techniques to increase the density of integrated circuit devices, a multi-gate transistor has been proposed in which a silicon body in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the silicon body.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. Prior art literature

[65535] Korean Published Patent Application: 10-2020-0111997 A (Published Oct. 05, 2020) The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved performance.

[0005] Another technical problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device with improved performance.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to some embodiments for achieving the above technical problem comprises: a substrate including a first region and a second region; a plurality of first bridge patterns sequentially stacked on the first region and spaced apart from each other and each extending in a first direction; a first gate structure extending in a second direction intersecting the first direction and penetrating by the plurality of first bridge patterns; a first epitaxial pattern on the side of the first gate structure connected to the plurality of first bridge patterns and including a first impurity having a first conductivity type; a first silicide pattern on the first epitaxial pattern that overlaps with the plurality of first bridge patterns in a first direction; a plurality of second bridge patterns sequentially stacked on the second region and spaced apart from each other and each extending in a third direction; a second gate structure extending in a fourth direction intersecting the third direction and penetrating by the plurality of second bridge patterns; a second epitaxial pattern on the side of the second gate structure connected to the plurality of second bridge patterns and including a second impurity having a second conductivity type different from the first conductivity type; and on the second epitaxial pattern, It includes a second silicide pattern that overlaps with a plurality of second bridge patterns in a third direction, wherein the first silicide pattern and the second silicide pattern have different stress characteristics.

[0008] A semiconductor device according to some embodiments for achieving the above technical problem comprises: a substrate including a first region and a second region; a plurality of first bridge patterns sequentially stacked on the first region and spaced apart from each other and each extending in a first direction; a first gate structure extending in a second direction intersecting the first direction and penetrating by the plurality of first bridge patterns; a first epitaxial pattern on a side of the first gate structure connected to the plurality of first bridge patterns and containing a first impurity having a first conductivity type; a first silicide pattern surrounding the first epitaxial pattern; a plurality of second bridge patterns sequentially stacked on the second region and spaced apart from each other and each extending in a third direction; a second gate structure extending in a fourth direction intersecting the third direction and penetrating by the plurality of second bridge patterns; a second epitaxial pattern on a side of the second gate structure connected to the plurality of second bridge patterns and containing a second impurity having a second conductivity type different from the first conductivity type; and a second silicide pattern surrounding the second epitaxial pattern. The first epitaxial pattern includes a first epitaxial trench that overlaps with a plurality of first bridge patterns in a first direction, and the first silicide pattern completely fills the first epitaxial trench, and the second epitaxial pattern includes a second epitaxial trench that overlaps with a plurality of second bridge patterns in a third direction, and the second silicide pattern completely fills the second epitaxial trench, and the first silicide pattern and the second silicide pattern have different stress characteristics.

[0009] A semiconductor device according to some embodiments for achieving the above technical problem comprises: a substrate including a PFET region and an NFET region; a plurality of first bridge patterns sequentially stacked on the PFET region and spaced apart from each other and each extending in a first direction; a first gate structure extending in a second direction intersecting the first direction and penetrating by the plurality of first bridge patterns; a first epitaxial pattern including p-type impurities connected to the plurality of first bridge patterns on a side of the first gate structure; a first silicide pattern overlapping with the plurality of first bridge patterns in a first direction on the first epitaxial pattern; a plurality of second bridge patterns sequentially stacked on the NFET region and spaced apart from each other and each extending in a third direction; a second gate structure extending in a fourth direction intersecting the third direction and penetrating by the plurality of second bridge patterns; a second epitaxial pattern including n-type impurities connected to the plurality of second bridge patterns on a side of the second gate structure; and a second epitaxial pattern overlapping with the plurality of second bridge patterns in a third direction on the second epitaxial pattern. It includes a second silicide pattern, wherein the second silicide pattern has greater tensile stress characteristics than the first silicide pattern, the concentration of p-type impurities in the first epitaxial pattern decreases as it moves away from the first silicide pattern, and the concentration of n-type impurities in the second epitaxial pattern decreases as it moves away from the second silicide pattern.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is a perspective view for illustrating a semiconductor device according to some embodiments. Figure 2 is a cross-sectional view taken along A1-A1 and A2-A2 of Figure 1. Figure 3a is a graph illustrating the doping concentration of the first epitaxial pattern of Figures 1 and 2. Figure 3b is a graph illustrating the doping concentration of the second epitaxial pattern of Figures 1 and 2. Figure 4 is a cross-sectional view taken along B1-B1 and B2-B2 of Figure 1. Figures 5 and 6 are various other cross-sectional views cut along A1-A1 and A2-A2 of Figure 1. FIGS. 7 and FIGS. 8 are various cross-sectional views for illustrating a semiconductor device according to some embodiments. FIG. 9 is a perspective view for illustrating a semiconductor device according to some embodiments. FIG. 10 is a cross-sectional view taken along C1-C1 and C2-C2 of FIG. 9. FIG. 11 is a perspective view for illustrating a semiconductor device according to some embodiments. FIG. 12 is a cross-sectional view taken along D1-D1 and D2-D2 of FIG. 11. FIG. 13 is a perspective view for illustrating a semiconductor device according to some embodiments. FIG. 14 is a cross-sectional view taken along E1-E1 and E2-E2 of FIG. 13. FIGS. 15 to 36 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0012] In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention.

[0013] In addition, in this specification, "identical" means not only completely identical but also includes minute differences that may occur due to process margins, etc.

[0014] Hereinafter, a semiconductor device according to exemplary embodiments will be described with reference to FIGS. 1 to 14.

[0015] FIG. 1 is a perspective view illustrating a semiconductor device according to some embodiment. FIG. 2 is a cross-sectional view taken along A1-A1 and A2-A2 of FIG. 1. FIG. 3a is a graph illustrating the doping concentration of the first epitaxial pattern of FIG. 1 and FIG. 2. FIG. 3b is a graph illustrating the doping concentration of the second epitaxial pattern of FIG. 1 and FIG. 2. FIG. 4 is a cross-sectional view taken along B1-B1 and B2-B2 of FIG. 1.

[0016] Referring to FIGS. 1 to 4, a semiconductor device according to some embodiments comprises a substrate (100), a field insulating film (105), a first active pattern (AP1), a second active pattern (AP2), a first gate structure (GS1), a second gate structure (GS2), a first gate spacer (140), a second gate spacer (240), a first gate capping pattern (150), a second gate capping pattern (250), a first epitaxial pattern (160), a second epitaxial pattern (260), a first silicide pattern (190), a second silicide pattern (290), an interlayer insulating film (180), a first source / drain contact (CA1), and a second source / drain contact (CA2).

[0017] The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate, or may include other materials, for example, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate (100) may be a base substrate on which an epitaxial layer is formed. For convenience of explanation, the substrate (100) is described below as a silicon substrate.

[0018] The substrate (100) may include a first region (I) and a second region (II). The first region (I) and the second region (II) may be regions connected to each other or regions spaced apart from each other. Transistors of different conductivity types may be formed in the first region (I) and the second region (II). In the following description, the first region (I) is described as a PFET region and the second region (II) is described as an NFET region.

[0019] In some embodiments, the upper surface of the substrate (100) may include a {100} crystal plane. For example, the upper surface of the substrate (100) may be one of a (-1 0 0) plane, a (0 1 0) plane, a (0 -1 0) plane, a (0 0 1) plane, or a (0 0 -1) plane.

[0020] A first active pattern (AP1) may be formed on a first region (I) of a substrate (100). The first active pattern (AP1) may extend in a first direction (X1) parallel to the upper surface of the substrate (100). The first active pattern (AP1) may include a plurality of bridge patterns (e.g., first to third bridge patterns (111 to 113)) that are stacked sequentially on the upper surface of the substrate (100) and extend in the first direction (X1) while being spaced apart from each other. This first active pattern (AP1) may include an MBCFET comprising a multi-bridge channel. ® It can be used as a channel area. The number of bridge patterns included in the first active pattern (AP1) is merely exemplary and is not limited to what is illustrated.

[0021] In some embodiments, the first active pattern (AP1) may further include a first pin pattern (110). The first pin pattern (110) may protrude from the upper surface of the substrate (100) and extend in a first direction (X1). The first pin pattern (110) may be formed by etching a portion of the substrate (100) or may be an epitaxial layer grown from the substrate (100). The first to third bridge patterns (111 to 113) may be stacked sequentially on the upper surface of the first pin pattern (110).

[0022] The width of the first active pattern (AP1) (W11 in FIG. 1) is shown as being constant in the height direction (i.e., the third direction (Z1)), but this is merely illustrative. Depending on the characteristics of the etching process (or patterning process) for forming the first active pattern (AP1), the width of the first active pattern (AP1) (W11 in FIG. 1) may decrease as it moves away from the substrate (100). For example, unlike what is shown, the width of the first bridge pattern (111) may be smaller than the width of the first pin pattern (110), the width of the second bridge pattern (112) may be smaller than the width of the first bridge pattern (111), and the width of the third bridge pattern (113) may be smaller than the width of the second bridge pattern (112).

[0023] A second active pattern (AP2) may be formed on a second region (II) of the substrate (100). The second active pattern (AP2) may extend in a fourth direction (X2) parallel to the upper surface of the substrate (100). The second active pattern (AP2) may include a plurality of bridge patterns (e.g., fourth to sixth bridge patterns (211 to 213)) that are stacked sequentially on the upper surface of the substrate (100) and extend in the fourth direction (X2) while being spaced apart from each other. This second active pattern (AP2) may include an MBCFET comprising a multi-bridge channel. ®It can be used as a channel area. The number of bridge patterns included in the second active pattern (AP2) is merely exemplary and is not limited to what is illustrated.

[0024] In some embodiments, the second active pattern (AP2) may further include a second pin pattern (210). The second pin pattern (210) may protrude from the upper surface of the substrate (100) and extend in a fourth direction (X2). The second pin pattern (210) may be formed by etching a portion of the substrate (100) or may be an epitaxial layer grown from the substrate (100). The fourth to sixth bridge patterns (211 to 213) may be stacked sequentially on the upper surface of the second pin pattern (210).

[0025] The width of the second active pattern (AP2) (W21 in FIG. 1) is shown as being constant in the height direction (i.e., the third direction (Z1)), but this is merely illustrative. Depending on the characteristics of the etching process (or patterning process) for forming the second active pattern (AP2), the width of the second active pattern (AP2) (W21 in FIG. 1) may decrease as it moves away from the substrate (100). For example, unlike what is shown, the width of the fourth bridge pattern (211) may be smaller than the width of the second pin pattern (210), the width of the fifth bridge pattern (212) may be smaller than the width of the fourth bridge pattern (211), and the width of the sixth bridge pattern (213) may be smaller than the width of the fifth bridge pattern (212).

[0026] The first active pattern (AP1) and the second active pattern (AP2) may each include silicon (Si) or germanium (Ge), which are elemental semiconductor materials. Alternatively, the first active pattern (AP1) and the second active pattern (AP2) may each include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound, a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound in which a group IV element is doped therein. The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with at least one of the group V elements phosphorus (P), arsenic (As), and antimony (Sb). For example, in the following description, the first active pattern (AP1) and the second active pattern (AP2) are each described as silicon (Si) patterns.

[0027] In some embodiments, the first active pattern (AP1) and the second active pattern (AP2) may be placed at the same level. Here, being placed at the same level means being placed at the same height relative to the upper surface of the substrate (100). For example, as shown in FIGS. 2 and 4, the first to third bridge patterns (111–113) and the fourth to sixth bridge patterns (211–213) may be placed at the same height relative to each other.

[0028] A field insulating film (105) may be formed on a substrate (100). The field insulating film (105) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0029] In some embodiments, the field insulating film (105) may cover at least a portion of the side of the first pin pattern (110) and at least a portion of the side of the second pin pattern (210). Only the upper portion of the first pin pattern (110) and the upper portion of the second pin pattern (210) are shown protruding from the upper surface of the field insulating film (105), but this is merely illustrative. In another example, the upper surface of the field insulating film (105) may be positioned in a co-plane with the upper surface of the first pin pattern (110) and the upper surface of the second pin pattern (210).

[0030] A first gate structure (GS1) may be formed on a first region (I) of a substrate (100) and a field insulating film (105). The first gate structure (GS1) may intersect with a first active pattern (AP1). For example, the first gate structure (GS1) may extend in a second direction (Y1) that intersects a first direction (X1) and is parallel to the upper surface of the substrate (100). The first to third bridge patterns (111 to 113) may each extend in the first direction (X1) and penetrate the first gate structure (GS1). That is, the first gate structure (GS1) may surround the perimeter of each of the first to third bridge patterns (111 to 113).

[0031] A second gate structure (GS2) may be formed on a second region (II) of the substrate (100) and on a field insulating film (105). The second gate structure (GS2) may intersect with a second active pattern (AP2). For example, the second gate structure (GS2) may extend in a fifth direction (Y2) that intersects a fourth direction (X2) and is parallel to the upper surface of the substrate (100). Fourth to sixth bridge patterns (211 to 213) may each extend in the fourth direction (X2) and penetrate the second gate structure (GS2). That is, the second gate structure (GS2) may surround the perimeter of each of the fourth to sixth bridge patterns (211 to 213).

[0032] The first gate structure (GS1) may include a first gate dielectric film (120) and a first gate electrode (130), and the second gate structure (GS2) may include a second gate dielectric film (220) and a second gate electrode (230).

[0033] The first gate dielectric film (120) may be laminated on the first active pattern (AP1). The first gate dielectric film (120) may surround the perimeter of the first active pattern (AP1). Additionally, the first gate dielectric film (120) may extend along the upper surface of the field insulating film (105) and the surface of the first pin pattern (110) protruding from the field insulating film (105).

[0034] The second gate dielectric film (220) may be laminated on the second active pattern (AP2). The second gate dielectric film (220) may surround the perimeter of the second active pattern (AP2). Additionally, the second gate dielectric film (220) may extend along the upper surface of the field insulating film (105) and the surface of the second pin pattern (210) protruding from the field insulating film (105).

[0035] The first gate dielectric film (120) and the second gate dielectric film (220) may each comprise, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may be, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), hafnium oxynitride (HfO2). x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La2O x N y ), aluminum oxynitride (Al2O x Ny ), titanium oxynitride (TiO₂ x N y ), strontium titanium oxynitride (SrTiO2) x N y ), Lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y2O x It may include at least one of Ny) and combinations thereof, but is not limited thereto.

[0036] In some embodiments, the first gate dielectric film (120) may include a first interface film (122) and a first high dielectric film (124) that are sequentially stacked on a first active pattern (AP1). In some embodiments, the second gate dielectric film (220) may include a second interface film (222) and a second high dielectric film (224) that are sequentially stacked on a second active pattern (AP2).

[0037] The first interface film (122) may be conformally extended along the perimeter of each of the first to third bridge patterns (111 to 113). The second interface film (222) may be conformally extended along the perimeter of each of the fourth to sixth bridge patterns (211 to 213). The first interface film (122) and the second interface film (222) may each comprise at least one of, for example, silicon oxide, silicon oxynitride, or silicon nitride. In some embodiments, the first interface film (122) may comprise an oxide of the first active pattern (AP1), and the second interface film (222) may comprise an oxide of the second active pattern (AP2).

[0038] The first high dielectric film (124) may be conformally extended along the perimeter of the first interface film (122). The second high dielectric film (224) may be conformally extended along the perimeter of the second interface film (222). The first high dielectric film (124) and the second high dielectric film (224) may each include, for example, the high dielectric constant material.

[0039] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the first gate dielectric film (120) and / or the second gate dielectric film (220) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0040] The ferroelectric material film may have negative capacitance, and the paraelectric material film may have positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance decreases compared to the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

[0041] When the ferroelectric material film having negative capacitance and the paraelectric material film having positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and the paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than about 60 mV / decade at room temperature.

[0042] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, for example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0043] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0044] When the ferroelectric material film comprises hafnium oxide, the dopant included in the ferroelectric material film may comprise, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0045] When the dopant is aluminum (Al), the ferroelectric material film may contain about 3 at% to about 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0046] When the dopant is silicon (Si), the ferroelectric material film may contain about 2 at% to about 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 at% to 80 at% zirconium.

[0047] The above-mentioned paraelectric material film may have paraelectric properties. The above-mentioned paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the above-mentioned paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0048] The ferroelectric material film and the paraelectric material film may contain the same material. The ferroelectric material film may have ferroelectric properties, while the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film is different from the crystal structure of the hafnium oxide contained in the paraelectric material film.

[0049] The above-mentioned ferroelectric material film may have a thickness having ferroelectric properties. The thickness of the above-mentioned ferroelectric material film may be, for example, 0.5 nm to 10 nm, but is not limited thereto. Since the critical thickness exhibiting ferroelectric properties may vary for each ferroelectric material, the thickness of the above-mentioned ferroelectric material film may vary depending on the ferroelectric material.

[0050] For example, the first gate dielectric film (120) and / or the second gate dielectric film (220) may include a single ferroelectric material film. As another example, the first gate dielectric film (120) and / or the second gate dielectric film (220) may include a plurality of ferroelectric material films spaced apart from each other. The first gate dielectric film (120) and / or the second gate dielectric film (220) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0051] The first gate electrode (130) may be formed on the substrate (100) and the field insulating film (105). Additionally, the first gate electrode (130) may be laminated on the first gate dielectric film (120). That is, the first gate dielectric film (120) may be interposed between the first active pattern (AP1) and the first gate electrode (130). Additionally, the first gate dielectric film (120) may be interposed between the first pin pattern (110) and the first gate electrode (130). The first gate electrode (130) may be formed, for example, by a replacement process, but is not limited thereto.

[0052] The second gate electrode (230) may be formed on the substrate (100) and the field insulating film (105). Additionally, the second gate electrode (230) may be laminated on the second gate dielectric film (220). That is, the second gate dielectric film (220) may be interposed between the second active pattern (AP2) and the second gate electrode (230). Additionally, the second gate dielectric film (220) may be interposed between the second pin pattern (210) and the second gate electrode (230). The second gate electrode (230) may be formed, for example, by a replacement process, but is not limited thereto.

[0053] Although the first gate electrode (130) and the second gate electrode (230) are each illustrated as having a single film, this is merely illustrative, and it is understood that the first gate electrode (130) and the second gate electrode (230) may each be formed by stacking multiple conductive layers. For example, each of the first gate electrode (130) and the second gate electrode (230) may include a work function control film that controls the work function and a filling conductive film that fills the space formed by the work function control film. The work function control film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al.

[0054] A first gate spacer (140) may be formed on a substrate (100) and a field insulating film (105). The first gate spacer (140) may extend along the side of the first gate structure (GS1). In some embodiments, a portion of the first gate dielectric film (120) may be interposed between the first gate electrode (130) and the first gate spacer (140). For example, the first gate dielectric film (120) may extend further along at least a portion of the inner side of the first gate spacer (140). Such a first gate dielectric film (120) may be formed by a replacement process, but is not limited thereto.

[0055] A second gate spacer (240) may be formed on the substrate (100) and the field insulating film (105). The second gate spacer (240) may extend along the side of the second gate structure (GS2). In some embodiments, a portion of the second gate dielectric film (220) may be interposed between the second gate electrode (230) and the second gate spacer (240). For example, the second gate dielectric film (220) may extend further along at least a portion of the inner side of the second gate spacer (240). Such a second gate dielectric film (220) may be formed by a replacement process, but is not limited thereto.

[0056] The first gate spacer (140) and the second gate spacer (240) may each include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and combinations thereof, but are not limited thereto.

[0057] The first gate capping pattern (150) may extend along the upper surface of the first gate structure (GS1). In some embodiments, the first gate capping pattern (150) may cover the upper surface of the first gate structure (GS1) and the upper surface of the first gate spacer (140). In some embodiments, the upper surface of the first gate structure (GS1) and the upper surface of the first gate spacer (140) may include an upwardly concave surface.

[0058] The second gate capping pattern (250) may extend along the upper surface of the second gate structure (GS2). In some embodiments, the second gate capping pattern (250) may cover the upper surface of the second gate structure (GS2) and the upper surface of the second gate spacer (240). In some embodiments, the upper surface of the second gate structure (GS2) and the upper surface of the second gate spacer (240) may include an upwardly concave surface.

[0059] The first gate capping pattern (150) and the second gate capping pattern (250) may each include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and combinations thereof, but are not limited thereto.

[0060] The first epitaxial pattern (160) may be formed on the upper surface of the substrate (100) and on at least one side (e.g., both sides) of the first gate structure (GS1). Additionally, the first epitaxial pattern (160) may be connected to the first active pattern (AP1). For example, each of the first to third bridge patterns (111 to 113) may be connected to the first epitaxial pattern (160) by penetrating the first gate structure (GS1) and the first gate spacer (140). The first epitaxial pattern (160) may be electrically isolated from the first gate electrode (130) by the first gate dielectric film (120) and / or the first gate spacer (140). The first epitaxial pattern (160) may include an epitaxial layer. For example, the first epitaxial pattern (160) can be formed from the first active pattern (AP1) by an epitaxial growth method. This first epitaxial pattern (160) can be provided as a source / drain region of a transistor (e.g., PFET) formed on the first region (I).

[0061] The width of the first direction (X1) of the first epitaxial pattern (160) is shown as constant in the height direction (i.e., the third direction (Z1)), but this is merely illustrative. Depending on the characteristics of the etching process (or recessing process) performed on the first active pattern (AP1) to form the first epitaxial pattern (160), the width of the first direction (X1) of the first epitaxial pattern (160) may decrease toward the substrate (100) as shown.

[0062] The first epitaxial pattern (160) may include a first epitaxial trench (160t) within it. For example, as illustrated in FIG. 2, the first epitaxial trench (160t) may be defined by at least a portion of the upper surface of the first epitaxial pattern (160). The first epitaxial trench (160t) may extend in a second direction (Y1). For example, the first epitaxial pattern (160) may be 'U' shaped in a cross-section intersecting the second direction (Y1). In some embodiments, the first epitaxial trench (160t) may be a deep trench that overlaps the first to third bridge patterns (111–113) in the first direction (X1). For example, the lower surface of the first epitaxial trench (160t) may be lower than the upper surface of the first bridge pattern (111), and the upper surface of the first epitaxial trench (160t) may be higher than the lower surface of the third bridge pattern (113).

[0063] In some embodiments, the upper surface of the first epitaxial pattern (160) may include a first inclined surface (160s). The first inclined surface (160s) may be adjacent to the first gate structure (GS1). Additionally, the height of the first inclined surface (160s) may decrease as it moves away from the first gate structure (GS1). In some embodiments, the first inclined surface (160s) may include a {111} crystal plane. For example, the first inclined surface (160s) may be one of a (1 1 1) plane, a (1 1 -1) plane, a (1 -1 1) plane, a (1 -1 -1) plane, a (-1 1 1) plane, a (-1 1 -1) plane, a (-1 -1 1) plane, and a (-1 -1 -1) plane. In some embodiments, the first inclined surface (160s) may extend from a position higher than the upper surface of the top bridge pattern (e.g., the third bridge pattern (113)). For example, the upper part of the first epitaxial pattern (160) may come into contact with the outer surface of the first gate spacer (160) positioned on the upper surface of the top bridge pattern (e.g., the third bridge pattern (113)).

[0064] In some embodiments, the first epitaxial trench (160t) may extend downward from the first inclined plane (160s) toward the substrate (100). Only the width of the first direction (X1) of the first epitaxial trench (160t) in the height direction (i.e., the third direction (Z1)) is shown as constant, but this is merely exemplary. Unlike what is shown, if the width of the first direction (X1) of the first epitaxial pattern (160) decreases toward the substrate (100), the width of the first direction (X1) of the first epitaxial trench (160t) may also decrease toward the substrate (100).

[0065] In some embodiments, the width of the first epitaxial pattern (160) in the second direction (Y1) (W12 in FIG. 1) may be the same as the width of the first active pattern (AP1) (W11 in FIG. 1). Only the width of the first epitaxial pattern (160) in the second direction (Y1) (W12 in FIG. 1) in the height direction (i.e., the third direction (Z1)) is shown as constant, but this is merely illustrative. Unlike what is shown, if the width of the first active pattern (AP1) (W11 in FIG. 1) decreases as it moves away from the substrate (100), the width of the first epitaxial pattern (160) in the second direction (Y1) may also decrease as it moves away from the substrate (100).

[0066] The first epitaxial pattern (160) may include a first impurity having a first conductivity type. For example, when the first region (I) is a PFET region, the first epitaxial pattern (160) may include a p-type impurity or an impurity to prevent the diffusion of the p-type impurity. The p-type impurity may include, for example, at least one of boron (B), indium (In), gallium (Ga), aluminum (Al), and combinations thereof.

[0067] In some embodiments, the first epitaxial pattern (160) may further include a compressive stress material. For example, when the first active pattern (AP1) is a silicon pattern, the first epitaxial pattern (160) may include a material having a larger lattice constant than silicon (Si) (e.g., silicon germanium (SiGe)). The compressive stress material can apply compressive stress to the first active pattern (AP1) to improve the carrier mobility of the channel region.

[0068] The second epitaxial pattern (260) may be formed on the upper surface of the substrate (100) and on at least one side (e.g., both sides) of the second gate structure (GS2). Additionally, the second epitaxial pattern (260) may be connected to the second active pattern (AP2). For example, each of the fourth to sixth bridge patterns (211–213) may be connected to the second epitaxial pattern (260) by penetrating the second gate structure (GS2) and the second gate spacer (240). The second epitaxial pattern (260) may be electrically isolated from the second gate electrode (230) by the second gate dielectric film (220) and / or the second gate spacer (240). The second epitaxial pattern (260) may include an epitaxial layer. For example, the second epitaxial pattern (260) can be formed from the second active pattern (AP2) by an epitaxial growth method. This second epitaxial pattern (260) can be provided as a source / drain region of a transistor (e.g., NFET) formed on the second region (II).

[0069] The width of the fourth direction (X2) of the second epitaxial pattern (260) is shown as constant in the height direction (i.e., the sixth direction (Z2)), but this is merely illustrative. Depending on the characteristics of the etching process (or recessing process) performed on the second active pattern (AP2) to form the second epitaxial pattern (260), the width of the fourth direction (X2) of the second epitaxial pattern (260) may decrease toward the substrate (100) as shown.

[0070] The second epitaxial pattern (260) may include a second epitaxial trench (260t) within it. For example, as illustrated in FIG. 2, the second epitaxial trench (260t) may be defined by at least a portion of the upper surface of the second epitaxial pattern (260). The second epitaxial trench (260t) may extend in a fifth direction (Y2). For example, the second epitaxial pattern (260) may be 'U' shaped in a cross-section intersecting the fifth direction (Y2). In some embodiments, the second epitaxial trench (260t) may be a deep trench that overlaps the fourth to sixth bridge patterns (211–213) in the fourth direction (X2). For example, the lower surface of the second epitaxial trench (260t) may be lower than the upper surface of the fourth bridge pattern (211), and the upper surface of the second epitaxial trench (260t) may be higher than the lower surface of the sixth bridge pattern (213).

[0071] In some embodiments, the upper surface of the second epitaxial pattern (260) may include a second inclined surface (260s). The second inclined surface (260s) may be adjacent to the second gate structure (GS2). Additionally, the height of the second inclined surface (260s) may decrease as it moves away from the second gate structure (GS2). In some embodiments, the second inclined surface (260s) may include a {111} crystal plane. For example, the second inclined surface (260s) may be one of a (1 1 1) plane, a (1 1 -1) plane, a (1 -1 1) plane, a (1 -1 -1) plane, a (-1 1 1) plane, a (-1 1 -1) plane, a (-1 -1 1) plane, and a (-1 -1 -1) plane. In some embodiments, the second inclined surface (260s) may extend from a position higher than the upper surface of the uppermost bridge pattern (e.g., the sixth bridge pattern (213)). For example, the upper part of the second epitaxial pattern (260) may come into contact with the outer surface of the second gate spacer (260) positioned on the upper surface of the uppermost bridge pattern (e.g., the sixth bridge pattern (213)).

[0072] In some embodiments, the second epitaxial trench (260t) may extend downward from the second inclined plane (260s) toward the substrate (100). Only the width of the fourth direction (X2) of the second epitaxial trench (260t) in the height direction (i.e., the sixth direction (Z2)) is shown as constant, but this is merely exemplary. Unlike what is shown, if the width of the fourth direction (X2) of the second epitaxial pattern (260) decreases toward the substrate (100), the width of the fourth direction (X2) of the second epitaxial trench (260t) may also decrease toward the substrate (100).

[0073] In some embodiments, the width of the second epitaxial pattern (260) in the fifth direction (Y2) (W22 in FIG. 1) may be the same as the width of the second active pattern (AP2) (W21 in FIG. 1). Only the width of the second epitaxial pattern (260) in the fifth direction (Y2) (W22 in FIG. 1) in the height direction (i.e., the sixth direction (Z2)) is shown as constant, but this is merely illustrative. Unlike what is shown, if the width of the second active pattern (AP2) (W21 in FIG. 1) decreases as it moves away from the substrate (100), the width of the second epitaxial pattern (260) in the fifth direction (Y2) may also decrease as it moves away from the substrate (100).

[0074] The second epitaxial pattern (260) may include a second impurity having a second conductivity type different from the first conductivity type. For example, if the second region (II) is an NFET region, the second epitaxial pattern (260) may include an n-type impurity or an impurity to prevent the diffusion of the n-type impurity. The n-type impurity may include, for example, at least one of phosphorus (P), arsenic (As), antimony (Sb), and combinations thereof.

[0075] In some embodiments, the second epitaxial pattern (260) may further include a tensile stress material. For example, when the second active pattern (AP2) is a silicon pattern, the second epitaxial pattern (260) may include a material having a smaller lattice constant than silicon (Si) (e.g., silicon carbide (SiC)). The tensile stress material can apply tensile stress to the second active pattern (AP2) to improve the carrier mobility of the channel region.

[0076] A first silicide pattern (190) may be formed on a first epitaxial pattern (160). The first silicide pattern (190) may be connected to the first epitaxial pattern (160). The first silicide pattern (190) may surround the outer surface of the first epitaxial pattern (160). For example, as shown in FIG. 1, the first silicide pattern (190) may cover the side and top surfaces of the first epitaxial pattern (160). Additionally, as shown in FIG. 2, the first silicide pattern (190) may fill at least a portion of the first epitaxial trench (160t). Through this, the contact area between the first epitaxial pattern (160) and the first silicide pattern (190) is improved, and the contact resistance of the first epitaxial pattern (160) can be improved.

[0077] In some embodiments, the first silicide pattern (190) can completely fill the first epitaxial trench (160t) of the first epitaxial pattern (160). For example, with respect to the upper surface of the substrate (100), the height of the upper surface of the first silicide pattern (190) may be higher than the height of the upper surface of the first epitaxial trench (160t).

[0078] In some embodiments, the concentration of the first impurity (e.g., boron (B), indium (In), gallium (Ga) and / or aluminum (Al)) in the first epitaxial pattern (160) may decrease as it moves away from the first silicide pattern (190). That is, the concentration of the first impurity in the first epitaxial pattern (160) may be highest at the interface with the first silicide pattern (190). For example, a first point (P1) may be defined on the interface between the first epitaxial pattern (160) and the first silicide pattern (190), and a second point (P2) may be defined on the interface between the first epitaxial pattern (160) and the first pin pattern (110). As shown in FIG. 3a, the doping concentration of the first epitaxial pattern (160) can be gradually reduced in the direction from the first point (P1) toward the second point (P2).

[0079] In some embodiments, the first silicide pattern (190) may include a third inclined surface (190s). The height of the third inclined surface (190s) may decrease as it moves away from the first gate structure (GS1).

[0080] A second silicide pattern (290) may be formed on a second epitaxial pattern (260). The second silicide pattern (290) may be connected to the second epitaxial pattern (260). The second silicide pattern (290) may surround the outer surface of the second epitaxial pattern (260). For example, as shown in FIG. 1, the second silicide pattern (290) may cover the side and top surfaces of the second epitaxial pattern (260). Additionally, as shown in FIG. 2, the second silicide pattern (290) may fill at least a portion of the second epitaxial trench (260t). Through this, the contact area between the second epitaxial pattern (260) and the second silicide pattern (290) is improved, and the contact resistance of the second epitaxial pattern (260) can be improved.

[0081] In some embodiments, the second silicide pattern (290) may completely fill the second epitaxial trench (260t) of the second epitaxial pattern (260). For example, with respect to the upper surface of the substrate (100), the height of the upper surface of the second silicide pattern (290) may be higher than the height of the upper surface of the second epitaxial trench (260t).

[0082] In some embodiments, the concentration of the second impurity (e.g., phosphorus (P), arsenic (As) and / or antimony (Sb)) in the second epitaxial pattern (260) may decrease as it moves away from the second silicide pattern (290). That is, the concentration of the second impurity in the second epitaxial pattern (260) may be highest at the interface with the second silicide pattern (290). For example, a third point (P3) may be defined on the interface between the second epitaxial pattern (260) and the second silicide pattern (290), and a fourth point (P4) may be defined on the interface between the second epitaxial pattern (260) and the second pin pattern (210). As shown in FIG. 3b, the doping concentration of the second epitaxial pattern (260) can be gradually reduced in the direction from the third point (P3) toward the fourth point (P4).

[0083] In some embodiments, the second silicide pattern (290) may include a fourth inclined surface (290s). The height of the fourth inclined surface (290s) may decrease as it moves away from the second gate structure (GS2).

[0084] The first silicide pattern (190) and the second silicide pattern (290) may have different stress characteristics. For example, if the first region (I) is a PFET region and the second region (II) is an NFET region, the second silicide pattern (290) may have greater tensile stress characteristics than the first silicide pattern (190).

[0085] For example, the first silicide pattern (190) may include a metal silicide having relatively small tensile stress characteristics or compressive stress characteristics, such as nickel silicide (NiSi) or molybdenum silicide (MoSi2). This first silicide pattern (190) can improve the carrier mobility of the channel region by applying compressive stress to the first epitaxial pattern (160) and the first active pattern (AP1).

[0086] Additionally, for example, the second silicide pattern (290) may include a metal silicide having relatively large tensile stress characteristics, such as titanium silicide (TiSi2) or cobalt silicide (CoSi2). This second silicide pattern (290) can improve the carrier mobility of the channel region by applying compressive stress to the second epitaxial pattern (260) and the second active pattern (AP2).

[0087] An interlayer insulating film (180) may be formed on a substrate (100) and a field insulating film (105). The interlayer insulating film (180) may be formed to fill the space on the outer surface of the first gate spacer (140) and the space on the outer surface of the second gate spacer (240). For example, the interlayer insulating film (180) may cover the field insulating film (105), the first epitaxial pattern (160), and the second epitaxial pattern (260). Although only the upper surface of the first gate capping pattern (150) and the upper surface of the second gate capping pattern (250) are shown as being exposed, this is merely exemplary. As another example, the interlayer insulating film (180) may cover the upper surface of the first gate capping pattern (150) and the upper surface of the second gate capping pattern (250).

[0088] The interlayer insulating film (180) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide. The above low dielectric constant material may include, for example, at least one of FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and combinations thereof, but is not limited thereto.

[0089] In some embodiments, a first liner film (182) covering the first silicide pattern (190) and the second silicide pattern (290) may be formed. The first liner film (182) may extend conformally along the profiles of the surface of the first silicide pattern (190) and the surface of the second silicide pattern (290). The first liner film (182) may also extend further along the upper surface of the field insulating film (105), the side of the first gate spacer (140), and the side of the second gate spacer (240). An interlayer insulating film (180) may be formed on the first liner film (182).

[0090] The first liner film (182) may comprise a material having an etch selectivity ratio with respect to the interlayer insulating film (180). For example, when the interlayer insulating film (180) comprises silicon oxide, the first liner film (182) may comprise at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boronitride (SiBN), silicon boronitride (SiOBN), silicon carbonate (SiOC), and combinations thereof. This first liner film (182) may be provided as an etch stop layer in an etching process for the interlayer insulating film (180).

[0091] The first source / drain contact (CA1) can be connected to the first silicide pattern (190). For example, the first source / drain contact (CA1) can extend in a third direction (Z1) to penetrate the interlayer insulating film (180) and the first liner film (182), and can be connected to the upper surface of the first silicide pattern (190).

[0092] The second source / drain contact (CA2) can be connected to the second silicide pattern (290). For example, the second source / drain contact (CA2) can extend in the sixth direction (Z2) to penetrate the interlayer insulating film (180) and the first liner film (182), and can be connected to the upper surface of the second silicide pattern (290).

[0093] In some embodiments, a second liner film (184) may be further formed on the interlayer insulating film (180) and the first liner film (182). The second liner film (184) may extend conformally along the profiles of the side of the first source / drain contact (CA1) and the side of the second source / drain contact (CA2). The first source / drain contact (CA1) and the second source / drain contact (CA2) may each penetrate the second liner film (184) to be connected to the first silicide pattern (190) and the second silicide pattern (290).

[0094] The second liner film (184) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide.

[0095] In some embodiments, the first source / drain contact (CA1) may include a first barrier metal film (194) and a first metal film (196) that are sequentially stacked on the first silicide pattern (190). In some embodiments, the second source / drain contact (CA2) may include a second barrier metal film (294) and a second metal film (296) that are sequentially stacked on the second silicide pattern (290).

[0096] A first barrier metal film (194) may be formed on a first silicide pattern (190). The first barrier metal film (194) may be conformally extended along the upper surface of the first silicide pattern (190) and the profile of the second liner film (184). A second barrier metal film (294) may be formed on a second silicide pattern (290). The second barrier metal film (294) may be conformally extended along the upper surface of the second silicide pattern (290) and the profile of the second liner film (184). The first barrier metal film (194) and the second barrier metal film (294) may each include a conductive metal nitride, such as titanium nitride, tantalum nitride, or tungsten nitride, but are not limited thereto. For example, the first barrier metal film (194) and the second barrier metal film (294) may each include titanium nitride (TiN).

[0097] A first metal film (196) may be formed on a first barrier metal film (194). The first metal film (196) may fill the area remaining after the first barrier metal film (194) is filled on the first silicide pattern (190). A second metal film (296) may be formed on a second barrier metal film (294). The second metal film (296) may fill the area remaining after the second barrier metal film (294) is filled on the second silicide pattern (290). The first metal film (196) and the second metal film (296) may each include a metallic material such as, for example, cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphorus (CoWP), but are not limited thereto. For example, the first metal film (196) and the second metal film (296) may each contain cobalt (Co).

[0098] To reduce contact resistance between the source / drain region and the source / drain contact, an epitaxial pattern including a deep trench (e.g., a first epitaxial trench (160t) or a second epitaxial trench (260t)) may be used. However, due to the formation of the deep trench, the stress induced by the epitaxial pattern may be reduced, and the channel resistance may increase. For example, when the channel of the PFET is a silicon pattern, a silicon germanium (SiGe) pattern having a larger lattice constant than silicon (Si) may be used as the source / drain region of the PFET. However, if a deep trench is formed within the silicon germanium pattern, the volume of the silicon germanium pattern is reduced, thereby reducing the compressive stress applied to the channel region (silicon pattern).

[0099] In a semiconductor device according to some embodiments, the performance of the semiconductor device can be improved by using a first epitaxial pattern (160) and a second epitaxial pattern (260) each having deep trenches, and using a first silicide pattern (190) and a second silicide pattern (290) having different stress characteristics.

[0100] Specifically, as described above, the first epitaxial pattern (160) provided as the source / drain region of the PFET may include a first epitaxial trench (160t) which is a deep trench, and the first silicide pattern (190) may fill at least a portion of the first epitaxial trench (160t). In this case, the first silicide pattern (190) may have relatively small tensile stress or compressive stress characteristics, so that the channel resistance can be improved by compensating for the volume reduction of the first epitaxial pattern (160) caused by the first epitaxial trench (160t). In particular, when the first silicide pattern (190) completely fills the first epitaxial trench (160t), the stress characteristics are maximized, and the channel resistance can be further improved. Through this, not only the contact resistance for the first epitaxial pattern (160) but also the channel resistance of the first active pattern (AP1) is improved, so that a semiconductor device with improved performance can be provided.

[0101] Additionally, as described above, in a semiconductor device according to some embodiments, a second epitaxial pattern (260) provided as a source / drain region of an NFET may include a second epitaxial trench (260t) which is a deep trench, and a second silicide pattern (290) may fill at least a portion of the second epitaxial trench (260t). In this case, since the second silicide pattern (290) may have relatively large tensile stress characteristics, the channel resistance may be improved by compensating for the volume reduction of the second epitaxial pattern (260) caused by the second epitaxial trench (260t). In particular, when the second silicide pattern (290) completely fills the second epitaxial trench (260t), the stress characteristics are maximized and the channel resistance may be further improved. Through this, not only the contact resistance for the second epitaxial pattern (260) but also the channel resistance of the second active pattern (AP2) is improved, so that a semiconductor device with improved performance can be provided.

[0102] FIGS. 5 and 6 are various other cross-sectional views taken along A1-A1 and A2-A2 of FIG. 1. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 4 are briefly explained or omitted.

[0103] Referring to FIG. 5, a semiconductor device according to some embodiments further includes an internal spacer (145).

[0104] An internal spacer (145) may be formed on the side of the first gate electrode (130) between the first to third bridge patterns (111 to 113). Additionally, an internal spacer (145) may also be formed on the side of the first gate electrode (130) between the first pin pattern (110) and the first bridge pattern (111). The first gate electrode (130) between the first to third bridge patterns (111 to 113) may be electrically isolated from the first epitaxial pattern (160) by the first gate dielectric film (120) and / or the internal spacer (145).

[0105] The internal spacer (145) may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and combinations thereof, but is not limited thereto. The internal spacer (145) may include the same material as the first gate spacer (140) or may include a different material from the first gate spacer (140). Only the thickness of the internal spacer (145) that is the same as the thickness of the first gate spacer (140) is shown, but this is merely exemplary.

[0106] Although the internal spacer (145) is shown only as being formed on the first region (I), this is merely exemplary, and the internal spacer (145) may be formed on both the first region (I) and the second region (II).

[0107] Referring to FIG. 6, in a semiconductor device according to some embodiments, the first silicide pattern (190) and / or the second silicide pattern (290) includes a deep trench.

[0108] For example, the thickness of the first silicide pattern (190) may be formed so as not to completely fill the first epitaxial trench (160t). This first silicide pattern (190) may include a first silicide trench (190t) within it. The first silicide trench (190t) may be defined by at least a portion of the upper surface of the first silicide pattern (190). The first silicide trench (190t) may extend in a second direction (Y1). For example, the first silicide pattern (190) may be 'U' shaped in the cross-section intersecting the second direction (Y1). In some embodiments, the first silicide trench (190t) may be a deep trench that overlaps the first to third bridge patterns (111–113) in the first direction (X1).

[0109] Alternatively, for example, the thickness of the second silicide pattern (290) may be formed so as not to completely fill the second epitaxial trench (260t). This second silicide pattern (290) may include a second silicide trench (290t) within it. The second silicide trench (290t) may be defined by at least a portion of the upper surface of the second silicide pattern (290). The second silicide trench (290t) may extend in a fifth direction (Y2). For example, the second silicide pattern (290) may be 'U' shaped in a cross-section intersecting the fifth direction (Y2). In some embodiments, the second silicide trench (290t) may be a deep trench that overlaps the fourth to sixth bridge patterns (211–213) in the fourth direction (X2).

[0110] The first source / drain contact (CA1) can fill the first silicide trench (190t). The lower portion of this first source / drain contact (CA1) can overlap with the first to third bridge patterns (111–113) in the first direction (X1). The second source / drain contact (CA2) can fill the second silicide trench (290t). The lower portion of this second source / drain contact (CA2) can overlap with the fourth to sixth bridge patterns (211–213) in the fourth direction (X2).

[0111] Although it is illustrated that both the first silicide pattern (190) and the second silicide pattern (290) include a deep trench, this is merely exemplary, and only one of the first silicide pattern (190) and the second silicide pattern (290) may include a deep trench. For example, the first silicide pattern (190) may include a first silicide trench (190t), and the second silicide pattern (290) may completely fill a second epitaxial trench (260t). As another example, the first silicide pattern (190) may completely fill a first epitaxial trench (160t), and the second silicide pattern (290) may include a second silicide trench (290t).

[0112] FIGS. 7 and 8 are various cross-sectional views for illustrating semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 6 are briefly described or omitted.

[0113] Referring to FIGS. 7 and FIGS. 8, a semiconductor device according to some embodiments further includes a front wiring structure (FS) and a rear wiring structure (BS).

[0114] A front wiring structure (FS) may be disposed on the front side of a substrate (100) where a first active pattern (AP1) and a second active pattern (AP2) are formed. For example, the front wiring structure (FS) may be formed on an interlayer insulating film (180). A rear wiring structure (BS) may be disposed on the back side of the substrate (100) opposite to the front side of the substrate (100).

[0115] The front wiring structure (FS) may include a front wiring inter-insulating film (510), a plurality of front wiring patterns (FM1 to FM3), and a plurality of front via patterns (FV1 to FV3). The front wiring patterns (FM1 to FM3) may be stacked sequentially on an inter-layer insulating film (180). The front via patterns (FV1 to FV3) may interconnect the front wiring patterns (FM1 to FM3). The front wiring patterns (FM1 to FM3) and the front via patterns (FV1 to FV3) may each be mutually insulated by the front wiring inter-insulating film (510). The number of layers, number, and arrangement of the front wiring inter-insulating film (510), front wiring patterns (FM1 to FM3), and front via patterns (FV1 to FV3) are merely exemplary and are not limited to those illustrated.

[0116] The front wiring structure (FS) can provide signal lines and / or power lines for various electronic devices (e.g., PFET on the first region (I) and / or NFET on the second region (II)) formed on the substrate (100). For example, a first front via pattern (FV1) of the front wiring structure (FS) can be connected to a first source / drain contact (CA1) and / or a second source / drain contact (CA2).

[0117] Although not specifically illustrated, the front wiring patterns (FM1 to FM3) and front via patterns (FV1 to FV3) may each include a barrier conductive film and a filling conductive film. The barrier conductive film may include a metal or a metal nitride to prevent diffusion of the filling conductive film. The barrier conductive film may include, for example, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof, but is not limited thereto. The filling conductive film may include, for example, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and alloys thereof, but is not limited thereto.

[0118] The rear wiring structure (BS) may include a rear wiring inter-insulating film (520), a plurality of rear wiring patterns (BM1, BM2), and a plurality of rear via patterns (BV1, BV2). The rear wiring patterns (BM1, BM2) may be stacked sequentially on the rear surface of the substrate (100). The rear via patterns (BV1, BV2) may interconnect the rear wiring patterns (BM1, BM2). The rear wiring patterns (BM1, BM2) and the rear via patterns (BV1, BV2) may each be mutually insulated by the rear wiring inter-insulating film (520). The number of layers, number, and arrangement of the rear wiring inter-insulating film (520), rear wiring patterns (BM1, BM2), and rear via patterns (BV1, BV2) are merely exemplary and are not limited to those illustrated.

[0119] In some embodiments, the back wiring structure (BS) may provide a Power Delivery Network (PDN) for various electronic devices formed on the substrate (100) (e.g., a PFET on the first region (I) and / or an NFET on the second region (II)). For example, a power supply voltage supplied from an external source (e.g., a source voltage (V) SS ) or drain voltage (V DD )) can be provided as a first epitaxial pattern (160) and / or a second epitaxial pattern (260) through a rear wiring structure (BS).

[0120] Although not specifically illustrated, the rear wiring patterns (BM1, BM2) and rear via patterns (BV1, BV2) may each include a barrier conductive film and a filling conductive film. The barrier conductive film may include a metal or a metal nitride to prevent diffusion of the filling conductive film. The barrier conductive film may include, for example, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof, but is not limited thereto. The filling conductive film may include, for example, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru), and alloys thereof, but is not limited thereto.

[0121] In some embodiments, a first lower contact (DC1) and a second lower contact (DC2) may be further formed. The first lower contact (DC1) may electrically connect the rear wiring structure (BS) and the first epitaxial pattern (160), and the second lower contact (DC2) may electrically connect the rear wiring structure (BS) and the second epitaxial pattern (260). A power supply voltage supplied from an external source (e.g., source voltage (V) SS ) or drain voltage (V DD)) can be provided as a first epitaxial pattern (160) through a rear wiring structure (BS) and a first lower contact (DC1), and can be provided as a second epitaxial pattern (260) through a rear wiring structure (BS) and a second lower contact (DC2).

[0122] For example, the first lower contact (DC1) may extend in a third direction (Z1) and penetrate the substrate (100) and the rear insulating film (102). The first lower contact (DC1) may electrically connect the power rail (BR) of the rear wiring structure (BS) and the first epitaxial pattern (160). For example, as shown in FIG. 7, the first lower contact (DC1) may penetrate the substrate (100) and the first epitaxial pattern (160) and be connected to the lower surface of the first silicide pattern (190). As another example, as shown in FIG. 8, the first lower contact (DC1) may penetrate the substrate (100) and the first epitaxial pattern (160) and fill the first silicide trench (190t).

[0123] Additionally, for example, the second lower contact (DC2) may extend in the sixth direction (Z2) and penetrate the substrate (100) and the rear insulating film (102). The second lower contact (DC2) may electrically connect the power rail (BR) of the rear wiring structure (BS) and the second epitaxial pattern (260). For example, as shown in FIG. 7, the second lower contact (DC2) may penetrate the substrate (100) and the second epitaxial pattern (260) to be connected to the second silicide pattern (290). As another example, as shown in FIG. 8, the second lower contact (DC2) may penetrate the substrate (100) and the second epitaxial pattern (260) to fill the second silicide trench (290t).

[0124] In some embodiments, a first contact spacer (550) may be formed extending along the side of a first lower contact (DC1). The first contact spacer (550) may electrically separate the first lower contact (DC1) from the substrate (100). In some embodiments, a second contact spacer (560) may be formed extending along the side of a second lower contact (DC2). The second contact spacer (560) may electrically separate the second lower contact (DC2) from the substrate (100). The first contact spacer (550) and the second contact spacer (560) may each comprise an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but are not limited thereto.

[0125] In some embodiments, the first lower contact (DC1) may include a third barrier metal film (554) and a third metal film (556) that are sequentially stacked on the first silicide pattern (190). In some embodiments, the second lower contact (DC2) may include a fourth barrier metal film (564) and a fourth metal film (566) that are sequentially stacked on the second silicide pattern (290).

[0126] The third barrier metal film (554) and the fourth barrier metal film (564) may each include a conductive metal nitride such as titanium nitride, tantalum nitride, or tungsten nitride, but are not limited thereto. For example, the third barrier metal film (554) and the fourth barrier metal film (564) may each include titanium nitride (TiN).

[0127] The third metal film (556) and the fourth metal film (3666) may each include a metallic material such as, for example, cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphorus (CoWP), but are not limited thereto. For example, the third metal film (556) and the fourth metal film (3666) may each include cobalt (Co).

[0128] FIG. 9 is a perspective view illustrating a semiconductor device according to some embodiments. FIG. 10 is a cross-sectional view taken along C1-C1 and C2-C2 of FIG. 9. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 8 are briefly described or omitted.

[0129] Referring to FIG. 9 and FIG. 10, in a semiconductor device according to some embodiments, the size (width and height) of the first epitaxial pattern (160) is smaller than the first active pattern (AP1), or the size (width and height) of the second epitaxial pattern (260) is smaller than the second active pattern (AP2).

[0130] For example, the width of the second direction (Y1) of the first epitaxial pattern (160) (W12 in FIG. 9) may be smaller than the width of the first active pattern (AP1) (W11 in FIG. 9). Additionally, the height of the top of the first epitaxial pattern (160) may be lower than the top surface of the top bridge pattern (e.g., the third bridge pattern (113)). In some embodiments, the first inclined surface (160s) may extend from a position higher than the top surface of the top bridge pattern (e.g., the third bridge pattern (113)).

[0131] Alternatively, for example, the width of the fifth direction (Y2) of the second epitaxial pattern (260) (W22 in FIG. 9) may be smaller than the width of the second active pattern (AP2) (W21 in FIG. 9). Additionally, the height of the top of the second epitaxial pattern (260) may be lower than the top surface of the top bridge pattern (e.g., the sixth bridge pattern (213)). In some embodiments, the second inclined surface (260s) may extend from a position higher than the top surface of the top bridge pattern (e.g., the sixth bridge pattern (213)).

[0132] Only cases where the size of the first epitaxial pattern (160) and the size of the second epitaxial pattern (260) are both smaller than the first active pattern (AP1) and the second active pattern (AP2) are illustrated, but this is merely illustrative. As another example, only the size of the first epitaxial pattern (160) may be smaller than the first active pattern (AP1), or only the size of the second epitaxial pattern (260) may be smaller than the second active pattern (AP2).

[0133] FIG. 11 is a perspective view illustrating a semiconductor device according to some embodiments. FIG. 12 is a cross-sectional view taken along D1-D1 and D2-D2 of FIG. 11. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 8 are briefly described or omitted.

[0134] Referring to FIGS. 11 and 12, a semiconductor device according to some embodiments further includes a first blocking film (162) or a second blocking film (262).

[0135] A first blocking film (162) may be interposed between a first epitaxial pattern (160) and a first silicide pattern (190). The first blocking film (162) may surround the outer surface of the first epitaxial pattern (160). The first silicide pattern (190) may surround the outer surface of the first blocking film (162). For example, as illustrated in FIG. 11, the first blocking film (162) may cover the side and top surfaces of the first epitaxial pattern (160), and the first silicide pattern (190) may cover the side and top surfaces of the first blocking film (162). In some embodiments, the first blocking film (162) may include an epitaxial layer grown from the first epitaxial pattern (160) by an epitaxial growth method. The thickness of the first blocking film (162) may be, for example, about 1 nm to about 5 nm, but is not limited thereto.

[0136] A second blocking film (262) may be interposed between the second epitaxial pattern (260) and the second silicide pattern (290). The second blocking film (262) may surround the outer surface of the second epitaxial pattern (260). The second silicide pattern (290) may surround the outer surface of the second blocking film (262). For example, as illustrated in FIG. 11, the second blocking film (262) may cover the side and top surfaces of the second epitaxial pattern (260), and the second silicide pattern (290) may cover the side and top surfaces of the second blocking film (262). In some embodiments, the second blocking film (262) may include an epitaxial layer grown from the second epitaxial pattern (260) by an epitaxial growth method. The thickness of the second blocking film (262) may be, for example, about 1 nm to about 5 nm, but is not limited thereto.

[0137] In some embodiments, the first blocking film (162) and the second blocking film (262) may each comprise silicon (Si). In some embodiments, the first blocking film (162) may further comprise the first impurity. For example, the first blocking film (162) may comprise a silicon film doped with the first impurity (e.g., boron (B), indium (In), gallium (Ga) and / or aluminum (Al)). In some embodiments, the second blocking film (262) may further comprise the second impurity. For example, the second blocking film (262) may comprise a silicon film doped with the second impurity (e.g., phosphorus (P), arsenic (As) and / or antimony (Sb)).

[0138] Although it is shown that both the first blocking film (162) and the second blocking film (262) are formed, this is merely illustrative, and one of the first blocking film (162) and the second blocking film (262) may be omitted.

[0139] FIG. 13 is a perspective view illustrating a semiconductor device according to some embodiments. FIG. 14 is a cross-sectional view taken along E1-E1 and E2-E2 of FIG. 13. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 8 are briefly described or omitted.

[0140] Referring to FIG. 13 and FIG. 14, in a semiconductor device according to some embodiments, a portion of the first source / drain contact (CA1) is interposed between the first silicide pattern (190) and the first liner film (182), or a portion of the second source / drain contact (CA2) is interposed between the second silicide pattern (290) and the first liner film (182).

[0141] For example, the lower portion of the first source / drain contact (CA1) may cover a portion of the side and / or upper surface of the first silicide pattern (190). The first liner film (182) may extend conformally along the surface of the first silicide pattern (190) and the surface of the lower portion of the first source / drain contact (CA1).

[0142] Alternatively, for example, the lower portion of the second source / drain contact (CA2) may cover a portion of the side and / or upper surface of the second silicide pattern (290). The first liner film (182) may extend conformally along the surface of the second silicide pattern (290) and the surface of the lower portion of the second source / drain contact (CA2).

[0143] Although it is illustrated that the first source / drain contact (CA1) is interposed between the first silicide pattern (190) and the first liner film (182), and the second source / drain contact (CA2) is interposed between the second silicide pattern (290) and the first liner film (182), this is merely illustrative. As another example, the first source / drain contact (CA1) may not be interposed between the first silicide pattern (190) and the first liner film (182), or the second source / drain contact (CA2) may not be interposed between the second silicide pattern (290) and the first liner film (182).

[0144] Hereinafter, a method for manufacturing a semiconductor device according to exemplary embodiments will be described with reference to FIGS. 1 to 36.

[0145] FIGS. 15 to 36 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 14 are briefly explained or omitted.

[0146] Referring to FIG. 15, a first active pattern (AP1), a first sacrifice pattern (310), a first dummy gate structure (DG1), and a first gate spacer (140) are formed on a first region (I) of a substrate (100), and a second active pattern (AP2), a second sacrifice pattern (410), a second dummy gate structure (DG2), and a second gate spacer (240) are formed on a second region (II) of the substrate (100).

[0147] For example, a first material film and a second material film may be formed by alternately stacking on a first region (I) and a second region (II) of a substrate (100). Subsequently, a patterning process for patterning the first material film and the second material film may be performed.

[0148] The first material film patterned in the first region (I) can form a first sacrificial pattern (310), and the second material film patterned in the first region (I) can form first to third bridge patterns (111 to 113) that are alternately stacked with the first sacrificial pattern (310). Additionally, the first material film patterned in the second region (II) can form a second sacrificial pattern (410), and the second material film patterned in the second region (II) can form fourth to sixth bridge patterns (211 to 213) that are alternately stacked with the second sacrificial pattern (410).

[0149] The sacrifice patterns (310, 410) may have an etching selectivity with respect to the bridge patterns (111–113, 211–213). For example, the bridge patterns (111–113, 211–213) may each include silicon (Si), and the sacrifice patterns (310, 410) may each include silicon germanium (SiGe).

[0150] In some embodiments, during the process of patterning the first material film and the second material film, a portion of the substrate (100) may be etched to form a first pin pattern (110) and a second pin pattern (210). Subsequently, a field insulating film (105) may be formed on the substrate (100). The field insulating film (105) may cover at least a portion of the side of the first pin pattern (110) and at least a portion of the side of the second pin pattern (210).

[0151] Next, a first dummy gate structure (DG1) may be formed on the first active pattern (AP1) and the first sacrifice pattern (310), and a second dummy gate structure (DG2) may be formed on the second active pattern (AP2) and the second sacrifice pattern (410).

[0152] The first dummy gate structure (DG1) and the second dummy gate structure (DG2) may each extend along the upper surface of the substrate (100) and the upper surface of the field insulating film (105). The first dummy gate structure (DG1) may intersect with the first active pattern (AP1). For example, the first dummy gate structure (DG1) may extend in the second direction (Y1). The second dummy gate structure (DG2) may intersect with the second active pattern (AP2). For example, the second dummy gate structure (DG2) may extend in the fifth direction (Y2).

[0153] In some embodiments, the first dummy gate structure (DG1) may include a first dummy gate dielectric film (320) and a first dummy gate electrode (330), and the second dummy gate structure (DG2) may include a second dummy gate dielectric film (420) and a second dummy gate electrode (430). For example, a dielectric film and an electrode film may be formed by sequentially stacking on a substrate (100) and a field insulating film (105). Subsequently, a first mask pattern (350) extending in a second direction (Y1) may be formed on the electrode film on a first region (I). Additionally, a second mask pattern (450) extending in a fifth direction (Y2) may be formed on the electrode film on a second region (II). Subsequently, a patterning process may be performed to pattern the dielectric film and the electrode film using the first mask pattern (350) and the second mask pattern (450) as etching masks. The dielectric film patterned in the first region (I) can form a first dummy gate dielectric film (320), and the electrode film patterned in the first region (I) can form a first dummy gate electrode (330). Additionally, the dielectric film patterned in the second region (II) can form a second dummy gate dielectric film (420), and the electrode film patterned in the second region (II) can form a second dummy gate electrode (430).

[0154] The first dummy gate structure (DG1) and the second dummy gate structure (DG2) may have different etching selectivity ratios with respect to the bridge patterns (111–113, 211–213) and the sacrifice patterns (310, 410). For example, the first dummy gate electrode (330) and the second dummy gate electrode (430) may each comprise polysilicon (poly Si).

[0155] Subsequently, a first gate spacer (140) and a second gate spacer (240) may be formed. The first gate spacer (140) may be formed on the substrate (100) and the field insulating film (105). The first gate spacer (140) may extend along the side of the first dummy gate structure (DG1). The second gate spacer (240) may be formed on the substrate (100) and the field insulating film (105). The second gate spacer (240) may extend along the side of the second dummy gate structure (DG2).

[0156] Referring to FIG. 16, a first recess process is performed on the first active pattern (AP1) and the first sacrifice pattern (310).

[0157] As the above first recess process is performed, a portion of the first to third bridge patterns (111 to 113) and a portion of the first sacrifice pattern (310) disposed on the outside of the first dummy gate structure (DG1) may be removed to form a first recess (110r). In some embodiments, the upper portion of the first pin pattern (110) may be removed during the process of forming the first recess (110r).

[0158] In some embodiments, after the first recess (110r) is formed, a recess process for the first sacrifice pattern (310) may be additionally performed. Subsequently, an insulating film may be formed to fill the area of ​​the recessed first sacrifice pattern (310). Through this, an internal spacer (145 in FIG. 5) may be formed on the first area (I).

[0159] Referring to FIGS. 16 and 17, a first epitaxial pattern (160) is formed within a first recess (110r).

[0160] The first epitaxial pattern (160) can fill a portion of the first recess (110r). The first epitaxial pattern (160) can be formed by an epitaxial growth method using the first active pattern (AP1) as a seed layer. Through this, the first epitaxial pattern (160) connected to the first active pattern (AP1) can be formed.

[0161] The first epitaxial pattern (160) may include a first epitaxial trench (160t). For example, the thickness of the first epitaxial pattern (160) may be formed so as not to completely fill the first recess (110r). Through this, the first epitaxial pattern (160) having a 'U' shape in the cross-section intersecting the second direction (Y1) may be formed.

[0162] Referring to FIG. 18, a first blocking film (162) and a first sacrificial epitaxial pattern (164) are formed on a first epitaxial pattern (160).

[0163] The first blocking film (162) can surround the outer surface of the first epitaxial pattern (160). The first blocking film (162) can be formed by an epitaxial growth method using the first epitaxial pattern (160) as a seed layer.

[0164] The first sacrificial epitaxial pattern (164) may surround the outer surface of the first blocking membrane (162). The first sacrificial epitaxial pattern (164) may be formed by an epitaxial growth method using the first blocking membrane (162) as a seed layer. The first sacrificial epitaxial pattern (164) is illustrated as being pentagonal in the cross-section intersecting the first direction (X1), but this is merely illustrative. Of course, depending on the epitaxial growth conditions, the cross-section of the first sacrificial epitaxial pattern (164) may vary.

[0165] The first sacrificial epitaxial pattern (164) may have an etching selectivity with respect to the first blocking film (162). For example, the first blocking film (162) may include silicon (Si), and the first sacrificial epitaxial pattern (164) may include silicon germanium (SiGe).

[0166] Referring to FIG. 19, a second recess process is performed on the second active pattern (AP2) and the second sacrifice pattern (410).

[0167] As the above second recess process is performed, a portion of the fourth to sixth bridge patterns (211 to 213) and a portion of the second sacrifice pattern (410) disposed on the outside of the second dummy gate structure (DG2) may be removed to form a second recess (210r). In some embodiments, the upper portion of the second pin pattern (210) may be removed during the process of forming the second recess (210r).

[0168] Referring to FIGS. 19 and 20, a second epitaxial pattern (260) is formed within the second recess (210r).

[0169] The second epitaxial pattern (260) can fill a portion of the second recess (210r). The second epitaxial pattern (260) can be formed by an epitaxial growth method using the second active pattern (AP2) as a seed layer. Through this, the second epitaxial pattern (260) connected to the second active pattern (AP2) can be formed.

[0170] The second epitaxial pattern (260) may include a second epitaxial trench (260t). For example, the thickness of the second epitaxial pattern (260) may be formed so as not to completely fill the second recess (210r). Through this, a second epitaxial pattern (260) having a 'U' shape may be formed in the cross-section intersecting the fifth direction (Y2).

[0171] Referring to FIG. 21, a second blocking film (262) and a second sacrificial epitaxial pattern (264) are formed on the second epitaxial pattern (260).

[0172] The second blocking film (262) can surround the outer surface of the second epitaxial pattern (260). The second blocking film (262) can be formed by an epitaxial growth method using the second epitaxial pattern (260) as a seed layer.

[0173] The second sacrificial epitaxial pattern (264) may surround the outer surface of the second blocking membrane (262). The second sacrificial epitaxial pattern (264) may be formed by an epitaxial growth method using the second blocking membrane (262) as a seed layer. The second sacrificial epitaxial pattern (264) is illustrated as being pentagonal in the cross-section intersecting the fourth direction (X2), but this is merely illustrative. Of course, depending on the epitaxial growth conditions, the cross-section of the second sacrificial epitaxial pattern (264) may vary.

[0174] The second sacrificial epitaxial pattern (264) may have an etch selectivity with respect to the second blocking film (262). For example, the second blocking film (262) may include silicon (Si), and the second sacrificial epitaxial pattern (264) may include silicon germanium (SiGe).

[0175] Referring to FIG. 22, a first liner film (182) and an interlayer insulating film (180) are formed.

[0176] The first liner film (182) may be conformally extended along the profile of the surface of the first sacrificial epitaxial pattern (164) and the surface of the second sacrificial epitaxial pattern (264). The first liner film (182) may be further extended along the upper surface of the field insulating film (105), the outer surface of the first gate spacer (140), and the outer surface of the second gate spacer (240). An interlayer insulating film (180) may be formed on the first liner film (182).

[0177] Referring to FIGS. 22 and 23, the first dummy gate structure (DG1) and the second dummy gate structure (DG2) are removed.

[0178] As described above, since the first dummy gate structure (DG1) and the second dummy gate structure (DG2) may have different etching selectivity than the bridge patterns (111–113, 211–213) and sacrifice patterns (310, 410), the first dummy gate structure (DG1) and the second dummy gate structure (DG2) may be selectively removed. As the first dummy gate structure (DG1) is removed, the first active pattern (AP1) and the first sacrifice pattern (310) disposed inside the first gate spacer (140) may be exposed. Additionally, as the second dummy gate structure (DG2) is removed, the second active pattern (AP2) and the second sacrifice pattern (410) disposed inside the second gate spacer (240) may be exposed.

[0179] Referring to FIGS. 23 and 24, the first sacrifice pattern (310) and the second sacrifice pattern (410) are removed.

[0180] As described above, since the bridge patterns (111–113, 211–213) and the sacrifice patterns (310, 410) may have different etching selectivity ratios, the first sacrifice pattern (310) and the second sacrifice pattern (410) may be selectively removed. As the first sacrifice pattern (310) and the second sacrifice pattern (410) are removed, first to third bridge patterns (111–113) spaced apart from each other may be formed on the first region (I) of the substrate (100), and fourth to sixth bridge patterns (211–213) spaced apart from each other may be formed on the second region (II) of the substrate (100).

[0181] Referring to FIGS. 25 and 26, a first gate structure (GS1) and a second gate structure (GS2) are formed. For reference, FIG. 26 is a cross-sectional view taken along A1-A1 and A2-A2 of FIG. 25.

[0182] For example, a first gate dielectric film (120) and a first gate electrode (130) may be stacked sequentially on a first active pattern (AP1), and a second gate dielectric film (220) and a second gate electrode (230) may be stacked sequentially on a second active pattern (AP2). Subsequently, a first gate capping pattern (150) may be formed on the first gate electrode (130), and a second gate capping pattern (250) may be formed on the second gate electrode (230). In some embodiments, the first gate capping pattern (150) and the second gate capping pattern (250) may be formed after an etch-back process is performed on the first gate electrode (130) and the second gate electrode (230).

[0183] Referring to FIG. 27, a first contact hole (180h1) and a second contact hole (180h2) are formed within the interlayer insulating film (180).

[0184] The first contact hole (180h1) can be extended in the third direction (Z1) to penetrate the interlayer insulating film (180). Additionally, the first contact hole (180h1) can penetrate the first liner film (182) to expose the first sacrificial epitaxial pattern (164). The second contact hole (180h2) can be extended in the sixth direction (Z2) to penetrate the interlayer insulating film (180). Additionally, the second contact hole (180h2) can penetrate the first liner film (182) to expose the second sacrificial epitaxial pattern (264).

[0185] Referring to FIG. 28, a first sacrificial blocking membrane (362) is formed.

[0186] The first sacrificial blocking film (362) may cover the first sacrificial epitaxial pattern (164) and the second sacrificial epitaxial pattern (264). For example, the first sacrificial blocking film (362) may extend conformally along the profiles of the first contact hole (180h1) and the second contact hole (180h2). The first sacrificial blocking film (362) may include, for example, a silicon nitride film, but is not limited thereto.

[0187] Referring to FIG. 29, the first sacrificial epitaxial pattern (164) is removed.

[0188] For example, a first mask film (372) may be formed that exposes the first sacrificial blocking film (362) on the first region (I) and covers the first sacrificial blocking film (362) on the second region (II). That is, the first mask film (372) may open the first region (I). The first mask film (372) may include, for example, a spin-on hardmask (SOH), but is not limited thereto.

[0189] Subsequently, an etching process may be performed to remove the first sacrificial epitaxial pattern (164) by penetrating the first sacrificial blocking film (362) on the first region (I). As described above, since the first sacrificial epitaxial pattern (164) may have an etching selectivity ratio with respect to the first blocking film (162), the first sacrificial epitaxial pattern (164) may be selectively removed. The etching process may include, for example, a dry etching process or a wet etching process, but is not limited thereto.

[0190] Referring to FIG. 30, a first doping process (DP1) is performed on a first epitaxial pattern (160) and / or a first blocking film (162).

[0191] The first doping process (DP1) may dope the first impurity (e.g., boron (B), indium (In), gallium (Ga) and / or aluminum (Al)) into the first epitaxial pattern (160) and / or the first blocking film (162). The first doping process (DP1) may include, for example, plasma doping (PLAD), but is not limited thereto. As the first doping process (DP1) is performed on the upper surface of the first blocking film (162), the concentration of the first impurity in the first epitaxial pattern (160) may decrease as it moves away from the first blocking film (162).

[0192] Referring to FIG. 31, a first silicide pattern (190) is formed on a first epitaxial pattern (160).

[0193] For example, the first mask layer (372) may be removed. Subsequently, a first silicide pattern (190) may be formed to fill at least a portion of the area from which the first sacrificial epitaxial pattern (164) was removed. Since the second sacrificial epitaxial pattern (264) is protected by the first sacrificial blocking layer (362), the first silicide pattern (190) may be optionally formed on the first blocking layer (162). The first silicide pattern (190) may fill at least a portion of the first epitaxial trench (160t). In some embodiments, the first silicide pattern (190) may completely fill the first epitaxial trench (160t) of the first epitaxial pattern (160).

[0194] The first silicide pattern (190) can be formed through various silicide processes.

[0195] In some embodiments, a metal film may be formed on the first blocking film (162), and an element included in the metal film may react with the first blocking film (162) and / or the first epitaxial pattern (160) to form a first silicide pattern (190). In FIG. 31, only the first blocking film (162) is shown as being entirely silicided and the first epitaxial pattern (160) as not being silicided is illustrated, but this is merely exemplary. As another example, the upper part of the first epitaxial pattern (160) as well as the first blocking film (162) may be silicided. In such a case, as described above in the description relating to FIG. 9 and FIG. 10, the size of the first epitaxial pattern (160) may be smaller than the first active pattern (AP1). As another example, only a portion of the first blocking film (162) may be silicided. In this case, the first blocking film (162) may be interposed between the first epitaxial pattern (160) and the first silicide pattern (190), as described above in the description relating to FIGS. 11 and 12.

[0196] In some embodiments, the first silicide pattern (190) may be formed by a chemical vapor deposition method using a metal element. In some embodiments, the first silicide pattern (190) may be formed on the first blocking film (162). In this way, the first blocking film (162) may be interposed between the first epitaxial pattern (160) and the first silicide pattern (190), as described above in the description relating to FIGS. 11 and 12.

[0197] Referring to FIG. 32, the first sacrificial blocking membrane (362) is removed and the second sacrificial blocking membrane (364) is formed.

[0198] The second sacrificial blocking film (364) may cover the first silicide pattern (190). For example, the second sacrificial blocking film (364) may extend conformally along the profile of the upper surface of the first silicide pattern (190). The second sacrificial blocking film (364) may include, for example, a silicon nitride film, but is not limited thereto.

[0199] Referring to FIG. 33, the second sacrificial epitaxial pattern (264) is removed.

[0200] For example, a second mask film (374) may be formed that exposes the second sacrificial blocking film (364) on the second region (II) and covers the second sacrificial blocking film (364) on the first region (I). That is, the second mask film (374) may open the second region (II). The second mask film (374) may include, for example, a spin-on hardmask (SOH), but is not limited thereto.

[0201] Subsequently, an etching process may be performed to remove the second sacrificial epitaxial pattern (264) by penetrating the second sacrificial blocking film (364) on the second region (II). As described above, since the second sacrificial epitaxial pattern (264) may have an etching selectivity ratio with respect to the second blocking film (262), the second sacrificial epitaxial pattern (264) may be selectively removed. The etching process may include, for example, a dry etching process or a wet etching process, but is not limited thereto.

[0202] Referring to FIG. 34, a second doping process (DP2) is performed on the second epitaxial pattern (260) and / or the second blocking film (262).

[0203] The second doping process (DP2) may dope the second impurity (e.g., phosphorus (P), arsenic (As), and / or antimony (Sb)) into the second epitaxial pattern (260) and / or the second blocking film (262). The second doping process (DP2) may include, for example, plasma doping (PLAD), but is not limited thereto. As the second doping process (DP2) is performed on the upper surface of the second blocking film (262), the concentration of the second impurity in the second epitaxial pattern (260) may decrease as it moves away from the second blocking film (262).

[0204] Referring to FIG. 35, a second silicide pattern (290) is formed on the second epitaxial pattern (260).

[0205] For example, the second mask layer (374) may be removed. Subsequently, a second silicide pattern (290) may be formed to fill at least a portion of the area from which the second sacrificial epitaxial pattern (264) was removed. Since the first silicide pattern (190) is protected by the second sacrificial blocking layer (364), the second silicide pattern (290) may be optionally formed on the second blocking layer (262). The second silicide pattern (290) may fill at least a portion of the second epitaxial trench (260t). In some embodiments, the second silicide pattern (290) may completely fill the second epitaxial trench (260t) of the second epitaxial pattern (260).

[0206] The second silicide pattern (290) can be formed through various silicide processes.

[0207] In some embodiments, a metal film may be formed on the second blocking film (262), and an element included in the metal film may react with the second blocking film (262) and / or the second epitaxial pattern (260) to form a second silicide pattern (290). In FIG. 35, only the second blocking film (262) is shown as being entirely silicided and the second epitaxial pattern (260) as not being silicided is illustrated, but this is merely illustrative. As another example, the upper part of the second epitaxial pattern (260) as well as the second blocking film (262) may be silicided. In this case, as described above in the description relating to FIG. 9 and FIG. 10, the size of the second epitaxial pattern (260) may be smaller than the second active pattern (AP2). As another example, only a portion of the second blocking film (262) may be silicided. In this case, as described above in the description relating to FIGS. 11 and 12, the second blocking film (262) may be interposed between the second epitaxial pattern (260) and the second silicide pattern (290).

[0208] In some embodiments, the second silicide pattern (290) may be formed by a chemical vapor deposition method using a metal element. In some embodiments, the second silicide pattern (290) may be formed on the second blocking film (262). In this way, the second blocking film (262) may be interposed between the second epitaxial pattern (260) and the second silicide pattern (290), as described above in the description relating to FIGS. 11 and 12.

[0209] Referring to FIG. 36, the second sacrificial blocking membrane (364) is removed.

[0210] As the second sacrificial blocking film (364) is removed, the first silicide pattern (190) may be exposed by the first contact hole (180h1). Additionally, as the second sacrificial blocking film (364) is removed, the second silicide pattern (290) may be exposed by the second contact hole (180h2).

[0211] Next, referring to FIGS. 1 and 2, a first source / drain contact (CA1) is formed in a first contact hole (180h1), and a second source / drain contact (CA2) is formed in a second contact hole (180h2). Through this, a first source / drain contact (CA1) connected to a first silicide pattern (190) and a second source / drain contact (CA2) connected to a second silicide pattern (290) can be formed.

[0212] In some embodiments, the first silicide pattern (190) may not completely fill the area where the first sacrificial epitaxial pattern (164) has been removed. In such cases, as described above in the description relating to FIGS. 13 and 14, a portion of the first source / drain contact (CA1) may be interposed between the first silicide pattern (190) and the first liner film (182).

[0213] In some embodiments, the second silicide pattern (290) may not completely fill the area where the second sacrificial epitaxial pattern (264) has been removed. In such cases, as described above in the description relating to FIGS. 13 and 14, a portion of the second source / drain contact (CA2) may be interposed between the second silicide pattern (290) and the first liner film (182).

[0214] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0215] 100: Substrate 105: Field insulating film 110: First pin pattern 111~113: First to third bridge patterns 122: First interface 124: First dielectric film 130: First gate electrode 140: First gate spacer 150: 1st gate capping pattern 160: 1st epitaxial pattern 180: Interlayer insulating film 182: First liner film 184: Second liner film 190: First silicide pattern 210: Second pin pattern 211~213: Fourth to sixth bridge patterns 222: Second interface 224: Second dielectric film 230: Second gate electrode 240: Second gate spacer 250: Second gate capping pattern 260: Second epitaxial pattern 290: Second Silicide Pattern AP1: First active pattern AP2: Second active pattern CA1: 1st Source / Drain Contact CA2: 2nd Source / Drain Contact GS1: 1st gate structure GS2: 2nd gate structure

Claims

Claim 1 A substrate comprising a first region and a second region; a plurality of first bridge patterns sequentially stacked on the first region and spaced apart from each other, each extending in a first direction; a first gate structure extending in a second direction intersecting the first direction and penetrating by the plurality of first bridge patterns; a first epitaxial pattern on a side of the first gate structure connected to the plurality of first bridge patterns, comprising a first impurity having a first conductivity type and including a first epitaxial trench; a first silicide pattern filling at least a portion of the first epitaxial trench and overlapping with the plurality of first bridge patterns in the first direction; a plurality of second bridge patterns sequentially stacked on the second region and spaced apart from each other, each extending in a third direction; a second gate structure extending in a fourth direction intersecting the third direction and penetrating by the plurality of second bridge patterns; and a second impurity having a second conductivity type different from the first conductivity type, connected to the plurality of second bridge patterns on a side of the second gate structure A semiconductor device comprising: a second epitaxial pattern including a second epitaxial trench; and a second silicide pattern filling at least a portion of the second epitaxial trench and overlapping with the plurality of second bridge patterns in the third direction, wherein the first silicide pattern and the second silicide pattern have different stress characteristics. Claim 2 A semiconductor device according to claim 1, wherein the first conductivity type is p-type, the second conductivity type is n-type, and the second silicide pattern has a tensile stress characteristic greater than that of the first silicide pattern. Claim 3 A semiconductor device according to claim 2, wherein the first silicide pattern has compressive stress characteristics and the second silicide pattern has tensile stress characteristics. Claim 4 A semiconductor device according to claim 1, wherein the first silicide pattern covers the upper surface of the first epitaxial pattern and the second silicide pattern covers the upper surface of the second epitaxial pattern. Claim 5 A semiconductor device according to claim 1, further comprising a blocking film interposed between at least one of the first epitaxial pattern and the first silicide pattern and between the second epitaxial pattern and the second silicide pattern. Claim 6 In claim 5, the blocking film comprises silicon (Si), forming a semiconductor device. Claim 7 A semiconductor device according to claim 1, further comprising: a first source / drain contact connected to an upper surface of the first silicide pattern on the first silicide pattern; and a second source / drain contact connected to an upper surface of the second silicide pattern on the second silicide pattern. Claim 8 A semiconductor device according to claim 1, wherein the concentration of the first impurity decreases as it moves away from the first silicide pattern, and the concentration of the second impurity decreases as it moves away from the second silicide pattern. Claim 9 A substrate comprising a first region and a second region; a plurality of first bridge patterns sequentially stacked on the first region and spaced apart from each other, each extending in a first direction; a first gate structure extending in a second direction intersecting the first direction and penetrating by the plurality of first bridge patterns; a first epitaxial pattern on a side of the first gate structure connected to the plurality of first bridge patterns and comprising a first impurity having a first conductivity type; a first silicide pattern surrounding the first epitaxial pattern; a plurality of second bridge patterns sequentially stacked on the second region and spaced apart from each other, each extending in a third direction; a second gate structure extending in a fourth direction intersecting the third direction and penetrating by the plurality of second bridge patterns; a second epitaxial pattern on a side of the second gate structure connected to the plurality of second bridge patterns and comprising a second impurity having a second conductivity type different from the first conductivity type; A semiconductor device comprising a second silicide pattern surrounding the second epitaxial pattern, wherein the first epitaxial pattern comprises a first epitaxial trench that overlaps with the plurality of first bridge patterns in the first direction, the first silicide pattern completely fills the first epitaxial trench, the second epitaxial pattern comprises a second epitaxial trench that overlaps with the plurality of second bridge patterns in the third direction, the second silicide pattern completely fills the second epitaxial trench, and the first silicide pattern and the second silicide pattern have different stress characteristics. Claim 10 A substrate comprising a PFET region and an NFET region; a plurality of first bridge patterns sequentially stacked on the PFET region and spaced apart from each other, each extending in a first direction; a first gate structure extending in a second direction intersecting the first direction and penetrating by the plurality of first bridge patterns; a first epitaxial pattern on a side of the first gate structure connected to the plurality of first bridge patterns, containing p-type impurities, and including a first epitaxial trench; a first silicide pattern filling at least a portion of the first epitaxial trench and overlapping with the plurality of first bridge patterns in the first direction; a plurality of second bridge patterns sequentially stacked on the NFET region and spaced apart from each other, each extending in a third direction; a second gate structure extending in a fourth direction intersecting the third direction and penetrating by the plurality of second bridge patterns; and a second epitaxial trench on a side of the second gate structure connected to the plurality of second bridge patterns, containing n-type impurities, and including a second epitaxial trench. A semiconductor device comprising: a second epitaxial pattern; and a second silicide pattern that fills at least a portion of the second epitaxial trench and overlaps the plurality of second bridge patterns in the third direction, wherein the second silicide pattern has a greater tensile stress characteristic than the first silicide pattern, the concentration of the p-type impurity in the first epitaxial pattern decreases as it moves away from the first silicide pattern, and the concentration of the n-type impurity in the second epitaxial pattern decreases as it moves away from the second silicide pattern.

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