Semiconductor device

Abstract

The present invention provides a semiconductor device capable of improving device performance and reliability. The semiconductor device comprises a back interlayer insulating film, a back wiring line having a line shape disposed within the back interlayer insulating film and including a first surface and a second surface opposite in a first direction, a pin-shaped pattern disposed on the first surface of the back wiring line and extending in a second direction, a field insulating film disposed on the sidewall of the pin-shaped pattern, a source / drain pattern on the pin-shaped pattern, a source / drain contact disposed on the source / drain pattern and connected to the source / drain pattern, and a contact connection via connecting the back wiring line and the source / drain contact and contacting the back wiring line, wherein the contact connection via includes a first surface connected to the source / drain contact and a second surface contacting the back wiring line, and the height from the second surface of the back wiring line to the upper surface of the field insulating film is smaller than the height from the second surface of the back wiring line to the first surface of the contact connection via.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0002] As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed.

[0004] Meanwhile, as the pitch size of a semiconductor device decreases, research is needed to reduce capacitance and ensure electrical stability between contacts within the semiconductor device. Patent Document 1 discloses a back power supply network (BSPDN) including a power rail that supplies power to a semiconductor device. Prior art literature

[65535] U.S. Patent Publication US 2022-0230947 A1 (Published July 21, 2022) The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a semiconductor device capable of improving device performance and reliability.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] One aspect of the semiconductor device of the present invention for solving the above problem comprises a rear interlayer insulating film, a rear wiring line disposed within the rear interlayer insulating film and having a line shape including a first surface and a second surface opposite in a first direction, a pin-shaped pattern disposed on the first surface of the rear wiring line and extending in a second direction, a field insulating film disposed on the sidewall of the pin-shaped pattern, a source / drain pattern on the pin-shaped pattern, a source / drain contact disposed on the source / drain pattern and connected to the source / drain pattern, and a contact connection via connecting the rear wiring line and the source / drain contact and contacting the rear wiring line, wherein the contact connection via includes a first surface connected to the source / drain contact and a second surface contacting the rear wiring line, and the height from the second surface of the rear wiring line to the upper surface of the field insulating film is smaller than the height from the second surface of the rear wiring line to the first surface of the contact connection via.

[0008] Another aspect of the semiconductor device of the present invention for solving the above problem comprises: a rear interlayer insulating film; a rear wiring line disposed within the rear interlayer insulating film and having a line shape, comprising a first surface and a second surface opposite in a first direction; a first device isolation structure disposed on the rear wiring line and extending in a second direction; a second device isolation structure disposed on the rear wiring line and extending in a second direction and spaced apart from the first device isolation structure in a third direction; a pin-shaped pattern disposed on the rear wiring line and extending in a third direction; a gate electrode disposed on the pin-shaped pattern and extending in a second direction; a source / drain pattern disposed on the pin-shaped pattern and connected to the pin-shaped pattern; a source / drain contact disposed on the source / drain pattern and connected to the source / drain pattern; a contact connection via disposed between the first device isolation structure and the second device isolation structure and contacting the rear wiring line, wherein the width of the contact connection via increases as it moves away from the rear wiring line; and on the first device isolation structure and the second device isolation structure It includes a front wiring line that is positioned, extends in a third direction, and connects the source / drain contact and the contact connection via.

[0009] Another aspect of a semiconductor device of the present invention for solving the above problem comprises: a fin-shaped pattern including a first surface and a second surface that extend in a first direction and are opposite in a second direction; a sheet pattern disposed on the first surface of the fin-shaped pattern and spaced apart from the fin-shaped pattern in a second direction; a gate electrode disposed on the first surface of the fin-shaped pattern, extending in a third direction and surrounding the sheet pattern; a source / drain pattern disposed on the first surface of the fin-shaped pattern and in contact with the sheet pattern; a source / drain contact disposed on the source / drain pattern and connected to the source / drain pattern; an insertion insulating film disposed on the second surface of the fin-shaped pattern and in contact with the second surface of the fin-shaped pattern; a back wiring line disposed on the second surface of the fin-shaped pattern, extending in a first direction and including a first surface and a second surface that are opposite in a second direction; and a contact connection via connecting the back wiring line and the source / drain contact and in contact with the back wiring line, wherein the contact connection via comprises a first surface connected to the source / drain contact and a back wiring It includes a second surface that contacts the line, and the height from the second surface of the rear wiring line to the first surface of the pin-shaped pattern is smaller than the height from the second surface of the rear wiring line to the first surface of the contact connection via.

[0010] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 2 to 7 are cross-sectional views taken along A-A, B-B, C-C, D-D, E-E, and F-F of FIG. 1. FIGS. 8 and 9 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 10 and FIGS. 11 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 12 and FIGS. 13 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 14 and FIGS. 15 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 16 to 18 are drawings illustrating a semiconductor device according to some embodiments. FIG. 19 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 20 and 21 are cross-sectional views taken along A-A and C-C of FIG. 19. FIGS. 22 and FIGS. 23 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 24 to 31 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0012] In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it goes without saying that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it goes without saying that the first element or component mentioned below may be the second element or component within the technical scope of the present invention.

[0013] In the drawings relating to a semiconductor device according to some embodiments, exemplarily, a fin-type transistor (FinFET) including a channel region having a fin-shaped pattern, a transistor including a nanowire or a nanosheet, and an MBCFET TM A (Multi-Bridge Channel Field Effect Transistor) has been illustrated, but is not limited thereto.

[0014] A semiconductor device according to some embodiments may include a tunneling FET, a three-dimensional (3D) transistor, or a vertical FET. Of course, a semiconductor device according to some embodiments may include a planar transistor. Additionally, the technical concept of the present invention may be applied to two-dimensional material-based transistors (2D material-based FETs) and their heterostructures. Furthermore, a semiconductor device according to some embodiments may include a bipolar junction transistor, a horizontal dual diffusion transistor (LDMOS), etc.

[0015] With reference to FIGS. 1 to 7, a semiconductor device according to some embodiments will be described.

[0016] FIG. 1 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIGS. 2 through 7 are cross-sectional views taken along A-A, B-B, C-C, D-D, E-E, and F-F of FIG. 1.

[0017] For convenience of explanation, the front wiring via (196), front wiring line (197), and wiring connection via (198) are not shown in FIG. 1.

[0018] Referring to FIGS. 1 through 7, a semiconductor device according to some embodiments comprises a first active pattern (AP1), a second active pattern (AP2), a third active pattern (AP3), a fourth active pattern (AP4), a first back wiring line (50), a second back wiring line (60), a first gate electrode (120), a second gate electrode (220), a first source / drain pattern (150), a second source / drain pattern (250), a third source / drain pattern (350), a first device isolation structure (160), a first source / drain contact (170), a second source / drain contact (270), a third source / drain contact (370), a fourth source / drain contact (470), a first contact connection via (180), and a second contact connection It may include vias (280) and a front wiring structure (195).

[0019] The first rear wiring line (50) and the second rear wiring line (60) may be placed within the rear interlayer insulating film (290). The first rear wiring line (50) and the second rear wiring line (60) may each have a line shape extending in the first direction (D1). The first rear wiring line (50) may be spaced apart from the second rear wiring line (60) in the second direction (D2).

[0020] For example, the first rear wiring line (50) and the second rear wiring line (60) may be power lines that supply power to the semiconductor device. For another example, the first rear wiring line (50) and the second rear wiring line (60) may be signal lines that supply operation signals to the semiconductor device. For yet another example, one of the first rear wiring line (50) and the second rear wiring line (60) may be a power line and the other may be a signal line.

[0021] The first rear wiring line (50) may include a first surface (50_S1) and a second surface (50_S2) opposite in the third direction (D3). The second rear wiring line (60) may include a first surface (60_S1) and a second surface (60_S2) opposite in the third direction (D3). Here, the first direction (D1) may intersect with the second direction (D2) and the third direction (D3). Additionally, the second direction (D2) may intersect with the third direction (D3).

[0022] For example, the first rear wiring line (50) may have a trapezoidal cross-section. In a semiconductor device according to some embodiments, the width (W11) of the first surface (50_S1) of the first rear wiring line in the second direction (D2) may be smaller than the width (W12) of the second surface (50_S2) of the first rear wiring line in the second direction (D2).

[0023] For example, the first rear wiring line (50) and the second rear wiring line (60) can be formed using a damascene process. After forming a trench extending in the first direction (D1) in the rear interlayer insulating film (290), the first rear wiring line (50) can be formed by filling the trench.

[0024] The first rear wiring line (50) and the second rear wiring line (60) are depicted as having a single conductive film structure, but are not limited thereto. Unlike what is depicted, the first rear wiring line (50) and the second rear wiring line (60) may have multiple conductive film structures, such as the first contact connection via (180) and the second contact connection via (280).

[0025] The first rear wiring line (50) and the second rear wiring line (60) may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material. The two-dimensional material may include a two-dimensional allotrope or a two-dimensional compound, and may include, for example, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide, but is not limited thereto. That is, the above-described two-dimensional materials are listed only as examples, so the two-dimensional materials that may be included in the semiconductor device of the present invention are not limited by the above-described materials.

[0026] The back interlayer insulating film (290) may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material. The dielectric constant of the low dielectric constant material may have a value smaller than 3.9, which is the dielectric constant of silicon oxide.

[0027] Each active pattern (AP1, AP2, AP3, AP4) can be disposed on the back interlayer insulating film (290). Each active pattern (AP1, AP2, AP3, AP4) can be extended in a first direction (D1).

[0028] For example, each active pattern (AP1, AP2, AP3, AP4) may be placed on the first rear wiring line (50) and the second rear wiring line (60). Each active pattern (AP1, AP2, AP3, AP4) may be placed on the first surface (50_S1) of the first rear wiring line and the first surface (50_S1) of the second rear wiring line. The first surface (50_S1) of the first rear wiring line and the first surface (50_S1) of the second rear wiring line may face each active pattern (AP1, AP2, AP3, AP4).

[0029] The first active pattern (AP1) may be spaced apart from the second active pattern (AP2) in the first direction (D1). The first active pattern (AP1) and the second active pattern (AP2) may be aligned in a line along the first direction (D1).

[0030] The third active pattern (AP3) may be spaced apart from the fourth active pattern (AP4) in the first direction (D1). The third active pattern (AP3) and the fourth active pattern (AP4) may be aligned in a line along the first direction (D1).

[0031] The first active pattern (AP1) can be separated from the third active pattern (AP3) in the second direction (D2). The second active pattern (AP2) can be separated from the fourth active pattern (AP4) in the second direction (D2).

[0032] The first active pattern (AP1) and the second active pattern (AP2) may be placed in a region where transistors of the same conductivity type are formed. The third active pattern (AP3) and the fourth active pattern (AP4) may be placed in a region where transistors of the same conductivity type are formed.

[0033] For example, the first active pattern (AP1) can be placed in a region where a P-type transistor is formed. The third active pattern (AP3) can be placed in a region where an N-type transistor is formed.

[0034] Each active pattern (AP1, AP2, AP3, AP4) may be a multichannel active pattern. For example, the first active pattern (AP1) may include a first sub-pattern (BP1) and a plurality of first sheet patterns (NS1). The second active pattern (AP2) may include a second sub-pattern (BP2) and a plurality of second sheet patterns (NS2). The third active pattern (AP3) may include a third sub-pattern (BP3) and a plurality of third sheet patterns (NS3). Although not illustrated, the fourth active pattern (AP4) may include a fourth sub-pattern and a plurality of fourth sheet patterns. In a semiconductor device according to some embodiments, each active pattern (AP1, AP2, AP3, AP4) may be an active pattern comprising a nanosheet or a nanowire.

[0035] The details regarding the third sub-pattern (BP3) described below may be applied to the fourth sub-pattern. Additionally, the details regarding the third sheet pattern (NS3) described below may be applied to the fourth sheet pattern.

[0036] Each lower pattern (BP1, BP2, BP3) can be placed on the rear interlayer insulating film (290). Each lower pattern (BP1, BP2, BP3) can protrude in a third direction (D3). Each lower pattern (BP1, BP2, BP3) can be a pin-shaped pattern.

[0037] Each lower pattern (BP1, BP2, BP3) can be extended in a first direction (D1). The first lower pattern (BP1) can be spaced apart from the second lower pattern (BP2) in the first direction (D1). The third lower pattern (BP3) can be spaced apart from the fourth lower pattern in the first direction (D1). The first lower pattern (BP1) can be spaced apart from the third lower pattern (BP3) in the second direction (D2). The second lower pattern (BP2) can be spaced apart from the fourth lower pattern in the second direction (D2).

[0038] The first lower pattern (BP1) may include a first surface (BP1_US) and a second surface (BP1_BS) opposite in the third direction (D3). The third lower pattern (BP3) may include a first surface (BP3_US) and a second surface (BP3_BS) opposite in the third direction (D3).

[0039] The second surface (BP1_BS) of the first lower pattern and the second surface (BP3_BS) of the third lower pattern can be viewed from the rear interlayer insulating film (290), the first rear wiring line (50), and the second rear wiring line (60). The first rear wiring line (50) and the second rear wiring line (60) can be placed on the second surface (BP1_BS) of the first lower pattern and the second surface (BP3_BS) of the third lower pattern.

[0040] The second lower pattern (BP2) may include a second surface (BP2_BS) facing the rear interlayer insulating film (290). Although not illustrated, the second lower pattern (BP2) may include a first surface opposite to the second surface (BP2_BS) of the second lower pattern in the third direction (D3). Additionally, the fourth lower pattern included in the fourth active pattern (AP4) may also include a first surface and a second surface opposite to the third direction (D3).

[0041] Taking the first lower pattern (BP1) as an example, the second surface (BP1_BS) of the first lower pattern may be the lower surface of the first lower pattern (BP1). The first surface (BP1_US) of the first lower pattern may be the upper surface of the first lower pattern (BP1).

[0042] The first lower pattern (BP1) may include a side wall (BP1_SW) connecting the first surface (BP1_US) of the first lower pattern and the second surface (BP1_BS) of the first lower pattern. The third lower pattern (BP3) may include a side wall (BP3_SW) connecting the first surface (BP3_US) of the third lower pattern and the second surface (BP3_BS) of the third lower pattern. The side wall (BP1_SW) of the first lower pattern and the side wall (BP3_SW) of the third lower pattern may extend in a first direction (D1). The side wall (BP1_SW) of the first lower pattern and the side wall (BP3_SW) of the third lower pattern may each be defined by a pin trench (FT). Although not illustrated, the second lower pattern (BP2) and the fourth lower pattern may include a side wall extending in the first direction (D1).

[0043] A plurality of first sheet patterns (NS1) may be placed on a first lower pattern (BP1). A plurality of first sheet patterns (NS1) may be placed on a first surface (BP1_US) of the first lower pattern. A plurality of first sheet patterns (NS1) may be spaced apart from the first lower pattern (BP1) in a third direction (D3).

[0044] A plurality of second sheet patterns (NS2) may be disposed on the second lower pattern (BP2). A plurality of second sheet patterns (NS2) may be disposed on the first surface of the second lower pattern (BP2). A plurality of second sheet patterns (NS2) may be spaced apart from the second lower pattern (BP2) in a third direction (D3).

[0045] A plurality of third sheet patterns (NS3) may be placed on the third lower pattern (BP3). A plurality of third sheet patterns (NS3) may be placed on the first surface (BP3_US) of the third lower pattern. A plurality of third sheet patterns (NS3) may be spaced apart from the third lower pattern (BP3) in a third direction (D3).

[0046] Although not illustrated, in the fourth active pattern (AP4), a plurality of fourth sheet patterns may be placed on the fourth lower pattern. A plurality of fourth sheet patterns may be spaced apart from the fourth lower pattern in the third direction (D3). Sheet patterns (NS1, NS2, NS3) may be placed on the first surface (50_S1) of the first rear wiring line and the first surface (60_S1) of the second rear wiring line.

[0047] The sheet patterns (NS1, NS2, NS3) may each include an upper surface and a lower surface opposite in the third direction (D3). The lower surfaces of the sheet patterns (NS1, NS2, NS3) may face the first rear wiring line (50) and the second rear wiring line (60), respectively. Although the sheet patterns (NS1, NS2, NS3) are illustrated as being arranged in three places in the third direction (D3), this is for convenience of explanation only and is not limited thereto.

[0048] Each sheet pattern (NS1, NS2, NS3) may include the topmost sheet pattern furthest from each lower pattern (BP1, BP2, BP3). For example, the top surface of the active pattern (AP1, AP2, AP3) may be the top surface of the topmost sheet pattern among the sheet patterns (NS1, NS2, NS3). The top surface of the fourth active pattern (AP4) may be the top surface of the topmost sheet pattern among the fourth sheet patterns.

[0049] Each sub-pattern (BP1, BP2, BP3) may include silicon or germanium, which are elemental semiconductor materials. Additionally, each sub-pattern (BP1, BP2, BP3) may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0050] Group IV-IV compound semiconductors may be, for example, binary compounds, ternary compounds containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds doped with a Group IV element.

[0051] A III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0052] Each sheet pattern (NS1, NS2, NS3) may include one of an elemental semiconductor material such as silicon or germanium, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. Taking the first sheet pattern (NS1) as an example, the width of the first sheet pattern (NS1) in the second direction (D2) may increase or decrease in proportion to the width of the first lower pattern (BP1) in the second direction (D2). Although the width of each first sheet pattern (NS1) placed on the first lower pattern (BP1) in the second direction (D2) is depicted as being the same, it is not limited thereto.

[0053] The field insulating film (105) may be placed on the first rear wiring line (50) and the second rear wiring line (60). For example, the field insulating film (105) may be placed on the first surface (50_S1) of the first rear wiring line and the first surface (60_S1) of the second rear wiring line.

[0054] For example, with the first lower pattern (BP1) and the third lower pattern (BP3), the field insulating film (105) may be placed on the sidewall (BP1_SW) of the first lower pattern and the sidewall (BP3_SW) of the third lower pattern. In one example, the field insulating film (105) may cover the entire sidewall (BP1_SW) of the first lower pattern and the entire sidewall (BP3_SW) of the third lower pattern. In another example, unlike what is illustrated, the field insulating film (105) may cover a portion of the sidewall (BP1_SW) of the first lower pattern and / or a portion of the sidewall (BP3_SW) of the third lower pattern.

[0055] The field insulating film (105) does not cover the first surface (BP1_US) of the first lower pattern and the first surface (BP3_US) of the third lower pattern. Although not shown, the field insulating film (105) does not cover the first surface of the second lower pattern (BP2) and the first surface of the fourth lower pattern. Based on the first rear wiring line (50) and the second rear wiring line (60), each sheet pattern (NS1, NS2, NS3) is positioned higher than the upper surface (105US) of the field insulating film.

[0056] The field insulating film (105) may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. Although the field insulating film (105) is depicted as a single film, this is for convenience of explanation only and is not limited thereto.

[0057] The insertion insulating film (295) may be placed between the rear interlayer insulating film (290) and the lower patterns (BP1, BP2, BP3). The insertion insulating film (295) may be placed between the rear interlayer insulating film (290) and the field insulating film (105). Although not shown, the insertion insulating film (295) may be placed between the rear interlayer insulating film (290) and the fourth lower pattern. The insertion insulating film (295) may be placed on the first surface (50_S1) of the first rear wiring line and the first surface (60_S1) of the second rear wiring line.

[0058] The insertion insulating film (295) may be placed on the second surface (BP1_BS) of the first lower pattern, the second surface (BP2_BS) of the second lower pattern, and the second surface (BP3_BS) of the third lower pattern. The insertion insulating film (295) may be in contact with the second surface (BP1_BS) of the first lower pattern, the second surface (BP2_BS) of the second lower pattern, and the second surface (BP3_BS) of the third lower pattern.

[0059] The insert insulating film (295) may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material. The boundary between the insert insulating film (295) and the back interlayer insulating film (290), and the boundary between the insert insulating film (295) and the field insulating film (105) are depicted as being distinct, but are not limited thereto. If the insert insulating film (295) and the back interlayer insulating film (290) contain the same material, the boundary between the insert insulating film (295) and the back interlayer insulating film (290) may not be distinct. If the insert insulating film (295) and the field insulating film (105) contain the same material, the boundary between the insert insulating film (295) and the field insulating film (105) may not be distinct.

[0060] The first gate structure (GS1) and the second gate structure (GS2) may be disposed on the upper surface (105US) of the field insulating film. The first gate structure (GS1) and the second gate structure (GS2) may each extend in a second direction (D2).

[0061] The first gate structure (GS1) may be spaced apart in the first direction (D1). The first gate structures (GS1) may be adjacent to each other in the first direction (D1).

[0062] Although not shown, the second gate structure (GS2) may be spaced apart in the first direction (D1). The second gate structure (GS2) may be adjacent to each other in the first direction (D1).

[0063] The first gate structure (GS1) can be placed on the first active pattern (AP1) and the third active pattern (AP3). The first gate structure (GS1) can intersect the first active pattern (AP1) and the third active pattern (AP3).

[0064] The first gate structure (GS1) can intersect with the first lower pattern (BP1) and the third lower pattern (BP3). The first gate structure (GS1) can wrap each of the first sheet patterns (NS1). The first gate structure (GS1) can wrap each of the third sheet patterns (NS3).

[0065] The second gate structure (GS2) may be placed on the second active pattern (AP2) and the fourth active pattern (AP4). The second gate structure (GS2) may intersect the second active pattern (AP2) and the fourth active pattern (AP4).

[0066] The second gate structure (GS2) can intersect with the second lower pattern (BP2) and the fourth lower pattern. The second gate structure (GS2) can wrap each second sheet pattern (NS2). The second gate structure (GS2) can wrap each fourth sheet pattern.

[0067] The first gate structure (GS1) is depicted as being positioned across the first active pattern (AP1) and the third active pattern (AP3), but is not limited thereto. Unlike what is depicted, a portion of the first gate structure (GS1) may be separated into two parts by a gate isolation structure positioned on the field insulating film (105) and positioned on the first active pattern (AP1) and the third active pattern (AP3). The description of the first gate structure (GS1) described above may, of course, be applied to the second gate structure (GS2).

[0068] The first gate structure (GS1) may include, for example, a first gate electrode (120), a first gate insulating film (130), a first gate spacer (140), and a first gate capping pattern (145). The second gate structure (GS2) may include, for example, a second gate electrode (220), a second gate insulating film (230), a second gate spacer (240), and a second gate capping pattern (245).

[0069] The first gate structure (GS1) may include a plurality of first inner gate structures (INT_GS1) disposed between the first sheet pattern (NS1) adjacent in the third direction (D3) and between the first lower pattern (BP1) and the first sheet pattern (NS1). The first inner gate structure (INT_GS1) may be disposed between the first surface (BP1_US) of the first lower pattern and the lower surface of the first sheet pattern (NS1), and between the upper surface of the first sheet pattern (NS1) facing in the third direction (D3) and the lower surface of the first sheet pattern (NS1).

[0070] The number of first inner gate structures (INT_GS1) may be the same as the number of first sheet patterns (NS1). The first inner gate structures (INT_GS1) contact the first surface (BP1_US) of the first lower pattern, the upper surface of the first sheet pattern (NS1), and the lower surface of the first sheet pattern (NS1).

[0071] The first inner gate structure (INT_GS1) includes a first gate electrode (120) and a first gate insulating film (130) disposed between adjacent first sheet patterns (NS1) and between the first lower pattern (BP1) and the first sheet pattern (NS1). Although not illustrated, the first inner gate structure (INT_GS1) may be disposed between adjacent third sheet patterns (NS3) in a third direction (D3) and between the third lower pattern (BP3) and the third sheet pattern (NS3).

[0072] The second gate structure (GS2) may include a plurality of second inner gate structures (INT_GS2) disposed between second sheet patterns (NS2) adjacent in the third direction (D3) and between the second lower pattern (BP2) and the second sheet pattern (NS2). Although not illustrated, the second inner gate structure (INT_GS2) may be disposed between fourth sheet patterns adjacent in the third direction (D3) and between the fourth lower pattern and the fourth sheet pattern. The description of the second inner gate structure (INT_GS2) may be substantially the same as the description of the first inner gate structure (INT_GS1).

[0073] The following description focuses on the first active pattern (AP1) and the first gate structure (GS1), and the third active pattern (AP3) and the first gate structure (GS1). The description of the second gate structure (GS2) may be substantially the same as the description of the first gate structure (GS1).

[0074] The first gate electrode (120) may be placed on the first lower pattern (BP1) and the third lower pattern (BP3). For example, the first gate electrode (120) may be placed on the first surface (BP1_US) of the first lower pattern and the first surface (BP3_US) of the third lower pattern.

[0075] The first gate electrode (120) may extend in a second direction (D2). The first gate electrode (120) may intersect with the first lower pattern (BP1) and the third lower pattern (BP3). The first gate electrode (120) may wrap around the first sheet pattern (NS1) and the third sheet pattern (NS3).

[0076] In the cross-sectional view as in FIG. 2, the upper surface of the first gate electrode (120) is depicted as a concave curved surface, but is not limited thereto. Of course, the upper surface of the first gate electrode (120) can be a flat surface.

[0077] The first gate electrode (120) and the second gate electrode (220) may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrode (120) and the second gate electrode (220) are, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), It may include at least one of molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but is not limited thereto. Conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the materials described above, but are not limited thereto.

[0078] The first gate insulating film (130) may extend along the upper surface (105US) of the field insulating film, the first surface (BP1_US) of the first lower pattern, and the first surface (BP3_US) of the third lower pattern. The first gate insulating film (130) may wrap around a plurality of first sheet patterns (NS1). The first gate insulating film (130) may wrap around a plurality of third sheet patterns (NS3). The first gate insulating film (130) may be arranged along the perimeter of the first sheet pattern (NS1) and the perimeter of the third sheet pattern (NS3). The first gate electrode (120) is placed on the first gate insulating film (130).

[0079] A first gate insulating film (130) is disposed between the first gate electrode (120) and the first sheet pattern (NS1), and between the first gate electrode (120) and the third sheet pattern (NS3). In a semiconductor device according to some embodiments, the first gate insulating film (130) included in the first inner gate structure (INT_GS1) may come into contact with a first source / drain pattern (150) to be described later.

[0080] The first gate insulating film (130) and the second gate insulating film (230) may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. High dielectric constant materials may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0081] Although the first gate insulating film (130) and the second gate insulating film (230) are depicted as single films, this is for convenience of explanation only and is not limited thereto. The first gate insulating film (130) and the second gate insulating film (230) may include multiple films. Taking the first gate insulating film (130) as an example, the first gate insulating film (130) may include an interfacial layer disposed between the first active pattern (AP1) and the first gate electrode (120), and between the third active pattern (AP3) and the first gate electrode (120), and a high dielectric constant insulating film. For example, the interfacial layer may not be formed along the profile of the upper surface (105US) of the field insulating film.

[0082] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the first gate insulating film (130) and the second gate insulating film (230) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0083] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0084] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0085] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0086] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0087] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0088] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0089] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0090] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0091] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0092] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0093] For example, the first gate insulating film (130) and the second gate insulating film (230) may include a single ferroelectric material film. For another example, the first gate insulating film (130) and the second gate insulating film (230) may include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film (130) and the second gate insulating film (230) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0094] The first gate spacer (140) may be disposed on the sidewall of the first gate electrode (120). For example, the first gate spacer (140) may be disposed on the long sidewall of the first gate electrode extending in the second direction (D2). The first gate spacer (140) may not be disposed between the first lower pattern (BP1) and the first sheet pattern (NS1), and between the first sheet pattern (NS1) adjacent in the third direction (D3).

[0095] The second gate spacer (240) may be placed on the side wall of the second gate electrode (220). The second gate spacer (240) may not be placed between the second lower pattern (BP2) and the second sheet pattern (NS2), and between the second sheet pattern (NS2) adjacent in the third direction (D3).

[0096] Unlike what is illustrated, the first gate spacer (140) and / or the second gate spacer (240) may include an inner spacer. The inner spacer may be positioned between the first lower pattern (BP1) and the first sheet pattern (NS1), and between the first sheet pattern (NS1) adjacent in the third direction (D3). Alternatively, the inner spacer may be positioned between the second lower pattern (BP2) and the second sheet pattern (NS2), and between the second sheet pattern (NS2) adjacent in the third direction (D3).

[0097] The first gate spacer (140) and the second gate spacer (240) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonate (SiOC), and combinations thereof. Although the first gate spacer (140) and the second gate spacer (240) are depicted as single films, this is for convenience of explanation only and is not limited thereto.

[0098] A first gate capping pattern (145) may be placed on a first gate electrode (120). The upper surface of the first gate capping pattern (145) may be the upper surface of a first gate structure (GS1). A second gate capping pattern (245) may be placed on a second gate electrode (220). The upper surface of the second gate capping pattern (245) may be the upper surface of a second gate structure (GS2).

[0099] Unlike what is illustrated, the first gate capping pattern (145) may be placed between the first gate spacers (140). The second gate capping pattern (245) may be placed between the second gate spacers (240).

[0100] The first gate capping pattern (145) and the second gate capping pattern (245) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN) and combinations thereof.

[0101] Unlike what is depicted, the first gate structure (GS1) and the second gate structure (GS2) may not include gate capping patterns (145, 245).

[0102] The first source / drain pattern (150) may be placed on the first lower pattern (BP1). For example, the first source / drain pattern (150) may be placed on the first surface (BP1_US) of the first lower pattern. The first source / drain pattern (150) may be placed on the side of the first gate electrode (120). The first source / drain pattern (150) may be in contact with the first active pattern (AP1). The first source / drain pattern (150) may be in contact with the first sheet pattern (NS1). The first source / drain pattern (150) is connected to the first sheet pattern (NS1) and the first lower pattern (BP1). For example, the first source / drain pattern (150) may be in contact with the first inner gate structure (INT_GS1).

[0103] The second source / drain pattern (250) may be placed on the second lower pattern (BP2). For example, the second source / drain pattern (250) may be placed on the first surface of the second lower pattern (BP2). The second source / drain pattern (250) may be placed on the side of the second gate electrode (220). The second source / drain pattern (250) may be in contact with the second active pattern (AP2). The second source / drain pattern (250) may be in contact with the second sheet pattern (NS2). The second source / drain pattern (250) is connected to the second sheet pattern (NS2) and the second lower pattern (BP2). For example, the second source / drain pattern (250) may be in contact with the second inner gate structure (INT_GS2).

[0104] The third source / drain pattern (350) may be placed on the third lower pattern (BP3). For example, the third source / drain pattern (350) may be placed on the first surface (BP3_US) of the third lower pattern. The third source / drain pattern (350) may be placed on the side of the first gate electrode (120). Although not illustrated, the third source / drain pattern (350) may be in contact with the third sheet pattern (NS3).

[0105] Although not illustrated, the fourth source / drain pattern may be placed on the fourth lower pattern. The fourth source / drain pattern may be placed on the side of the second gate electrode (220). The fourth source / drain pattern may be in contact with the fourth sheet pattern.

[0106] For example, a cross-sectional view cut along the third active pattern (AP3) and the fourth active pattern (AP4) in the first direction (D1) may be similar to FIG. 2. The third source / drain pattern (350) may be in contact with the first gate insulating film (130) included in the first inner gate structure (INT_GS1). The fourth source / drain pattern may be in contact with the second gate insulating film (230) included in the second inner gate structure (INT_GS2).

[0107] Although not illustrated, as another example, an inner spacer may be further disposed between the first inner gate structure (INT_GS1) and the third source / drain pattern (350), and between the second inner gate structure (INT_GS2) and the fourth source / drain pattern. In this case, the third source / drain pattern (350) does not come into contact with the first gate insulating film (130) included in the first inner gate structure (INT_GS1). The fourth source / drain pattern does not come into contact with the second gate insulating film (230) included in the second inner gate structure (INT_GS2).

[0108] Source / drain patterns (150, 250, 350) may be placed on the first surface (50_S1) of the first rear wiring line and the first surface (60_S1) of the second rear wiring line. Since the first lower pattern (BP1) is spaced apart from the second lower pattern (BP2) in the first direction (D1), the first source / drain pattern (150) is spaced apart from the second source / drain pattern (250) in the first direction (D1). The third source / drain pattern (350) is spaced apart from the fourth source / drain pattern in the first direction (D1). The first source / drain pattern (150) is spaced apart from the third source / drain pattern (350) in the second direction (D2). The second source / drain pattern (250) is spaced apart from the fourth source / drain pattern in the second direction (D2).

[0109] The first source / drain pattern (150) may be included in the source / drain of a transistor using the first sheet pattern (NS1) as the channel region. The second source / drain pattern (250) may be included in the source / drain of a transistor using the second sheet pattern (NS2) as the channel region. The third source / drain pattern (350) may be included in the source / drain of a transistor using the third sheet pattern (NS3) as the channel region. The fourth source / drain pattern may be included in the source / drain of a transistor using the fourth sheet pattern as the channel region.

[0110] The source / drain patterns (150, 250, 350) may each include an epitaxial pattern. The source / drain patterns (150, 250, 350) may each include a semiconductor material.

[0111] The first source / drain pattern (150) and the second source / drain pattern (250) may include a p-type dopant. The p-type dopant may include at least one of boron (B) and gallium (Ga), but is not limited thereto. The third source / drain pattern (350) and the fourth source / drain pattern may include an n-type dopant. The n-type dopant may include at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), but is not limited thereto.

[0112] The source / drain etch stop layer (156) may extend along the outer wall of the gate spacer (140) and the side wall of the source / drain pattern (150, 250, 350). The source / drain etch stop layer (156) may extend along the upper surface (105US) of the field insulating film.

[0113] The source / drain etch stop layer (156) may not extend along the sidewalls of the first gate capping pattern (145) and the second gate capping pattern (245). Unlike what is illustrated, the source / drain etch stop layer (156) may extend along the sidewalls of the first gate capping pattern (145) and the second gate capping pattern (245).

[0114] The source / drain etching stop layer (156) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0115] A pair of first element isolation structures (160) may be placed on a rear interlayer insulating film (290), a first rear wiring line (50), and a second rear wiring line (60). The first element isolation structures (160) may be placed on a first surface (50_S1) of the first rear wiring line and a first surface (60_S1) of the second rear wiring line.

[0116] A pair of first element isolation structures (160) may include a first sub-element isolation structure (160_1) and a second sub-element isolation structure (160_2). The first sub-element isolation structure (160_1) and the second sub-element isolation structure (160_2) may each extend in a second direction (D2). The first sub-element isolation structure (160_1) may be spaced apart from the second sub-element isolation structure (160_2) in a first direction (D1).

[0117] The first device isolation structure (160) can isolate the first lower pattern (BP1) and the second lower pattern (BP2). The first device isolation structure (160) can isolate the third lower pattern (BP3) and the fourth lower pattern. The first active pattern (AP1) and the second active pattern (AP2) are not placed between the first sub-device isolation structure (160_1) and the second sub-device isolation structure (160_2). For example, the first lower pattern (BP1) and the second lower pattern (BP2) are not placed between the first sub-device isolation structure (160_1) and the second sub-device isolation structure (160_2). A portion of the field insulating film (105) may be placed between the first sub-device isolation structure (160_1) and the second sub-device isolation structure (160_2) adjacent in the first direction (D1).

[0118] Unlike what is depicted, a dummy active pattern containing a semiconductor material may be disposed between the first sub-element isolation structure (160_1) and the second sub-element isolation structure (160_2).

[0119] A first lower pattern (BP1) may protrude in a first direction (D1) from a first sub-element isolation structure (160_1). A second lower pattern (BP2) may protrude in a first direction (D1) from a second sub-element isolation structure (160_2). Although not illustrated, a third lower pattern (BP3) may protrude in a first direction (D1) from a first sub-element isolation structure (160_1). A fourth lower pattern may protrude in a first direction (D1) from a second sub-element isolation structure (160_2).

[0120] With respect to the second surface (BP1_BS) of the first lower pattern, the height of the upper surface of the first sub-element isolation structure (160_1) may be the same as the height of the upper surface of the first gate capping pattern (145). Unlike what is illustrated, with respect to the second surface (BP1_BS) of the first lower pattern, the upper surface of the first sub-element isolation structure (160_1) may be higher than the upper surface of the first gate capping pattern (145).

[0121] The first device isolation structure (160) may include an insulating material. The first device isolation structure (160) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonate (SiOC), and combinations thereof. The first sub-device isolation structure (160_1) and the second sub-device isolation structure (160_2) are shown as being single films, but are not limited thereto.

[0122] An insulating residual pattern may be disposed between the first sub-device isolation structure (160_1) and the first source / drain pattern (150). An insulating residual pattern may be disposed between the second sub-device isolation structure (160_2) and the second source / drain pattern (250). The insulating residual pattern may include the same material as the gate insulating film (130, 230).

[0123] Between the first sub-device isolation structure (160_1) and the second sub-device isolation structure (160_2), a first upper interlayer insulating film (190) and a source / drain etching stop film (156) may be disposed. For example, between the first sub-device isolation structure (160_1) and the source / drain etching stop film (156), an insulating spacer pattern in contact with the source / drain etching stop film (156) may be disposed. The insulating spacer pattern may include the same material as the first gate spacer (140).

[0124] For example, the first source / drain pattern (150) and the third source / drain pattern (350) may be placed between the first gate electrode (120) adjacent in the first direction (D1). For another example, the first source / drain pattern (150) and the third source / drain pattern (350) may be placed between the first gate electrode (120) and the first sub-device isolation structure (160_1).

[0125] For example, the second source / drain pattern (250) and the fourth source / drain pattern may be placed between the second gate electrode (220) adjacent in the first direction (D1). For another example, the second source / drain pattern (250) and the fourth source / drain pattern may be placed between the second gate electrode (220) and the second sub-device isolation structure (160_2).

[0126] The gate isolation structure (120CT) can be placed on the field insulating film (105). A portion of the gate isolation structure (120CT) can be indented into the field insulating film (105).

[0127] The gate isolation structure (120CT) can be spaced apart in the second direction (D2). Active patterns (AP1, AP2, AP3, AP4) can be placed between the first gate isolation structure (GCS1) adjacent in the second direction (D2).

[0128] The first gate electrode (120) and the second gate electrode (220) may be disposed between adjacent gate separation structures (120CT) in the second direction (D2). The gate separation structures (120CT) may separate the gate electrodes adjacent in the second direction (D2). When the first gate electrode (120) and the second gate electrode (220) include a sidewall extending in the first direction (D1), the sidewall of the first gate electrode (120) and the sidewall of the second gate electrode (220) face the gate separation structures (120CT).

[0129] For example, the gate isolation structure (120CT) can be placed along the boundary of a standard cell. For example, the gate isolation structure (120CT) can be a standard cell isolation structure.

[0130] The gate isolation structure (120CT) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbon (SiOC), aluminum oxide (AlO), and combinations thereof. The gate isolation structure (120CT) is depicted as a single film, but is not limited thereto.

[0131] The upper surface of the gate isolation structure (120CT) may be placed in the same plane as the upper surface of the first gate capping pattern (145), but is not limited thereto.

[0132] The first upper interlayer insulating film (190) is placed on the upper surface (105US) of the field insulating film. The first upper interlayer insulating film (190) is placed on the source / drain etching stop film (156). The first upper interlayer insulating film (190) may be placed on the source / drain pattern (150, 250, 350).

[0133] The first upper interlayer insulating film (190) may not cover the upper surface of the first gate capping pattern (145) and the upper surface of the second gate capping pattern (245). The first upper interlayer insulating film (190) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0134] The first source / drain contact (170) may be placed on the upper surface (105US) of the field insulating film. The first source / drain contact (170) may be placed on the first source / drain pattern (150). The first source / drain contact (170) is electrically connected to the first source / drain pattern (150).

[0135] The first source / drain contact (170) can be connected to the first rear wiring line (50) through the first contact connection via (180). Although not shown, a portion of the first source / drain contact (170) may not be connected to the first contact connection via (180).

[0136] The second source / drain contact (270) may be placed on the upper surface (105US) of the field insulating film. The second source / drain contact (270) may be placed on the second source / drain pattern (250). The second source / drain contact (270) is electrically connected to the second source / drain pattern (250).

[0137] The second source / drain contact (270) can be connected to the first rear wiring line (50) through the first contact connection via (180). Although not shown, part of the second source / drain contact (270) may not be connected to the first contact connection via (180).

[0138] The third source / drain contact (370) may be placed on the upper surface (105US) of the field insulating film. The third source / drain contact (370) may be placed on the third source / drain pattern (350). The third source / drain contact (370) is electrically connected to the third source / drain pattern (350).

[0139] The third source / drain contact (370) can be connected to the second rear wiring line (60) through the second contact connection via (280). Although not shown, part of the third source / drain contact (370) may not be connected to the second contact connection via (280).

[0140] The fourth source / drain contact (470) may be placed on the upper surface (105US) of the field insulating film. The fourth source / drain contact (470) may be placed on the fourth source / drain pattern. The fourth source / drain contact (470) is electrically connected to the fourth source / drain pattern.

[0141] The fourth source / drain contact (470) can be connected to the second rear wiring line (60) through the second contact connection via (280). Although not shown, part of the fourth source / drain contact (470) may not be connected to the second contact connection via (280).

[0142] The first connecting source / drain contact (172) may be placed on the first source / drain pattern (150) and the third source / drain pattern (350). The first connecting source / drain contact (172) is electrically connected to the first source / drain pattern (150) and the third source / drain pattern (350).

[0143] The second connection source / drain contact (272) may be placed on the second source / drain pattern (250) and the fourth source / drain pattern. The second connection source / drain contact (272) is electrically connected to the second source / drain pattern (250) and the fourth source / drain pattern. The first connection source / drain contact (172) and the second connection source / drain contact (272) may not be electrically connected to the first rear wiring line (50) and the second rear wiring line (60).

[0144] With respect to the upper surface (105US) of the field insulating film, the height of the upper surface of the first source / drain contact (170) may be the same as the height of the upper surface of the second source / drain contact (270). With respect to the upper surface (105US) of the field insulating film, the height of the upper surface of the first source / drain contact (170) may be the same as the height of the upper surface of the third source / drain contact (370) and the height of the upper surface of the fourth source / drain contact (470).

[0145] A first contact silicide film (155) may be disposed between a first source / drain contact (170) and a first source / drain pattern (150), and between a first connecting source / drain contact (172) and a first source / drain pattern (150). A second contact silicide film (255) may be disposed between a second source / drain contact (270) and a second source / drain pattern (250), and between a second connecting source / drain contact (272) and a second source / drain pattern (250). A third contact silicide film (355) may be disposed between a third source / drain contact (370) and a third source / drain pattern (350), and between a first connecting source / drain contact (172) and a third source / drain pattern (350). Although not shown, a contact silicide film may be disposed between the fourth source / drain contact (470) and the fourth source / drain pattern, and between the second connecting source / drain contact (272) and the fourth source / drain pattern.

[0146] A first gate contact (175) is placed on a first gate electrode (120). The first gate contact (175) can penetrate a first gate capping pattern (145). The first gate contact (175) is connected to the first gate electrode (120). The first gate contact (175) connects the front wiring line (197) and the first gate electrode (120). A second gate contact (275) can be placed on a second gate electrode (220). The second gate contact (275) connects the front wiring line (197) and the second gate electrode (220).

[0147] Source / drain contacts (170, 270, 370, 470) and connected source / drain contacts (172, 272) are illustrated as having a single conductive film structure, but are not limited thereto. Unlike illustrated, source / drain contacts (170, 270, 370, 470) and connected source / drain contacts (172, 272) may have a multi-conductive film structure including a contact barrier film and a contact plug film.

[0148] The gate contact (175, 275) is depicted as having a single conductive film structure, but is not limited thereto. Unlike what is depicted, the gate contact (175, 275) may have a multi-conductive film structure including a contact barrier film and a contact plug film.

[0149] Source / drain contacts (170, 270, 370, 470), connected source / drain contacts (172, 272), and gate contacts (175, 275) may comprise at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The contact silicide film (155, 255, 355) may comprise a metal silicide material.

[0150] A first contact connection via (180) may be placed between a first sub-element isolation structure (160_1) and a second sub-element isolation structure (160_2). The first contact connection via (180) may connect a first rear wiring line (50) and a first source / drain contact (170). The first contact connection via (180) may connect a first rear wiring line (50) and a second source / drain contact (270).

[0151] The first contact connection via (180) contacts the first rear wiring line (50). In other words, the first contact connection via (180) is electrically connected to the first rear wiring line (50) without any other conduction pattern.

[0152] The first contact connection via (180) does not overlap with the first source / drain contact (170) in the second direction (D2). The first contact connection via (180) does not overlap with the second source / drain contact (270) in the second direction (D2). The first contact connection via (180) may be separated from the first source / drain contact (170) in the first direction (D1). The first contact connection via (180) may be separated from the second source / drain contact (270) in the first direction (D1).

[0153] A second contact connection via (280) may be placed between a first sub-element isolation structure (160_1) and a second sub-element isolation structure (160_2). The second contact connection via (280) may connect a second rear wiring line (60) and a third source / drain contact (370). The second contact connection via (280) may connect a second rear wiring line (60) and a fourth source / drain contact (470).

[0154] The second contact connection via (280) can be connected to the second rear wiring line (60). The second contact connection via (280) contacts the second rear wiring line (60).

[0155] The second contact connection via (280) does not overlap with the third source / drain contact (370) in the second direction (D2). The second contact connection via (280) does not overlap with the fourth source / drain contact (470) in the second direction (D2). The second contact connection via (280) may be separated from the third source / drain contact (370) in the first direction (D1). The second contact connection via (280) may be separated from the fourth source / drain contact (470) in the first direction (D1).

[0156] The shape in which the second contact connection via (280) is connected to the third source / drain contact (370) and the fourth source / drain contact (470) may be similar to FIG. 7.

[0157] The first contact connection via (180) can be connected to the first rear wiring line (50) by penetrating the source / drain etching stop layer (156) and the field insulating layer (105). The second contact connection via (280) can be connected to the second rear wiring line (60) by penetrating the source / drain etching stop layer (156) and the field insulating layer (105). The first contact connection via (180) can be spaced apart from the second contact connection via (280) in a second direction (D2). The first contact connection via (180) and the second contact connection via (280) can be arranged in the second direction (D2).

[0158] The width of the first contact connection via (180) in the first direction (D1) may increase as it moves away from the first rear wiring line (50). The width of the first contact connection via (180) in the second direction (D2) may increase as it moves away from the first rear wiring line (50). The description regarding the width of the sixth contact connection via (680) may be substantially the same as the description regarding the width of the fifth contact connection via (580).

[0159] The following description focuses on the first contact connection via (180). The description of the second contact connection via (280) may be substantially the same as the description of the first contact connection via (180).

[0160] The first contact connection via (180) may include a first surface (180_S1) and a second surface (180_S2) opposite in the third direction (D3). The first surface (180_S1) of the first contact connection via may be connected to the first source / drain contact (170) and the second source / drain contact (270). The second surface (180_S2) of the first contact connection via may be connected to the first rear wiring line (50). The second surface (180_S2) of the first contact connection via contacts the first rear wiring line (50).

[0161] For example, the height (H13) from the second side (50_S2) of the first rear wiring line to the upper surface of the first source / drain contact (170) may be the same as the height (H16) from the second side (50_S2) of the first rear wiring line to the first side (180_S1) of the first contact connection via.

[0162] For example, the height (H15) from the second surface (50_S2) of the first rear wiring line to the upper surface (105US) of the field insulating film is smaller than the height (H16) from the second surface (50_S2) of the first rear wiring line to the first surface (180_S1) of the first contact connection via. The height (H12) from the second surface (50_S2) of the first rear wiring line to the first surface (BP1_US) of the first lower pattern is smaller than the height (H16) from the second surface (50_S2) of the first rear wiring line to the first surface (180_S1) of the first contact connection via. The first surface (180_S1) of the first contact connection via protrudes in a third direction (D3) from the first surface (BP1_US) of the first lower pattern and the upper surface (105US) of the field insulating film.

[0163] The height (H15) from the second surface (50_S2) of the first rear wiring line to the upper surface (105US) of the field insulating film is greater than the height (H14) from the second surface (50_S2) of the first rear wiring line to the second surface (180_S2) of the first contact connection via. The height (H12) from the second surface (50_S2) of the first rear wiring line to the first surface (BP1_US) of the first lower pattern is greater than the height (H14) from the second surface (50_S2) of the first rear wiring line to the second surface (180_S2) of the first contact connection via. A portion of the first contact connection via (180) must be surrounded by the field insulating film (150).

[0164] For example, the height (H11) from the second side (50_S2) of the first rear wiring line to the second side (BP1_BS) of the first lower pattern is greater than the height (H14) from the second side (50_S2) of the first rear wiring line to the second side (180_S2) of the first contact connection via. With respect to the second side (50_S2) of the first rear wiring line, the second side (BP1_BS) of the first lower pattern may be higher than the second side (180_S2) of the first contact connection via. The height (H11) from the second side (50_S2) of the first rear wiring line to the second side (BP1_BS) of the first lower pattern may be the height from the second side (50_S2) of the first rear wiring line to the lowest part of the first lower pattern (BP1).

[0165] A connecting via liner (181) may be placed on the sidewall of the first contact connecting via (180) and the sidewall of the second contact connecting via (280). Unlike what is illustrated, the connecting via liner (181) may not be placed on the sidewall of the first contact connecting via (180) and the sidewall of the second contact connecting via (280).

[0166] The first contact connection via (180) may include a first contact connection barrier membrane (180a) and a first contact connection plug (180b). The first contact connection barrier membrane (180a) may extend along the sidewall (180b_SW) of the first contact connection plug.

[0167] The second contact connection via (280) may include a second contact connection barrier membrane (280a) and a second contact connection plug (280b). The second contact connection barrier membrane (280a) may extend along the side wall (280b_SW) of the second contact connection plug.

[0168] For example, the first contact connection plug (180b) contacts the first rear wiring line (50). The second contact connection plug (280b) contacts the second rear wiring line (60).

[0169] For example, in the case of the first contact connection via (180), the first surface (180_S1) of the first contact connection via and the second surface (180_S2) of the first contact connection via can be defined by the first contact connection barrier film (180a) and the first contact connection plug (180b).

[0170] The first contact connection barrier film (180a) and the second contact connection barrier film (280a) may comprise at least one of, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material. The first contact connection plug (180b) and the second contact connection plug (280b) may comprise one of a metal and a metal alloy.

[0171] For example, the first contact connection plug (180b) and the second contact connection plug (280b) may have a single conductive film structure. Alternatively, the first contact connection plug (180b) and the second contact connection plug (280b) may include a conductive material and be formed as a single film.

[0172] Unlike what is illustrated, the first contact connection via (180) and the second contact connection via (280) may have a single conductive film structure. In this case, the first contact connection via (180) and the second contact connection via (280) may include a contact connection plug without a contact connection barrier film.

[0173] The connecting via liner (181) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0174] By directly connecting the first contact connection via (180) to the first rear wiring line (50) which has a line shape, the resistance between the first rear wiring line (50) and the first contact connection via (180) can be reduced. Through this, the performance and reliability of the semiconductor device can be improved.

[0175] The second upper interlayer insulating film (191) may be disposed on the first upper interlayer insulating film (190), the first gate structure (GS1), the second gate structure (GS2), the source / drain contacts (170, 270, 370, 470), and the contact connection vias (180, 280). The second upper interlayer insulating film (191) may comprise, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0176] The front wiring structure (195) may be placed within the second upper layer insulating film (191). The front wiring structure (195) may include a front wiring via (196), a front wiring line (197), and a wiring connection via (198). The wiring connection via (198) may connect the front wiring line (197) and the contact connection via (180, 280).

[0177] The front wiring structure (195) can be connected to source / drain contacts (170, 270, 370, 470), connected source / drain contacts (172, 272), and gate contacts (175, 275). The front wiring structure (195) can be connected to contact connection vias (180, 280).

[0178] The front wiring line (197) may include a first front wiring line (197_1) and a second front wiring line (197_2). The first front wiring line (197_1) and the second front wiring line (197_2) may each be extended in a first direction (D1).

[0179] The front wiring line (197) may be placed on the first element isolation structure (160). For example, the front wiring line (197) may be placed on the first sub-element isolation structure (160_1) and the second sub-element isolation structure (160_2).

[0180] The first front wiring line (197_1) can connect the first source / drain contact (170) and the first contact connection via (180). The first source / drain contact (170) can be positioned between the first source / drain pattern (150) and the first front wiring line (197_1). The first front wiring line (197_1) can connect the second source / drain contact (270) and the first contact connection via (180). The first face (180_S1) of the first contact connection via is connected to the first front wiring line (197_1). For example, the first front wiring line (197_1) can be connected to the first contact connection via (180) through the wiring connection via (198).

[0181] The second front wiring line (197_2) can connect the third source / drain contact (370) and the second contact connection via (280). The third source / drain contact (370) can be positioned between the third source / drain pattern (350) and the second front wiring line (197_2). The second front wiring line (197_2) can connect the fourth source / drain contact (470) and the second contact connection via (280). For example, the second front wiring line (197_2) can be connected to the second contact connection via (280) through the wiring connection via (198).

[0182] Front wiring via (196). The front wiring line (197) and wiring connection via (198) may each include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0183] The front wiring via (196), front wiring line (197), and wiring connection via (198) are each depicted as having a single conductive film structure, but are not limited thereto. Unlike what is depicted, for example, at least one of the front wiring via (196), front wiring line (197), and wiring connection via (198) may have a multi-conductive film structure. For another example, the front wiring structure (195) may have an integral structure in which there is no boundary between the front wiring via (196) and the front wiring line (197), and between the wiring connection via (198) and the front wiring line (197).

[0184] FIGS. 8 and 9 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 10 and 11 are drawings for illustrating a semiconductor device according to some embodiments. FIGS. 12 and 13 are drawings for illustrating a semiconductor device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIGS. 1 through 7.

[0185] Referring to FIGS. 8 and 9, in a semiconductor device according to some embodiments, a first contact connection barrier film (180a) may be placed between a first contact connection plug (180b) and a first rear wiring line (50).

[0186] The first contact connection plug (180b) may not come into contact with the first rear wiring line (50). The second side (180_S2) of the first contact connection via may be defined by the first contact connection barrier film (180a).

[0187] The second contact connection barrier membrane (280a) may be placed between the second contact connection plug (280b) and the second rear wiring line (60). The second contact connection plug (280b) may not come into contact with the second rear wiring line (60).

[0188] Referring to FIG. 4, FIG. 10 and FIG. 11, in a semiconductor device according to some embodiments, the height (H11) from the second surface (50_S2) of the first rear wiring line to the second surface (BP1_BS) of the first lower pattern may be smaller than the height (H14) from the second surface (50_S2) of the first rear wiring line to the second surface (180_S2) of the first contact connection via.

[0189] Based on the second side (50_S2) of the first rear wiring line, the second side (BP1_BS) of the first lower pattern may be lower than the second side (180_S2) of the first contact connection via.

[0190] Unlike what is depicted, the height (H11) from the second side (50_S2) of the first rear wiring line to the second side (BP1_BS) of the first lower pattern may be the same as the height (H14) from the second side (50_S2) of the first rear wiring line to the second side (180_S2) of the first contact connection via.

[0191] Referring to FIGS. 4, 12 and 13, in a semiconductor device according to some embodiments, a first front wiring line (197_1) can be directly connected to a first contact connection via (180).

[0192] The first front wiring line (197_1) can contact the first face (180_S1) of the first contact connection via. The first contact connection via (180) can be connected to the first front wiring line (197_1) without the wiring connection via (198).

[0193] The second front wiring line (197_2) can be directly connected to the second contact connection via (280). The second contact connection via (280) can be connected to the second front wiring line (197_2) without the wiring connection via (198).

[0194] The height (H13) from the second side (50_S2) of the first rear wiring line to the upper surface of the first source / drain contact (170) may be smaller than the height (H16) from the second side (50_S2) of the first rear wiring line to the first side (180_S1) of the first contact connection via.

[0195] FIGS. 14 and FIGS. 15 are drawings for illustrating semiconductor devices according to several embodiments. FIGS. 16 to 18 are drawings for illustrating semiconductor devices according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIGS. 1 to 7.

[0196] Referring to FIG. 14, in a semiconductor device according to some embodiments, the width (W11) of the first surface (50_S1) of the first rear wiring line in the second direction (D2) may be larger than the width (W12) of the second surface (50_S2) of the first rear wiring line in the second direction (D2).

[0197] For example, the first rear wiring line (50) and the second rear wiring line (60) can be formed using an etching process. A conductive film can be formed on the insert insulating film (295). The first rear wiring line (50) and the second rear wiring line (60) can be formed by patterning the conductive film on the insert insulating film (295). Subsequently, a rear interlayer insulating film (295) covering the sidewalls of the first rear wiring line (50) and the second rear wiring line (60) can be formed.

[0198] Referring to FIG. 15, in a semiconductor device according to some embodiments, a first gate insulating film (130) may be disposed between a first gate electrode (120) and a gate isolation structure (120CT).

[0199] The first gate insulating film (130) can be extended in a third direction (D3) along the sidewall of the first gate electrode (120).

[0200] Referring to FIGS. 16 to 18, in a semiconductor device according to some embodiments, active patterns (AP1, AP2, AP3, AP4) each do not include a sheet pattern.

[0201] The active patterns (AP1, AP2, AP3, AP4) may be pin-shaped patterns protruding above the upper surface (105US) of the field insulating film. In FIG. 18, the field insulating film (105) may cover a portion of the sidewall (AP1_SW) of the first active pattern and a portion of the sidewall (AP3_SW) of the third active pattern. Although not shown, the field insulating film (105) may cover a portion of the sidewall of the second active pattern (AP2) and a portion of the sidewall of the fourth active pattern (AP4).

[0202] The first gate structure (GS1) does not include the first inner gate structure (INT_GS1). The second gate structure (GS2) does not include the second inner gate structure (INT_GS2).

[0203] In FIG. 16, the first sub-element isolation structure (160_1) and the second sub-element isolation structure (160_2) can be extended to the lower surface of the first active pattern (AP1_BS) and the lower surface of the second active pattern (AP2_BS).

[0204] In FIG. 17, a first sub-device isolation structure (160_1) and a second sub-device isolation structure (160_2) may be disposed on the upper surface (105US) of a field insulating film. The first sub-device isolation structure (160_1) may wrap around the end of a first active pattern (AP1). The second sub-device isolation structure (160_2) may wrap around the end of a second active pattern (AP2). The first sub-device isolation structure (160_1) and the second sub-device isolation structure (160_2) do not extend to the lower surface (AP1_BS) of the first active pattern and the lower surface (AP2_BS) of the second active pattern. For example, the first sub-device isolation structure (160_1) and the second sub-device isolation structure (160_2) may have the same stacked film structure as the first gate structure (GS1) and the second gate structure (GS2).

[0205] FIG. 19 is a layout diagram illustrating a semiconductor device according to several embodiments. FIG. 20 and FIG. 21 are cross-sectional views taken along A-A and C-C of FIG. 19. For convenience of explanation, the description will focus on the differences from the description using FIG. 1 to 7.

[0206] For reference, a cross-sectional view taken in the second direction (D2) of the portion where the fourth contact connection via (480) and the sixth contact connection via (680) are placed may be substantially the same as FIG. 21.

[0207] Referring to FIGS. 19 to 21, a semiconductor device according to some embodiments may include third to sixth contact connection vias (380, 480, 580, 680).

[0208] The second element isolation structure (165) may be placed on the rear interlayer insulating film (290), the first rear wiring line (50), and the second rear wiring line (60). The second element isolation structure (165) may be placed on the first surface of the first rear wiring line (50_S1 in FIG. 3) and the first surface of the second rear wiring line (60_S1 in FIG. 3).

[0209] A second device isolation structure (165) may be placed between a first active pattern (AP1) and a second active pattern (AP2). A second device isolation structure (165) may be placed between a third active pattern (AP3) and a fourth active pattern (AP4). A second device isolation structure (165) may be placed between a first source / drain pattern (150) and a second source / drain pattern (250). Although not illustrated, a second device isolation structure (165) may be placed between a third source / drain pattern (350) and a fourth source / drain pattern.

[0210] The second element isolation structure (165) can separate the first lower pattern (BP1) and the second lower pattern (BP2). The second element isolation structure (165) can separate the third lower pattern (BP3) and the fourth lower pattern. The first lower pattern (BP1) and the second lower pattern (BP2) can each protrude in a first direction (D1) from the second element isolation structure (165). Although not illustrated, the third lower pattern (BP3) and the fourth lower pattern can each protrude in a first direction (D1) from the second element isolation structure (165).

[0211] A third contact connection via (380) may be placed between the first source / drain contact (170) and the first rear wiring line (50). The third contact connection via (380) may connect the first source / drain contact (170) and the first rear wiring line (50). The third contact connection via (380) contacts the first rear wiring line (50). The third contact connection via (380) overlaps the first source / drain contact (170) in the second direction (D2).

[0212] A fifth contact connection via (580) may be placed between the third source / drain contact (370) and the second rear wiring line (60). The fifth contact connection via (580) may connect the third source / drain contact (370) and the second rear wiring line (60). The fifth contact connection via (580) contacts the second rear wiring line (60). The fifth contact connection via (580) overlaps the third source / drain contact (370) in the second direction (D2).

[0213] The fourth contact connection via (480) can connect the second source / drain contact (270) and the first rear wiring line (50). The third contact connection via (380) overlaps the first source / drain contact (170) in the second direction (D2).

[0214] The sixth contact connection via (680) can connect the fourth source / drain contact (470) and the second rear wiring line (60). The sixth contact connection via (680) overlaps the fourth source / drain contact (470) in the second direction (D2).

[0215] Although not shown, the fourth contact connection via (480) contacts the first rear wiring line (50). The sixth contact connection via (680) contacts the second rear wiring line (60).

[0216] The third contact connection via (380) and the fourth contact connection via (480) can be connected to the first back wiring line (50) by penetrating the source / drain etch stop layer (156) and the field insulating layer (105). The third contact connection via (380) can be spaced apart from the fourth contact connection via (480) in a first direction (D1). The third contact connection via (380) and the fourth contact connection via (480) can be arranged in the first direction (D1).

[0217] The fifth contact connection via (580) and the sixth contact connection via (680) can be connected to the second rear wiring line (60) by penetrating the source / drain etch stop layer (156) and the field insulating layer (105). The fourth contact connection via (480) can be spaced apart from the sixth contact connection via (680) in a first direction (D1). The fourth contact connection via (480) and the sixth contact connection via (680) can be arranged in the first direction (D1).

[0218] The first source / drain contact (170) connected to the third contact connection via (380) is shown to be aligned in the second direction (D2) with the third source / drain contact (370) connected to the fifth contact connection via (580), but this is for convenience of explanation only and is not limited thereto.

[0219] The third contact connection via (380) is described as an example. In a cross-sectional view such as FIG. 21, part of the third contact connection via (380) overlaps with the first source / drain contact (170) in the third direction (D3), and the remainder of the third contact connection via (380) may not overlap with the first source / drain contact (170) in the third direction (D3).

[0220] The third contact connection via (380) may include a first surface (380_S1) and a second surface (380_S2) opposite in the third direction (D3). The first surface (380_S1) of the third contact connection via may be connected to the first source / drain contact (170). The second surface (380_S2) of the third contact connection via may be connected to the first rear wiring line (50). The second surface (380_S2) of the third contact connection via contacts the first rear wiring line (50).

[0221] For example, the height (H13) from the second side (50_S2 in FIG. 3) of the first rear wiring line to the upper surface of the first source / drain contact (170) may be the same as the height (H16) from the second side (50_S2) of the first rear wiring line to the first side (380_S1) of the third contact connection via.

[0222] For example, the height (H15) from the second side (50_S2) of the first rear wiring line to the upper side (105US) of the field insulating film is smaller than the height (H16) from the second side (50_S2) of the first rear wiring line to the first side (380_S1) of the third contact connection via. The height (H12) from the second side (50_S2) of the first rear wiring line to the first side (BP1_US) of the first lower pattern is smaller than the height (H16) from the second side (50_S2) of the first rear wiring line to the first side (380_S1) of the third contact connection via.

[0223] The height (H15) from the second surface (50_S2) of the first rear wiring line to the upper surface (105US) of the field insulating film is greater than the height (H14) from the second surface (50_S2) of the first rear wiring line to the second surface (380_S2) of the third contact connection via. The height (H12) from the second surface (50_S2) of the first rear wiring line to the first surface (BP1_US) of the first lower pattern is greater than the height (H14) from the second surface (50_S2) of the first rear wiring line to the second surface (380_S2) of the third contact connection via.

[0224] A connecting via liner (181) may be placed on the sidewall of the third contact connecting via (380) and the sidewall of the fifth contact connecting via (580). Although not illustrated, a connecting via liner (181) may be placed on the sidewall of the fourth contact connecting via (480) and the sidewall of the sixth contact connecting via (680).

[0225] The third contact connection via (380) may include a third contact connection barrier membrane (380a) and a third contact connection plug (380b). The third contact connection barrier membrane (380a) may extend along the side wall of the third contact connection plug (380b).

[0226] The fifth contact connection via (580) may include a fifth contact connection barrier membrane (580a) and a fifth contact connection plug (580b). The fifth contact connection barrier membrane (580a) may extend along the side wall of the fifth contact connection plug (580b).

[0227] Although not shown, the fourth contact connection via (480) may include a fourth contact connection barrier membrane and a fourth contact connection plug. The sixth contact connection via (680) may include a sixth contact connection barrier membrane and a sixth contact connection plug.

[0228] The description of the third to sixth contact connection vias (380, 480, 580, 680) may be substantially the same as the description of the first and second contact connection vias (180, 280 in FIG. 7).

[0229] The front wiring structure (195) may include front wiring vias (196) and front wiring lines (197). The front wiring structure (195) may not include wiring connection vias (198 in FIG. 6 and FIG. 7).

[0230] The third to sixth contact connection vias (380, 480, 580, 680) are not connected to the first to fourth source / drain contacts (170, 270, 370, 470) through the front wiring line (197).

[0231] FIGS. 22 and FIGS. 23 are drawings illustrating semiconductor devices according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIGS. 19 to 21.

[0232] Referring to FIG. 22, in a semiconductor device according to some embodiments, the first source / drain contact (170) may cover the entire third contact connection via (380).

[0233] The entire third contact connection via (380) may overlap the first source / drain contact (170) and the third direction (D3). From a cross-sectional view, the first source / drain contact (170) may cover the entire first surface (380_S1) of the third contact connection via.

[0234] The height (H13) from the second surface (50_S2 in FIG. 3) of the first rear wiring line to the upper surface of the first source / drain contact (170) may be greater than the height (H16) from the second surface (50_S2) of the first rear wiring line to the first surface (380_S1) of the third contact connection via.

[0235] Referring to FIG. 23, in a semiconductor device according to some embodiments, the entire third contact connection via (380) may not overlap with the first source / drain contact (170) in the third direction (D3).

[0236] The connection conductive pattern (199) can connect the third contact connection via (180) and the first source / drain contact (170). The connection conductive pattern (199) can be disposed on the first surface (380_S1) of the third contact connection via and on the upper surface of the first source / drain contact (170). The connection conductive pattern (199) includes a conductive material.

[0237] Of course, the details regarding the third contact connection via (380) described in FIGS. 22 and 23 can be applied to the fourth to sixth contact connection vias (480, 580, 680).

[0238] FIGS. 24 to 31 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. Using FIGS. 24 to 31, a semiconductor device described using FIGS. 1 to 7 can be manufactured.

[0239] Referring to FIGS. 1, 24 and 25, a first source / drain pattern (150) is formed on a first lower pattern (BP1). A third source / drain pattern (350) is formed on a third lower pattern (BP3). The first lower pattern (BP1) and the third lower pattern (BP3) may protrude from the substrate (100).

[0240] A source / drain etch stop layer (156) is formed along the profiles of the first source / drain pattern (150) and the third source / drain pattern (350). The source / drain etch stop layer (156) is formed along the upper surface (105US) of the field insulating film. A first upper interlayer insulating film (190) is formed on the source / drain etch stop layer (156).

[0241] A gate isolation structure (120CT) may be formed within the first upper interlayer insulating film (190). Subsequently, a first source / drain contact (170) is formed on the first source / drain pattern (150). A third source / drain contact (370) is formed on the third source / drain pattern (350).

[0242] Additionally, a first contact connection via (180) and a second contact connection via (280) extending in a third direction (D3) are formed between the first sub-element isolation structure (160_1) and the second sub-element isolation structure (160_2).

[0243] Next, a front wiring via (196), a front wiring line (197), and a wiring connection via (198) are formed.

[0244] Referring to FIGS. 26 and 27, the substrate (100) is removed to expose the first lower pattern (BP1) and the third lower pattern (BP3).

[0245] While the first lower pattern (BP1) and the third lower pattern (BP3) are exposed, the first contact connection via (180) and the second contact connection via (280) may also be exposed.

[0246] Referring to FIGS. 28 and 29, a portion of the field insulating film (105), a portion of the first lower pattern (BP1), and a portion of the third lower pattern (BP3) are removed.

[0247] Through this, a portion of the first contact connection via (180) and a portion of the second contact connection via (280) may protrude beyond the field insulating film (105). Additionally, a portion of the first contact connection via (180) and a portion of the second contact connection via (280) may protrude beyond the second surface (BP1_BS) of the first lower pattern and the second surface (BP3_BS) of the third lower pattern.

[0248] Referring to FIGS. 30 and 31, the insertion insulating film (295) is formed on the second surface (BP1_BS) of the first lower pattern and the second surface (BP3_BS) of the third lower pattern.

[0249] The insertion insulating film (295) may also be formed on the field insulating film (105). After the insertion insulating film (295) is formed, the first contact connection via (180) and the second contact connection via (280) are exposed.

[0250] Referring to FIGS. 2 to 7, the rear interlayer insulating film (290) may be formed on the insert insulating film (295). The first rear wiring line (50) and the second rear wiring line (60) may be formed within the rear interlayer insulating film (290).

[0251] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0252] 50, 60: Rear wiring lines 105: Field insulation film 120, 220: Gate electrodes 130, 230: Gate insulating film 160, 165: Device isolation structure 175, 275: Gate contact 195: Front wiring structure 197: Front wiring line 170, 270, 370, 470: Source / Drain Contact 180, 280, 380, 480, 580, 680: Contact connection vias AP1, AP2, AP3, AP4: Activation pattern BP1, BP2, BP3: Lower pattern NS1, NS2, NS3: Sheet Pattern

Claims

Claim 1 A semiconductor device comprising: a rear interlayer insulating film; a rear wiring line disposed within the rear interlayer insulating film and having a line shape, comprising a first surface and a second surface opposite each other in a first direction; a pin-shaped pattern disposed on the first surface of the rear wiring line and extending in a second direction; a field insulating film disposed on the sidewall of the pin-shaped pattern; a source / drain pattern on the pin-shaped pattern; a source / drain contact disposed on the source / drain pattern and connected to the source / drain pattern; and a contact connection via connecting the rear wiring line and the source / drain contact and contacting the rear wiring line, wherein the contact connection via comprises a first surface connected to the source / drain contact and a second surface contacting the rear wiring line, and the height from the second surface of the rear wiring line to the upper surface of the field insulating film is smaller than the height from the second surface of the rear wiring line to the first surface of the contact connection via. Claim 2 In claim 1, the contact connection via comprises a contact connection plug and a contact connection barrier film extending along the sidewall of the contact connection plug, and the contact connection plug is a semiconductor device in contact with the rear wiring line. Claim 3 In claim 1, the contact connection via comprises a contact connection plug and a contact connection barrier film extending along the sidewall of the contact connection plug, and the contact connection barrier film is a semiconductor device disposed between the contact connection plug and the rear wiring line. Claim 4 A semiconductor device according to claim 1, further comprising an insertion insulating film disposed between the fin-shaped pattern and the rear interlayer insulating film, wherein the fin-shaped pattern comprises a lower surface facing the rear interlayer insulating film, and the insertion insulating film is in contact with the lower surface of the fin-shaped pattern. Claim 5 A semiconductor device according to claim 1, wherein the height from the second surface of the rear wiring line to the lowest part of the pin-shaped pattern is greater than the height from the second surface of the rear wiring line to the second surface of the contact connection via. Claim 6 A semiconductor device according to claim 1, further comprising a first element isolation structure disposed on the rear wiring line and extending in a third direction, and a second element isolation structure disposed on the rear wiring line and extending in the third direction and spaced apart from the first element isolation structure in the second direction, wherein the contact connection via is disposed between the first element isolation structure and the second element isolation structure. Claim 7 A semiconductor device according to claim 6, further comprising a front wiring structure disposed on the source / drain contact, wherein the front wiring structure comprises a front wiring line extending in the second direction, the source / drain contact disposed between the source / drain pattern and the front wiring line, and the front wiring line connecting the source / drain contact and the contact connection via. Claim 8 In claim 1, the contact connection via is a semiconductor device that overlaps with the source / drain contact in a third direction. Claim 9 A rear interlayer insulating film; a rear wiring line disposed within the rear interlayer insulating film, comprising a first surface and a second surface opposite each other in a first direction, and having a line shape; a first device isolation structure disposed on the rear wiring line and extending in a second direction; a second device isolation structure disposed on the rear wiring line and extending in the second direction and spaced apart from the first device isolation structure in a third direction; a pin-shaped pattern disposed on the rear wiring line and extending in the third direction; a gate electrode disposed on the pin-shaped pattern and extending in the second direction; a source / drain pattern disposed on the pin-shaped pattern and connected to the pin-shaped pattern; a source / drain contact disposed on the source / drain pattern and connected to the source / drain pattern; a contact connection via disposed between the first device isolation structure and the second device isolation structure and contacting the rear wiring line, wherein the width of the contact connection via increases as it moves away from the rear wiring line; A semiconductor device comprising a front wiring line disposed on the first element isolation structure and the second element isolation structure, extending in the third direction, and connecting the source / drain contact and the contact connection via. Claim 10 A pin-shaped pattern extending in a first direction and including a first surface and a second surface opposite to each other in a second direction; a sheet pattern disposed on the first surface of the pin-shaped pattern and spaced apart from the pin-shaped pattern in the second direction; a gate electrode disposed on the first surface of the pin-shaped pattern, extending in a third direction, and surrounding the sheet pattern; a source / drain pattern disposed on the first surface of the pin-shaped pattern and in contact with the sheet pattern; a source / drain contact disposed on the source / drain pattern and connected to the source / drain pattern; an insertion insulating film disposed on the second surface of the pin-shaped pattern and in contact with the second surface of the pin-shaped pattern; a rear wiring line disposed on the second surface of the pin-shaped pattern, extending in the first direction, and including a first surface and a second surface opposite to each other in the second direction; A semiconductor device comprising a contact connection via that connects the rear wiring line and the source / drain contact and contacts the rear wiring line, wherein the contact connection via comprises a first surface connected to the source / drain contact and a second surface contacting the rear wiring line, and the height from the second surface of the rear wiring line to the first surface of the pin-shaped pattern is smaller than the height from the second surface of the rear wiring line to the first surface of the contact connection via.

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