Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package comprises a package substrate including a first surface and a second surface opposite each other, a first-1 substrate pad and a first-2 substrate pad having a maximum width smaller than the maximum width of the first-1 substrate pad on the first surface of the package substrate, a first connection terminal disposed on the first-1 and first-2 substrate pads, a second-1 substrate pad and a second-2 substrate pad having a maximum width smaller than the maximum width of the second-1 substrate pad on the second surface of the package substrate, an interposer disposed on the second surface of the package substrate, a second connection terminal between the second-1 and second-2 substrate pads and the interposer, and a first semiconductor chip disposed on the interposer, wherein the first-1 substrate pad and the second-1 substrate pad transmit a first signal, a ground signal, or a power signal, and the first-2 substrate pad and the second-2 substrate pad transmit a second signal having a speed faster than the first signal.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0002] Due to the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In line with this trend, high package density or high mounting density is emerging as a critical factor. One package developed in response to this is the Ball Grid Array (BGA) package. Compared to conventional plastic packages, BGA packages offer advantages such as the ability to reduce the mounting area on the module board and superior electrical characteristics.

[0003] Unlike conventional plastic packages, BGA packages use a printed circuit board instead of a lead frame. Since the printed circuit board can provide the front surface opposite the side where the semiconductor chip is mounted as a formation area for solder balls, which serve as external connection terminals, it offers an advantage in terms of mounting density on the module board. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor package with improved product reliability.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises a package substrate having a first surface and a second surface opposite to each other, a first-1 substrate pad and a first-2 substrate pad having a maximum width smaller than the maximum width of the first-1 substrate pad on the first surface of the package substrate, a first connection terminal disposed on the first-1 and first-2 substrate pads, a second-1 substrate pad and a second-2 substrate pad having a maximum width smaller than the maximum width of the second-1 substrate pad on the second surface of the package substrate, an interposer disposed on the second surface of the package substrate, a second connection terminal between the second-1 and second-2 substrate pads and the interposer, and a first semiconductor chip disposed on the interposer, wherein the first-1 substrate pad and the second-1 substrate pad transmit a first signal, a ground signal, or a power signal, and the first-2 substrate pad and the second-2 substrate pad transmit a second signal having a speed faster than the first signal.

[0007] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises: a package substrate including a first surface and a second surface opposite to each other; a first connection terminal disposed on the first surface of the package substrate; an interposer on the second surface of the package substrate including a third surface opposite to the second surface and a fourth surface opposite to the third surface; on the third surface of the interposer, a first-1 connection pad and a first-2 connection pad having a maximum width smaller than the maximum width of the first-1 connection pad; a second connection terminal between the first-1 and first-2 connection pads and the package substrate; on the fourth surface of the interposer, a second-1 connection pad and a second-2 connection pad having the same maximum width as each other; a semiconductor chip disposed on the fourth surface of the interposer; and a third connection terminal between the second-1 and second-2 connection pads and the semiconductor chip, wherein the first-1 connection pad and the second-1 connection pad transmit a first signal, a ground signal, or a power signal, and the first-2 connection pad and the second-2 connection pad transmit more than the first signal It transmits a second signal with high speed.

[0008] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises: a package substrate having a first surface and a second surface opposite to each other; on the first surface of the package substrate, a first-1 substrate pad and a first-2 substrate pad having a maximum width smaller than the maximum width of the first-1 substrate pad; a first connection terminal disposed on the first-1 and first-2 substrate pads; on the second surface of the package substrate, a second-1 substrate pad and a second-2 substrate pad having a maximum width smaller than the maximum width of the second-1 substrate pad; on the second surface of the package substrate, an interposer having a third surface opposite to the second surface and a fourth surface opposite to the third surface; on the third surface of the interposer, a first-1 connection pad and a first-2 connection pad having a maximum width smaller than the maximum width of the first-1 connection pad; a second connection terminal disposed between the second-1 substrate pad and the first-1 connection pad and between the second-2 substrate pad and the first-2 connection pad; and on the fourth surface of the interposer, having a maximum width equal to each other. A semiconductor chip disposed on a fourth surface of an interposer, a second-1 connection pad and a second-2 connection pad, a first chip pad and a second chip pad having the same width as each other on a fifth surface of the semiconductor chip opposite to the fourth surface of the interposer, and a third connection terminal disposed between the second-1 connection pad and the first chip pad and between the second-2 connection pad and the second chip pad, wherein the first-1 substrate pad, the second-1 substrate pad, the first-1 connection pad, the second-1 connection pad and the first chip pad transmit a first signal, a ground signal, or a power signal, and the first-2 substrate pad, the second-2 substrate pad, the first-2 connection pad, the second-2 connection pad and the second chip pad transmit a second signal having a different speed from the first signal.

[0009] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0010] FIG. 1 is a drawing for illustrating a semiconductor package according to some embodiments. Figure 2 is a drawing for explaining the first substrate pad of Figure 1. Figure 3 is a drawing for explaining the second substrate pad of Figure 1. FIG. 4 is a drawing for explaining the first connection pad of FIG. 1. Figure 5 is a drawing for explaining the second connection pad of Figure 1. Figure 6 is a graph showing the loss of high-speed signals according to the size of the first-2 substrate pad and the second-1 connection pad of Figure 1. FIGS. 7 to 13 are drawings for illustrating semiconductor packages according to some embodiments. Specific details for implementing the invention

[0011] FIG. 1 is a drawing for illustrating a semiconductor package according to some embodiments. FIG. 2 is a drawing for illustrating a first substrate pad of FIG. 1. FIG. 3 is a drawing for illustrating a second substrate pad of FIG. 1. FIG. 4 is a drawing for illustrating a first connection pad of FIG. 1. FIG. 5 is a drawing for illustrating a second connection pad of FIG. 1. FIG. 6 is a graph showing the loss of a high-speed signal according to the size of the first-second substrate pad and the second-first connection pad of FIG. 1.

[0012] Referring to FIGS. 1 to 5, a semiconductor package according to some embodiments comprises a package substrate (100), a first substrate pad (111, 112), a first solder resist (110), a second substrate pad (121, 122), a second solder resist (120), a first wiring pattern (101, 102), a first connection terminal (131, 132), a first interposer (200), a first connection pad (211, 212), a first passivation layer (210), a second connection pad (221, 222), a second passivation layer (220), a second wiring pattern (201, 202), a second connection terminal (231, 232), a first underfill material layer (240), a first semiconductor chip (300), a first chip pad (315), a third passivation layer (310), a third connection terminal (330). It may include a second underfill material layer (340) and a heat dissipation structure (500).

[0013] The package substrate (100) may include a first surface (100a) and a second surface (100b) that are opposite to each other. The package substrate (100) may be, for example, a printed circuit board (PCB). When the package substrate (100) is a printed circuit board, the package substrate (100) may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the package substrate (100) may include at least one material selected from FR4, tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer.

[0014] The first substrate pads (111, 112) may be disposed on the first surface (100a) of the package substrate (100). The first solder resist (110) may be disposed on the first surface (100a) of the package substrate (100). The first substrate pads (111, 112) may be disposed within the first solder resist (110). The first solder resist (110) may expose at least a portion of the first substrate pads (111, 112).

[0015] The second substrate pads (121, 122) may be disposed on the second surface (100b) of the package substrate (100). The second solder resist (120) may be disposed on the second surface (100b) of the package substrate (100). The second substrate pads (121, 122) may be disposed within the second solder resist (120). The second solder resist (120) may expose at least a portion of the second substrate pads (121, 122). The first and second substrate pads (111, 112, 121, 122) may each include a metallic material such as, for example, copper (Cu) or aluminum (Al), but are not limited thereto.

[0016] The first wiring pattern (101, 102) may be disposed within the package substrate (100). The first wiring pattern (101, 102) may include a plurality of wirings and vias spaced apart in a direction toward the second surface (100b) from the first surface (100a) of the package substrate (100) or in a direction parallel to the first surface (100a). The first wiring pattern (101, 102) may include a metallic material such as copper (Cu) or aluminum (Al), but is not limited thereto. The number, spacing, arrangement, etc. of the first wiring pattern (101, 102) are merely examples and are not limited thereto.

[0017] The first wiring pattern (101, 102) can perform various functions depending on the design. For example, the first wiring pattern (101, 102) may include a ground (GND) pattern, a power (PWR) pattern, and a signal (S) pattern. The signal (S) pattern can transmit various signals, such as data signals, excluding the ground (GND) pattern and the power (PWR) pattern. The first substrate pad (111, 112) and the second substrate pad (121, 122) are connected to the first wiring pattern (101, 102) to transmit ground, power, or signals.

[0018] In some embodiments, the first-1 wiring pattern (101) may include a first signal pattern among a ground (GND) pattern, a power (PWR) pattern, or a signal (S) pattern, and the first-2 wiring pattern (102) may include a second signal pattern among the signal (S) patterns. The second signal transmitted through the second signal pattern may be faster than the first signal transmitted through the first signal pattern. For example, the first signal may be a general signal and the second signal may be a high-speed signal. The first-1 substrate pad (111) and the second-1 substrate pad (121) may be connected to the first-1 wiring pattern (101) to transmit ground, power, or the first signal, and the first-2 substrate pad (112) and the second-2 substrate pad (122) may be connected to the first-2 wiring pattern (102) to transmit the second signal. The number, spacing, arrangement, etc. of the first substrate pads (111, 112) and the second substrate pads (121, 122) are merely examples and are not limited thereto.

[0019] In some embodiments, the maximum width (W11) of the first-1 substrate pad (111) and the maximum width (W12) of the first-2 substrate pad (112) may be different. The maximum width (W12) of the first-2 substrate pad (112) that transmits the second signal may be smaller than the maximum width (W11) of the first-1 substrate pad (111) that does not transmit the second signal. For example, the maximum width (W11) of the first-1 substrate pad (111) may be the diameter of the first-1 substrate pad (111), and the maximum width (W12) of the first-2 substrate pad (112) may be the diameter of the first-2 substrate pad (112).

[0020] In some embodiments, the maximum width (W21) of the second-1 substrate pad (121) and the maximum width (W22) of the second-2 substrate pad (122) may be different. The maximum width (W22) of the second-2 substrate pad (122) that transmits the second signal may be smaller than the maximum width (W21) of the second-1 substrate pad (121) that does not transmit the second signal. For example, the maximum width (W21) of the second-1 substrate pad (121) may be the diameter of the second-1 substrate pad (121), and the maximum width (W22) of the second-2 substrate pad (122) may be the diameter of the second-2 substrate pad (122).

[0021] The first connection terminal (131, 132) may be placed on the first substrate pad (111, 112). The first connection terminal (131) may be placed on the first substrate pad (111) and electrically connected to the first substrate pad (111), and the first connection terminal (132) may be placed on the first substrate pad (112) and electrically connected to the first substrate pad (112). The first connection terminal (131) may transmit ground, power, or the first signal, and the first connection terminal (132) may transmit the second signal.

[0022] For example, in the direction from the first surface (100a) of the package substrate (100) toward the second surface (100b), the bottom surface of the first-1 connection terminal (131) may be positioned substantially on the same plane as the bottom surface of the first-2 connection terminal (132). Alternatively, the maximum height from the first surface (100a) of the package substrate (100) to the first-1 connection terminal (131) may be substantially the same as the maximum height from the first surface (100a) of the package substrate (100) to the first-2 connection terminal (132).

[0023] In some embodiments, the maximum width (S11) of the first-1 connection terminal (131) may differ from the maximum width (S12) of the first-2 connection terminal (132). The maximum width (S12) of the first-2 connection terminal (132) that transmits the second signal may be larger than the maximum width (S11) of the first-1 connection terminal (131) that does not transmit the second signal. For example, substantially equal amounts of free connection terminals are formed on the first-1 and first-2 substrate pads (111, 112), respectively, but the maximum width (W11) of the first-1 substrate pad (111) and the maximum width (W12) of the first-2 substrate pad (112) may differ, so that the maximum width (S11) of the first-1 connection terminal (131) and the maximum width (S12) of the first-2 connection terminal (132) may differ from each other.

[0024] A first interposer (200) may be disposed on a package substrate (100). A first interposer (200) may be disposed on a second surface (100b) of the package substrate (100). The first interposer (200) may include a third surface (200a) and a fourth surface (200b) that are opposite to each other. The third surface (200a) of the first interposer (200) may be opposite to the second surface (200b) of the package substrate (100). The first interposer (200) may be, for example, a silicon interposer. Or, the first interposer (200) may include at least one of, for example, glass, ceramic, or plastic.

[0025] The first connection pads (211, 212) may be disposed on the third surface (200a) of the first interposer (200). The first passivation layer (210) may be disposed on the third surface (200a) of the first interposer (200). The first passivation layer (210) may expose at least a portion of the first connection pads (211, 212).

[0026] The second connection pads (221, 222) may be disposed on the fourth surface (200b) of the first interposer (200). The second passivation layer (220) may be disposed on the fourth surface (200b) of the first interposer (200). The second connection pads (221, 222) may be disposed within the second passivation layer (220). The second passivation layer (220) may expose at least a portion of the second connection pads (221, 222). The first and second connection pads (211, 212, 221, 222) may each include a metallic material such as, for example, copper (Cu) or aluminum (Al), but are not limited thereto.

[0027] The second wiring pattern (201, 202) may be placed within the first interposer (200). The second wiring pattern (201, 202) may include a plurality of wirings and vias spaced apart in a direction toward the third surface (200a) of the first interposer (200) toward the fourth surface (200b) or in a direction parallel to the third surface (200a). The second wiring pattern (201, 202) may include a metallic material such as copper (Cu) or aluminum (Al), but is not limited thereto. The number, spacing, arrangement, etc. of the second wiring pattern (201, 202) are merely examples and are not limited thereto.

[0028] In some embodiments, the second-1 wiring pattern (201) may be electrically connected to the first-1 wiring pattern (101) and the second-2 wiring pattern (202) may be electrically connected to the first-2 wiring pattern (102). The second-1 wiring pattern (201) may include a ground (GND) pattern, a power (PWR) pattern, or the first signal pattern, and the second-2 wiring pattern (202) may include the second signal pattern. The first-1 connection pad (211) and the second-1 connection pad (221) may be connected to the second-1 wiring pattern (201) to transmit ground, power, or the first signal, and the first-2 connection pad (212) and the second-2 connection pad (222) may be connected to the second-2 wiring pattern (202) to transmit the second signal. The number, spacing, arrangement, etc. of the first connecting pad (211, 212) and the second connecting pad (221, 222) are merely examples and are not limited thereto.

[0029] In some embodiments, the maximum width (W31) of the first-1 connection pad (211) and the maximum width (W32) of the first-2 connection pad (212) may be different. The maximum width (W22) of the first-2 connection pad (212) that transmits the second signal may be smaller than the maximum width (W31) of the first-1 connection pad (211) that does not transmit the second signal. For example, the maximum width (W31) of the first-1 connection pad (211) may be the diameter of the first-1 substrate pad (111), and the maximum width (W32) of the first-2 connection pad (212) may be the diameter of the first-2 substrate pad (112).

[0030] In some embodiments, the maximum width (W4) of the second-1 connection pad (221) that does not transmit the second signal and the maximum width (W4) of the second-2 connection pad (222) that transmits the second signal may be substantially the same. For example, the maximum width (W4) of the second-1 connection pad (221) may be the diameter of the second-1 connection pad (221), and the maximum width (W4) of the second-2 connection pad (222) may be the diameter of the second-2 connection pad (222).

[0031] The second connection terminal (231, 232) may be positioned between the package substrate (100) and the first interposer (200). The second connection terminal (231, 232) may be positioned between the second substrate pad (121, 122) and the first connection pad (211, 212). The second-1 connection terminal (231) may be positioned on the second-1 substrate pad (121) and the first-1 connection pad (211) to be electrically connected to the second-1 substrate pad (121) and the first-1 connection pad (211), and the second-2 connection terminal (232) may be positioned on the second-2 substrate pad (122) and the first-2 connection pad (212) to be electrically connected to the second-2 substrate pad (122) and the first-2 connection pad (212). The 2-1 connection terminal (231) can transmit ground, power, or the first signal, and the 2-2 connection terminal (232) can transmit the second signal.

[0032] In some embodiments, the maximum width (S21) of the second-1 connection terminal (231) may differ from the maximum width (S22) of the second-2 connection terminal (232). The maximum width (S22) of the second-2 connection terminal (232) that transmits the second signal may be larger than the maximum width (S21) of the second-1 connection terminal (231) that does not transmit the second signal. This may be due to the manufacturing process of the second connection terminals (231, 232). For example, substantially equal amounts of free connection terminals are formed on the second substrate pad (121, 122) or the first connection pad (211, 212), but the maximum width (W21) of the second-1 substrate pad (121) and the maximum width (W22) of the second-2 substrate pad (122) are different, and the maximum width (W31) of the first-1 connection pad (211) and the maximum width (W32) of the first-2 connection pad (212) are different, so that the maximum width (S21) of the second-1 connection terminal (231) and the maximum width (S22) of the second-2 connection terminal (232) may be different from each other.

[0033] The first underfill material layer (240) may be disposed between the package substrate (100) and the first interposer (200). The first underfill material layer (240) may fill the space between the package substrate (100) and the first interposer (200). The first underfill material layer (240) may fill the space between the second connection terminals (231, 232) and may wrap the second connection terminals (231, 232). Unlike what is illustrated, the first underfill material layer (240) may extend further along the sidewalls of the first passivation layer (210) and the first interposer (200). The first underfill material layer (240) may protect the second connection terminals (231, 232).

[0034] A first semiconductor chip (300) may be placed on a first interposer (200). A first semiconductor chip (300) may be placed on a fourth surface (200b) of the first interposer (200). The first semiconductor chip (300) may include a fifth surface (300a) and a sixth surface (300b) that are opposite to each other on the first interposer (200). The fifth surface (300a) of the first semiconductor chip (300) may be opposite to the fourth surface (200b) of the first interposer (200).

[0035] The first semiconductor chip (300) may be a logic semiconductor chip or a memory semiconductor chip. The logic semiconductor chip may be, for example, an application processor (AP) such as a CPU (Central Processing Unit), GPU (Graphic Processing Unit), FPGA (Field-Programmable Gate Array), digital signal processor, encryption processor, microprocessor, microcontroller, or ASIC (Application-Specific IC), but is not limited thereto. The memory semiconductor chip may be a volatile memory such as, for example, DRAM (dynamic random access memory) or SRAM (static random access memory), or a non-volatile memory such as Flash Memory, PRAM (Phase-change Random Access Memory), MRAM (Magnetic Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory).

[0036] The first chip pad (315) may be placed on the fifth surface (300a) of the first semiconductor chip (300). The first chip pad (315) may include a metallic material such as copper (Cu) or aluminum (Al), for example, but is not limited thereto. The number, spacing, and arrangement of the first chip pads (315) are merely examples and are not limited thereto.

[0037] The third passivation layer (310) may be disposed on the fifth surface (300a) of the first semiconductor chip (300). The third passivation layer (310) may expose at least a portion of the first chip pad (315). The first to third passivation layers (210, 220, 310) may each comprise silicon nitride. Alternatively, the first to third passivation layers (210, 220, 310) may each be composed of a passivation material, BCB (benzocyclobutene), polybenzene oxazole, polyimide, epoxy, silicon oxide, silicon nitride, or a combination thereof.

[0038] The third connection terminal (330) may be placed between the first interposer (200) and the first semiconductor chip (300). The third connection terminal (330) may be placed between the second connection pad (221, 222) and the first chip pad (315). The third connection terminal (330) may be placed on the second connection pad (221, 222) and the first chip pad (315) so as to be electrically connected to the second connection pad (221, 222) and the first chip pad (315). The third connection terminal (330) may be electrically connected to the second-first connection pad (221) to transmit ground, power, or the first signal, or electrically connected to the second-second connection pad (222) to transmit the second signal. Accordingly, the first chip pad (315) may transmit ground, power, or the first signal, or transmit the second signal.

[0039] In some embodiments, the first chip pad (315) may have substantially the same maximum width. The maximum width of the first chip pad (315) may be the diameter of the first chip pad (315). That is, the first chip pad (315) transmitting ground, power, or the first signal and the first chip pad (315) transmitting the second signal may have substantially the same maximum width. The third connection terminal (330) may have substantially the same maximum width. That is, the third connection terminal (330) transmitting ground, power, or the first signal and the third connection terminal (330) transmitting the second signal may have substantially the same maximum width.

[0040] The first to third connection terminals (130, 230, 330) may be, for example, solder bumps, but are not limited thereto. The first to third connection terminals (130, 230, 330) may each have various shapes such as lands, balls, pins, and pillars. The number, spacing, and arrangement of the first to third connection terminals (130, 230, 330) are not limited to those depicted and may vary depending on the design. The sizes of the first to third connection terminals (130, 230, 330) may differ from each other. For example, the size of the first connection terminal (130) may be larger than the size of the second connection terminal (230), and the size of the second connection terminal (230) may be larger than the size of the third connection terminal (330).

[0041] The first to third connecting terminals (130, 230, 330) may each include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but are not limited thereto.

[0042] The second underfill material layer (340) may be placed between the first interposer (200) and the first semiconductor chip (300). The second underfill material layer (340) may fill the space between the first interposer (200) and the first semiconductor chip (300). The second underfill material layer (340) may fill the space between the third connection terminals (330) and may wrap the third connection terminals (330). Unlike what is illustrated, the second underfill material layer (340) may extend further along the sidewalls of the third passivation layer (310) and the first semiconductor chip (300). The second underfill material layer (340) may protect the third connection terminals (330). The first underfill material layer (240) and the second underfill material layer (340) may each include an insulating polymer material such as, for example, epoxy molding compound (EMC), but are not limited thereto.

[0043] In some embodiments, the heat dissipation structure (500) is disposed on a second surface (100b) of the package substrate (100) and may cover the first interposer (200) and the first semiconductor chip (300). The heat dissipation structure (500) may be adhered, for example, to a sixth surface (300b) of the first semiconductor chip (300). The heat dissipation structure (500) may have various shapes different from those shown in the drawings. The heat dissipation structure (500) may include, for example, a metal or metal alloy including gold (Au), silver (Ag), copper (Cu), iron (Fe), etc., or a conductive material such as graphite, graphene, etc. The heat dissipation structure (500) may be attached to the package substrate (100), for example, by an adhesive. The adhesive may be a thermally conductive adhesive tape, a thermally conductive grease, a thermally conductive adhesive, etc.

[0044] The first solder resist (110) may cover at least a portion of the first substrate pads (111, 112). An impedance discontinuity may occur due to the capacitance caused by the first solder resist (110) between the first connection terminals (131, 132) and the first substrate pads (111, 112), and between the first connection terminals (131, 132) and the first substrate pads (111, 112). When a high-speed signal passes through the impedance discontinuity, some of it may be reflected, and consequently, the high-speed signal may be distorted, which may lower the quality of the high-speed signal. Such impedance discontinuity may also occur in the second substrate pads (121, 122), the first connection pads (211, 212), the second connection pads (221, 222), and the first chip pad (315).

[0045] However, in some embodiments of the semiconductor package, the maximum width of the first-2 substrate pad (112), the second-2 substrate pad (122), and the first-2 connection pad (212), to which a high-speed signal is transmitted, is smaller than the maximum width of the first-1 substrate pad (111), the second-1 substrate pad (121), and the first-1 connection pad (211), to which a high-speed signal is not transmitted, respectively. Therefore, the capacitance generated at the first-2 substrate pad (112), the second-2 substrate pad (122), and the first-2 connection pad (212) can be reduced, and the impedance discontinuity section can also be reduced.

[0046] Meanwhile, the second-2 connection pad (222) and the first chip pad (315), to which a high-speed signal is transmitted, are relatively small compared to the first-2 substrate pad (112), the second-2 substrate pad (122), and the first-2 connection pad (212). Therefore, the capacitance generated at the second-2 connection pad (222) and the first chip pad (315) is negligible compared to the capacitance generated at the first-2 substrate pad (112), the second-2 substrate pad (122), and the first-2 connection pad (212). Therefore, even if the maximum width of the second-2 connection pad (222) and the first chip pad (315) is substantially the same as the maximum width of the second-1 connection pad (221) and the first chip pad (315) that do not transmit high-speed signals, the quality of the high-speed signal can be improved or enhanced because the effect of reducing the capacitance generated in the first-2 substrate pad (112), the second-2 substrate pad (122), and the first-2 connection pad (212) is significant.

[0047] Specifically, when the maximum width of the first-2 substrate pad (112) is 380 μm, the capacitance generated at the first-2 substrate pad (112) is 80 fF, and when the maximum width of the first-2 connection pad (212) is 200 μm, the capacitance generated at the first-2 connection pad (212) is 50 fF. When the maximum width of the first-2 substrate pad (112) is 380 μm, the capacitance generated at the first-2 substrate pad (112) is 80 fF, and when the maximum width of the first-2 connection pad (212) is 200 μm, the capacitance generated at the first-2 connection pad (212) is 50 fF. When the maximum width of the first-2 substrate pad (112) and the maximum width of the first-2 substrate pad (112) are each reduced by about 15%, the capacitance generated in the first-2 substrate pad (112) and the capacitance generated in the first-2 connection pad (212) are each reduced by about 30%.

[0048] In FIG. 6, (A) is a graph showing the loss of a high-speed signal according to frequency when the maximum widths of the first substrate pads (111, 112) are equal to each other, the maximum widths of the second substrate pads (121, 122) are equal to each other, the maximum widths of the first connection pads (211, 212) are equal to each other, the maximum widths of the second connection pads (221, 222) are equal to each other, and the maximum widths of the first chip pads (315) are equal to each other. (B) is a graph showing the loss of a high-speed signal according to frequency when, in the case of (A), the maximum width of the first-second substrate pad (112) is made smaller than the maximum width of the first-first substrate pad (111), and the maximum width of the first-second connection pad (212) is made smaller than the maximum width of the first-first connection pad (211). If the maximum width of the first-second substrate pad (112) through which the high-speed signal is transmitted and the maximum width of the first-second connection pad (212) are reduced, the loss of the high-speed signal can be reduced. Accordingly, a high-speed signal having a wider frequency range can be used.

[0049] FIGS. 7 through 13 are drawings for illustrating semiconductor packages according to several embodiments. For reference, FIG. 13 is a drawing for illustrating the 2-1 connection pad and the 2-2 connection pad of FIG. 12. For convenience of explanation, the explanation will focus on the differences from the explanation using FIGS. 1 through 6.

[0050] Referring to FIG. 7, a semiconductor package according to some embodiments may include a molding layer (550).

[0051] A molding layer (550) may be disposed on a second surface (100b) of a package substrate (100). The molding layer (550) may cover the first interposer (200) and the first semiconductor chip (300) on the second solder resist (120). The molding layer (550) may cover the sidewalls of the first interposer (200) and the sidewalls of the first semiconductor chip (300). The molding layer (550) may, for example, cover the upper surface of the first semiconductor chip (300), but is not limited thereto. The molding layer (550) may, for another example, expose the upper surface of the first semiconductor chip (300). That is, the upper surface of the molding layer (550) may be disposed substantially on the same plane as the upper surface of the first semiconductor chip (300).

[0052] The molding layer (550) may, for example, cover the first and second underfill material layers (240, 340), but is not limited thereto. Unlike what is illustrated, the molding layer (550) may surround the second connection terminal (231, 232) and the third connection terminal (330) instead of the first and second underfill material layers (240, 340) and fill the space between the second connection terminal (231, 232) and the third connection terminal (330).

[0053] The molding layer (550) may include, for example, an epoxy molding compound (EMC) or two or more types of silicone hybrid materials. However, the technical concept of the present invention is not limited thereto.

[0054] Referring to FIG. 8, a semiconductor package according to some embodiments may further include a second semiconductor chip (400).

[0055] The second semiconductor chip (400) may be placed on the first interposer (200). The second semiconductor chip (400) may be placed on the fourth surface (200b) of the first interposer (200). The second semiconductor chip (400) may be placed on the fourth surface (200b) of the first interposer (200) spaced apart from the first semiconductor chip (300). The second semiconductor chip (400) may be a logic semiconductor chip or a memory semiconductor chip.

[0056] The second chip pad (415) may be placed on the second semiconductor chip (400). The second chip pad (415) may face the fourth surface (200b) of the first interposer (200). The second chip pad (415) may include a metallic material such as copper (Cu) or aluminum (Al), for example, but is not limited thereto. The number, spacing, arrangement, etc. of the second chip pads (415) are merely examples and are not limited thereto.

[0057] The fourth passivation layer (410) may be disposed on the second semiconductor chip (400). The fourth passivation layer (410) may face the fourth surface (200b) of the first interposer (200). The fourth passivation layer (410) may expose at least a portion of the second chip pad (415). The fourth passivation layer (410) may comprise silicon nitride. Alternatively, the fourth passivation layer (410) may be composed of a passivation material, BCB (benzocyclobutene), polybenzene oxazole, polyimide, epoxy, silicon oxide, silicon nitride, or a combination thereof.

[0058] The fourth connection terminal (430) may be placed between the first interposer (200) and the second semiconductor chip (400). The fourth connection terminal (430) may be placed between the second connection pad (221, 222) and the second chip pad (415). The fourth connection terminal (430) may be placed on the second connection pad (221, 222) and the second chip pad (415) so as to be electrically connected to the second connection pad (221, 222) and the second chip pad (415). The fourth connection terminal (430) may be electrically connected to the second-1 connection pad (221) to transmit ground, power, or the first signal, or electrically connected to the second-2 connection pad (222) to transmit the second signal. Accordingly, the second chip pad (415) may transmit ground, power, or the first signal, or transmit the second signal.

[0059] In some embodiments, the second chip pad (415) may have substantially the same maximum width. The maximum width of the second chip pad (415) may be the diameter of the second chip pad (415). That is, the second chip pad (415) that transmits ground, power, or the first signal and the second chip pad (415) that transmits the second signal may have substantially the same maximum width. The fourth connection terminal (430) may have substantially the same maximum width. That is, the fourth connection terminal (430) that transmits ground, power, or the first signal and the fourth connection terminal (430) that transmits the second signal may have substantially the same maximum width.

[0060] The fourth connection terminal (430) may be, for example, a solder bump, but is not limited thereto. The fourth connection terminal (430) may have various shapes such as a land, ball, pin, or pillar. The number, spacing, and arrangement of the fourth connection terminals (430) are not limited to those shown and may vary depending on the design. The sizes of the fourth connection terminals (430) may differ from each other. For example, the size of the first connection terminal (130) may be larger than the size of the second connection terminal (230), and the size of the second connection terminal (230) may be larger than the size of the fourth connection terminal (430).

[0061] The fourth connecting terminal (430) may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but is not limited thereto.

[0062] The third underfill material layer (440) may be placed between the first interposer (200) and the second semiconductor chip (400). The third underfill material layer (440) may fill the space between the first interposer (200) and the second semiconductor chip (400). The third underfill material layer (440) may fill the space between the fourth connection terminals (430) and may wrap the fourth connection terminals (430). Unlike what is illustrated, the third underfill material layer (440) may extend further along the sidewalls of the fourth passivation layer (410) and the second semiconductor chip (400). The third underfill material layer (440) may protect the fourth connection terminals (430). The third underfill material layer (440) may include, for example, an insulating polymer material such as an epoxy molding compound (EMC), but is not limited thereto.

[0063] In some embodiments, the heat dissipation structure (500) is disposed on a second surface (100b) of the package substrate (100) and may cover the first interposer (200), the first semiconductor chip (300), and the second semiconductor chip (400). The heat dissipation structure (500) may be adhered, for example, to the upper surface of the first semiconductor chip (300) and the upper surface of the second semiconductor chip (400).

[0064] Referring to FIG. 9, a semiconductor package according to some embodiments may further include a second interposer (250) and a second semiconductor chip (400).

[0065] The second interposer (250) may be spaced apart from the first interposer (200) on the second surface (100b) of the package substrate (100). The second interposer (250) may be, for example, a silicon interposer. Or the second interposer (250) may include at least one of, for example, glass, ceramic, or plastic.

[0066] The third connection pads (261, 262) and the fifth passivation layer (260) may be disposed on the lower surface of the second interposer (250), and the lower surface of the second interposer (250) may face the second surface (100b) of the package substrate (100). The fifth passivation layer (260) may expose at least a portion of the third connection pads (261, 262).

[0067] The fourth connection pad (271, 272) and the sixth passivation layer (270) may be disposed on the upper surface of the second interposer (250). The sixth passivation layer (270) may expose at least a portion of the fourth connection pad (271, 272). The third and fourth connection pads (261, 262, 271, 272) may each include a metallic material such as, for example, copper (Cu) or aluminum (Al), but are not limited thereto.

[0068] The third wiring pattern (251, 252) may be placed within the second interposer (250). Since the third-1 wiring pattern (251) and the third-2 wiring pattern (252) may be similar to the second-1 wiring pattern (201) and the second-2 wiring pattern (202), a detailed description is omitted below.

[0069] The second connection terminal (231, 232) may be positioned between the second substrate pad (121, 122) and the third connection pad (261, 262). The second-1 connection terminal (231) may be electrically connected to the second-1 substrate pad (121) and the third-1 connection pad (261), and the second-2 connection terminal (232) may be electrically connected to the second-2 substrate pad (122) and the third-2 connection pad (262). The third-1 connection pad (261) may be electrically connected to the third-1 wiring pattern (251) and the fourth-1 connection pad (271), and the third-2 connection pad (262) may be electrically connected to the third-2 wiring pattern (252) and the fourth-2 connection pad (272).

[0070] In some embodiments, the maximum width of the third-1 connection pad (261) and the maximum width of the third-2 connection pad (262) may be different. The maximum width of the third-2 connection pad (262) to which the second signal is transmitted may be smaller than the maximum width of the third-1 connection pad (261) to which the second signal is not transmitted. For example, the maximum width of the third-1 connection pad (261) may be the diameter of the third-1 connection pad (261), and the maximum width of the third-2 connection pad (262) may be the diameter of the third-2 connection pad (262).

[0071] In some embodiments, the maximum width of the 4-1 connection pad (271) to which the second signal is not transmitted and the maximum width of the 4-2 connection pad (272) to which the second signal is transmitted may be substantially the same. For example, the maximum width of the 4-1 connection pad (271) may be the diameter of the 4-1 connection pad (271), and the maximum width of the 4-2 connection pad (272) may be the diameter of the 4-2 connection pad (272).

[0072] The second semiconductor chip (400) may be placed on the second interposer (250). The fourth connection terminal (430) may be electrically connected to the fourth connection pad (271, 272) and the second chip pad (415). The second semiconductor chip (400), the fourth passivation layer (410), the second chip pad (415), and the third underfill material layer (440) are similar to those described using FIG. 8 and are therefore omitted below.

[0073] In some embodiments, the heat dissipation structure (500) is disposed on a second surface (100b) of the package substrate (100) and can cover the first interposer (200), the second interposer (250), the first semiconductor chip (300), and the second semiconductor chip (400).

[0074] Referring to FIG. 10, a semiconductor package according to some embodiments may include a first package (1000) and a second package (2000).

[0075] The first package (1000) may include a package substrate (100) and a second semiconductor chip (400). Second-third and second-fourth substrate pads (123, 124) may be disposed on the second surface (200a) of the package substrate (100). A second solder resist (120) may expose at least a portion of the second-third and second-fourth substrate pads (123, 124). The second-third substrate pad (123) may be electrically connected to the first-first wiring pattern (101), and the second-fourth substrate pad (124) may be electrically connected to the first-second wiring pattern (102). A fourth connection terminal (430) may be electrically connected to the second-third and second-fourth substrate pads (123, 124) and the second chip pad (415). The second semiconductor chip (400), the fourth passivation layer (410), the second chip pad (415), and the third underfill material layer (440) are similar to those described using FIG. 8, so they are omitted below.

[0076] In some embodiments, the maximum width of the second-fourth substrate pad (124) transmitting the second signal may be substantially the same as the maximum width of the second-third substrate pad (123) not transmitting the second signal. Or in some other embodiments, the maximum width of the second-fourth substrate pad (124) transmitting the second signal may be greater than the maximum width of the second-third substrate pad (123) not transmitting the second signal.

[0077] The second package (2000) may include an interposer (200) and a first semiconductor chip (300). The first package (1000) and the second package (2000) may be electrically connected by a second connection terminal (231, 232).

[0078] Referring to FIG. 11, a semiconductor package according to some embodiments may include a first package (1000) and a second package (2000). The first package (1000) is similar to that described using FIG. 10 and is therefore omitted below.

[0079] The second package (2000) may include an interposer (200) and a third semiconductor chip (600) and a fourth semiconductor chip (700) on the interposer (200). The fourth semiconductor chip (700) may be stacked on the third semiconductor chip (600). The number of semiconductor chips (e.g., the third semiconductor chip (600) and the fourth semiconductor chip (700)) disposed on the interposer (200) is merely an example and is not limited thereto. Additionally, unlike what is illustrated, a semiconductor chip spaced apart from the third and fourth semiconductor chips (600, 700) may be further disposed on the interposer (200).

[0080] A third semiconductor chip (600) may be attached to the upper surface of the interposer (200) by a first attachment layer (650). A fourth semiconductor chip (700) may be attached to the upper surface of the third semiconductor chip (600) by a second attachment layer (750). The first and second attachment layers (650, 750) may each include, for example, at least one of liquid epoxy, adhesive tape, a conductive medium, and combinations thereof, but are not limited thereto.

[0081] The third semiconductor chip (600) can be electrically connected to the interposer (200) by the first bonding wire (604). The fourth semiconductor chip (700) can be electrically connected to the interposer (200) by the second bonding wire (704). The first bonding wire (604) can electrically connect, for example, the third chip pad (602) of the third semiconductor chip (600) and the fifth connection pad (225) of the interposer (200). The second bonding wire (704) can electrically connect, for example, the fourth chip pad (702) of the fourth semiconductor chip (700) and the fifth connection pad (225) of the interposer (200).

[0082] Referring to FIG. 12 and FIG. 13, in a semiconductor package according to some embodiments, the maximum width (W42) of a second-2 connection pad (222) that is electrically connected to a second-2 wiring pattern (202) and transmits the second signal may be smaller than the maximum width (W41) of a second-1 connection pad (221) that is electrically connected to a second-1 wiring pattern (201) and does not transmit the second signal.

[0083] The third-1 connection terminal (331) may be electrically connected to the second-1 connection pad (221) and the first chip pad (315). The third-2 connection terminal (332) may be electrically connected to the second-2 connection pad (222) and the first chip pad (315). In some embodiments, the maximum width (S31) of the third-1 connection terminal (331) may differ from the maximum width (S32) of the third-2 connection terminal (332). The maximum width (S32) of the third-2 connection terminal (332) that transmits the second signal may be smaller than the maximum width (S31) of the third-1 connection terminal (331) that does not transmit the second signal.

[0084] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0085] 100: Package substrate 101, 102: First wiring pattern 110, 120: First and second solder resists 111, 112: First substrate pad 121, 122: Second substrate pad 130, 230, 330: 1st to 3rd connection terminals 201, 202: Second wiring pattern 211, 212: First connection pad 221, 222: 2nd connection pads 261, 262: 3rd connection pads 271, 272: 4th connection pad 210, 220, 310, 410: 1st to 4th passivation layers 240, 340, 440: First to third underfill material layers 200, 250: 1st and 2nd interposers 251, 252: 3rd wiring pattern 300, 400, 600, 700: 1st to 4th semiconductor chips 315, 415: 1st and 2nd chip pads 500: Heat dissipation structure 550: Molding layer

Claims

Claim 1 A semiconductor package comprising: a package substrate including a first surface and a second surface opposite to each other; a first-1 substrate pad and a first-2 substrate pad having a maximum width smaller than the maximum width of the first-1 substrate pad on the first surface of the package substrate; a first connection terminal disposed on the first-1 and the first-2 substrate pad; a second-1 substrate pad and a second-2 substrate pad having a maximum width smaller than the maximum width of the second-1 substrate pad on the second surface of the package substrate; an interposer disposed on the second surface of the package substrate; a second connection terminal between the second-1 and the second-2 substrate pad and the interposer; and a first semiconductor chip disposed on the interposer, wherein the first-1 substrate pad and the second-1 substrate pad transmit a first signal, a ground signal, or a power signal, and the first-2 substrate pad and the second-2 substrate pad transmit a second signal having a speed faster than the first signal. Claim 2 A semiconductor package according to claim 1, wherein the first connection terminal comprises a first-1 connection terminal on the first-1 substrate pad and a first-2 connection terminal on the first-2 substrate pad, and the maximum width of the first-2 connection terminal is greater than the maximum width of the first-1 connection terminal. Claim 3 A semiconductor package according to claim 2, wherein, in the direction from the first surface of the package substrate toward the second surface, the bottom surface of the first-2 connection terminal is disposed in the same plane as the bottom surface of the first-1 connection terminal. Claim 4 A semiconductor package according to claim 1, further comprising a first-1 connection pad and a first-2 connection pad having a maximum width smaller than the maximum width of the first-1 connection pad on a third surface of the interposer facing the second surface of the package substrate, wherein the second connection terminal comprises a second-1 connection terminal between the first-1 connection pad and the second-1 substrate pad and a second-2 connection terminal between the first-2 connection pad and the second-2 substrate pad. Claim 5 In claim 4, the semiconductor package in which the maximum width of the 2-2 connection terminal is greater than the maximum width of the 2-1 connection terminal. Claim 6 A semiconductor package according to claim 1, further comprising a second-1 connection pad and a second-2 connection pad having the same maximum width on a fourth surface of the interposer facing the first semiconductor chip, wherein the second-1 connection pad transmits the first signal, the ground signal, or the power signal, and the second-2 connection pad transmits the second signal. Claim 7 A semiconductor package according to claim 1, wherein on a fourth surface of the interposer facing the first semiconductor chip, a second-1 connection pad and a second-2 connection pad having a maximum width smaller than the maximum width of the second-1 connection pad, the second-1 connection pad transmits the first signal, the ground signal or the power signal, and the second-2 connection pad transmits the second signal. Claim 8 A semiconductor package according to claim 1, further comprising a heat dissipation structure covering the first semiconductor chip on the second surface of the package substrate. Claim 9 A package substrate comprising a first surface and a second surface opposite to each other; a first connection terminal disposed on the first surface of the package substrate; an interposer on the second surface of the package substrate comprising a third surface facing the second surface and a fourth surface opposite to the third surface; on the third surface of the interposer, a first-1 connection pad and a first-2 connection pad having a maximum width smaller than the maximum width of the first-1 connection pad; a second connection terminal between the first-1 and first-2 connection pads and the package substrate; on the fourth surface of the interposer, a second-1 connection pad and a second-2 connection pad having the same maximum width; and a semiconductor chip disposed on the fourth surface of the interposer. A semiconductor package comprising a third connection terminal between the 2-1 and 2-2 connection pads and the semiconductor chip, wherein the 1-1 connection pad and the 2-1 connection pad transmit a first signal, a ground signal, or a power signal, and the 1-2 connection pad and the 2-2 connection pad transmit a second signal having a faster speed than the first signal. Claim 10 A package substrate comprising a first surface and a second surface opposite to each other; on the first surface of the package substrate, a first-1 substrate pad and a first-2 substrate pad having a maximum width smaller than the maximum width of the first-1 substrate pad; a first connection terminal disposed on the first-1 and the first-2 substrate pads; on the second surface of the package substrate, a second-1 substrate pad and a second-2 substrate pad having a maximum width smaller than the maximum width of the second-1 substrate pad; on the second surface of the package substrate, an interposer comprising a third surface opposite to the second surface and a fourth surface opposite to the third surface; on the third surface of the interposer, a first-1 connection pad and a first-2 connection pad having a maximum width smaller than the maximum width of the first-1 connection pad; a second connection terminal disposed between the second-1 substrate pad and the first-1 connection pad, and between the second-2 substrate pad and the first-2 connection pad; on the fourth surface of the interposer, A semiconductor package comprising: a second-1 connection pad and a second-2 connection pad having the same maximum width; a semiconductor chip disposed on the fourth surface of the interposer; a first chip pad and a second chip pad having the same width on the fifth surface of the semiconductor chip opposite to the fourth surface of the interposer; and a third connection terminal disposed between the second-1 connection pad and the first chip pad, and between the second-2 connection pad and the second chip pad, wherein the first-1 substrate pad, the second-1 substrate pad, the first-1 connection pad, the second-1 connection pad, and the first chip pad transmit a first signal, a ground signal, or a power signal, and the first-2 substrate pad, the second-2 substrate pad, the first-2 connection pad, the second-2 connection pad, and the second chip pad transmit a second signal having a different speed from the first signal.

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