Chip package unit, chip package stack module

Abstract

A chip package unit, a chip package stack module, and a method for manufacturing the chip package stack module are provided. The chip package stack module includes upper and lower chip package units that are vertically stacked. Each chip package unit includes a plurality of conductive pillars, each having an upper pad and a lower pad on the top and bottom of the conductive pillars, respectively. The upper and lower chip package units are stacked by the lower pad of the upper chip package unit and the upper pad of the lower chip package unit, which are electrically connected to each other. The conductive pillar of the upper chip package unit is electrically connected to the corresponding conductive pillar of the lower chip package unit, so that the memory chip of the upper chip package unit and the memory chip of the lower chip package unit are electrically connected.

Description

Technology Field

[0001] The present invention relates to a chip package unit, a chip package stack module, and a method for manufacturing a chip package stack module, and in particular to a method for manufacturing a chip package unit, a chip package stack module, and a chip package stack module produced by a simplified manufacturing process with embedded conductive pillars. Background Technology

[0002] In semiconductor memory technology, at least two chips are stacked to expand memory function / capacity. In this chip stacking technology, chips are first stacked to form a chip stack through molding. However, if even a single defective chip is found among the stacked chips, the entire chip stack must be replaced or repaired. Consequently, production costs for manufacturers increase, making it unsuitable for mass production. To address the above problem, multiple pre-molded chip package units are used to form a chip stack, such as in the stacking technology provided in U.S. Patent No. 9,685,429 B2 (an equivalent patent including Chinese Patent No. 204885152 U and Taiwan Patent No. M509421) and U.S. Patent No. 8,502,378 B2 (an equivalent patent including Taiwan Patent No. I501365). As a result, production and quality control costs for manufacturers are reduced, and mass production of products becomes easier.

[0003] However, the above technologies still have certain disadvantages. For example, the conductive pillars of the chip package stack module in U.S. Patent No. 9,685,429 B2 are not integrally molded with the chip but are exposed and located outside the insulating layer. Consequently, the conductive pillars are susceptible to damage, and the yield of the final product is reduced. Furthermore, regarding the conductive pillars of the chip package stack module shown in U.S. Patent No. 8,502,378 B2, they are embedded in the insulating layer. However, the conductive pillars are formed by connecting two different conductive pins produced by two different manufacturing processes. Consequently, the manufacturing process becomes complex, which negatively impacts the reduction of manufacturing costs. The problem to be solved

[0004] Accordingly, the main object of the present invention is to provide a chip package unit, a chip package stack module, and a method for manufacturing the chip package stack module. The chip package stack module comprises at least two chip packages vertically stacked adjacent to each other. Each chip package unit comprises a plurality of conductive pillars, each having an upper pad and a lower pad provided at the top and bottom of the conductive pillars, respectively. An upper chip package unit is stacked on top of a lower chip package unit by means of the lower pad of the upper chip package unit and the upper pad of the lower chip package unit, which are electrically connected and coupled to each other. The conductive pillar of the upper chip package unit is electrically connected to the corresponding conductive pillar of the lower chip package unit, so that the memory chip of the upper chip package unit and the memory chip of the chip package unit are electrically connected. This can solve the problems of usable stack module products, including reduced yield due to easy damage to the exposed conductive pillars and complex manufacturing processes. means of solving the problem

[0005] To achieve the above objective, a chip package unit according to the present invention comprises a substrate, a patterned circuit layer, at least one memory chip, an insulating layer, a plurality of through holes, and a plurality of conductive pillars. The patterned circuit layer is disposed on the surface of the substrate, and the memory chip is electrically coupled to the patterned circuit layer by flip-chip technology. The insulating layer covers the substrate as well as the gap between the substrate and the memory chip. Each through hole penetrates the substrate and the insulating layer vertically and is arranged at a predetermined fixed position around the memory chip. Conductive pillars are formed correspondingly in the through holes, and an upper pad and a lower pad are provided at the top and bottom of each conductive pillar, respectively. The memory chip is electrically connected to each conductive pillar by the patterned circuit layer and is additionally electrically connected to the outside by the upper pad or the lower pad of the conductive pillar.

[0006] A chip package stack module according to the present invention comprises at least two chip package units that are adjacent to each other and stacked vertically relative to each other to form an upper chip package unit and a lower chip package unit. Each chip package unit is composed of a substrate, a patterned circuit layer, at least one memory chip, an insulating layer, a plurality of through holes, and a plurality of conductive pillars. The lower pad of the upper chip package unit and the upper pad of the lower chip package unit are vertically aligned with each other. The upper chip package unit is stacked on the lower chip package unit by means of the lower pad of the upper chip package unit and the upper pad of the lower chip package unit, which are electrically connected and coupled to each other. The conductive pillar of the upper chip package unit is electrically connected to the corresponding conductive pillar of the lower chip package unit, so that the memory chip of the upper chip package unit is electrically connected to the memory chip of the lower chip package unit.

[0007] Preferably, the chip package stack module further includes at least one solder ball disposed on the lower pad of the lowest chip package unit among each chip package unit.

[0008] The chip package stack module is additionally mounted on the printed circuit board (PCB).

[0009] A method for manufacturing the chip package stack module according to the present invention comprises the following steps: Step S1: providing at least two chip package units. Step S2: arranging two chip package units vertically at an upper position and a lower position to form an upper chip package unit and a lower chip package unit adjacent to each other, wherein the lower pad of the upper chip package unit and the upper pad of the lower chip package unit are vertically aligned with each other and correspond to each other. Step S3: stacking the upper chip package unit on top of the lower chip package unit to form a chip package stack module by means of the lower pad of the upper chip package unit and the upper pad of the lower chip package unit being electrically connected and coupled to each other. By doing so, the chip package stack module of the design can be mass-produced. Brief explanation of the drawing

[0010] FIG. 1 is a side cross-sectional view of a chip package stack module including two chip package units according to the present invention. FIG. 2 is a side cross-sectional view of a chip package unit according to the present invention. FIG. 3 is a schematic diagram illustrating an exploded view of an embodiment of FIG. 1 according to the present invention. FIG. 4 is a schematic diagram illustrating an exploded view of an embodiment of FIG. 1 in which a chip package unit according to the present invention is additionally stacked. FIG. 5 is a side cross-sectional view of a chip package stack module including three chip package units according to the present invention. Specific details for implementing the invention

[0011] Referring to FIGS. 1 and 5, a chip package stack module (1) according to the present invention comprises at least two chip package units (10) that are adjacent to each other and stacked vertically relative to each other to form an upper chip package unit (10) and a lower chip package unit (10). Each chip package unit (10) is composed of a substrate (11), a patterned circuit layer (12), at least one memory chip (13), an insulating layer (14), a plurality of through holes (17), and a plurality of conductive pillars (18), as shown in FIG. 2.

[0012] Referring to FIG. 2, a patterned circuit layer (12) is placed on the surface of a substrate (11), and a memory chip (13) is electrically coupled to the patterned circuit layer (12) by flip-chip technology. An insulating layer (14) covers the substrate (11) as well as the gap between the substrate (11) and the memory chip (13). Each through-hole (17) penetrates vertically through the substrate (11) and the insulating layer (14) and is arranged at a predetermined fixed position around the memory chip (13). Each through-hole (17) may be formed by laser drilling, mechanical drilling, or etching drilling, but is not limited thereto. Each conductive pillar (18) is formed in the corresponding through-hole (17), and an upper pad (15) and a lower pad (16) are provided at the top and bottom of each conductive pillar (18), respectively. The memory chip (13) is electrically connected to each conductive pillar (18) by a patterned circuit layer (12) and is additionally electrically connected to the outside by an upper pad (15) or a lower pad (16) of the conductive pillar (18).

[0013] Referring to FIGS. 1 and 5, the lower pad (16) of the upper chip package unit (10) corresponds to and is positioned on the upper pad (15) of the lower chip package unit (10). The upper chip package unit (10) is stacked on the lower chip package unit (10) by the lower pad (16) of the upper chip package unit (10) and the upper pad (15) of the lower chip package unit (10), which are electrically connected and coupled to each other. The conductive pillar (18) of the upper chip package unit (10) is electrically connected to the corresponding conductive pillar (18) of the lower chip package unit (10), and the memory chip (13) of the upper chip package unit (10) is electrically connected to the memory chip (13) of the lower chip package unit (10) for memory function / capacity expansion.

[0014] Referring to FIGS. 4 and 5, the number of chip package units (10) of the chip package stack module (1) is three, but is not limited thereto. This arrangement is advantageous for expanding memory function / capacity.

[0015] Referring to FIGS. 1, 3 and 5, in the chip package stack module (1), a conductive metal (30) is additionally provided between the lower pad (16) of the upper chip package unit (10) and the upper pad (15) of the lower chip package unit (10), but is not limited thereto. Thus, the lower pad (16) and the upper pad (15) are connected by the conductive metal (30) after reflow, and the connection strength is significantly increased.

[0016] Referring to FIGS. 1 and FIGS. 5, the chip package stack module (1) further includes at least one solder ball (20) placed on the lower pad (16) of the lowest chip package unit (10) among each chip package unit (10).

[0017] Referring to FIGS. 1 and FIGS. 5, the chip package stack module (1) is additionally mounted on the printed circuit board (PCB) (2), but is not limited thereto. The chip package stack module (1) is applied to the fan-out of the PCB (FOiP), but is not limited thereto.

[0018] Referring to FIGS. 1, FIGS. 3 and FIGS. 5, a method for manufacturing a chip package stack module (1) according to the present invention comprises the following steps.

[0019] Step S1: A step of providing at least two chip package units (10);

[0020] Step S2: A step of vertically arranging two chip package units (10) at an upper position and a lower position to form an upper chip package unit (10) and a lower chip package unit (10) adjacent to each other, wherein the lower pad (16) of the upper chip package unit (10) and the upper pad (15) of the lower chip package unit (10) are aligned vertically corresponding to each other;

[0021] Step S3: A step of stacking an upper chip package unit (10) on top of a lower chip package unit (10) to form a chip package stack module (1) by means of a lower pad (16) of an upper chip package unit (10) and an upper pad (15) of a lower chip package unit (10) that are electrically connected and coupled to each other as shown in FIGS. 1 and 5.

[0022] Compared to currently available stack modules, the chip package stack module (1) according to the present invention has the following advantages. (1) As shown in FIG. 2, through holes (17) penetrate the substrate (11) and the insulating layer (14) and are arranged at preset fixed positions around the memory chip (13), and conductive pillars (18) are formed in the corresponding through holes (17). Thus, the problem of currently available stack modules, in which the conductive pillars located outside the insulating layer and exposed are easily damaged and the yield is reduced, can be solved.

[0023] (2) A conductive pillar (18) is formed in the chip package unit (10) by vertically penetrating the substrate (11) and the insulating layer (14). Thus, the problem of the manufacturing process becoming complicated due to two different manufacturing processes used to produce two conductive pillars connected to each other in currently available stack modules can be resolved.

[0024] (3) During the method of manufacturing a chip package stack module (1) according to the present invention, two adjacent chip package units (10) are arranged perpendicularly to each other to form an upper chip package unit (10) and a lower chip package unit (10). The lower pad (16) of the upper chip package unit (10) and the upper pad (15) of the lower chip package unit (10) are aligned perpendicularly to each other as shown in FIGS. 3 and 4. Accordingly, the chip package units (10) are stacked more precisely with each other, which helps improve the stacking efficiency of the manufacturer.

Claims

Claim 1 A chip package unit comprising an upper side and a lower side, wherein the substrate — the substrate is composed of an upper side and a lower side, and the lower side of the substrate is the lower side of the chip package unit —; a patterned circuit layer disposed on the upper side of the substrate; at least one memory chip electrically coupled to the patterned circuit layer by flip-chip technology; an insulating layer covering the upper side of the substrate and the gap between the substrate and the memory chip — the insulating layer is composed of an upper side, and the upper side of the insulating layer is the upper side of each chip package unit —; a plurality of through holes, each of which vertically penetrates the upper side and lower side of each chip package unit and is arranged at preset fixed positions around the memory chip; A plurality of conductive pillars formed to correspond to through holes having upper and lower ends, each having an upper pad and a lower pad provided respectively, each facing each other; wherein the upper pad is located on the upper side of each chip package unit, and the lower pad is located on the lower side of each chip package unit, and the layout of the position of the upper pad on the upper side of each chip package unit is the same as the layout of the position of the lower pad on the lower side of each chip package unit, and the memory chip is electrically connected to each conductive pillar by a patterned circuit layer and is additionally electrically connected to the outside by the upper pad or lower pad of the conductive pillar. Claim 2 A chip package stack module comprises at least two chip package units, each chip package unit comprising a substrate, a patterned circuit layer, at least one memory chip, an insulating layer, a plurality of through holes, and a plurality of conductive pillars, each chip package unit is configured with an upper side and a lower side, the substrate of each chip package unit is configured with an upper side and a lower side, the lower side of the substrate is the lower side of the chip package unit, the patterned circuit layer of each chip package unit is disposed on the upper layer of the substrate, at least one memory chip of each chip package unit is electrically coupled to the patterned circuit layer by flip-chip technology, the insulating layer of each chip package unit covers the upper side of the substrate and the gap between the substrate and the memory chip, the insulating layer is configured with an upper side, the upper side of the insulating layer is the upper side of each chip package unit, the plurality of through holes of each chip package unit each vertically penetrate the upper side and lower side of each chip package unit and are arranged at preset fixed positions around the memory chip, and the plurality of conductive pillars of each chip package unit each It has an upper and lower end provided with an upper pad and a lower pad facing each other, formed to correspond to a through hole, the upper pad is located on the upper side of each chip package unit, and the lower pad is located on the lower side of each chip package unit, the memory chip is electrically connected to each conductive pillar by a patterned circuit layer and is additionally electrically connected to the outside by the upper pad or lower pad of the conductive pillar, the layout of the position of the upper pad on the upper side of each chip package unit is the same as the layout of the position of the lower pad on the lower side of each chip package unit, two chip package units are adjacent to each other and vertically stacked to form an upper chip package unit and a lower chip package unit, the lower pad of the upper chip package unit and the upper pad of the lower chip package unit correspond to each other vertically,A chip package stack module, wherein an upper chip package unit is stacked on a lower chip package unit by means of a lower pad of the upper chip package unit and an upper pad of the lower chip package unit that are electrically connected and coupled to each other, and the conductive pillars of the upper chip package unit are electrically connected to corresponding conductive pillars of the lower chip package unit, and the memory chips of the upper chip package unit are electrically connected to the memory chips of the lower chip package unit. Claim 3 In paragraph 2, the chip package stack module further comprises at least one solder ball disposed on the lower pad of the lowest chip package unit among the chip package units. Claim 4 In paragraph 2, the chip package stack module is a chip package stack module that is additionally mounted on a printed circuit board (PCB).

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