Computer-implemented method and multi-core computing apparatus for a resilient transactional memory.

Abstract

This disclosure pertains to a multi-core computing apparatus (100) configured to execute a transactional memory operation comprises computational units (1, 1b), each associated with a memory storage unit (2, 2b), a first control unit (10, 10b), and a second control unit (11, 11b), the computational units (1, 1b) communicating via an interconnect structure (3) with a directory-level control unit (9) and a shared cache memory unit (8), wherein the directory-level control unit (9) is configured to manage memory transactions and to detects conflicts based on transaction states stored in registers (11, 11b), the first control unit (10, 10b) being configured to allocate computational units (1, 1b) to transaction execution groups, the second control unit (11, 11b) being configured to stall execution until a second computational unit (1b) enters the transaction, wherein entering the transaction by the second computational unit (1b) comprises initiating the same transaction and confirming participation before memory locations (8) can be accessed.