RELIABILITY IMPROVEMENT METHODS FOR A PHYSICALLY INCLONABLE FUNCTIONAL BIT STRING GENERATION

Abstract

A non-clonable physical function integrated into the embedded hardware delay (help PUF) leverages entropy by monitoring path stability and measuring path delays from basic logic macros. Reliability and security enhancement techniques for the help PUF reduce bit-flip errors during bit string regeneration under environmental variations, improving cryptographic strength and the corresponding difficulty of pattern-building attacks. A voltage-based enrollment process traverses unstable paths on normally synthesized (glitchy) functional units and reduces bit-flip errors by performing enrollment at multiple controlled supply voltages using on-chip voltage regulators.