LDPC coding method and apparatus, and base station and readable storage medium
Patent Information
- Authority / Receiving Office
- MY · MY
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2020-07-17
- Publication Date
- 2026-07-02
AI Technical Summary
LDPC encoding has problems such as large latency, large resource consumption, and high hardware costs. Especially in 5G technology, the requirements for throughput rate and hardware resources have added new challenges.
By obtaining the expansion factor, the encoded original data is segmented, the shift value is determined and the check information is generated, breaking the dependence between the check information, and using a parallel mechanism to shorten the encoding delay and improve the throughput rate.
It effectively shortens the encoding delay, improves the system throughput rate, reduces hardware resource consumption and cost, and overcomes the problems of large LDPC encoding delay and resource consumption.
Abstract
Description
An LDPC encoding method, apparatus, base station, and readable storage medium
[0001] Cross-references to related applications
[0002] This application is based on and claims priority to Chinese Patent Application No. 201910754120.3, filed on August 15, 2019, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This invention relates to the field of communication technology, and in particular to an LDPC encoding method, apparatus, base station, and readable storage medium. Background Technology
[0004] Channel coding is an important component of wireless communication systems, and together with multiple access technology and multiple input multiple output technology, it constitutes the three key technologies of 5G air interface.
[0005] Since the Shannon formula was published, various error correction coding methods have emerged, which can be divided into two categories: block codes and lattice codes. Due to the limitation on the number of states, lattice codes, like traditional block codes, are suitable for short codes. The decoding complexity of both is exponentially related to the code length.
[0006] The Turbo codes currently used in 4G are long codes, with coding performance approaching the Shannon limit. Turbo codes employ a parallel, concatenated, recursive structure, and their component codes use systematic convolutional codes. Interleaving is introduced between encoders to reduce the correlation of information between them, mimicking random coding. In decoding, a soft-in-soft-out decoding algorithm and a feedback decoding method are used, making Turbo codes even closer to the Shannon limit. The drawback of Turbo codes is their high decoding complexity; with large code block lengths, the interleaver delay becomes excessive.
[0007] With the advent of 5G technology, 3GPP has determined that 5G communication will use LDPC codes as the long block coding scheme. LDPC codes are linear block codes with sparse parity-check matrices, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.
[0008] Different LDPC encoding structures have a significant impact on throughput and result in significant differences in hardware resource consumption.
[0009] Summary of the Invention
[0010] This invention provides an LDPC encoding method, apparatus, base station, and readable storage medium to at least partially solve the problems of high latency and high resource consumption in LDPC encoding in some situations.
[0011] In a first aspect, embodiments of the present invention provide an LDPC encoding method, the method comprising the following steps: obtaining original encoding data and an expansion factor, and segmenting the original encoding data based on the expansion factor to obtain segmented encoded data; determining a shift value based on the expansion factor, and generating verification information based on the shift value and the segmented encoded data to complete the encoding.
[0012] Secondly, embodiments of the present invention provide an LDPC encoding apparatus, the apparatus comprising: a data processing module, configured to acquire original encoding data and an expansion factor, segment the original encoding data based on the expansion factor to obtain segmented encoded data, and determine a shift value based on the expansion factor; and a verification information generation module, configured to generate verification information based on the shift value and the segmented encoded data to complete the encoding.
[0013] Thirdly, embodiments of the present invention provide a computer-readable storage medium storing an information transmission implementation program, wherein the program, when executed by a processor, implements the steps of the aforementioned encoding method.
[0014] Fourthly, embodiments of the present invention provide a base station, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the aforementioned encoding method.
[0015] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description
[0016] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:
[0017] Figure 1 is a flowchart of the first embodiment of the present invention;
[0018] Figure 2 is a flowchart of obtaining segmented coded data in the first embodiment of the present invention;
[0019] Figure 3 is a schematic diagram of the device structure according to the second embodiment of the present invention.
[0020] Figure 4 is a schematic diagram of data processing of the device according to the second embodiment of the present invention;
[0021] Figure 5 shows the basic matrix of the expansion factor 512 in the third embodiment of the present invention;
[0022] Figure 6 shows the pre-shifted basic matrix of the third embodiment of the present invention with an expansion factor of 512;
[0023] Figure 7 shows the basic matrix of the fourth embodiment of the present invention with an expansion factor of 256;
[0024] Figure 8 shows the pre-shifted basic matrix of the fourth embodiment of the present invention with an expansion factor of 256;
[0025] Figure 9 is a schematic diagram of the base station structure in the sixth embodiment of the present invention. Detailed Implementation
[0026] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
[0027] In a first aspect, the first embodiment of the present invention provides an LDPC encoding method, as shown in FIG1, the method comprising the following steps:
[0028] Step S1: Obtain the original encoded data and the expansion factor, and segment the original encoded data based on the expansion factor to obtain segmented encoded data.
[0029] Step S2: Store the segmented encoded data.
[0030] Step S3: Determine the shift value based on the expansion factor, and generate verification information based on the shift value and the segmented encoded data to complete the encoding.
[0031] This invention provides a solution to the problems of high encoding latency and high resource consumption in the prior art by segmenting the original encoded data based on the expansion factor, determining the shift value according to the expansion factor, and generating verification information based on the shift value and the segmented encoded data to complete the encoding. This breaks the dependency between the verification information during the encoding process.
[0032] In one embodiment of the present invention, the step of segmenting the original encoded data based on the expansion factor to obtain segmented encoded data, as shown in Figure 2, includes:
[0033] Step S11: Select the encoding base matrix according to the length of the encoded original data and the expansion factor;
[0034] Step S12: Segment the original encoded data based on the expansion factor to obtain segmented encoded data.
[0035] Specifically, in this embodiment, the encoding base matrix is divided into two parts: the left side is the non-parity matrix and the right side is the parity matrix. In this embodiment, the base matrix and the original encoded data have a corresponding relationship. For example, if the original encoded data is Z×8, where Z is the expansion factor, the encoding base matrix can be selected as 18×26, where the non-parity matrix is 18×8 and the parity matrix is 18×18.
[0036] By adopting the above technical solution, the method of shifting the selected encoding base matrix can break the dependency between various verification information during the encoding process, rationally arrange the encoding structure, and thus improve the encoding efficiency.
[0037] In one embodiment of the present invention, after segmenting the original encoded data based on the expansion factor to obtain segmented encoded data, the method further includes:
[0038] Step S2: Store the segmented encoded data.
[0039] By storing segmented encoded data, it is easier to schedule the data in later processing.
[0040] In one embodiment of the present invention, determining the shift value based on the expansion factor includes:
[0041] The shift value of the encoding base matrix corresponding to the expansion factor is calculated based on the verification formula for generating verification information in the base matrix.
[0042] Specifically, the shift value of the parity matrix of the encoding base matrix corresponding to the expansion factor is calculated according to the parity formula for generating parity information in the base matrix. This method can be based on the base matrix as a prototype, and the cyclic shift information of each element is calculated according to the parity formula for generating parity information in the parity matrix, which is the shift value, and the encoding control information is generated accordingly. Thus, the shift value corresponding to each element in the base matrix is obtained, and the pre-shifted base matrix can also be calculated based on the corresponding shift values of the base matrix.
[0043] In yet another embodiment of the present invention, after determining the shift value based on the expansion factor, the method further includes:
[0044] The intermediate encoding value is determined based on the original encoded data, the encoding base matrix, and the shift value.
[0045] Specifically, in this embodiment, the original encoded data can be modulo-2 added based on the non-parity matrix on the left side of the encoding base matrix to obtain the intermediate encoded value. Specifically, the pre-shifted base matrix can be calculated based on the aforementioned shift value using the encoding base matrix. Then, the original encoded data can be modulo-2 added based on the pre-shifted base matrix to obtain the intermediate encoded value. After obtaining the intermediate encoded value, it can also be stored in this embodiment.
[0046] The step of generating verification information based on the shift value and the segmented encoded data includes:
[0047] Starting with the shift value, generate verification information based on the intermediate encoded value.
[0048] Specifically, after obtaining the intermediate encoded value, the verification information is generated based on the aforementioned shift value as the starting position.
[0049] Compared to some other scenarios, the method described in the first embodiment of this invention breaks the dependency between various verification information during the encoding process, rationally lays out the encoding structure, and enables the use of a parallel mechanism to shorten the encoding latency consumed in the entire physical layer link. At the same time, this parallel mechanism improves the overall system throughput, so that encoding is no longer a bottleneck for improving system throughput, and overcomes the problems and defects of large LDPC encoding latency, large resource consumption, and high hardware cost in some other scenarios.
[0050] Secondly, a second embodiment of the present invention provides an LDPC encoding device, as shown in FIG3, the device comprising:
[0051] The data processing module is used to acquire the original encoded data and the expansion factor, and to segment the original encoded data based on the expansion factor to obtain segmented encoded data, and to determine the shift value according to the expansion factor;
[0052] The verification information generation module is used to generate verification information based on the shift value and the segmented encoded data to complete the encoding.
[0053] In this embodiment of the invention, the data processing module segments the original encoded data based on the expansion factor to obtain segmented encoded data, determines the shift value according to the expansion factor, and the verification information generation module generates verification information based on the shift value and the segmented encoded data to complete the encoding. This breaks the dependency between the various verification information during the encoding process, thereby solving the problem of fixed compensation values and inability to automatically correct in some situations.
[0054] In an optional embodiment of the present invention, the data processing module is configured to select an encoding base matrix based on the length of the encoded original data and the expansion factor;
[0055] Based on the expansion factor, the original encoded data is segmented to obtain segmented encoded data.
[0056] Specifically, as shown in Figure 4, in this embodiment, the data processing module includes the data preprocessing module and the pre-shifting module shown in Figure 4;
[0057] The data preprocessing module is used to select the encoding base matrix according to the length of the original encoded data and the expansion factor, that is, to select the encoding base matrix according to the original length of the data before encoding and the expansion factor in Figure 4, and to obtain segmented encoded data from the original encoded data based on the encoding base matrix, and to output the segmented data according to the data preprocessing module in Figure 4.
[0058] In this embodiment, the encoding base matrix is divided into two parts: the left side is the non-parity matrix and the right side is the parity matrix. In this embodiment, the base matrix and the original encoded data have a corresponding relationship. For example, if the original encoded data is Z×8, where Z is the expansion factor, the encoding base matrix can be selected as 18×26, where the non-parity matrix is 18×8 and the parity matrix is 18×18.
[0059] By adopting the above technical solution, the scheme of selecting the encoding base matrix through the data preprocessing module can break the dependency between various verification information during the encoding process, rationally arrange the encoding structure, and thus improve the encoding efficiency.
[0060] In one embodiment of the present invention, the data processing module is used to calculate the shift value of the encoding base matrix corresponding to the expansion factor according to the verification formula for generating verification information in the base matrix.
[0061] Specifically, the data processing module calculates the shift value of the parity matrix of the encoding base matrix corresponding to the expansion factor based on the parity formula used to generate the parity information in the base matrix. The pre-shift module of the data processing module can use the base matrix as a prototype, calculate the corresponding parity information index for the shift jump according to the order in which the parity information is generated from the parity matrix, which is the shift value, and generate encoding control information accordingly. Through the pre-shift module, the shift value corresponding to each element in the base matrix is obtained, and the pre-shifted base matrix can also be calculated based on the corresponding shift values of the base matrix.
[0062] The data processing module is also used to determine the intermediate encoding value based on the original encoded data and the encoding base matrix.
[0063] Specifically, referring to Figure 4, the data processing module may also include an intermediate value calculation module. In this embodiment, the intermediate value calculation module can perform a modulo-2 addition operation on the original encoded data based on the non-check matrix on the left side of the encoding base matrix. Specifically, it can obtain the pre-shift base matrix based on the aforementioned pre-shift module, and perform a modulo-2 addition operation on the original encoded data to obtain the encoding intermediate value, thereby obtaining the encoding intermediate value.
[0064] The verification information generation module is used to generate verification information based on the intermediate encoded value, starting from the shift value.
[0065] Specifically, after obtaining the intermediate encoded value, the verification information generation module generates verification information based on the intermediate encoded value, starting from the aforementioned shift value.
[0066] In one embodiment of the present invention, the device further includes:
[0067] The storage module is used to store the segmented encoded data and, after obtaining the intermediate encoded value, to store the intermediate encoded value.
[0068] Compared to some other situations, the device described in the second embodiment of the present invention breaks the dependency between various verification information during the encoding process, rationally lays out the encoding structure, and enables the use of a parallel mechanism to shorten the encoding latency consumed in the entire physical layer link. At the same time, this parallel mechanism improves the overall system throughput, so that encoding is no longer a bottleneck for improving system throughput, and overcomes the problems and defects of large LDPC encoding latency, large resource consumption, and high hardware cost in some other situations.
[0069] Thirdly, the third embodiment of the present invention provides an implementation case of the LDPC encoding method based on the first embodiment. This embodiment describes the encoding process of the LDPC encoding module when receiving data and selecting the basic matrix in Figure 5.
[0070] S101, Receive the encoded raw data, which is a Z×8 matrix. Select the base matrix as shown in Figure 5. The base matrix is 18×26, where the non-parity matrix is 18×8 and the parity matrix is 18×18.
[0071] S102, based on the expansion factor Z = 512, perform code block segmentation on the original encoded data. Each piece of data to be encoded is denoted as C, where C is 512 × 8. The non-parity check matrix has 18 rows and 8 columns; therefore, the original encoded data is divided into 8 parts for storage, denoted as [C0, C1, C2, C3, C4, C5, C6, C7], with each part being 512 × 1. The index value is 0.
[0072] S103, Figure 5, basic matrix, row 0: check information is the output result of row 0 and column 8. All 8 elements in row 0 of the non-check matrix are 0, indicating no shifting. [C0, C1, C2, C3, C4, C5, C6, C7] are multiplied and added with the 8 elements in row 0 of the non-check matrix, the result denoted as M0. M0 + V0 = 0, the shift value is 0, directly yielding V0. V0 is the check information of the encoded result in row 0.
[0073] S104, the first row of the basic matrix in Figure 5, [C0, C1, C2, C3, C4, C5, C6, C7], is multiplied and added with the 8 elements of the first row of the non-parity matrix. The result is denoted as M1. M1 + V0' + V1 = 0, where V0' is the result of shifting V0 405 times, and V1 is the parity information of the encoded result in the first row.
[0074] Here, M1+V0'+V1=0 is converted to M1 according to the basic matrix in Figure 5. 107 +V0 0 +V1 107 =0, the shift value is 107. Take the 107th element of M1 and the 0th element of V0 to get the value of the 107th element of V1, and store it directly into the 107th storage space corresponding to the encoding verification information V1.
[0075] Figure 5 is processed to obtain Figure 6. Intermediate values are then obtained by performing calculations on the original data based on Figure 6. M1 107 The value is obtained as follows: In the pre-shift matrix of Figure 6, the first non-parity matrix is [51, -1, -1, 91, 390, -1, 277, 107]. This indicates that C0 is shifted 51 times and participates in the calculation, C3 is shifted 91 times, C4 is shifted 390 times, C6 is shifted 277 times, and C7 is shifted 107 times. The blank space is -1, indicating that it does not participate in the calculation. Thus, the first element M1 obtained is M1. 107 .
[0076] S105, the second row of the basic matrix in Figure 5, [C0, C1, C2, C3, C4, C5, C6, C7], is multiplied and added with the 8 elements of the second row of the non-parity matrix. The result is denoted as M2. M2 + V1' + V2 = 0, where V1' is the result of shifting V1 195 times, and V2 is the parity information of the encoded result in the second row.
[0077] Here, M2+V1'+V2=0 is converted to M2 according to the basic matrix in Figure 5. 424 +V1 107 +V2 424 =0, the shift value is 424. Take the 424th element of M2 and V1 from step S104. 107 The value of the 424th element of V2 is obtained and directly stored in the 424th storage space corresponding to the encoding verification information V2.
[0078] M2 424 The value is obtained through the following method: The second non-parity matrix in the pre-shift matrix of Figure 6 is [412, 73, 43, 382, 115, 396, 284, 425]. This indicates that C0 is shifted 412 times for budgeting, C1 is shifted 73 times, C2 is shifted 73 times, C3 is shifted 382 times, C4 is shifted 115 times, C5 is shifted 396 times, C6 is shifted 284 times, and C7 is shifted 425 times. Thus, the first element M2 obtained is M2. 424 .
[0079] S106, the third row of the basic matrix in Figure 5, [C0, C1, C2, C3, C4, C5, C6, C7], is multiplied and added with the 8 elements of the third row of the non-parity matrix. The result is denoted as M3. M3+V2'+V3=0, where V2' is the result of shifting V2 161 times, and V3 is the parity information of the encoded result in the third row.
[0080] Here, M3+V2'+V3=0 is converted to M3 according to the basic matrix in Figure 5. 263 +V2 424 +V3 263 =0, the shift value is 263. Take the 263rd element of M3 and V2 from step S105. 424 The value of the 263rd element of V3 is obtained and directly stored in the 263rd storage space corresponding to the encoding verification information V2.
[0081] M3 263 The value is obtained through the following method: In the pre-shift matrix of Figure 6, the second non-parity matrix is [-1, 165, 219, 473, -1, 116, -1, 264], which means that C0 is not shifted, C1 is shifted 165 times, C2 is shifted 219 times, C3 is shifted 473 times, C4 is not shifted, C5 is shifted 116 times, C6 is not shifted, and C7 is shifted 264 times. Thus, the first element M3 obtained is M3. 263 .
[0082] S107, and so on, calculate up to the 17th row of the basic matrix in Figure 5: [C0, C1, C2, C3, C4, C5, C6, C7] and perform a multiplication and addition operation with the 8 elements of the 17th row of the non-check matrix. The result is denoted as M17. M17+V1'+V17=0, where V1' is the result of shifting V1 90 times, and V17 is the check information of the encoded result in the 17th row.
[0083] Here, M17+V1'+V17=0 is converted to M17 according to the basic matrix in Figure 5. 17 +V1 107 +V17 17 =0, the shift value is 17. Take the 17th element of M17 and V1 from step S104. 107The value of the 17th element of V17 is obtained and directly stored in the 17th storage space corresponding to the encoding verification information V17.
[0084] M17 17 The value is obtained as follows: In the pre-shift matrix of Figure 6, the 17th non-parity matrix is [233, 266, -1, -1, -1, -1, -1, -1, 17, -1], indicating that C0 is shifted 233 times, C1 is shifted 266 times, C6 is shifted 17 times, and C2, C3, C4, C5, and C7 are not shifted. Thus, the first element M17 obtained is M17. 17 Increment the index value by 1.
[0085] S108, repeat S103 to S107 until the index value equals the expansion factor 512, indicating that the encoding is complete, and output the encoded results M0, V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17.
[0086] Fourthly, the fourth embodiment of the present invention provides an implementation example of the LDPC encoding method based on the first embodiment. This embodiment describes the encoding process of the LDPC encoding module when receiving data and selecting the basic matrix in Figure 7.
[0087] S201, Receive the encoded raw data, which is a Z×22 matrix. The selected base matrix is shown in Figure 7. The base matrix is 46×68, where the non-parity matrix is 46×22 and the parity matrix is 46×46.
[0088] S202, perform code block segmentation on the original encoded data based on the expansion factor = 256. Each piece of data to be encoded is denoted as C, where C is 256 × 22. The non-parity check matrix has 46 rows and 22 columns. Therefore, the original encoded data is divided into 22 parts for storage, denoted as [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21], with each part being 256 × 1. The index value is 0.
[0089] S203, rows 0 to 3 of the basic matrix in Figure 7.
[0090] The sequence [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21] is multiplied and added to the 22 elements in the 0th row of the non-parity check matrix. The result is denoted as M0. M0 + V0' + V1 = 0, where V0' is the result of shifting V0 once, and V1 is the parity check information of the first row of the encoded result.
[0091] The sequence [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21] is multiplied and added with the 22 elements in the first row of the non-parity check matrix. The result is denoted as M1. M1 + V0 + V1 + V2 = 0, where V0 and V2 are the parity check information of the encoded results in the 0th and 2nd rows, respectively.
[0092] The sequence [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21] is multiplied and added to the 22 elements in the second row of the non-parity check matrix. The result is denoted as M2. M2 + V2 + V3 = 0, where V3 represents the parity check information of the encoded result in the third row.
[0093] The multiplication and addition operation is performed on the 22 elements in the third row of the non-parity check matrix [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21] and the result is denoted as M3. M3 + V0' + V3 = 0, where V0' is the result of shifting V0 once.
[0094] M0+V0'+V1=0
[0095] M1+V0+V1+V2=0
[0096] M2 + V2 + V3 = 0
[0097] M3+V0'+V3=0
[0098] Rows 0 through 3 of the basic matrix are used together to obtain V0, V1, V2, and V3.
[0099] S204, the fourth row of the basic matrix in Figure 7
[0100] The sequence [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21] is multiplied and added to the 22 elements in the 4th row of the non-parity check matrix. The result is denoted as M4. M4 + V4 = 0, where V4 is the parity check information of the encoded result in the 4th row.
[0101] The M4 value is obtained as follows: In the pre-shift matrix of Figure 8, the fourth non-parity matrix is [157, 102, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]. This indicates that C0 is shifted 157 times, C1 is shifted 102 times, and the rest are not shifted. Thus, the first M4 element obtained is M4. 0 .
[0102] S205, row 5 of the basic matrix in Figure 7
[0103] The sequence [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21] is multiplied and added with the 22 elements in the 5th row of the non-parity check matrix. The result is denoted as M5. M5 + V0' + V5 = 0, where V0' represents V0 shifted by 115, and V5 represents the parity check information of the encoded result in the 5th row.
[0104] Convert M5+V0'+V5=0 to M5 according to the basic matrix in Figure 7. 141 +V0 0 +V5 141 =0, the shift value is 141. Take the 141st element of M5 and V0 from step S202. 0 The value of the 141st element of V5 is obtained and directly stored in the storage space corresponding to the encoding verification information 5.
[0105] M5 141 The value is obtained as follows: In the pre-shift matrix of Figure 8, the 5th non-parity matrix is [90, 121, -1, 79, -1, -1, -1, -1, -1, -1, -1, -1, -1, 116, -1, -1, -1, 169, -1, -1, -1, -1, -1, 8]. This indicates that C0 is shifted 90 times, C1 is shifted 121 times, C3 is shifted 79 times, C12 is shifted 116 times, C16 is shifted 169 times, C21 is shifted 8 times, and the rest are not shifted. Thus, the first obtained M5 element is M5. 141 .
[0106] S206, row 6 of the basic matrix in Figure 7
[0107] The sequence [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21] is multiplied and added to the 22 elements in the 6th row of the non-parity check matrix. The result is denoted as M6. M6 + V6 = 0, where V6 is the parity check information of the encoded result in the 6th row.
[0108] The M6 value is obtained as follows: In the pre-shift matrix of Figure 8, the 6th non-parity matrix is [183, -1, -1, -1, -1, -1, -1, 22, -1, -1, -1, 28, 67, -1, 244, -1, -1, -1, 11, 157, -1, 211, -1]. This indicates that C0 is shifted 183 times, C6 is shifted 22 times, C10 is shifted 28 times, C11 is shifted 67 times, C13 is shifted 244 times, C17 is shifted 11 times, C18 is shifted 157 times, C20 is shifted 211 times, and the rest are not shifted. Thus, the first M6 element obtained is M6. 0 .
[0109] S207, and so on, are calculated up to row 45 of the basic matrix in Figure 7:
[0110] The sequence [C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21] is multiplied and added to the 22 elements in the 45th row of the non-parity check matrix. The result is denoted as M45. M45 + V45 = 0, where V45 is the parity check information of the encoded result in the 45th row.
[0111] The M45 value is obtained as follows: In the pre-shift matrix of Figure 8, the 45th non-parity matrix is [-1, 149, -1, -1, -1, -1, 151, -1, -1, -1, 167, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1], indicating that C1 is shifted 149 times, C6 is shifted 151 times, C10 is shifted 167 times, and the rest are not shifted. Thus, the first M45 element obtained is M45. 0 Increment the index value by 1.
[0112] S208, repeat S202~207 until the index value equals the code block extension factor 256, indicating that the encoding is complete, and output the encoding results M0, V0, V1, V2, ..., V15.
[0113] Fifthly, a fifth embodiment of the present invention provides a computer-readable storage medium storing an information transmission implementation program, wherein the program, when executed by a processor, implements the steps of the encoding method of the first embodiment.
[0114] In a sixth aspect, referring to FIG9, the sixth embodiment of the present invention provides a base station, including a memory 901, a processor 902, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the encoding method of the first embodiment.
[0115] The embodiments of the present invention obtain segmented encoded data by segmenting the original encoded data based on the expansion factor, determine the shift value according to the expansion factor, and generate verification information based on the shift value and the segmented encoded data to complete the encoding. This solves the problems of large encoding delay and high resource consumption in some cases and achieves positive technical results.
[0116] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0117] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0118] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence or in some cases, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0119] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.
Claims
1. An LDPC encoding method, comprising the following steps: Obtain the original encoded data and the expansion factor, and segment the original encoded data based on the expansion factor to obtain segmented encoded data; The shift value is determined based on the expansion factor, and verification information is generated based on the shift value and the segmented encoded data to complete the encoding.
2. The method according to claim 1, wherein, After obtaining the original encoded data and the expansion factor, the method further includes: The encoding base matrix is selected based on the length of the original encoded data and the expansion factor.
3. The method according to claim 1, wherein, After segmenting the original encoded data based on the expansion factor to obtain segmented encoded data, the method further includes: The segmented encoded data is stored.
4. The method according to claim 2, wherein, Determining the shift value based on the expansion factor includes: The shift value of the encoding base matrix corresponding to the expansion factor is calculated based on the verification formula for generating verification information in the base matrix.
5. The method according to claim 2, wherein, After determining the shift value based on the expansion factor, the method further includes: The intermediate encoding value is determined based on the original encoded data, the basic encoded matrix, and the shift value. The step of generating verification information based on the shift value and the segmented encoded data includes: Starting with the shift value, generate verification information based on the intermediate encoded value.
6. An LDPC encoding device, comprising: The data processing module is used to acquire the original encoded data and the expansion factor, and to segment the original encoded data based on the expansion factor to obtain segmented encoded data, and to determine the shift value according to the expansion factor; The verification information generation module is used to generate verification information based on the shift value and the segmented encoded data to complete the encoding.
7. The apparatus according to claim 6, wherein, The data processing module is used to select the encoding base matrix based on the length of the encoded original data and the expansion factor.
8. The apparatus according to claim 6, wherein, The device further includes: A storage module is used to store the segmented encoded data.
9. The apparatus according to claim 7, wherein, The data processing module is used to calculate the shift value of the encoding base matrix corresponding to the expansion factor according to the verification formula for generating verification information in the base matrix.
10. The apparatus according to claim 7, wherein, The data processing module is further configured to determine the intermediate encoded value based on the original encoded data, the encoding base matrix, and the shift value; The verification information generation module is used to generate verification information based on the intermediate encoded value, starting from the shift value.
11. A computer-readable storage medium, wherein, The computer-readable storage medium stores an implementation program for information transmission, which, when executed by a processor, implements the steps of the encoding method as described in any one of claims 1 to 5.
12. A base station, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein, When the computer program is executed by the processor, it implements the steps of the encoding method as described in any one of claims 1 to 5.