Data processing method for memory device, apparatus, and system

Abstract

This application discloses a data processing method for a memory device, an apparatus, and a system, and relates to the field of data storage technologies, so that memory capacity expansion can be implemented, and the memory capacity expansion is not limited by an original quantity of DDR channels. The memory device includes a controller (12), a first memory (13), and a second memory (14), the controller separately communicates with a processor (11), the first memory, and the second memory, and read / write performance of the first memory is higher than read / write performance of the second memory. The method includes: receiving an operation request of the processor, where the operation request includes a logical address; and accessing the first memory or the second memory based on the logical address.

Description

Data processing methods, apparatus and systems for memory devices

[0001] This application claims priority to Chinese patent application No. 202010124905.5, filed with the State Intellectual Property Office of China on February 27, 2020, entitled "A Memory Device", and Chinese patent application No. 202010740899.6, filed with the State Intellectual Property Office of China on July 28, 2020, entitled "Data Processing Method, Apparatus and System for Memory Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of data storage technology, and in particular to data processing methods, apparatus and systems for memory devices. Background Technology

[0003] In traditional technology, the memory controller is built into the central processing unit (CPU), and the memory controller communicates with the dynamic random access memory (DRAM) via a double data rate (DDR) parallel bus, as shown in Figure 1. The CPU accesses the DRAM through the DDR parallel bus.

[0004] With the evolution of manufacturing processes, the number of CPU cores is increasing rapidly. However, limited by the physical constraints of CPU area and DRAM scaling, the growth rate of memory channel count, capacity, and bandwidth cannot fully match that of the CPU, severely impacting overall system performance and creating the memory wall problem. Therefore, solving the memory wall problem is urgently needed.

[0005] One technical solution to the memory wall is shown in Figure 2. Specifically, the memory controller connects to storage class memory (SCM) via a DDR parallel bus to achieve memory expansion. However, this solution occupies additional DDR channels, thus limiting memory capacity expansion to the number of DDR channels. That is, once all DDR channels are used up, memory capacity expansion is no longer possible.

[0006] Summary of the Invention

[0007] This application provides a data processing method, apparatus, and system for memory devices, which can expand memory capacity without being limited by the original number of DDR channels.

[0008] To achieve the above objectives, this application adopts the following technical solution:

[0009] Firstly, a data processing method for a memory device is provided. The memory device includes a controller, a first memory, and a second memory. The controller communicates with a processor, the first memory, and the second memory. The read / write performance of the first memory is higher than that of the second memory. The method includes: receiving an operation request from the processor; the operation request containing a logical address; and accessing the first memory or the second memory based on the logical address. This technical solution enables memory capacity expansion. Furthermore, on the one hand, memory capacity expansion is not limited by the original number of DDR channels. On the other hand, compared with existing technologies, the cost of memory capacity expansion is lower. Moreover, when implementing data operation requests, no application modification or adaptation is required, no corresponding driver installation is required on the operating system, and no BIOS configuration is required, thus simplifying implementation. A detailed analysis can be found below.

[0010] In one possible design, the operation request is a write operation; accessing either the first or second memory based on a logical address specifically includes: writing the data to be written to the storage space indicated by the first physical address in the first memory, where the first physical address is the physical address in the first memory corresponding to the logical address. Since the read / write performance of the first memory is higher than that of the second memory, prioritizing writing data to the first memory helps improve the efficiency of writing data.

[0011] In one possible design, the method further includes: flushing data that meets a first condition from the first memory to the second memory. The data meeting the first condition includes at least one of the following: data whose amount in the first memory is greater than or equal to a first threshold; data whose storage time is greater than or equal to a second threshold; or data whose probability of being read is less than or equal to a third threshold. This technical solution can be considered a data persistence process. On the one hand, this helps free up storage space in the first memory, allowing the processor to continue writing data to it, thereby expanding memory capacity. On the other hand, compared to some traditional technologies that only persist data when the system is powered off, this technical solution does not require a dedicated high-capacity power supply for data persistence, thus helping to save costs.

[0012] In one possible design, the method further includes writing data from the second memory that meets the second condition into the first memory. The data meeting the second condition includes at least one of the following: data to be read predicted based on already read data; data with a probability of being read that is greater than or equal to a fourth threshold; or data to be read when the first memory has not been read, determined based on a read operation sent by the processor. Thus, if the second condition is set reasonably, it can help improve the efficiency of subsequent data reading.

[0013] In one possible design, the method further includes: the operation request is a read operation, accessing either a first memory or a second memory based on a logical address; specifically, if the first memory contains data to be read, then the data to be read is read from the first memory based on the logical address; if the first memory does not contain data to be read, then the data to be read is read from the second memory based on the logical address. Since the read / write performance of the first memory is higher than that of the second memory, this helps to improve the data read rate.

[0014] Secondly, a controller is provided that communicates with a processor, a first memory, and a second memory. The read / write performance of the first memory is higher than that of the second memory. The controller includes a bus interface, a first processor, and a memory controller. The bus interface is used to receive operation requests sent by the processor, and the operation requests include logical addresses. The first processor is used to send a first instruction to the memory controller based on the logical address. The memory controller is used to access the first memory or the second memory based on the first instruction. The first processor can be referred to as a CPU processor, such as an ARM processor or an x86 processor.

[0015] In one possible design, the operation request is a write operation; the memory controller is specifically used to write the data to be written to the storage space indicated by the first physical address of the first memory; the first physical address is the physical address in the first memory that corresponds to the logical address.

[0016] In one possible design, the first processor is further configured to send a second instruction to the memory controller; the memory controller is further configured to, based on the second instruction, flush data in the first memory that meets a first condition to the second memory. The data that meets the first condition includes at least one of the following: data whose amount in the first memory is greater than or equal to a first threshold; data whose storage time is greater than or equal to a second threshold; data whose probability of being read is less than or equal to a third threshold; or, data to be read when the first memory has not been read, determined based on the read operation sent by the processor.

[0017] In one possible design, the first processor is further configured to send a third instruction to the memory controller; the memory controller is further configured to write data in the second memory that meets a second condition into the first memory based on the third instruction. The data that meets the second condition includes at least one of the following: data to be read predicted based on already read data; or data with a probability of being read that is greater than or equal to a fourth threshold.

[0018] In one possible design, the operation request is a read operation, and the memory controller is specifically used to: read the data to be read from the first memory according to the logical address when the first memory contains the data to be read; and read the data to be read from the second memory according to the logical address when the first memory does not contain the data to be read.

[0019] In one possible design, the controller is applied to a memory device, which also includes a first memory and a second memory.

[0020] Thirdly, a controller is provided that communicates with a processor, a first memory, and a second memory respectively; the read / write performance of the first memory is higher than that of the second memory; the controller includes: a receiving unit for receiving an operation request from the processor; the operation request includes a logical address; and a processing unit for accessing the first memory or the second memory according to the logical address.

[0021] In one possible design, the operation request is a write operation; the processing unit is specifically used to: write the data to be written to the storage space indicated by the first physical address of the first memory according to the logical address; the first physical address is the physical address in the first memory corresponding to the logical address.

[0022] In one possible design, the processing unit is further configured to: flush data in the first memory that meets the first condition to the second memory. The data that meets the first condition includes at least one of the following: data whose amount in the first memory is greater than or equal to a first threshold; data whose storage time is greater than or equal to a second threshold; or data whose probability of being read is less than or equal to a third threshold.

[0023] In one possible design, the processing unit is further configured to: write data in the second memory that satisfies the second condition into the first memory. The data satisfying the second condition includes at least one of the following: data to be read predicted based on already read data; data with a probability of being read and equal to a fourth threshold; or, data to be read when the first memory has not been read, determined based on a read operation sent by the processor.

[0024] In one possible design, the operation request is a read operation; the processing unit is specifically used to: when the first memory stores data to be read, read the data to be read from the first memory according to the logical address; when the first memory does not store data to be read, read the data to be read from the second memory according to the logical address.

[0025] In one possible design, the controller is applied to a memory device, which also includes a first memory and a second memory.

[0026] Based on any of the technical solutions provided in the first to third aspects above, the following are several possible designs:

[0027] In one possible design, the persistence performance of the first memory is lower than that of the second memory.

[0028] In one possible design, the first memory is DRAM and the second memory is SCM;

[0029] In one possible design, the first memory is DRAM and the second memory is NAND Flash.

[0030] In one possible design, the controller communicates with the processor via a serial bus.

[0031] In one possible design, the serial bus includes the PCIe bus.

[0032] In one possible design, the memory device is specifically a memory module. Alternatively, the memory device includes a motherboard and a memory module, with the controller fixed on the motherboard, and the memory module comprising a first memory and a second memory.

[0033] Fourthly, a computer system is provided, comprising: a processor, a controller, a first memory, and a second memory. The controller communicates with the processor, the first memory, and the second memory respectively; the read / write performance of the first memory is higher than that of the second memory. The controller is used to execute any method of the first aspect or any possible design provided in the first aspect.

[0034] Fifthly, a chip system is provided, which includes any controller in the second aspect or any possible embodiment of the second aspect, or includes any controller in the third aspect or any possible embodiment of the third aspect.

[0035] In a sixth aspect, a computer-readable storage medium is provided, such as a non-transient computer-readable storage medium. A computer program (or instructions) is stored thereon, which, when executed on a computer, causes the computer to perform any of the methods provided by any possible implementation of the first aspect described above.

[0036] In a seventh aspect, a computer program product is provided that, when run on a computer, causes any method provided by the first aspect or any possible implementation thereof to be executed.

[0037] It is understood that any of the controllers, computer systems, computer storage media, computer program products or chip systems provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.

[0038] In this application, the names of the aforementioned controllers or functional modules do not limit the devices or functional modules themselves. In actual implementation, these devices or functional modules may appear under other names. As long as the functions of each device or functional module are similar to those in this application, they fall within the scope of the claims of this application and their equivalents.

[0039] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0040] Figure 1 is a schematic diagram of the connection relationship between the CPU and DRAM in traditional technology;

[0041] Figure 2 is a schematic diagram of a system for expanding memory capacity using conventional technology;

[0042] Figure 3 is a schematic diagram of the structure of a computer system provided in an embodiment of this application;

[0043] Figure 4A is a schematic diagram of another computer system provided in an embodiment of this application;

[0044] Figure 4B is a schematic diagram of another computer system provided in an embodiment of this application;

[0045] Figure 5 is a schematic diagram of another computer system provided in an embodiment of this application;

[0046] Figure 6 is a schematic diagram of the structure of a controller provided in an embodiment of this application;

[0047] Figure 7 is a schematic diagram of the hardware structure of a computer system provided in an embodiment of this application;

[0048] Figure 8 is a schematic diagram of the hardware structure of another computer system provided in an embodiment of this application;

[0049] Figure 9 is a schematic diagram of the hardware structure of another computer system provided in an embodiment of this application;

[0050] Figure 10A is a flowchart illustrating a method for writing data according to an embodiment of this application;

[0051] Figure 10B is a schematic diagram of a method for a controller to execute writing data based on the method provided in Figure 10A according to an embodiment of this application;

[0052] Figure 11A is a flowchart illustrating a method for exchanging data from a first memory to a second memory according to an embodiment of this application;

[0053] Figure 11B is a schematic diagram of a method for a controller to perform data exchange from a first memory to a second memory based on Figure 11A according to an embodiment of this application;

[0054] Figure 12 is a flowchart illustrating a method for writing data and exchanging data from a first memory to a second memory according to an embodiment of this application.

[0055] Figure 13A is a flowchart illustrating a method for reading data according to an embodiment of this application;

[0056] Figure 13B is a schematic diagram of a controller performing data reading based on the data provided in Figure 13A according to an embodiment of this application;

[0057] Figure 14A is a flowchart illustrating a method for exchanging data from a first memory to a second memory according to an embodiment of this application;

[0058] Figure 14B is a schematic diagram of a method for a controller to perform data exchange from the second memory to the first memory based on Figure 14A according to an embodiment of this application;

[0059] Figure 15 is a schematic diagram of another controller provided in this application;

[0060] Figure 16 is a schematic diagram of another controller provided in this application. Detailed Implementation

[0061] The following explains some of the terms used in the embodiments of this application:

[0062] 1) Memory Expansion

[0063] Memory expansion refers to increasing memory capacity, bandwidth, etc.

[0064] 2) Memory persistence

[0065] Traditional DRAM memory is a volatile solution, meaning data is lost after power failure. Critical data in memory needs to be backed up constantly, and this data needs to be reloaded after power loss. In scenarios with stringent data integrity requirements, the need for persistent memory will continue to grow.

[0066] Data persisted in memory will not be lost after the system is powered off.

[0067] This product (hereinafter referred to as the traditional product) was proposed to address the issue of persistent memory expansion. It is a traditional 288-pin dual in-line memory (DIMM) module, essentially an SCM (Sustainable Memory Center). The technical essence of this traditional product is shown in Figure 2. This solution occupies additional DDR channels, thus limiting memory capacity expansion to the number of DDR channels.

[0068] 3) Other terms

[0069] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0070] In the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0071] In this application, the term "at least one" means one or more, and the term "multiple" means two or more. For example, multiple second messages refer to two or more second messages. The terms "system" and "network" are often used interchangeably in this document.

[0072] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0073] It should also be understood that the term "and / or" as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. The term "and / or" describes an association between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects are in an "or" relationship.

[0074] It should also be understood that, in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0075] It should be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0076] It should also be understood that the term “comprising” (also referred to as “includes”, “including”, “comprises” and / or “comprising”) as used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0077] It should also be understood that the term "if" can be interpreted as meaning "when" or "upon" or "in response to determination" or "in response to detection." Similarly, depending on the context, the phrases "if determination..." or "if detection [the stated condition or event]" can be interpreted as meaning "when determination..." or "in response to determination..." or "when detection [the stated condition or event]" or "in response to detection [the stated condition or event]."

[0078] It should be understood that the phrases "an embodiment," "an embodiment," and "a possible implementation" used throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment or implementation is included in at least one embodiment of this application. Therefore, the phrases "in an embodiment," "an embodiment," or "a possible implementation" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0079] The computer system provided in the embodiments of this application will now be described with reference to the accompanying drawings.

[0080] Figure 3 shows a schematic diagram of a computer system 1 provided in an embodiment of this application. The computer system 1 shown in Figure 3 includes: a processor 11, a controller 12, a first memory 13, and a second memory 14. The controller 12 communicates with the processor 11, the first memory 13, and the second memory 14. In this embodiment, the controller 12, the first memory, and the second memory can constitute a memory device. The specific product form is not limited in this embodiment; for example, it can be a memory module, or it can include a motherboard and a memory module.

[0081] Optionally, the controller 12 and the processor 11 can communicate via a serial bus. For example, the serial bus can be a peripheral component interconnect express (PCIe) bus, etc. The specific examples below will all be illustrated using this example.

[0082] Optionally, the controller 12 and the processor 11 can communicate via a parallel bus.

[0083] The first memory 13 and the second memory 14 are different types of memory, and the read / write performance of the first memory 13 is higher than that of the second memory 14 (e.g., the read / write speed of the first memory 13 is higher than that of the second memory). The first memory 13 and the second memory 14 are respectively connected to the controller 12 through memory interfaces.

[0084] Optionally, the persistence performance of the first memory 13 is lower than that of the second memory 14.

[0085] For example, the first memory 13 is DRAM, and the second memory 14 is SCM. In this case, the first memory 13 is connected to the controller 12 via a DRAM interface, and the second memory 14 is connected to the controller 12 via an SCM interface.

[0086] For example, the first memory 13 is DRAM, and the second memory 14 is NAND flash memory. NAND flash memory is hereinafter referred to as NAND. In this case, the first memory 13 communicates with the controller 12 through the DRAM interface, and the second memory 14 communicates with the controller 12 through the NAND interface.

[0087] Processor 11 is used to send read and / or write instructions to controller 12. Processor 11 may be a CPU, etc.

[0088] The controller 12 is used to read data stored in the first memory 13 based on read instructions sent by the processor 11, and to feed back the read data to the processor 11. It also writes data to the first memory 13 based on write instructions sent by the processor 11. In addition, the controller 12 also has one or more functions such as controlling the exchange of data between the first memory 13 and the second memory 14, localized memory management, address mapping, hotspot data analysis, or data prefetching and unloading management. A description of these functions can be found below.

[0089] Specifically, controller 12 may include a first memory controller and a second memory controller. The first memory controller is used to read and write to the first memory 13, and the second memory controller is used to read and write to the second memory 14. Taking the first memory 13 as DRAM and the second memory 14 as SCM as an example, the first memory controller is specifically a DRAM controller (which is equivalent to the "memory controller" described in conventional technology, as shown in Figure 1); the second memory controller is specifically an SCM controller.

[0090] Optionally, the processor 11 may or may not have a built-in memory controller.

[0091] The following is a detailed explanation of the computer system 1 shown in Figure 3 through specific examples:

[0092] Taking processor 11 as a CPU, first memory 13 as DRAM, and second memory 14 as SCM as an example, the first memory controller in controller 12 is used to read and write to the DRAM. The second memory controller in controller 12 is used to read and write to the SCM. The first memory controller communicates with the DRAM via a DDR parallel bus. Figures 4A and 4B show schematic diagrams of the structures of two computer systems provided in this application based on this example.

[0093] In the computer system shown in Figure 4A, the CPU does not have a built-in memory controller. Compared to the computer system shown in Figure 1, the improvements of the computer system shown in Figure 4A can be considered as follows: First, the memory controller built into the CPU in Figure 1 has been moved outside the CPU. In other words, the memory controller built into the CPU in Figure 1 and the first memory controller in the controller shown in Figure 4A can be considered the same device. Second, a second memory controller is set in the controller to realize the reading and writing of the newly added SCM. Third, the connection between the controller and the CPU has been increased.

[0094] The computer system shown in Figure 4A increases memory capacity by adding an SCM. This scheme does not use the DDR parallel bus between the original memory controller (equivalent to the memory controller in Figure 1) and the original DRAM (equivalent to the DRAM in Figure 1). Therefore, memory capacity expansion is not limited by the original number of DDR channels. Specifically, the DDR parallel bus between the original memory controller and the original DRAM is the DDR parallel bus between the first memory controller and the DRAM in Figure 4A.

[0095] In the computer system shown in Figure 4B, the CPU has a built-in memory controller. Compared to the computer system shown in Figure 1, the improvements of the computer system shown in Figure 4B can be considered as follows: Based on Figure 1, the CPU is connected to the controller via a serial bus. Furthermore, this controller is also connected to DRAM and SCM, and it includes a first memory controller and a second memory controller to enable reading and writing to the newly added DRAM and SCM. In this embodiment, to distinguish between the DRAM connected to the CPU's built-in memory controller and the DRAM connected to the first memory controller, the DRAM connected to the CPU's built-in memory controller is referred to as the "original DRAM" in Figure 4B.

[0096] The computer system shown in Figure 4B increases memory capacity by adding DRAM and SCM. This technical solution does not use the original DDR parallel bus between the memory controller and the original DRAM; therefore, memory capacity expansion is not limited by the original number of DDR channels. Specifically, the original DDR parallel bus between the memory controller and the original DRAM refers to the DDR parallel bus between the CPU's built-in memory controller and the original DRAM in Figure 4B.

[0097] Furthermore, in the computer systems shown in Figures 4A and 4B, since the controller is responsible for reading, writing, and exchanging data in memory (including DRAM and SCM), if the controller prioritizes writing data to DRAM and reading data from DRAM, then the CPU will perceive that it is constantly accessing a large-capacity DRAM (here, "large capacity" actually refers to the capacity of the SCM, relative to the capacity of the DRAM itself), but will not perceive that this large-capacity DRAM is actually the SCM. For example, assuming the DRAM capacity is 1GB and the SCM capacity is 10GB, then the CPU will perceive a 10GB memory capacity, where the 1GB DRAM is used as a cache for the 10GB SCM.

[0098] On the one hand, since the CPU is unaware of the newly added SCM, it is also unaware of the data read / write and data exchange processes executed by the controller. Therefore, the data read / write and data exchange processes do not require application modifications or adaptations, the operating system to install corresponding drivers, or the Basic Input Output System (BIOS) configuration.

[0099] It should be noted that traditional products require application modifications and adaptations, the installation of corresponding drivers in the operating system, and BIOS configuration to achieve data persistence.

[0100] It should also be noted that the technical solution provided in this application supports partial and full persistence of data written by the CPU. Data persistence can be considered as data being written from DRAM to SCM. The specific process of persistence can be referred to below. Based on the above description, when applied to data persistence scenarios, comparing traditional products and the technical solution provided in this application: traditional products tend to move persistence management upwards, with a high degree of "softening" (i.e., software implementation); the technical solution provided in this application tends to push persistence management downwards, with a high degree of "hardening" (i.e., hardware implementation).

[0101] On the other hand, since the cost of SCM is lower than that of DRAM, this technical solution helps to achieve low-cost memory capacity expansion compared to existing technical solutions that "expand memory capacity by adding additional DRAM" (e.g., the technical solution shown in Figure 2).

[0102] It should be noted that even in actual implementation, when the controller has no data to be read in the DRAM, it will still read the data from the SCM. This requires adjusting the data exchange strategy between the DRAM and the SCM to balance the overall read / write performance and cost of the computer system, thereby optimizing the overall performance of the computer system. A detailed description of the data exchange strategy provided in the embodiments of this application can be found below.

[0103] In summary, the computer system provided in this application embodiment can achieve memory capacity expansion. Furthermore, on the one hand, memory capacity expansion is not limited by the original number of DDR channels. On the other hand, compared with existing technologies (as shown in Figure 2), the cost of memory capacity expansion is lower. Moreover, when the computer system performs data read and write operations, no application modification or adaptation is required, no corresponding drivers need to be installed on the operating system, and no BIOS configuration is required, thus simplifying implementation. In addition, this technical solution can expand memory bandwidth while expanding memory capacity. Specifically, expanding memory bandwidth is from the perspective of the serial bus; since the serial bus does not occupy the CPU's original DDR channels, it can expand (or increase) memory bandwidth.

[0104] The computer system 1 shown in FIG3 provided in the embodiments of this application will be described in detail below:

[0105] Figure 5 shows a schematic diagram of another computer system 1 provided in an embodiment of this application. Figure 5 is drawn based on Figure 3. Specifically, the controller 12 in Figure 3 may include the following modules / devices:

[0106] Serial host interface 121 is used for communication between controller 12 and processor 11. Optionally, serial host interface 121 can be a front-side bus interface based on a low-latency serial bus and high-speed SerDes serial-to-parallel conversion, supporting memory semantics. SerDes is short for serializer / deserializer.

[0107] The hybrid memory management unit (HMMU) 122 is used to combine the features of the first memory 13 and the second memory 14 to realize functions such as localized memory management, address mapping, hotspot data analysis, and data prefetching and unloading management.

[0108] First memory controller 123: used for data read / write control and management of first memory 13.

[0109] Second memory controller 124: used for data read / write control and management of second memory 14.

[0110] Data switch engine 125: This is a key module used to establish a data path between hybrid media. Data switch engine 125 is connected to the first memory controller 123 and the second memory controller 124 respectively, and is used to exchange data between the first memory 13 and the second memory 14 by controlling the first memory controller 123 and the second memory controller 124. For example, it can read data stored in the first memory 13 and write it to the second memory 14 to achieve data persistence. Conversely, it can read data stored in the second memory 14 and write it to the first memory 13 to enable the controller 12 to quickly read data.

[0111] Firmware module 127: This module is used to implement key algorithms such as memory persistence, mixed media management, and table entry mapping.

[0112] It should be noted that the connection relationship between the modules / devices shown in Figure 5 can be referred to Figure 5, and will not be repeated here.

[0113] Figure 6 shows a schematic diagram of the structure of a controller 12 provided in an embodiment of this application. Figure 6 is drawn based on Figure 5. Furthermore, Figure 6 is illustrated using the example of "processor 11 specifically being a CPU, first memory 13 specifically being DRAM, and second memory 14 specifically being SCM".

[0114] The serial bus interface 121 may include a port physical layer (PHY), high-speed Serdes (HS Serdes), and a memory protocol module. The PHY represents the physical layer of the storage medium, the HS Serdes are used for serial-to-parallel conversion, and the memory protocol module is used to parse protocols related to data storage.

[0115] The first memory controller 123 (specifically a DRAM controller) may include:

[0116] Read queue: This is a queue control module consisting of all read requests in the first memory controller 12.

[0117] Write queue: This is a queue control module consisting of all write requests in the first memory controller 123.

[0118] The transaction module is the control module in the first memory controller 123 that initiates read and write operation commands to the DRAM. The transaction module can also be referred to as the interaction module.

[0119] DDR interface: This is the module that initiates read and write operation commands to the DRAM.

[0120] DDRPHY: This is the physical interface of the DRAM controller.

[0121] The second memory controller (specifically the SCM controller) 124 may include:

[0122] IO sequencer: A module that schedules SCM read and write IO requests. Optionally, the IO sequencer may include a normal queue and an urgent queue.

[0123] Backend datapath: Modules that process data for SCM, including but not limited to at least one of the following modules: error checking and correcting (ECC) module, scrambling (SCR) module, or encryption / decryption module, etc.

[0124] SCM interface: This is the module that initiates read and write operation commands to the SCM.

[0125] SCMPHY: This is the physical interface of the SCM controller.

[0126] Optionally, the second memory controller 124 may also include:

[0127] Redundant Array of Independent Disks (RAID) module: A module that performs RAID operations on SCM data.

[0128] Data buffer: Serves as a buffer for SCM read and write data, and can be, for example, static random-access memory (SRAM).

[0129] Firmware module 127 may include:

[0130] The hybrid flash translation layer (HFTL) is a Hybrid-FTL algorithm provided in this application embodiment that supports hybrid media table management. It optimizes memory semantics and is used to access the first or second memory based on the logical address in the operation request from the processor, i.e., to map the logical address to the physical address of the first or second memory. HFTL can be used to implement some functions of firmware module 127. Of course, firmware module 127 can also include other functional modules to implement other functions of firmware module 127. Additionally, as an example, HFTL and HMMU122 can be located in the CPU system of controller 12. Furthermore, the CPU system can also include a CPU processor, such as an ARM (advanced RISC) processor. RISC is an abbreviation for reduced instruction set computer. It should be noted that the ARM processor can also be replaced by other types of processors, such as x86 processors. The specific examples below are all based on ARM processors.

[0131] Based on Figure 5, the controller 12 may also include:

[0132] DDR datapath control module 128: This is the control module that initiates read requests to the DRAM controller.

[0133] SCM datapath control module 129: This is the control module that initiates read requests to the SCM controller.

[0134] Optionally, the controller 12 may also include:

[0135] Compression / decompression module 130: This is a hardware implementation of a high-performance memory compression / decompression algorithm. The compression and decompression modules can be implemented using the same hardware or different hardware. Alternatively, at least one of the compression and decompression modules can be implemented in software, or a combination of software and hardware. This application does not limit this implementation.

[0136] The hardware accelerator system 131 is a high-performance hardware acceleration unit that can assist in accelerating the algorithms of HMMU and HFTL.

[0137] It should be noted that, in actual implementation, the management of entries in the HMMU and HFTL (such as adding, modifying, or deleting entries) can be performed by the CPU processor in the CPU system (such as the ARM processor described in this article) or by the hardware acceleration system 131. For ease of explanation, the specific examples below will all use the example of the management of entries in the HMMU and HFTL being performed by the ARM processor.

[0138] It is understood that Figure 6 is merely an example, and in actual implementation, the controller 12 may contain more or fewer devices / modules than shown in Figure 6. Furthermore, the specific implementation of each module shown in Figure 6, etc., can be referenced from relevant prior art, provided it does not conflict with the technical solutions described in the embodiments of this application.

[0139] It should be noted that when the first memory 13 and the second memory 14 are other types of memory, those skilled in the art can determine the specific implementation of the controller 12 based on the description in Figure 6, which will not be elaborated here.

[0140] The following describes the specific implementation of computer system 1 in terms of hardware. Specifically, the controller 12 described above can be implemented using a chip.

[0141] In one implementation, as shown in Figure 7, the controller 12, the first memory 13, and the second memory 14 can be housed on a hardware module, which can be interconnected with the processor 11 via a serial bus. This implementation allows for persistent memory storage on a single module. Optionally, the hardware module can be customized. As an example, this hardware module can also be called a memory expansion module or a memory module; that is, the memory device described above exists specifically in the form of a memory module.

[0142] Taking a first memory module 13 as DRAM and a second memory module 14 as SCM as an example, the hardware module can be similar in form to a standard DIMM module. The difference is that the DIMM module uses DRAM chips and runs on a parallel bus, while this hardware module uses hybrid media chips (i.e., DRAM chips and SCM chips) and runs on a serial bus. In specific implementation, the processor 11 can support access to this hardware module on the serial bus through custom semantics.

[0143] Optionally, the aforementioned hardware module can be a standard PCIe module. The PCIe module is interconnected with the processor 11 via the PCIe bus, as shown in Figure 8. This implementation scheme allows for customization of the hardware module. In specific implementation, the processor 11 can support access to the hardware module on the PCIe bus. The module's form is similar to that of a standard PCIe disk. Taking the first memory 13 as DRAM and the second memory 14 as SCM as an example, the difference between this module's form and that of a standard PCIe disk is that a standard PCIe disk uses NAND flash memory, supporting only IO semantics (block semantics), while this module uses mixed media chips, supporting only memory semantics.

[0144] In practice, this implementation requires customized hardware and the conversion of I / O semantics to memory semantics via the standard PCIe bus. The access bandwidth is limited by the PCIe standard (e.g., the bandwidth of a single PCIe 4.0 lane is 2GB / s).

[0145] In another implementation, as shown in Figure 9, the controller 12 can be soldered onto the motherboard, with one side interconnected with the processor 11 via a serial bus. The other side can connect to the first memory 13 and the second memory 14. Taking the first memory 13 as DRAM and the second memory 14 as SCM as an example, this other side can connect to a standard DIMM-type DRAM memory module and a customized DIMM-type SCM memory module. In this case, the memory device described above exists specifically in the form of a motherboard, the first memory, and the second memory. Optionally, the first memory and the second memory are located in a hardware module (or memory module), in which case the memory device described above exists specifically in the form of a motherboard and a memory module.

[0146] In practical implementation, this scheme solders the controller 12 onto the motherboard. Memory expansion and persistence can be achieved by inserting DRAM memory modules and customized SCM memory modules into the motherboard's standard DIMM slots. Hybrid media memory modules can also be directly customized. This scheme requires a reserved space for the controller 12 on the motherboard to achieve memory expansion and persistence, and the expansion capability is limited by the maximum number of channels supported by a single chip.

[0147] It is understood that, based on any of the above implementation methods, the capacity of the first memory 13 and the capacity of the second memory 14 can be configured according to one or more of the following conditions: the performance of the first memory 13 and the second memory 14, the cost of the hardware module, and the application scenario. This application embodiment does not limit this.

[0148] The data read / write process and data exchange process provided in the embodiments of this application are described below with reference to the accompanying drawings:

[0149] Data writing process

[0150] Figure 10A is a flowchart illustrating a method for writing data according to an embodiment of this application. The method shown in Figure 10A can be applied to the computer system shown in Figure 3. The method shown in Figure 10A may include the following steps:

[0151] S101: The processor sends a write operation to the controller, which includes the data to be written and the first logical address.

[0152] It's important to note that for the processor, the address carried in a write operation is a physical address. For the controller, the address carried in a write operation is a logical address. This description uses the controller as an example.

[0153] S102: The controller translates the first logical address into the first physical address of the first memory, and writes the data to be written into the storage space indicated by the first physical address in the first memory. Then the controller updates the HMMU information it maintains.

[0154] Optionally, the controller may update its own maintained HMMU information by writing first information into its own maintained HMMU information, the first information being used to indicate that data at the first logical address has been cached in the first memory.

[0155] As an example, S102 can be considered as a data caching process.

[0156] S103: The controller determines whether old data corresponding to the first logical address exists in the second memory. That is, whether the storage space indicated by the physical address of the second memory obtained from the translation of the first logical address contains data.

[0157] If so, it means that the old data corresponding to the first logical address has been flushed to the second memory, then execute S104.

[0158] If not, the data writing process ends.

[0159] Here, the old data is relative to the data to be written in S101. Both the old data and the data to be written are data corresponding to the first logical address, but in terms of writing time, the old data is written first, while the data to be written is written later.

[0160] S104: The controller marks the old data corresponding to the first logical address recorded in the second memory as invalid data.

[0161] It should be noted that invalid data can be deleted during garbage collection (GC), thus saving storage space.

[0162] After executing S104, the data writing process ends.

[0163] In this embodiment, the controller prioritizes writing data to the first memory. Since the read / write performance of the first memory is higher than that of the second memory, this embodiment helps to improve data writing efficiency.

[0164] Figure 10B is a schematic diagram illustrating a method for a controller to perform data writing based on Figure 10A, according to an embodiment of this application. The method shown in Figure 10B can be applied to the controller shown in Figure 6. The method shown in Figure 10B may include the following steps:

[0165] S201: The serial bus interface receives write operations sent by the processor and parses the write operation. The write operation includes the data to be written and a first logical address.

[0166] Specifically, the PHY in the serial bus interface receives write operations sent by the processor, and the HS Serdes, in conjunction with the memory protocol (i.e., the parallel transmission protocol), performs serial-to-parallel conversion on the write operation. The process of performing this conversion can be considered the concrete implementation of parsing the write operation.

[0167] S202: The serial bus interface will send the first logical address obtained after parsing the write operation to the CPU system.

[0168] S203: The ARM processor in the CPU system converts the first logical address into a first physical address based on the correspondence between logical addresses and DRAM physical addresses. Then, the first physical address is sent to the DDR data path control module, which in turn sends a DRAM write instruction to the write queue in the DRAM controller. The DRAM write instruction includes the first physical address.

[0169] S204: The serial bus interface will send the data to be written obtained after parsing the write operation to the compression module for compression. The compression module will then send the compressed data to be written to the operation module of the DRAM controller via the DDR interface of the DRAM controller.

[0170] In this embodiment, the execution order of S203 and S204 is not limited.

[0171] S205: The operation module in the DRAM controller writes the data to be written to the memory space indicated by the first physical address of the DRAM based on the DRAM write instruction received from the write queue. Subsequently, the DRAM controller sends a response indicating that the data to be written has been completed to the ARM processor in the CPU system, so that the ARM processor in the CPU system executes S206.

[0172] Optionally, S203 and S206 can be executed in parallel. That is, executing S206 does not require waiting for the DRAM controller to send a response to the ARM processor in the CPU system indicating that the data to be written has been completed. This helps to reduce the pressure on the ARM processor.

[0173] S206: The ARM processor in the CPU system updates the HMMU information. Specifically, it adds first information to the HMMU information, which indicates that data at the first logical address has been cached in DRAM.

[0174] S207: If the ARM processor in the CPU system determines that old data corresponding to the first logical address already exists in the SCM, it marks the old data as invalid data.

[0175] Subsequently, when the SCM controller executes the invalid data reclamation mechanism, it can delete the data in the storage space corresponding to the second physical address in the SCM based on the execution result of S207. Here, the second physical address is the physical address in the SCM that is translated from the first logical address.

[0176] The technical solutions shown in Figures 10A and 10B above are illustrated using the data read / write granularity of the first memory as an example. However, the specific implementation is not limited to this. For instance, the data read / write granularity of the second memory is typically larger than that of the first memory. Taking DRAM as the first memory and SCM as the second memory, the data read / write granularity of DRAM can be 8 bytes, while the data read granularity of SCM is a page (or page), for example, a page size of 4KB. In one example, after receiving a write operation including the data to be written and a first logical address, the controller can determine whether the data in the logical page containing the first logical address already exists in the first memory. If so, the data to be written is written to the storage space indicated by the physical address corresponding to the first logical address in the first memory. If not, the data corresponding to the logical page containing the first logical address is read from the second memory, and the data corresponding to the first logical address in the read data is replaced with the data to be written, resulting in new data corresponding to the logical page containing the first logical address. This new data is then written to the storage space indicated by the physical address corresponding to that logical page in the first memory. Subsequently, the controller can mark the data corresponding to the logical page containing the first logical address in the second memory as invalid data. This technical solution ensures that all data corresponding to a page is in the first and / or second memory, thereby improving data reading efficiency. The specific data reading process in this case will not be elaborated here.

[0177] The process of data being swapped from the first memory to the second memory

[0178] Figure 11A is a flowchart illustrating a method for exchanging data from a first memory to a second memory according to an embodiment of this application. The method shown in Figure 11A can be applied to the computer system shown in Figure 3. The method shown in Figure 11A may include the following steps:

[0179] S301: The controller determines whether there is data in the first memory that meets the first condition. The presence of data in the first memory that meets the first condition can be considered as the presence of data in the first memory that meets the criteria for being flushed to the second memory.

[0180] If yes, then execute S302. If no, then S301 can be executed again the next time the triggering condition of S301 is met.

[0181] Optionally, the data that satisfies the first condition includes at least one of the following:

[0182] Data when the amount of data in the first memory is greater than or equal to the first threshold;

[0183] Data whose storage time is greater than or equal to the second threshold;

[0184] Data whose probability of being read and hit is less than or equal to the third threshold. For example, data in the first memory with a probability of being read and hit less than or equal to the third threshold within a preset time period.

[0185] As an example, the first threshold, second threshold, and third threshold mentioned above can be considered as a spatial threshold, a temporal threshold, and a popularity threshold, respectively. That is, embodiments of this application can determine whether the data in the first memory meets the criteria for being flushed to the second memory based on at least one of the spatial threshold, temporal threshold, and popularity threshold. Of course, the specific implementation is not limited to this. For example, if the proportion of the data stored in the first memory to the total data volume in the first memory is greater than or equal to a fourth threshold, then the data stored in the first memory is considered to meet the first condition, etc.

[0186] This application embodiment does not limit the triggering conditions for the controller to execute S301. For example, the controller can execute S301 periodically or trigger it. For example, triggering the controller to execute S301 may include: the controller executes S301 after executing S104 once or multiple times. That is, the controller executes S301 after completing the data writing process once or multiple times. As another example, a specific example of the controller triggering the execution of S301 may be included in the embodiment shown in Figure 12 below, as detailed below.

[0187] S302: The controller flushes the data that meets the first condition from the first memory to the second memory. Specifically, the controller reads the data that meets the first condition from the first memory and stores the read data in the second memory.

[0188] As an example, since the persistence performance of the first memory is lower than that of the second memory, the process of flushing data from the first memory to the second memory can be considered as a data persistence process. In this embodiment, the controller performs the data persistence process when data satisfying the first condition exists in the first memory. This helps to free up storage space in the first memory, allowing the processor to continue storing data in it, thereby expanding memory capacity. Furthermore, compared to some conventional technologies that only perform data persistence when the system is powered off, this solution does not require a dedicated high-capacity power supply for data persistence, thus saving costs.

[0189] After executing S302, the data persistence process ends.

[0190] In this embodiment, when data satisfying the first condition exists in the first memory, the controller swaps this data from the first memory to the second memory. Optionally, the controller can delete the swapped-out data from the first memory. This helps to free up storage space in the first memory, allowing the processor to write more data into it; furthermore, data stored in the second memory is generally not lost when the system loses power, thus achieving data persistence. Of course, persistence here can refer to the persistence of some or all of the data written by the processor.

[0191] Figure 11B is a schematic diagram illustrating a method for a controller to exchange data from a first memory to a second memory, based on the information provided in Figure 11A, according to an embodiment of this application. The method shown in Figure 11B can be applied to the controller shown in Figure 6. The method shown in Figure 11B may include the following steps:

[0192] S401: The ARM processor in the CPU system determines whether there is data in the DRAM that meets the first condition.

[0193] If yes, then execute S402. If not, then S401 can be executed again the next time the triggering condition of S401 is met.

[0194] S402: The ARM processor in the CPU system sends a DRAM data swap-out command to the data exchange engine. The DRAM data swap-out command is used to swap the data to be swapped out from DRAM to SCM.

[0195] Optionally, the ARM processor in the CPU system can also send the physical address, page size, and SCM physical page information of the data to be swapped out in DRAM to the data exchange engine. Alternatively, one or more of the physical address, page size, or SCM physical page information of the data to be swapped out in DRAM can be carried in the DRAM data swapping command.

[0196] S403: The data exchange engine sends memory read commands to the read queue of the DRAM controller via the DDR data channel control module. The memory read command includes the physical address of the data to be swapped out in the DRAM.

[0197] S404: The operation module in the DRAM controller reads the data to be swapped out from the DRAM based on the memory read instruction received from the read queue.

[0198] S405: The operation module in the DRAM controller returns the read data to be swapped out to the data exchange engine.

[0199] S406: The data exchange engine writes the data to be swapped out returned by the DRAM controller to the pre-allocated data cache space.

[0200] S407: The data exchange engine sends an instruction to the IO sequence generator to flush the data to be swapped out to the SCM, and informs the IO sequence generator of the location information of the data to be swapped out in the data buffer space, etc.

[0201] S408: The IO sequence generator sends a write data command to the SCM data channel control module to activate the operation corresponding to the data to be swapped out and allocate channel resources for the data to be swapped out. This write data command includes information such as the location of the data to be swapped out in the data buffer space. This operation includes, but is not limited to, at least one of the following: cyclic redundancy check (CRC) verification, scrambling operation, ECC operation, RAID operation, or encryption operation.

[0202] S409: The SCM data channel control module retrieves the data to be swapped out from the data buffer space based on the write data command issued by the IO sequence generator.

[0203] Subsequently, the SCM data channel control module sends a response to the IO sequence generator indicating completion of data retrieval (not shown in Figure 11B). Following this, the data to be swapped out is sent from the data buffer space, through the RAID module and backend data channels, to the SCM interface. The dashed lines with arrows in Figure 11B illustrate the data flow of the data to be swapped out. It should be noted that in actual implementation, the SCM data channel control module can send commands to the backend data channels to establish a data flow path for the data to be swapped out.

[0204] S410: The IO sequence generator sends write data commands to the SCM interface and configures the corresponding physical information of the SCM.

[0205] The execution order of S408 and S410 is not limited in this embodiment. For example, they can be executed simultaneously or sequentially.

[0206] S411: After receiving the data to be swapped out, the SCM interface, based on the write data instruction issued by the IO sequence generator and the physical information configured in S410, issues a write command sequence to the SCM and transmits the data to be swapped out to the SCM.

[0207] Subsequently, the SCM interface sends a response to the IO sequence generator indicating that the data to be swapped out has been written to the SCM.

[0208] S412: The IO sequence generator sends an HFTL report write command completion to the ARM processor in the CPU system, so that the ARM processor updates the corresponding HFTL table entry information. A specific example of the updated table entry information can be found in S207.

[0209] Specifically, the IO sequence generator can execute S412 after receiving the response from the SCM data channel control module that the data to be swapped out has been captured (as described in S409) and the response from the SCM interface that the data to be swapped out has been written to the SCM (as described in S411).

[0210] S413: The ARM processor in the CPU system updates the corresponding entries in the HMMU. For a specific example of the updated entries, please refer to S206.

[0211] The process of writing data and swapping data from the first memory to the second memory

[0212] Figure 10A above describes the data writing process, and Figure 11A above describes the data persistence process. Figure 12 below describes an application example combining the two processes.

[0213] Figure 12 is a flowchart illustrating a method for writing data and swapping data from a first memory to a second memory according to an embodiment of this application. The method shown in Figure 12 includes the following steps:

[0214] S501~S502: Refer to S101~S102 above.

[0215] S503: The controller determines whether there is data in the first memory that meets the first condition. See S301 for details.

[0216] If yes, then execute S504; otherwise, execute S505.

[0217] S504: The controller flushes the data that meets the first condition from the first memory to the second memory. See S302 for details.

[0218] After executing S504, the data persistence process ends.

[0219] S505: The controller determines whether the old data corresponding to the first logical address exists in the second memory. See S103 for details.

[0220] If yes, then execute S506. If no, then the current data writing process ends.

[0221] S506: The controller marks the old data corresponding to the first logical address recorded in the second memory as invalid data. See S104 for details.

[0222] After executing S506, the current data writing process ends.

[0223] Comparing Figures 12 and 10A, we can see that in the technical solution shown in Figure 10A, the controller marks the old data corresponding to the first logical address recorded in the second memory as invalid data only if the data is cached in the first memory and it is confirmed that the old data corresponding to the first logical address exists in the second memory. In the technical solution shown in Figure 12, the controller marks the old data corresponding to the first logical address recorded in the second memory as invalid data only if the data is cached in the first memory, it is confirmed that the old data corresponding to the first logical address exists in the second memory, and the flushing standard is met. This is because if the flushing standard is met, the data corresponding to the first logical address in the second memory has already been updated to the latest data, therefore, it does not need to be marked as invalid data again. This saves processing steps and improves processing efficiency.

[0224] Data reading process

[0225] Figure 13A is a flowchart illustrating a method for reading data according to an embodiment of this application. The method shown in Figure 13A can be applied to the computer system shown in Figure 3. The method shown in Figure 13A may include the following steps:

[0226] S601: The processor sends a read operation to the controller, which includes the logical address to be read.

[0227] S602: The controller translates the logical address to be read into the physical address of the first memory.

[0228] S603: The controller determines whether data is stored in the storage space indicated by the physical address of the first memory.

[0229] If not, execute S604; if yes, execute S606.

[0230] S604: The controller translates the logical address to be read into the physical address of the second memory.

[0231] S605: The controller reads data from the storage space indicated by the physical address of the second memory and writes the read data into the first memory.

[0232] S606: The controller reads data from the storage space indicated by the physical address of the first memory.

[0233] S607: The controller returns the read data to the processor.

[0234] After executing S607, the data reading process ends.

[0235] In this embodiment, the controller preferentially reads data from the first memory. Since the read / write performance of the first memory is higher than that of the second memory, this technical solution helps to improve the data reading rate.

[0236] Figure 13B is a schematic diagram illustrating a process of a controller performing data reading based on the data provided in Figure 13A according to an embodiment of this application. The method shown in Figure 13B can be applied to the controller shown in Figure 6. The method shown in Figure 13B may include the following steps:

[0237] S701: The serial bus interface receives read operations sent by the processor and parses them. This operation includes the logical address to be read.

[0238] Specifically, the PHY in the serial bus interface receives read operations sent by the processor, and the HS Serdes, in conjunction with the memory protocol (i.e., the parallel transmission protocol), performs serial-to-parallel conversion on the read operation. The process of performing this conversion can be considered the concrete implementation of parsing the read operation.

[0239] S702: The serial bus interface will send the logical address to be read obtained from the read operation to the DDR data channel control module.

[0240] S703: The DDR data channel control queries the ARM processor in the CPU system to check whether the data (i.e., the data to be read) stored in the memory space indicated by the logical address to be read is located in DRAM.

[0241] If the ARM processor in the CPU system determines that the data to be read is located in DRAM, i.e., a DRAM read hit, then it executes S704.

[0242] If the ARM processor in the CPU system determines that the data to be read is not located in DRAM, i.e., the DRAM read is not successful, it executes the process of swapping the data to be read from the second memory to the first memory. The specific implementation of this process can be referred to in the embodiment shown in Figure 14B below. Then, S704 is executed.

[0243] Whether a DRAM read is successful and the physical address of the data to be read in the DRAM can both be obtained by the ARM processor in the CPU system by querying the HMMU.

[0244] S704: The ARM processor in the CPU system returns information such as the physical address of the data to be read in DRAM to the DDR data channel control module. The physical address of the data to be read in DRAM is obtained by translating the logical address.

[0245] S705: The DDR data channel control module sends memory read commands to the read queue of the DRAM controller. These memory read commands contain information such as the physical address of the data to be read in the DRAM.

[0246] S706: The operation module in the DRAM controller reads the data to be read based on the memory read instruction received from the read queue. The DRAM controller can send the read data to the decompression module, which decompresses the data and then returns the decompressed data to the processor through the serial bus interface. The dashed lines with arrows in Figure 13B illustrate the data flow of the data to be read.

[0247] The process of swapping data from the second memory to the first memory

[0248] Figure 14A is a flowchart illustrating a method for exchanging data from a second memory to a first memory according to an embodiment of this application. The method shown in Figure 14A can be applied to the computer system shown in Figure 3. The method shown in Figure 14A may include the following steps:

[0249] S801: The controller determines whether there is data in the second memory that meets the second condition. The existence of data in the second memory that meets the second condition can be considered as the presence of standard data in the second memory that would be swapped to the first memory.

[0250] If yes, then execute S802. If no, then end. Subsequently, the controller can return to execute S801 the next time the trigger condition of S801 is met.

[0251] Optionally, the data that satisfies the second condition includes at least one of the following:

[0252] Data to be read is predicted based on already read data;

[0253] Data whose probability of being read and matched is greater than or equal to the fourth threshold;

[0254] Alternatively, based on the read operations sent by the processor, determine the data to be read when there is no read hit in the first memory.

[0255] It should be noted that in the specific implementation, the data read by the processor in chronological order has a certain correlation. Therefore, the controller can predict the data to be read based on historical read data. The prediction method can refer to existing technologies and will not be elaborated here. Since the predicted data to be read has a high probability of being read by the processor later, the controller can swap the predicted data to be read from the second memory to the first memory, which can improve the efficiency of subsequent data reading.

[0256] The aforementioned fourth threshold can be considered a time threshold or a hot data threshold. In other words, data with a probability of being read that is greater than or equal to the fourth threshold can be considered hot data. Hot data has a higher probability of being read by the processor subsequently. Therefore, the controller can swap the predicted data to be read from the second memory to the first memory, which can improve the efficiency of subsequent data reading.

[0257] Based on the read operation sent by the processor, the data to be read is determined when there is no read hit in the first memory, specifically the data to be read shown in Figure 13A. In other words, one of the triggering conditions for the controller to swap data from the second memory to the first memory can be that no read hit occurs in the first memory during the controller's read operation.

[0258] S802: The controller swaps data that meets the second condition from the second memory to the first memory. Specifically, the controller reads data that meets the second condition from the second memory and stores the read data in the first memory.

[0259] After executing S802, this data exchange process ends.

[0260] In this embodiment, when data satisfying the second condition exists in the second memory, the controller swaps this data from the second memory to the first memory. This, when the second condition is set appropriately, helps improve the efficiency of subsequent data reading.

[0261] Figure 14B is a schematic diagram illustrating a method for a controller to exchange data from a second memory to a first memory, based on the information provided in Figure 14A, according to an embodiment of this application. The method shown in Figure 14B can be applied to the controller shown in Figure 6. The method shown in Figure 14B may include the following steps:

[0262] S901: The ARM processor in the CPU system determines whether there is data in the second memory that meets the second condition.

[0263] If yes, then execute S902. If no, then end. Subsequently, the controller can return to execute S901 the next time the trigger condition of S901 is met.

[0264] S902: The ARM processor in the CPU system determines the physical address of the data in the second memory that meets the second condition, and uses this physical address as the third physical address; and issues a read command to the IO sequence generator. This read command includes the third physical address.

[0265] S903: The IO sequence generator sends a read data command to the SCM interface and configures the corresponding physical information.

[0266] S904: The SCM interface issues a sequence of read commands to the SCM and waits for the SCM to prepare the data.

[0267] S905: After the SCM data preparation is complete, the SCM interface returns the relevant IO preparation completion information to the IO sequence generator.

[0268] S906: The IO sequence generator sends a read data command to the SCM data channel control module, activates the corresponding operation for the data, including but not limited to: CRC / De-scramble / ECC / RAID / Decryption, and allocates data channel resources.

[0269] Subsequently, the data to be swapped out is transmitted from the SCM to the backend data channel via the SCM interface. After error correction and decoding by the backend data channel, the data is sent to the data buffer space via the RAID module. The dashed line with arrows in Figure 14B illustrates the data flow of the data to be swapped out. In specific implementation, the SCM data channel control module sends a command to the backend data channel to establish the data flow channel for the data to be swapped out.

[0270] S907: After the data is written to the data cache space, the IO sequence generator notifies the data exchange engine that the data to be flushed to DRAM is ready in the data cache space and informs the data of its location in the data cache space.

[0271] S908: The data exchange engine issues DRAM write commands and sends them to the write queue of the DRAM controller through the DDR data channel control module.

[0272] S909: The data exchange engine reads data from the location corresponding to the data cache space.

[0273] S910: The data exchange engine writes the data returned from the data cache space to the specified physical address of the DRAM through the DRAM controller. This specified physical address of the DRAM corresponds to the same physical address as the third physical address mentioned above.

[0274] S911: The data exchange engine has completed sending a read command to the ARM processor in the CPU system.

[0275] S912: The ARM processor in the CPU system updates the corresponding entry information in the HMMU. Specifically, after executing S915, the HMMU information maintained by the HMMU is marked with "The data corresponding to the third physical address (or the logical address corresponding to the third physical address, or the physical address corresponding to the third physical address in DRAM) has been written to DRAM".

[0276] The foregoing mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, it includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0277] This application embodiment can divide the controller into functional modules according to the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0278] Figure 15 shows a schematic diagram of a controller according to an embodiment of this application. The controller 150 shown in Figure 15 communicates with a processor, a first memory, and a second memory; the read / write performance of the first memory is higher than that of the second memory. The controller 150 includes a receiving unit 1501 and a processing unit 1502. The receiving unit 1501 is used to receive operation requests sent by the processor, the operation requests including logical addresses. The processing unit 1502 is used to access the first memory or the second memory according to the logical address.

[0279] Specifically, the operation request is a write operation, and the processing unit 1502 is specifically used to write the data to be written to the storage space indicated by the first physical address in the first memory according to the logical address; the first physical address is the physical address in the first memory corresponding to the logical address of the write operation. For example, referring to Figure 10A, the receiving unit 1501 can be used to execute the receiving step corresponding to S101, and the processing unit 1502 can be used to execute S102.

[0280] Optionally, the processing unit 1502 is further configured to flush data in the first memory that meets the first condition to the second memory. The data that meets the first condition includes at least one of the following: data whose amount of data in the first memory is greater than or equal to a first threshold; data whose storage time is greater than or equal to a second threshold; or data whose probability of being read is less than or equal to a third threshold. For example, referring to Figure 11A, the processing unit 1502 can be configured to execute S301 and S302. Flush all data in the first memory when the amount of data in the first memory is greater than or equal to the first threshold.

[0281] Optionally, the processing unit 1502 is further configured to write data in the second memory that meets the second condition into the first memory. The data that meets the second condition includes at least one of the following: data to be read predicted based on already read data; data with a probability of being read and equal to a fourth threshold; or data to be read when the first memory has not been read, determined based on a read operation sent by the processor. For example, referring to FIG14A, the processing unit 1502 can be used to execute S801 and S802.

[0282] Specifically, the operation request is a read operation. Processing unit 1502 is specifically used to read the data to be read from the first memory according to the logical address if the first memory contains the data to be read; and to read the data to be read from the second memory according to the logical address if the first memory does not contain the data to be read. For example, referring to Figure 13A, receiving unit 1501 is also used to execute the receiving step corresponding to S601, and processing unit 1502 is also used to execute S603 to S606.

[0283] Optionally, the persistence performance of the first memory may be lower than that of the second memory. For example, the first memory may be DRAM and the second memory may be SCM; or, the first memory may be DRAM and the second memory may be NAND.

[0284] Optionally, the controller 150 communicates with the processor via a serial bus. For example, the serial bus includes a PCIe bus.

[0285] Optionally, the controller 150 is applied to a memory device, which also includes a first memory and a second memory.

[0286] Optionally, the memory device is specifically a memory module. Alternatively, the memory device includes a motherboard and a memory module, with the controller 150 fixed on the motherboard, and the memory module including a first memory and a second memory.

[0287] For a detailed description of the above-mentioned optional methods, please refer to the foregoing method embodiments, which will not be repeated here. Furthermore, the explanation of any of the controllers 150 provided above and the description of their beneficial effects can be found in the corresponding method embodiments described above, and will not be repeated here.

[0288] As an example, referring to Figure 5, the functions implemented by the receiving unit 1501 can be implemented through the serial bus interface 121 in Figure 5, and the functions implemented by the processing unit 1502 can be implemented through other devices / modules in the controller 12 in Figure 5 other than the serial bus interface 121.

[0289] Figure 16 shows a schematic diagram of another controller provided in an embodiment of this application. The controller 160 shown in Figure 16 communicates with a processor, a first memory, and a second memory; the read / write performance of the first memory is higher than that of the second memory. The controller 160 includes a bus interface 1601, a first processor 1602, and a memory controller 1603. The bus interface 1601 is used to receive operation requests sent by the processor, the operation requests including a logical address. The first processor 1602 is used to send a first instruction to the memory controller according to the logical address. The memory controller 1603 is used to access the first memory or the second memory based on the first instruction. For example, referring to Figure 10B, the bus interface 1601 can be used to execute S201, the first processor 1602 can be used to execute S203, and the memory controller 1603 can be used to execute S205.

[0290] Optionally, the operation request is a write operation; the memory controller 1603 is specifically used to write the data to be written to the storage space indicated by the first physical address of the first memory; the first physical address is the physical address in the first memory that corresponds to the logical address.

[0291] Optionally, the first processor 1603 is further configured to send a second instruction to the memory controller 1603; the memory controller 1603 is further configured to, based on the second instruction, flush data in the first memory that meets the first condition to the second memory. The data that meets the first condition includes at least one of the following: data whose amount in the first memory is greater than or equal to a first threshold; data whose storage time is greater than or equal to a second threshold; data whose probability of being read is less than or equal to a third threshold; or, data to be read when no read hit occurs in the first memory, determined based on the read operation sent by the processor. For example, referring to Figure 11B, the first processor 1603 can be used to execute S402.

[0292] Optionally, the first processor 1602 is further configured to send a third instruction to the memory controller 1603; the memory controller 1603 is further configured to write data in the second memory that meets the second condition into the first memory based on the third instruction. The data that meets the second condition includes at least one of the following: data to be read predicted based on already read data; or data with a probability of being read that is greater than or equal to a fourth threshold.

[0293] Optionally, the operation request is a read operation. Specifically, the memory controller 1603 is used to read the data to be read from the first memory according to the logical address when the first memory stores the data to be read; and to read the data to be read from the second memory according to the logical address when the first memory does not store the data to be read.

[0294] Optionally, the persistence performance of the first memory may be lower than that of the second memory. For example, the first memory may be DRAM and the second memory may be SCM; or, the first memory may be DRAM and the second memory may be NAND.

[0295] Optionally, the controller 160 communicates with the processor via a serial bus. For example, the serial bus includes a PCIe bus.

[0296] Optionally, the controller 160 is applied to a memory device, which also includes a first memory and a second memory.

[0297] Optionally, the controller 160 is fixed to the memory module, for example, the memory device is specifically a memory module.

[0298] Optionally, the controller 160 is fixed to the motherboard. For example, the memory device includes the motherboard and the memory module, which includes a first memory and a second memory.

[0299] Optionally, the memory controller 1603 may include a first memory controller and a second memory controller. The first memory controller is used to control a first memory access, and the second memory controller is used to control a second memory access.

[0300] For a detailed description of the above-mentioned optional methods, please refer to the foregoing method embodiments, which will not be repeated here. Furthermore, the explanation of any of the controllers 160 provided above and the description of their beneficial effects can be found in the corresponding method embodiments described above, and will not be repeated here.

[0301] This application also provides a chip system including at least one controller. Of course, the chip system may also include other discrete devices, and this application does not specifically limit this.

[0302] Another embodiment of this application also provides a computer-readable storage medium storing instructions that, when executed on a controller, cause the controller to perform each step of the method flow shown in the above method embodiment.

[0303] In some embodiments, the disclosed method may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0304] In some embodiments, a computer program product is also provided, the computer program product including a computer program for executing computer processes on a computing device.

[0305] In one embodiment, the computer program product is provided using a signal-bearing medium. The signal-bearing medium may include one or more program instructions that, when executed by one or more processors, can provide some or all of the functions performed by the controller described above, as will not be elaborated further here.

[0306] In some examples, the signal-carrying medium may include computer-readable media, such as, but not limited to, hard disk drives, compact discs (CDs), digital video discs (DVDs), digital magnetic tapes, memory, read-only memory (ROM), or random access memory (RAM), etc.

[0307] In some implementations, the signal-bearing medium may include a computer-recordable medium, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, and so on.

[0308] In some implementations, the signal carrying medium may include a communication medium, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).

[0309] The signal-bearing medium can be a wireless communication medium (e.g., a wireless communication medium conforming to the IEEE 802.11 standard or other transmission protocols). One or more program instructions can be, for example, computer-executable instructions or logical implementation instructions.

[0310] It should be understood that the arrangements described herein are for illustrative purposes only. Therefore, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements may be omitted depending on the desired outcome. Furthermore, many of the described elements are functional entities that can be implemented as discrete or distributed components, or in any suitable combination and location with other components.

[0311] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs).

Claims

1. A data processing method for a memory device, characterized in that, The memory device includes a controller, a first memory, and a second memory; the controller communicates with the processor, the first memory, and the second memory, respectively. The read / write performance of the first memory is higher than that of the second memory; the method includes: Receive the operation request from the processor; the operation request includes a logical address; Access the first memory or the second memory according to the logical address.

2. The method according to claim 1, characterized in that, The operation request is a write operation; the access to the first memory or the second memory according to the logical address specifically includes: According to the logical address, the data to be written is written to the storage space indicated by the first physical address of the first memory; the first physical address is the physical address in the first memory corresponding to the logical address.

3. The method according to claim 1 or 2, characterized in that, The method further includes: The data in the first memory that meets the first condition is flushed to the second memory. The data that satisfies the first condition includes at least one of the following: The data in the first memory when the amount of data is greater than or equal to the first threshold; Data whose storage time is greater than or equal to the second threshold; Alternatively, data whose probability of being read and hit is less than or equal to the third threshold.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: Write the data in the second memory that meets the second condition into the first memory; The data that satisfies the second condition includes at least one of the following: Data to be read is predicted based on already read data; Data whose probability of being read and matched is greater than or equal to the fourth threshold; Alternatively, based on the read operation sent by the processor, determine the data to be read when the first memory has no read hit.

5. The method according to any one of claims 1 to 3, characterized in that, The operation request is a read operation, and the step of accessing the first memory or the second memory according to the logical address specifically includes: When the first memory contains data to be read, the data to be read is read from the first memory according to the logical address; If the data to be read is not stored in the first memory, the data to be read is read from the second memory according to the logical address.

6. The method according to any one of claims 1 to 5, characterized in that, The persistence performance of the first memory is lower than that of the second memory.

7. The method according to claim 6, characterized in that, The first memory is dynamic random access memory (DRAM), and the second memory is storage class memory (SCM). Alternatively, the first memory is DRAM and the second memory is NAND Flash.

8. The method according to any one of claims 1 to 7, characterized in that, The controller communicates with the processor via a serial bus.

9. The method according to claim 8, characterized in that, The serial bus includes the PCIe bus for rapid peripheral component interconnection.

10. The method according to any one of claims 1 to 9, characterized in that, The memory device is specifically a memory module; Alternatively, the memory device may include a motherboard and a memory module, with the controller fixed on the motherboard, and the memory module comprising the first memory and the second memory.

11. A controller, characterized in that, The controller communicates with the processor, the first memory, and the second memory, respectively. The read / write performance of the first memory is higher than that of the second memory; the controller includes: a bus interface, a first processor, and a memory controller; The bus interface is used to receive operation requests sent by the processor, the operation requests including logical addresses; The first processor is configured to send a first instruction to the memory controller according to the logical address; The memory controller is used to access the first memory or the second memory based on the first instruction.

12. The controller according to claim 11, characterized in that, The operation request is a write operation; the memory controller is specifically used to write the data to be written to the storage space indicated by the first physical address of the first memory; the first physical address is the physical address in the first memory that corresponds to the logical address.

13. The controller according to claim 11 or 12, characterized in that, The first processor is further configured to send a second instruction to the memory controller; The memory controller is further configured to, based on the second instruction, flush data in the first memory that meets the first condition to the second memory; The data that satisfies the first condition includes at least one of the following: The data in the first memory when the amount of data is greater than or equal to the first threshold; Data whose storage time is greater than or equal to the second threshold; Data whose probability of being read and matched is less than or equal to the third threshold; Alternatively, based on the read operation sent by the processor, determine the data to be read when the first memory has no read hit.

14. The controller according to any one of claims 11 to 13, characterized in that, The first processor is further configured to send a third instruction to the memory controller; The memory controller is also configured to write data in the second memory that meets the second condition into the first memory based on the third instruction; The data that satisfies the second condition includes at least one of the following: Data to be read is predicted based on already read data; Alternatively, data whose probability of being read and hit is greater than or equal to the fourth threshold.

15. The controller according to claim 11, characterized in that, The operation request is a read operation, and the memory controller is specifically used for: When the first memory contains data to be read, the data to be read is read from the first memory according to the logical address; If the data to be read is not stored in the first memory, the data to be read is read from the second memory according to the logical address.

16. The controller according to any one of claims 11 to 15, characterized in that, The persistence performance of the first memory is lower than that of the second memory.

17. The controller according to claim 16, characterized in that, The first memory is dynamic random access memory (DRAM), and the second memory is storage class memory (SCM). Alternatively, the first memory is DRAM and the second memory is NAND Flash.

18. The controller according to any one of claims 11 to 17, characterized in that, The controller communicates with the processor via a serial bus.

19. The controller according to claim 18, characterized in that, The serial bus includes the PCIe bus for rapid peripheral component interconnection.

20. The controller according to any one of claims 11 to 19, characterized in that, The controller is applied to a memory device, the memory device further comprising the first memory and the second memory; The memory device is specifically a memory module; Alternatively, the memory device may include a motherboard and a memory module, with the controller fixed on the motherboard, and the memory module comprising the first memory and the second memory.

21. A controller, characterized in that, The controller communicates with the processor, the first memory, and the second memory, respectively. The read / write performance of the first memory is higher than that of the second memory; the controller includes: A receiving unit is configured to receive an operation request from the processor; the operation request includes a logical address. A processing unit is configured to access the first memory or the second memory based on the logical address.

22. The controller according to claim 21, characterized in that, The operation request is a write operation; The processing unit is specifically used to: write the data to be written to the storage space indicated by the first physical address of the first memory according to the logical address; the first physical address is the physical address in the first memory corresponding to the logical address.

23. The controller according to claim 21 or 22, characterized in that, The processing unit is also used for: The data in the first memory that meets the first condition is flushed to the second memory. The data that satisfies the first condition includes at least one of the following: The data in the first memory when the amount of data is greater than or equal to the first threshold; Data whose storage time is greater than or equal to the second threshold; Alternatively, data whose probability of being read and hit is less than or equal to the third threshold.

24. The controller according to any one of claims 21-23, characterized in that, The processing unit is also used for: Write the data in the second memory that meets the second condition into the first memory; The data that satisfies the second condition includes at least one of the following: Data to be read is predicted based on already read data; Data whose probability of being read and matched is greater than or equal to the fourth threshold; Alternatively, based on the read operation sent by the processor, determine the data to be read when the first memory has no read hit.

25. The controller according to claim 21 or 22, characterized in that, The operation request is a read operation; The processing unit is specifically used for: When the first memory contains data to be read, the data to be read is read from the first memory according to the logical address; If the data to be read is not stored in the first memory, the data to be read is read from the second memory according to the logical address.

26. The controller according to any one of claims 21 to 25, characterized in that, The persistence performance of the first memory is lower than that of the second memory.

27. The controller according to claim 26, characterized in that, The first memory is dynamic random access memory (DRAM), and the second memory is storage class memory (SCM). Alternatively, the first memory is DRAM and the second memory is NAND Flash.

28. The controller according to any one of claims 21 to 27, characterized in that, The controller communicates with the processor via a serial bus.

29. The controller according to claim 28, characterized in that, The serial bus includes the PCIe bus for rapid peripheral component interconnection.

30. The controller according to any one of claims 21 to 29, characterized in that, The controller is applied to a memory device, the memory device further comprising the first memory and the second memory; The memory device is specifically a memory module; Alternatively, the memory device may include a motherboard and a memory module, with the controller fixed on the motherboard, and the memory module comprising the first memory and the second memory.

31. A computer system, characterized in that, include: Processor, controller, first memory, and second memory; The controller communicates with the processor, the first memory, and the second memory respectively; The read / write performance of the first memory is higher than that of the second memory; The controller is used to perform the method as described in any one of claims 1 to 10.

32. A chip system, characterized in that, The chip system includes the controller as described in any one of claims 11 to 30.