AMPLIFIER DEVICE WITH FEEDBACK AND FEED-FORWARD CONTROL

Abstract

AMPLIFIER DEVICE WITH FEEDBACK AND FEED-FORWARD CONTROL An amplifier device comprises a signal input for receiving a reference signal and. amplifier circuitry. The amplifier device further comprises a feedforward signal path providing a feed-fonNard signal. First signal combining circuitry is configured to generate an error signal representative of a difference between the reference signal and a signal proportional to a signal at an output of the amplifier circuitry. Signal processing circuitry is configured to process the error signal to obtain a first signal. Second signal combining circuitry is configured to combine the first signal and the feedfonNard signal to obtain a combine signal which is applied to an input of the amplifier circuitry. The signal processing circuitry comprises a limiter configured to limit an amplitude of a second signal to a predetermined value thereby obtaining a limited second signal. The signal processing circuitry is configured to obtain the first signal based on the limited second signal.

Description

Technical field

[0001] The present disclosure is related to amplifier systems, particularly to power amplifier systems such as radio frequency (RF) power amplifier systems utilizing feedback control and feed-forward control. Background art

[0002] Power amplifiers, such as RF amplifiers, are used in a wide variety of applications including, but not limited to, magnetic resonance imaging (MRI) and semiconductor plasma processing. In these applications, power amplifiers need to have very linear and stable performance in terms of both power and phase. Such specifications cannot be achieved by the power amplifier itself, since a higher efficiency comes at a cost of deteriorated linearity. ln MRI applications, generally used Class-AB, B orC amplifiers have reasonable efficiency, but gain compression, memory effects and thermal drift distort the output signal resulting in a deteriorated image quality.

[0003] It is known to improve the performance of an amplifier in terms of linearity and stability by implementing a feedback control loop. Different types of control loop methods can be used, such as Cartesian feedback and polar feedback. The Cartesian feedback control has a number ofadvantages overotherfeedback control loop methods mainly because bandwidth requirements can be reduced compared to other feedback methods.

[0004] One disadvantage of feedback control is that the open-loop gain depends on the gain ofthe power amplifier. Since an amplifier in higher efficiency modes such as class-AB, B, or C has a significant non-linear behaviour, there is a significant variation in gain when power is varied. As a result, the control loop must be designed that it is stable over the entire range of power and gain. To obtain this effect, the control loop is designed to have lower open-loop gain at low power. Another disadvantage is thatwhen a step variation ofpower is applied, the open-loop signal path needs to process the full signal level amplitude.

[0005] To compensate for these effects, it is known to add feed-fonNard control and (feed-forward) distortion compensation, also referred to as predistortion. ln predistortion, the non-linear behaviour of the amplifier is modelled and a compensation signal is generated. The input to the amplifier is adapted based on the compensation signal to compensate for the non-linear distortion. Hyun H. Boo et al., in DigitallyAssisted FeedfonNard Compensation of Cartesian-Feedback Power-Amplifier Systems, IEEE Transactions on Circuits and Systems ll. Express Briefs, Vol. 58, No. 8, August 2011, disclose that the bandwidth and the in-band linearity of Cartesian-feedback RF power amplifier systems can be enhanced by digitally assisted feed-fonNard compensation. A feed-fonNard quadrature predistorted signal is applied in the intermediate frequency path upstream of the quadrature up-converter. The predistorted signal is obtained through a look-up table (LUT), appropriately trained using the control loop.

[0006] US 2010 / 0327932 discloses an amplifier system with Cartesian feedback and feed-fonNard compensation. The system includes a phase / gain compensator which multiplies a received signal with a complex value to perform phase shift correction and possibly compensating for the gain as well. The phase / gain compensator can be arranged in the main signal path, between reference input and the amplifier, in the feedback path or in the feed-fonNard path. The complex value can be adaptively determined by a model.

[0007] Feed-fonNard predistortion can counteract the non-linear gain characteristics of the power amplifier, hence resolving the issue of fluctuating open-loop gain and obtaining a consistent total gain and constant loop response. However, there is still a need in the art to further improve transient behaviour of the above systems, particularly for large step responses. Summary

[0008] It is an object of the present disclosure to provide systems and methods allowing to improve transientbehaviourofa power amplifier system, particularly when a large step variation or power pulse is applied. It is an object to improve transient behaviourwhen power is changed suddenly both from low powerto high power and from high powerto low power. It is an object to provide such systems and methods which are easy to implement, have a small footprint and / or provide improved performance.

[0009] According to a first aspect of the present disclosure, there is therefore provided an amplifier device, as set out in the appended claims. An amplifier device according to the present disclosure comprises a signal input for receiving a reference signal, a signal output and amplifier circuitry. The amplifier circuitry comprises an amplifier input and an amplifier output, which is coupled to the signal output, e.g. the amplifier output can be the signal output.A main signal path can be defined between the signal input and the signal output and the amplifier circuitry is arranged in the main signal path. The amplifier device further comprises a feed-fonNard signal path configured to provide a feed-fonNard signal, e.g. representative of the reference signal. First signal combining circuitry is configured to generate an error signal representative ofa difference between the reference signal and a signal proportional to a signal at the amplifier output. The first signal combining circuitry hence can have a first input coupled to the signal input, a second input coupled to the amplifier output and a first output. The error signal is advantageously provided at the first output and hence applied to the main signal path. The main signal path is hence part of a feedback control loop path, advantageously a Cartesian feedback control loop path. Signal processing circuitry, e.g. arranged in the main signal path, is configured to process the error signal to obtain a first signal. Second signal combining circuitry is configured to combine, e.g. to add, the first signal and the feed-fonNard signal to obtain a combine signal which is applied to the amplifier input. The second signal combining circuitry hence can have a third input coupled to the first output, a fourth input coupled to the feed-fonNard signal path and a second output coupled to the amplifier input. The second signal combining circuitry is advantageously configured to provide the combine signal at the second output. The signal processing circuitry can comprise a loop filter configured to process a signal representative of the error signal to obtain the first signal.

[0010] According to an aspect of the present disclosure, the signal processing circuitry comprises a limiter, i.e., arranged in the main signal path between the first combining circuitry and the second combining circuitry. The limiter advantageously has an input coupled to the first output (output of the first combining circuitry) and an output coupled to the third input (input of the second combining circuitry). The limiter is configured to limit an amplitude of a second signal of the main signal path (as applied to the input of the limiter) to a predetermined value. Particularly the limiter is configured to limit the second signal such that it does not exceed the predetermined value at the output of the limiter. The second signal can be the error signal or any other processed signal obtained based on the error signal and hence which is representative of the error signal. Advantageously, the signal processing circuitry is configured to obtain the first signal based on the second signal limited by the limiter. The signal processing circuitry can e.g. be configured to apply filtering to the limited second signal to obtain the first signal, or any other appropriate signal processing operations.

[0011] The limiter hence is configured to provide for error limitation or error compression. This advantageously makes a significant improvement to step responses of the amplifier output because a large perturbation of the error signal can be prevented. By limiting (clipping or compressing) the error, the transient behaviour and / or settling time can be significantly improved, particularly for large and sudden variations of the input signal. In addition, the limiter allows for reducing voltage stress on the circuit components, increasing service life and reliability.

[0012] Such a limiter is particularly suitable in combination with a Cartesian feedback control loop path in which the signal processing circuitry is implemented with parallel in-phase and quadrature signal paths, i.e., signals having a quadrature phase relationship. Separate limiters are advantageously provided for the in-phase and quadrature signal paths and each can operate independently to provide for proper error compression of the respective signal paths without injecting any significant phase shift.

[0013] The feed-fonNard signal path is configured to add a feed-fonNard signal, advantageously representative of the reference signal, to the signal input to the amplifier circuitry, e.g. to a processed (limited) error signal. Advantageously, the feed- fonNard signal path adds the reference signal without adaptation, particularly downstream of the limiter. This reduces the amplitude of the error signal that needs to be processed by any signal control circuitry (e.g., loop filter) resulting in improved output performance and reduced transient behaviour.

[0014] The amplifier device advantageously comprises signal predistortion circuitry coupled to the amplifier input and configured to compensate at least in part a non-linearity of a gain of the amplifier circuitry. The predistortion circuitry allows for linearizing the amplifier output and therefore allows to obtain a coherent response at all power levels.

[0015] According to a second aspect, there is provided an apparatus including the amplifier device, as set out in the appended claims. The apparatus can comprise one or more antennas, such as one or more magnetic coils that are driven by the amplifier device of the present disclosure.

[0016] According to a third aspect, there is provided a method ofamplifying an electrical signal, as set out in the appended claims. The method is advantageously implemented in the amplifier device of the first aspect. Brief description of the drawings

[0017] Aspects of the present disclosure will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features and wherein:

[0018] Figure 1 represents a diagram of an amplifier device according to aspects of the present disclosure;

[0019] Figure 2 represents a diagram of a clipping circuit that can be implemented as limiter in the amplifier device of Fig. 1;

[0020] Figure 3 represents a diagram of an alternative clipping circuit;

[0021] Figure 4 represents a diagram of the amplifier device of Fig. 1 in which a predistorter is added;

[0022] Figure 5 represents a diagram of an alternative amplifier device with polyphase filter according to aspects of the present disclosure;

[0023] Figure 6 represents a diagram of yet an alternative amplifier device according to aspects of the present disclosure;

[0024] Figure 7 represents a diagram of an apparatus including antennas coupled to driving circuits which comprise amplifier devices as described herein;

[0025] Figure 8 represents a plot of simulations of the in-phase components of the reference signal, the clipped error signal and the output signal of the loop filter for the amplifier device of Fig. 1;

[0026] Figure 9 represents a plot of simulations of a rising edge step response for the amplifier device of Fig. 1 with and without limiter implemented;

[0027] Figure 10 represents a plot of simulations of a falling edge step response for the amplifier device of Fig. 1 with and without limiter implemented. Detailed description

[0028] Referring to Fig. 1, an amplifier device or system 10 is configured to increase the energy level of an electrical signal provided at an input 11 of the amplifier system 10 by a factor to obtain an amplified signal and to apply the amplified signal at an output 17. The amplified signal of output 17 is typically utilized to drive a load 9, particularly an antenna, such as a magnetic coil, e.g., of an MRI apparatus, a plasma system or a wireless communications system. The electrical signal can be provided at the input 11 as an analog signal, which can be in a radio frequency (RF) band, an intermediate frequency (lF) band, or which can be a baseband signal. Alternatively, the electrical signal can be provided at input 11 as a digital signal and the amplifier system 10 can comprise a digital to analog converter coupled to input 11 for converting the input signal to the analog domain. The amplified signal at the output 17 is in the analog domain and is typically at radio frequency.

[0029] The amplifier system 10 comprises a main signal path 100 from the input 11 to the output 17. A power amplifier (PA) 16, which is basically configured to increase the energy level of (Le, to amplify) the electrical signal, is arranged in the main signal path. The power amplifier 16 comprises an amplifier input 161 configured to receive an analog signal and an amplifier output 162 coupled to the output 17.

[0030] The amplifier system 10 further comprises a feedback control loop, particularly a Cartesian feedback control loop, in which the baseband signal information is processed in Cartesian form, including an in-phase signal path I and a quadrature signal path Q which are arranged in parallel along the main signal path 100. The Cartesian feedback control loop can comprise a signal splitterconfigured to splitthe input signal applied at input 11 in quadrature components (i.e., having a quadrature phase relationship) that are processed in individual signal paths | and Q. If the input signal is provided at input 11 at radio frequency, the Cartesian feedback control loop can comprise a frequency down-converter configured to down-convert the (RF) signal frequency to baseband or to an intermediate frequency. Advantageously, a quadrature down- converter 12 combines signal splitting and frequency down-converting operations. If the input signal is provided at input 11 in quadrature components and at baseband or intermediate frequency, e.g., the input signal is a digital signal, the quadrature down- converter 12 can be dispensed with and possibly be replaced with digital to analog converters.

[0031] The amplifier system 10 further comprises a quadrature up- converter 15 arranged in the main signal path. Quadrature up-converter 15 has inputs coupled to the l and Q signal paths respectively and has an output coupled to the amplifier input 161. The quadrature up-converter 15 is configured to convert the in-phase and quadrature signals of intermediate or baseband frequency to a combined signal of radio frequency which is input to the power amplifier 16.

[0032] Each of the signal paths | and Q comprise individual signal control circuitry 13, 14 respectively, configured to generate and process respective error signals, advantageously in an intermediate frequency band or at baseband. The signal control circuitry 13, 14 are arranged in the open-loop signal path, between the input 11 (quadrature down-converter 12) and the quadrature up-converter 15. The outputs of the signal control circuitry 13, 14 are coupled to the respective inputs of the quadrature up- converter 15.

[0033] Each of the signal control circuitry 13, 14 comprises a first summing circuitry 131, 141 respectively, and signal processing circuitry comprising a limiter 132, 142 respectively and advantageously a loop filter 133, 143 respectively. The signal control circuitry 13, 14 further comprises a feed-fonNard path 135, 145 respectively, coupled to a second summing circuitry 134, 144 respectively. First summing circuitry 131, 141 is configured to generate an error signal IERR, QERR, respectively, from a difference of a reference signal IREF, QREF received at respective reference inputs 136, 146 coupled to input 11, e.g. as output from quadrature down-converter 12, and a feedback signal IFB, QFB received at respective feedback inputs 137, 147. First summing circuitry 131, 141 is hence configured to operate as a subtractor.

[0034] Feedback input 137, 147 is coupled to a feedback loop 18 for receiving respective quadrature feedback signals IFB, QFB that are proportional to a signal at output 17. A (directional) coupler 181 is configured to sample the output of the power amplifier 16 and to attenuate it to a suitable level for applying it to a quadrature down- converter 182 which generates IFB and QFB . A phase shifter 183 is supplied with local oscillator signals L0 and configured to generate phase-shifted signals between the quadrature up-converter 15 and the quadrature down-converter 182 to ensure that the up-conversion and down-conversion processes are coherent. The outputs of the quadrature down-converter 182 are coupled to the first summing circuitry 131, 141 of the respective l and Q signal paths at the respective feedback inputs 137, 147. One advantage of the orthogonal nature of the Cartesian feedback system is that the l and Q signal paths can operate completely independently.

[0035] Each of the signal control circuitry 13, 14 can comprise a loop filter 133, 143 respectively. Any suitable loop filter can be implemented. The loop filter advantageously has unity gain. In some examples, the loop filter comprises a low pass filter. The loop filter can be implemented with a proportional-integral (Pl) control model, a proportional-integral-derivative (PlD) control model, or an integral control model.

[0036] To improve the transient behaviour of large step responses, each of the signal control circuitry 13, 14 comprises a limiter 132, 142 respectively. The limiter 132, 142 has an input coupled to respective summing circuitry 131, 141 and an output coupled to respective loop filter 133, 143. The limiter is configured to limit an (absolute value of the) amplitude of the error signal IERR, QERR of the respective l andQ signal paths such that it does not exceed a predetermined value. More generally, the limiter is configured to reduce the amplitude of an output signal (e.g., as output from the limiter) as a function of the amplitude of an input signal (e.g., as input to the limiter). In some examples, the amplitude of the output signal is reduced only when the amplitude of the input signal exceeds a first predetermined value. The amplitude of the output signal can be reduced such that it does not exceed the first predetermined value, or such that the amplitude of the output signal does not exceed a second predetermined valuewhich may be different from, or equal to, the first predetermined value (e.g. larger for positive amplitudes and smaller for negative amplitudes). Hence the limiter can be configured to attenuate the amplitude of the output signal when the amplitude of the input signal exceeds the first predetermined value. When the amplitude of the input signal does not exceed the first predetermined value, the limiter can be configured to pass the input signal to the output signal without attenuation. In some examples, the limiter can be configured to clip the amplitude of the signal input to it at the first predetermined value, i.e., the limiter can be a clipper circuit. In other examples, the limiter can be configured to compress, e.g., to squash, the amplitude ofthe signal input to it and thereby preventing the signal output by the limiter from exceeding the first or second predetermined value. The latter operations are also known as soft limiting or soft clipping.

[0037] The signal limiting (clipping or compression) provided by the limiter advantageously makes a significant improvement to the transient behaviour of step responses ofthe amplifier device 10. In addition, a large perturbation of the signal control circuitry 13, 14 of the main signal path 100, and of the loop filter 133, 143 in particular, can be prevented. By limiting the signal in the main signal path, particularly the error signal IERR QERR, the transient behaviour and / or settling time can be significantly improved. It has been found that this is particular true for large steps in input power. When applying a power step input and considering the feedback signal (IFB, QFB) to be initially zero, the step in the reference signal (IREF, QREF) will cause the error output from the summing circuitry 131, 141 initially to be equal to the reference signal and therefore very high. This can cause undesired transient behaviour in the amplifier output. The limiter 132, 142 is configured to reduce the amplitude of the error signal in the l and Q signal control paths only for larger input signals, which exceed a predetermined (power) level, whereas for smaller input signals the error signal amplitude is not changed, e.g., passes without attenuation. In addition, the load on the circuit components is reduced, increasing service life and reliability.

[0038] In a particular example, the limiter is configured to limit the amplitude of the signal input to it to a threshold level of between 1% and 70%, advantageously between 3% and 50%, advantageously between 5% and 30% of the amplitude of the reference signal at rated peak power of the amplifier device 10 (e.g., the amplitude of the reference signal as applied at the respective reference inputs 136, 146).

[0039] The signal control circuitry 13 and 14 can each have an independent limiter 132, 142, Le, operating independently with respect to each other. These limiters 132 and 142 can be identical to each other, e.g. limiting or reducing the error signal amplitude by same amounts, or they can operate on a different basis. Such operation may induce a small phase shift between the l andQ signals which can be easily absorbed by the other circuit components.

[0040] Advantageously, the limiters 132, 142 operate on either one or both positive and negative signal amplitudes, such as to clip either one or both positive and negative signal peaks. The limiters are hence configured to limit the signal amplitude when the amplifier device operates to increase power and / orwhen the amplifier device operates to reduce power. It will be appreciated that the limiter generally does not rotate the signal, i.e. no phase shift is applied.

[0041] Referring to Fig. 2, one exemplary clipping circuit 20 that can be implemented as combined first summing circuitry 131 and limiter 132, comprises an operational amplifier 21 and a resistor 22 in a feedback path of the operational amplifier 21. A pair of diodes D1, D2 are arranged in antiparallel across the resistor 22. The reference input 136 and thefeedback input 137 of the first summing circuitry are coupled to the inverting input of the operational amplifier 21 through respective resistors 23, 24 with advantageously equal resistance value R. The non-inverting input ofthe operational amplifier 21 can be connected to ground. A phase shifter 25 applies a 180° phase shift to the feedback signal IFB at feedback input 137. The clipping circuit 20 will clip the amplitude of the output signal IERR if the voltage across the feedback resistor 22 increases above the threshold voltage of the diode D1 or D2, and both positive and negative peaks can be clipped to obtain a limited error signal IERR,L|M. By properly choosing the resistor values R of resistors 22 and 23, 24, a clipping voltage can be defined in the in-phase (l) signal path. A same clipping circuit 20 can be provided as combined first summing circuitry 141 and limiter 142 for the quadrature (Q) signal path.

[0042] Referring to Fig. 3, another exemplary clipping circuit 30 is arranged as a combinational two-level diode clipper comprising a positively biased clipping diode D3 and a negatively biased clipping diode D4 in combination. Both positive and negative peaks can hence be clipped. lnstead of a clipping circuit, a compressor circuit can be used as limiter, which is configured to compress or attenuate the signal when it exceeds a predetermined value (e.g., soft clipping), whereas the signal passes unattenuated when it does not exceed the predetermined value.

[0043] lt will be appreciated that the output of the clipping circuits 20, 30, Le. the (clipped) error signal IERR, is applied as input to the corresponding loop filter 133 (or the loop filter 143 for the quadrature error signal).

[0044] Referring again to Fig. 1, advantageously, a feed-fonNard path 135, 145 is respectively provided in the l and Q signal paths. Feed-fonNard path 135 takes the reference signal IREF at the reference input 136 of the l signal path and adds it to the respective control signal ICRL, e.g. the output of the loop filter 133, in second summing circuitry 134. Feed-fonNard path 145 takes the reference signal QREF at the reference input 146 of the Q signal path and adds it to the control signal QCRL, e.g. the output of the loop filter 143, in second summing circuitry 144. Feed-fonNard paths 135, 145 advantageously have unity gain. Either one or both can, but need not, comprise a signal attenuator, a signal amplifier or signal filtering circuitry. These feed-fonNard paths are advantageously added to reduce the signal amplitude which needs to be processed by the first summing circuitry 131, 141 and loop filter 133, 143. The reference signal is therefore advantageously added to the output of the loop filter without attenuation or filtering.

[0045] Referring to Fig. 4, the amplifier device 10 can further comprise a predistortion path 19 configured to compensate at least in part the non-linear gain characteristics inherent to the power amplifier (PA) 16. Predistortion path 19 comprises predistortion circuitry 191 configured to generate a predistortion signal based on an input or reference signal applied at the input 11 for at least partially compensating a non- linearity of the power amplifier 16. To this end, the predistortion path can comprise an input 192 coupled to the input 11 of the amplifier device 10. The predistortion path 19 further comprises at its output circuitry, such as a variable gain amplifier 193, configured adapt the signal at the amplifier input 161 based on the predistortion signal. The predistortion signal determines the (tuneable) gain applied by the variable gain amplifier 193 to the signal input to the power amplifier 16, and hence forms a predistortion factor which is configured to compensate at least in part non-linearities of the power amplifier 16. The variable gain amplifier 193 can be replaced by other circuitry configured to adapt a signal based on the predistortion signal, such as a multiplier circuitry or a summing circuitry.

[0046] The predistortion circuitry 191 can comprise, or consist of, analog predistortion circuitry, digital predistortion circuitry, or a combination of both. An analog predistortion circuitry can comprise a signal detector, such as a log detector, a linear detector ora mixer, to detect an amplitude of the (analog) signal at input 192 and convert it to a representative voltage. The signal detector is coupled to a scaling circuit which applies a (variable) scaling factor representative of the predistortion to be applied, to obtain the predistortion signal which is applied as a tuneable gain to the variable gain amplifier 193. Optional filtering circuit can be provided to improve transient behaviour.

[0047] A digital predistortion circuitry can comprise an analog-to-digital converter (ADC) coupled to the input 192 if an analog signal is applied at the input 11. Digital predistortion circuitry is implemented with distortion compensation logic and is configured to generate a digital predistortion signal that is fed to a digital-to-analog converter for converting the digital predistortion signal to the analog domain for applying it as a tuneable gain to the variable gain amplifier 193. The distortion compensation logic can comprise a look-up table (LUT) or alternatively be implemented with polynomial coefficients for distortion compensation, such as in a micro-processing unit, e.g. an application specific integrated circuit (ASlC) or a field-programmable gate array (FPGA).

[0048] The predistortion circuitry 191 advantageously ensures that the total gain from both the variable gain amplifier 193 and the power amplifier 16 remains consistent, regardless of varying power outputs. As a result, it advantageously stabilizes fluctuations in the open-loop gain. This stability in total gain allows for a constant loop response, which can then be adjusted to maintain a consistent output quality across all power levels. Additionally, since it compensates non-linear gain effects of the power amplifier, the predistortion circuitry allows to keep the error signal amplitude in the feedback path relatively small, which advantageously relaxes specifications for the limiter 132, 142 and / or the feed-fonNard path 135, 145.

[0049] It will be appreciated that the input 192 to the predistortion path 19 can be coupled to the l and Q signal paths, i.e. downstream of the quadrature down- converter 12. The predistortion signal may then be applied upstream of the quadrature up-converter 15, resulting in separate predistortion paths for the | and Q signal paths, or alternatively downstream.

[0050] lt will further be appreciated that the l and Q signal paths, i.e. from respective reference inputs 136, 146 to the quadrature up-converter 15 are advantageously entirely in the analog domain. The limiter 132, 142 is therefore advantageously provided as analog signal processing circuitry.

[0051] Referring to Fig. 5, in some examples of the amplifier device 10, the loop filters 133, 143 ofthe signal control circuitry 13, 14 can be replaced with a polyphase filter 53 to obtain cross-coupling between the | and Q signal paths. Polyphase filter 53 receives as inputs, the in-phase and quadrature reference (input) signals, IREF and QREF respectively, and the in-phaseand quadrature feedback signals, IFB and QFB respectively. Polyphase filter 53 is configured to generate in-phase and quadrature error signals IERR and QERR respectively, which are applied to limiters 132, 142 respectively to obtain appropriately clipped error signals. It will be appreciated that polyphase filter 53 can hence combine summing circuitry 131, 141 and loop filter 133, 143. Such a polyphase filter can comprise, or consist of, one or more active polyphase filters as described in US 4723318, which can provide cross-coupling. The polyphase filter can comprise, or consist of a complex band pass error amplifier as described in US 8125270.

[0052] Referring to Fig. 6, the separate limiters of the | and Q signal paths can be replaced by a single limiter 62 arranged downstream of the quadrature up- converter 15. In this case, limiter 62 has an output coupled to a summing circuitry 234. Summing circuitry 234 has a first input coupled to a feed-fonNard path 235, feeding the reference signal from input 11, and a second input coupled to the limiter 62, taking the limited output of the quadrature up-converter 15. The output of summing circuitry 234 is coupled to the amplifier input 161. Limiter62 is configured to clip or reduce the combined control signal as output from the quadrature up-converter 15, prior to applying the signal to the power amplifier 16. Just like limiters 132, 142, limiter 62 can greatly improve the system performance when applying step responses in output power and reduce stress on the circuitry components of the open-loop signal paths (signal control circuitry 13 and 14). Signal limiter62 acts in the radio frequency band, ratherthan intermediate frequency or baseband like limiters 132, 142.

[0053] Referring to Fig. 7, an apparatus 70 can comprise one or multiple antennas, such as electromagnetic coils 71, 72, 73, coupled to a driving circuit 74. The driving circuit can comprise a control unit 75 coupled to amplifier devices 10, 10, 10, such as any of the amplifier devices described herein, which are coupled to a respective one of the coils 71-73. The control unit 75 is configured to generate analog or digital driving signals for operating the coils 71-73. These driving signals are fed to the respective amplifier device 10, 10, 10 which generates amplified driving signals for the respective coil. The control unit 75 can be positioned remote from the amplifier device 10, 10, 10 and can be configured to provide analog driving signals as input to the amplifier device 10, 10, 10. The apparatus 70 can be an MRI system in which the coils 71-73 are imaging coils, or a plasma processing system, in which the antennas are coupled to a plasma chamber for generating a plasma within the chamber.

[0054] It will be appreciated that while the foregoing examples describe amplifier devices implemented with Cartesian feedback control loops, aspects of the present disclosure can be equally applied to amplifier devices with other types of feedback control, such as polar feedback. Simulation results

[0055] A simulation was performed on the circuit of Fig. 1. The loop filter had a gain of two. The limiters 132, 142 were implemented as a clipping circuit as in Fig. 2, and the resistors R were selected to obtain positive and negative voltage clipping at about 0.25V. A sine wave of 1VpK was applied as reference signal IREF to the reference input of the l channel. A same wave was input as reference signal to the Q channel, but this is not shown as the resultwas equal to the l channel result. The feedback signal IFB was grounded. As a result, the error signal is equal to the reference signal. The relevant voltage waveforms are shown in Fig. 8. As can be seen, the output IERR,L|M of the limiter 132 is clipped at a voltage of approximately 0.25VpK. When fed to the loop filter 133, the higher harmonics of the clipped signal are filtered out, resulting again in a nice smooth sine wave IFILT. Since the gain of the used loop filterwas two, the amplitude of the filtered signal is larger, but would be lower if the loop filter had a unity gain configuration.

[0056] Referring to Fig. 9, a rising edge step 91 from 0 kW to 20 kWwas applied as input (reference). The response was simulated for the amplifier device of Fig. 1 with and without limiter. The loop filter had a gain of two. The response (amplifier output) 92, 93 without and with limiter (error clipping according to Fig. 8) respectively, is shown in Fig. 9. It can be seen that the response 93 with error signal clipping has a reduced overshoot. This hence reduces voltage stress on the system components.

[0057] Referring to Fig. 10, a falling edge step 95 from 20 kW to 0 kWwas applied as input (reference). The response was simulated for the amplifier device of Fig. 1 with and without limiter. Fig. 10 shows the response (amplifier output) 96, 97 without and with limiter (error clipping according to Fig. 8) respectively. It can be seen that the response 96 without error signal clipping (without limiter) gives rise to a significant ringing with peak up to 30 kW which takes more than 1 us. This is thought to be caused by the non-linear behaviour of the power amplifier. The response 97 with signal clipping has a single ringing lobe with peak reduced to 3kW compared to 30 kW if no limiter is used. The response settling time is 0.4 us, significantly shorter as well.

Claims

1. An amplifier device (10), comprising: a signal input (11), an amplifier circuit (16) comprising an amplifier input (161) and an amplifier output (162); a feed-forward signal path (135, 145, 235), a first signal combining circuit (131, 141) configured to a fault signal (IERR, QERR) representative of the difference between an on the signal input (11) receive reference signal (IREF, QREF) and a signal (IFB, QFB) proportional to a signal at the amplifier output (162) to generate; a signal recognition circuit (133, 143) configured to to process the error signal to obtain an initial signal (ICRL, QCRL), a second signal combining circuit (134, 144, 234) configured to the first signal (ICRL, QCRL) and a signal of the to combine feed-fonNard signal path to a the amplifier input (161) coupled output of the second signal combining circuit available; characterized by the fact that the signal protection circuit has a limiter (132, 142, 62) configured to an amplitude of a second signal to a to limit a predetermined value, includes, whereby a limited second signal (IERRM) is obtained, and because the signal recognition circuit is configured to obtain the first signal based on the limited second signal.

2. Amplifier device within the meaning of claim 1, where the limiter is (132, 142, 62) configured to have both a positive and a negative amplitude of the to limit the second signal.

3. Amplifier device within the meaning of claim 1 or 2, where the predetermined value between 1% and 70% of a peak amplitude of the reference signal at maximum nominal power lies, preferably, between 5% and 50% of the peak amplitude.

4. Amplifier device pursuant to any of the preceding claims, where the second signal is the error signal (IERR, QERR).

5. Amplifier device pursuant to any of the preceding claims, where the signal recognition circuit is further a loop filter (133, 143, 53) includes configured for the error signal (IERR, QERR) Recognize representative signal to obtain the first signal.

6. Amplifier device in accordance with the preceding claim, where an output of the limiter (132, 142) is connected to an input of the loop filter (133, 143).

7. Amplifier device pursuant to any of the preceding claims, where the limiter (132, 142, 62) includes a clipping circuit (20, 30).

8. Amplifier device pursuant to any of the preceding claims, comprising a Cartesian feedback loop path, where the signal protection circuit parallel first and second signal paths (|, Q) configured to recognize signals with a quadrature phase relationship includes 9. Amplifier device in accordance with the preceding claim, where each of the first and second signal paths the limiter (132, 142) includes.

10. Amplifying device within the meaning of claim 8 or 9, where each of the first and separate second signal paths (|, Q) from the first and second signal combining circuit and of the feed-forward signal path (135, 145) includes 11. Amplifier device pursuant to any of the preceding claims, where the feed-forward signal path (135, 145, 235) has an input linked to an input (136, 146) of the first signal combining circuit (131, 141).

12. Amplifier device pursuant to any of the preceding claims, further comprising a signal pre-distortion circuit (191) coupled to the amplifier input (161) and configured to at least partially a non-linearity of a gain of the amplifier circuit to compensate 13. Amplifier device pursuant to any of the preceding claims, configured to output an analog radio frequency signal to the amplifier output (162).

14. Amplifier device pursuant to any of the preceding claims, configured to receive an analog signal at the signal input (11).

15. Amplifier device pursuant to any of the preceding claims, where the signal recognition circuit (133, 143) consists of an analog schakeHng.

16. Device (70), comprising an antenna (71, 72, 73), in particular a electromagnetic coil, and one coupled to the antenna drive circuit (74) configured to use the antenna to magnetic to generate field, whereby the drive circuit the amplifier (10) of any which of the foregoing conclusions comprises.

17. Device in accordance with the preceding claim, where the antenna a magnetic resonant imaging coil is.

18. Method for amplifying an electrical signal, the method comprising: generating, for a reference signal to be amplified (IREF, QREF), of an error signal (IERR, QERR) representative of a difference between the reference signal and a signal (IFB,QFB) proportional to an output signal emitted by an amplifier (16), processing the error signal to a first signal obtain (ICRL, QCRL), combining the first signal with a feed-fonNard- signal representative of the reference signal to a combine signal obtaining and applying the combine signal to the amplifier to the to obtain an output signal; characterized by the fact that the processing of the error signal the limiting the amplitude of a second signal to a predetermined value to obtain a restricted signal (IERR), includes, where the first The signal is obtained based on the limited signal.

19. Method in accordance with the preceding conclusion, whereby the predetermined value between 1% and 70% of a peak amplitude of the reference signal at The maximum nominal power of the amplifier is, preferably, between 5% and 50% of the peak amplitude.

20. Method according to conclusion 18 or 19, involving the generation of the error signal generating quadrature components of the error signal (IREF, QREF) with includes a quadrature phase relation, preferably where the constraint of the amplitude of the second signal limiting an amplitude of each of includes the quadrature components of the second signal.

21. Method of working in accordance with any of Claims 18 to 20, whereby the second signal is the error signal (IERR, QERR), preferably further comprising the processing of the limited signal through a loop filter to the to obtain first signal.

22. Method of working pursuant to any of Claims 18 to 21, whereby the output signal is radio frequency. 1 / 7

Images