Gate trench semiconductor device with deep shielding regions and tuneable contact density

Abstract

A gate trench semiconductor device and a method of manufacturing such semiconductor device, the semiconductor device comprising gate trenches of different widths, wherein first gate trenches have a width narrower than a width of second gate trenches, wherein a first shielding region is located vertically below and at least partly laterally around a center of each of the first gate trenches, and wherein a second shielding region is located vertically below of each of the second gate trenches but not at least partly around a center of each of the second gate trenches.

Description

Technical field The present disclosure relates to gate trench semiconductor devices, a method of manufacturing gate trench devices, semiconductor packages comprising a gate trench devices and semiconductor chips comprising a gate trench device. Background Transistors with a gate oxide, such as the metal-oxide-semiconductor field-effect transistor (MOSFET) can face the issue of elevated electric fields at the oxide. This is especially true for power MOSFETs operated at high voltages, e.g., those made from silicon carbide. Under normal operating conditions a high potential difference is created between the gate and drain terminal. If the electric field at the gate interface is too large, a deterioration or destruction of the oxide layer can occur, especially if imperfections in the oxide or interface material are present. Summary A summary of aspects of certain examples disclosed herein is set forth below. lt should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and / or a combination of aspects that may not be set forth. By creation of a shielding region below the gate trench region of a semiconductor device, such as a transistor, MOSFET or power MOSFET, the electric field close to the gate oxide interface may be reduced. To fully harness the shielding potential, the shielding region may be connected to the source terminal in the depth of the semiconductor. The present disclosure aims to improve the tunability and manufacturability of such connected deep shielding regions with high integration density by employing gate trenches of laterally varying width. According to an aspect of the present disclosure, a gate trench semiconductor device is presented. The gate trench semiconductor may include gate trenches of different widths. First gate trenches may have a width narrower than a width of second gate trenches. A first shielding region may be located vertically below and at least partly laterally around a center of each of the first gate trenches. A second shielding region may be located vertically below of each of the second gate trenches but not at least partly around a center of each of the second gate trenches. In an embodiment, at least one of the first gate trenches may be located in a first region of the gate trench semiconductor device. At least one of the second gate trenches may be located in a second region of the gate trench semiconductor device parallel to the first region as seen from the top of the gate trench semiconductor device. In an embodiment, a first gate trench of the first gate trenches may be located laterally next to a second gate trench of the second gate trenches. In an embodiment, the gate trench semiconductor device may include a first implant region of a first conductivity type between the gate trenches. The gate trench semiconductor device may further include a first implant region of a second conductivity type between the gate trenches. The first implant region of the first conductivity type may be shallower in depth from a surface of the gate trench semiconductor device than the first implant region of the second conductivity type. A depth of the first implant region of the second conductivity type may be less than a depth of the gate trenches. In an embodiment, at the first gate trenches a second implant region of the second conductivity type may form the first shielding region. At the second gate trenches a second implant region of the second conductivity type may form the second shielding region. The first shielding region may contact the first implant region of the second conductivity type located between the first gate trenches. The second shielding region may not be in contact with the first implant region of the second conductivity type located between the second gate trenches. The first shielding region may contact the second shielding region. In an embodiment, the first shielding region may be connected to a terminal contact. In an embodiment, the gate trench semiconductor device may be a power semiconductor device. In an embodiment, the gate trench semiconductor device may be a MOSFET. In an embodiment, the gate trench semiconductor device may be a power MOSFET. In an embodiment, the gate trench semiconductor device may be a silicon carbide MOSFET. According to an aspect of the present disclosure, a method of manufacturing a gate trench semiconductor device is presented. The method may include etching a trench pattern into an epitaxial layer. The trench pattern may include first gate trenches having a width narrower than a width of second gate trenches. In an embodiment, the etching of the trench pattern may be such that the first gate trenches is located in a first region of the gate trench semiconductor device and the second gate trenches are located in a second region of the gate trench semiconductor device parallel to the first region as seen from the top of the gate trench semiconductor device. In an embodiment, the method may include implanting a first implant region of a first conductivity type between the gate trenches. The method may further include implanting a first implant region of a second conductivity type between the gate trenches. The first implant region of the first conductivity type may be shallower in depth from a surface of the gate trench semiconductor device than the first implant region of the second conductivity type. A depth of the first implant region of the second conductivity type may be less than a depth of the gate trenches. In an embodiment, the etching may be performed either before the implanting steps or after the implanting steps. The method may further include filling the first gate trenches and the second gate trenches, e.g., using a poly silicon, before performing the implanting steps. In an embodiment, the method may further include implanting a second implant region of the second conductivity type at the first gate trenches. Thereby, a first shielding region may be formed. The method may further include implanting a second implant region of the second conductivity type at the second gate trenches. Thereby, a second shielding region may be formed. The first shielding region may be located vertically below and at least partly laterally around a center of each of the first gate trenches. A second shielding region may be located vertically below of each of the second gate trenches but not at least partly around a center of each of the second gate trenches. The first shielding region may contact the first implant region of the second conductivity type located between the first gate trenches. The second shielding region may not contact the first implant region of the second conductivity type located between the second gate trenches. In an embodiment, a first gate trench may be aligned with a second gate trench to allow the first shielding region of the first gate trench to contact the second shielding region of the second gate trench. In an embodiment, a first gate trench of the first gate trenches may be located laterally next to a second gate trench of the second gate trenches. According to an aspect of the present disclosure, a semiconductor package is presented. The semiconductor package may include a gate trench semiconductor device having one or more of the above-described features. The gate trench semiconductor device having one or more of the above- described features may be a part of a semiconductor chip. Brief description of the Drawings Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbol indicate corresponding parts, in which: Fig. 1 is a simplified top-view of a part of a gate trench semiconductor device; Figs. 2, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A and 8B are cross-sectional side views of an example semiconductor device during steps in the manufacturing process, with the A-numbered figures showing views along Sect. A as indicated in Fig. 1 and the B-numbered figures showing views along Sect. B as indicated in Fig. 1; Fig. 9 shows a cross-sectional side views of an alternative example semiconductor device during a step in the manufacturing process; and Fig. 10 is a simplified top-view of a part of the alternative gate trench semiconductor device of Fig. 9. The figures are intended for illustrative purposes only, and do not serve as restriction of the scope of the protection as laid down by the claims. Detailed description It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the present disclosure is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope. Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single example of the present disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same example. Furthermore, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment. The solution presented by the present disclosure includes a novel way of contacting a shielding region implanted below the gate trench structure of a semiconductor device by laterally varying the gate trench width. A shielding region is located vertically below and at least partly laterally around the center of the gate trench. In an embodiment of the present disclosure, to fully use the shielding potential of the shielding region, it should not be left floating. Preferably the shielding region is electrically connected to the source potential. For this, the shielding region may be connected to the well region in the lateral depth of the semiconductor. Moreover, trenches with laterally varying widths are employed, as will be further detailed below. Fig. 1 is a simplified top-view of a part of a gate trench semiconductor device 100, such as a MOSFET or a power MOSFET. Different layers of the gate trench semiconductor device 100 are visualized in different gradients. In the following figures 2-9A, these layers will be further discussed. Multiple gate trench components 110 may be part of the gate trench semiconductor device 100. In an example embodiment, components 110 may be arranged side-by-side in the plane of the substrate enabling a high integration density. In Fig. 1, four of such components 110 are shown from left to right. Fig. 1 illustrates a gate trench semiconductor device 100 with gate trench components 110 having trenches of two different widths. First and narrower width trenches 102 are shown along section cut line A (depicted Sect. A). Note that only one of the four locations of the first and narrower width trenches 102 has been highlighted in Fig. 1. Second and wider width trenches 104 are shown along section cut line B (depicted Sect. B). Note that a similar cut line B, not shown, is present at the other side of section cut line A. Also note that only one of the eight locations of the second and wider width trenches 104 has been highlighted in Fig. 1. Figures 2-9 are cross-sectional side views of an example semiconductor device according to an aspect of the present disclosure. Figures denoted A Le, Figs. 3A- 8A represent cross sectional views along Sect. A of Fig. 1. Fig. 9 is an alternative embodiment of the embodiment of Fig. 8A. Figures denoted B, i.e., Figs. 3B-8B represent cross sectional views along Sect. B of Fig. 1. Figures 2-9 show subsequent steps in manufacturing a gate trench semiconductor device, such as gate trench semiconductor device 100, according to an aspect of the present disclosure. In a first step 200, a substrate 2 may be provided and an epitaxial layer 4 of a first-conductivity type may be deposited on the substrate 2. The epitaxial layer 4 serves as a drift layer for the semiconductor device. In the next figures, the substrate 2 will not be shown. In a further step 300A, 300B, a trench pattern may be etched into the epitaxial layer with varying width at Sect. A illustrated in Fig. 3A and Sect. B illustrated in Fig. 3B. In this example, the etched trenches 6A have a first and narrower width and the trenches 6B have a second and wider width. While only etching where the same trenches (narrower and wider) are shown in Figures 3A and 3B, the present disclosure is not limited to this specific pattern. The epitaxial layer 4 may also be etched with a (periodic and / or) repeated pattern of trenches (i.e., an etch pattern alternating between trenches 6A and 6B), depending on technical specifications. In a further step 400A, 400B, the trenches 6A, 6B may be filled with planarized poly silicon 8A, 8B. Optionally a first scattering oxide may be deposited or grown on the surface. In a further step 500A, 500B, a first implant of the first conductivity type 10A, 10B and a first implant of the second conductivity type 12A, 12B may be performed. The first conductivity implant 10A, 10B being shallower in depth from the surface than the second conductivity implant 12A, 12B. The depth of the second conductivity implants 12A, 12B are preferably less than the depth of the poly silicon 8A, 8B filled trenches. Instead of etching 300A, 300B the trenches 6A, 6B before the first implants of first 10A, 10B and second 12A, 12B conductivity, an alternative order of performing the implants 10A, 10B, 12A, 12B prior to the trench etching 300A, 300B and trench filling 400A, 400B is possible. In a further step 600A, 600B, the poly silicon 8A, 8B may be removed to obtain trenches 18A, 18B and optionally a second scatter oxide 14A, 14B may be deposited or grown on the surface of the trenches 18A, 18B. The removal of poly silicon spacers (or poly silicon) 8A and 8B may be performed by etching said poly silicon from the trenches 6A and 68 to form trenches 18A and 18B, respectively. For the narrower trenches 6A, the method may comprise the step of etching / removing all of the poly silicon 8A from said trench 6A in order to obtain trench 18A as illustrated in Figure 6A. During this step, the poly silicon is completely removed from the trench 6A. In this case, the dimensions of trench 6A and 18A may be identical. For the wider trenches 68 , the method may comprise the step of partially etching / removing the poly silicon 8B from the central region (i.e., not at the edges / sidewalls) of the trench 68 in order to obtain trench 18B as illustrated in 68. In this case, the remaining poly silicon (i.e., the portion of the poly silicon that was not removed in the etching process) 8B may partly remain on the side walls of the trenches 18B as implant blocking mask. In this case, the dimension of trench 68 may be larger (wider in the cross-section plane) than trench 18B. The amount of remaining poly silicon 8B at each sidewall of the trench may be similar, however the present disclosure is not limited hereto. The trench 18B is able to function as a trench provided that both sidewalls comprise poly silicon. An additional mask 16A, 168 may be used to block implanting in the mesa area in between the trenches. In a further step 700A, 700B, a second implant of the second conductivity 20A, 20B may be performed. Thus, a first shielding region 20A may be created vertically below and laterally around a center of each of the first and narrower trenched. Furthermore, a second shielding region 20B may be created vertically below each of the second and wider trenches. The implant depth of the second implant of the second conductivity 20A, 20B is preferably shallower than the trench depth. As shown in Fig. 7A, at the first and narrower trenches, the second implants of the second conductivity 20A may contact the first implants of second conductivity 12A, thereby forming a conductive path. By contrast, as shown in Fig. 7B, at the second and wider trenches, the second implants of the second conductivity 20B may not be in contact the first implants of second conductivity 12B. Optionally, the mask 16A, 16B may be used to shield part of the region in between trenches from the implant. Subsequent manufacturing of gates 22A, 22B (e.g., using heavily doped polysilicon), gate oxides, terminal contacts 26A, 26B at gate / drain / source, interlayer dielectrics, metallization layers 24A, 24B and passivation layers may be performed in step 800A, 800B to complete the gate trench semiconductor device. These steps are not a key feature of the solution of the present disclosure and are therefore not shown in detail. Regarding gates (or gate trenches) 22A and 22B, the etching pattern(s) for these trenches 22A and 22B is / are the same as those described for trenches 6A and 6B in Figures 3A and Figure 3B, respectively. In an alternative embodiment 900A shown in Fig. 9, step 700A may have been performed by implanting the second implant of the second conductivity 20A below and to one side of the first and narrower trenches (i.e., in Fig. 10 at Sect. A of semiconductor device 100, which is similar to Sect. A in Fig. 1 but with asymmetrical second implants of the second conductivity 20A along Sect. A). In the example of Fig. 9, the second implant of the second conductivity 20A has been implanted to the left of the first and narrower trenches. It will be understood that the configuration of Fig. 9 may be realized vertically mirrored. At Sect. A and Sect. A, the first implant of the second conductivity type 12A and the second implant of the second conductivity type 20A, 20A form shielding implant regions at the first and narrower trenches. At Sect. B, the first implant of the second conductivity type 12B and the second implant of the second conductivity type 20B form shielding implant regions at the second and wider trenches. The creation of a deep (shielding) region 20A, 20A, 20B located underneath the gate trench enables a space efficient, flexible and tuneable contact density. The contact density may be tuned by changing the width of the trenches along Sect. A, Sect. A and the width of the trenches along Sect. B. In a preferred embodiment, the trenches along Sect. A, Sect. A have a first and narrower width compared to the trenched along Sect. B having a second and wider width. This may be expressed as: Width trenches along Sect. A, Sect. A' < Width trenches along Sect. B. The difference in width and therewith the tuneability of the contact density may be expressed as a ratio between the widths. For example: ratio = Width trenches along Sect. A, Sect. A' / Width trenches along Sect. B, With Fati0<1. The shielding region 20A, 20A, 208 shields the gate from high electric fields and protects it from dielectric breakdown and aging processes commonly found in such structures. In the areas with narrower gate trenches (i.e., along Sect. A or Sect. A) the shielding region may be connected to the contact opening of the semiconductor device. The solution of the present disclosure may be applied to gate trench semiconductor devices, such as power semiconductor devices, power MOSFETs and silicon carbide MOSFETs. In an embodiment, the gate trench semiconductor device of the present disclosure, such as gate trench semiconductor device 100, 100, may be packaged into a semiconductor package. In an embodiment, the gate trench semiconductor device of the present disclosure, such as gate trench semiconductor device 100, 100, may be part of a semiconductor chip. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope thereof.

Claims

1. A gate trench semiconductor installation (100, 100') comprising gate trenches (6A, 68, 22A, 228) of various widths, in which first gate trenches (6A, 22A) have a width that is narrower than the width of second gate trenches (68, 228), in which a first shielding area (20A, 20A') is located vertically below and to the at least partially laterally around the center of each of the first gate trenches (6A, 22A) is located, and in which a second shielding area (208) is located vertically under each of the second gate trenches (68, 228) is located, but not at least partially around a middle of each of the second gate trenches (68, 228).

2. The gate trench semiconductor device according to claim 1, in which at least one of the first gate trenches (6A, 22A) is located in a first area (Sect. A, Sect. A') is located of the gate trench semiconductor device, and in which at least one of the second gate trenches (GB, 22B) is located in a second region (section B) of the gate trench semiconductor device parallel to the first area seen from the top of the gate trench semiconductor device.

3. The gate trench semiconductor device according to claim 2, in which a first gate trench of the first gate trenches (6A, 22A) situated laterally next to a second gate trench of the second gate trenches (GB, 22B) is located.

4. The gate trench semiconductor device according to one of the preceding claims, comprising: a first implant area of ​​a first conductivity type (10A, 10B) between the gate trenches (GA, GB, 22A, 22B); and a first implant area of ​​a second conductivity type (12A, 12B) between the gate trenches (GA, GB, 22A, 22B), in which the first implant area of ​​the first conductivity type (10A, 10B) is shallower when viewed from a surface of the gate trench semiconductor device than the first implant area of ​​the second conductivity type (12A, 12B), and in which a depth of the first implant area of ​​the second conductivity type (12A, 128) is smaller than the depth of the gate trenches (GA, GB, 22A, 22B).

5. The gate trench semiconductor device according to claim 4, where at the first gate trenches (GA, 22A) a second implant area of ​​the second conductivity type forms the first shielding area (20A, 20A"), where a second implant area is located at the slots of the second port (GB, 22B) forms the second shielding area of ​​the second conductivity type (208), where the first shielding area (20A, 20A') is in contact with the first implant area of ​​the second conductivity type (12A) located between the first gate trenches (GA, 22A) is located, where the second shielding area (20B) does not make contact with the first implant area of ​​the second conductivity type (12B) located between the second gate trenches (GB, 22B) is located, and where the first shielding area (20A, 20A') is in contact with the second shielding area (20B). G. The gate trench semiconductor device according to one of the preceding claims, where the first shielding area (20A, 20A') is connected to a terminal contact (24A, 2GA).

7. The gate trench semiconductor device according to one of the preceding claims, where the gate trench semiconductor device is one of the following: a power semiconductor device; a metal-oxide-semiconductor field-effect transistor, MOSFET; a power MOSFET; a silicon carbide MOSFET.

8. A method for manufacturing a gate trench semiconductor device (100, 100'), the method consisting of: etching (300A, 300B) of a trench pattern in an epitaxial layer, where the trench pattern consists of first gate trenches (GA, 22A) with a width that is narrower is then the width of second gate trenches (GB, 22B).

9. The method according to conclusion 8, whereby the trench pattern is such that etched that the first gate trenches (GA, 22A) are located in a first area (Sect. A, Sect. A') of the gate trench semiconductor device and where the second gate trenches (GB, 22B) are located in a second area (section B) of the gate trench semiconductor device parallel to the first area viewed from the top of the gate trench semiconductor device.

10. The method under Claim 8 or Claim 9, consisting of: implantation (500A, 500B) of a first implant area of ​​a first conductivity type (10A, 10B) between the gate trenches (GA, GB, 22A, 22B); and implantation (500A, 500B) of a first implant area of ​​a second conductivity type (12A, 12B) between the gate trenches (GA, GB, 22A, 22B), where the first implant area of ​​the first conductivity type (10A, 10B) is shallower when viewed from a surface of the gate trench semiconductor device than the first implant area of ​​the second conductivity type (12A, 12B), and where the depth of the first implant area of ​​the second conductivity type (12A, 12B) is smaller than the depth of the gate trenches (GA, GB, 22A, 22B).

11. The method according to conclusion 10, where the etching is performed or before the implantation steps (500A, 500B) or after the implantation steps (500A, 500B), and where the procedure further consists of filling the first gate trenches (GA, 22A) and the second gate trenches (GB, 22B), preferably using a polysilicone (8A, 8B), before performing the implantation steps (500A, 500B).

12. The method under claim 10 or claim 11, further consisting of: at the first gate trenches (GA, 22A), implant (700A) of a second implant area of ​​the second conductivity type, resulting in a first shielding area is formed (20A, 20A'); at the second gate trenches (GB, 22B), implanting (700B) of a second implant area of ​​the second conductivity type, resulting in a second shielding area is formed (20B), in which the first shielding area (20A, 20A') is located vertically below and to the at least partially laterally around the center of each of the first gate trenches (6A, 22A) is located, in which a second shielding area (208) is located vertically under each of the second gate trenches (GB, 22B) is located, but not at least partially around the middle of each of the second gate trenches (GB, 22B), where the first shielding area (20A, 20A') is in contact with the first implant area of ​​the second conductivity type (12A) located between the first gate trenches (GA, 22A) is located, and where the second shielding area (20B) does not make contact with the first implant area of ​​the second conductivity type (12B) located between the second gate trenches is located (GB, 22B).

13. The method according to conclusion 12, where, prior to implanting (700A) the second implant area of the second conductivity type, the method further includes removal (GOOA) of all the polysilicon (8A) filled in the first gate trench (GA) and forming trench 18A, and where, prior to implanting (700B) the second implant area of the second conductivity type, the method further includes removal (GOOB) from a central part of the polysilicon (8B) filled in the second gate trench (GB), where the remaining polysilicon (8B) forms the sidewalls of trench (8B).

14. The method under claim 12 or claim 13, where a first gate trench (GA, 22A) is aligned with a second gate trench (GB, 22B) so that the first shielding area (20A, 20A') of the first gate trench can make contact with the second shielding area (20B) of the second gate trench.

15. The method according to claim 14, whereby a first gate trench of the first gate trenches (GA, 22A) adjacent to a second gate trench of the second trenches (GB, 22B) is located.

16. A semiconductor package consisting of the gate trench semiconductor device according to one of the conclusions 1-7.

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