A process of metal gate integration in trench semiconductor devices

NL2039348B1Active Publication Date: 2026-07-07NEXPERIA BV
View PDF 1 Cites 0 Cited by

Patent Information

Authority / Receiving Office
NL · NL
Patent Type
Patents
Current Assignee / Owner
NEXPERIA BV
Filing Date
2024-12-13
Publication Date
2026-07-07
Patent Text Reader

Abstract

A process of fabricating a trench semiconductor device, the trench semiconductor device thus fabricated and a semiconductor package including such semiconductor device are presented. The process is characterized by the gate metal being formed before interlayer dielectric (ILD) deposition. A nitride-based spacer and a sacrificial layer are formed at the location of the gate metal before forming the gate metal. The nitride-based spacer and the sacrificial layer protect a gate oxide during formation of the active region of the trench semiconductor device. The sacrificial layer is removed after the formation of the active region and before forming the gate metal.
Need to check novelty before this filing date? Find Prior Art