Transmitter module and procedure for transmitting differential signals in a serial bus system

Abstract

A transmitter module and a method for transmitting differential signals in a serial bus system have been made available. The transmitter module comprises: a first transmitter stage for a first signal to be transmitted to a bus; a second transmitter stage for a second signal to be transmitted to the bus as a differential signal relative to the first signal; a third transmitter stage for the first signal; and a fourth transmitter stage for the second signal. The four transmitter stages are connected in a full bridge, with the first and fourth transmitter stages connected in series and the third and second transmitter stages connected in series. Each transmitter stage has at least two current stages, each with a switchable resistor, where the switchable resistors of a transmitter stage have different resistance values.

Description

_ 1 _ Description Transmitter module and method for transmitting differential signals in a serial bus system The present invention concerns a transmitting module and a transmission method. of differential signals in a serial bus system, where in particular a voltage source of Vcc = 3.3 V is used for transmitting / receiving devices. State of the art Differential signals are used, for example, in CAN bus systems or in Ethernet. bus systems according to the 10-8-8-8 standard for data transmission on a bus. Attached to the bus are devices in vehicles and / or other technical installations connected. The signals serially signal the data required for communication must be transferred between the devices over the bus. The devices form at the bus participant stations, which are also called hubs. Each participant station has at least one transmitting / receiving device that is also a transceiver is mentioned. For data transfer via CAN, for example, the international standard |SOll898-1:2015 Classical CAN and CAN FD standardized. CAN FD becomes currently often deployed with 2 Mbit / s data bitrate and 500 kbit / s arbitration bitrate. So-called CAN SIC transmit / receive devices enable the use of CAN FD with up to 8 Mbit / s possible. For higher data speeds of currently up to 20 lb / s, CAN XL is now available. With all the mentioned CAN-based bus systems, for a transmission signal TXD separately a bus signal CAN_H and ideally simultaneously a CAN_L bus signal is driven onto a bus. In doing so, at least in the first communication period in bus signals CAN_H, CAN_L a bus status active driven. The other bus status is not driven and establishes itself as a result of a Termination resistor for bus lines and bus conductors of the bus, respectively. As a result of the differently driven states can in a real bus system with branch lines, mismatches etc. the signal shapes of the bus signals CAN_H, CAN_L deviate from the ideal signal shape. This can lead to errors in the evaluation of the The bus receives bus signals. _ 2 _ Currently, in CAN bus systems for transmitting / receiving devices (transceivers) a voltage source of Vcc = 5 V used to the various to generate voltage levels for the differential signals on the bus. To reduce costs, consideration is being given to a to use a voltage source of Vcc = 3.3 V. Such a reduction of the supply voltage would be advantageous, since the voltage of 3.3 V in many contemporary microcontrollers are used. Moreover, many others can also components are powered by this voltage. Lowering the supply voltage from 5 V to 3.3 V only provides the desired result. advantage as existing devices for a CANbus with a power supply voltage be usable from 5V. For this, 5V participant stations (5V nodes) must and 3.3V participant stations (3.3V nodes) in random numbers simultaneously on a bus can communicate. It should be noted that the current CAN bus is due to the differential signals CAN_H, CAN_L have an average voltage of Vcc / 2, so 2.5 V. This is achieved because each bus participant station via a standardized resistance network with With the help of a current source, the bus tries to keep it at more or less exactly 2.5 V. The bus voltage essentially follows the lowest node voltage (voltage at the participant station), so it is typically slightly below 2.5 V. When transmitting, a CAN participant station (node) can, more specifically, its transmitting / receiving device switch between a dominant state and a recessive state. For the dominant state, it drives the CAN_H level to approx. 3.5 V and the CAN_L level at approx. 1.5 V. The difference between CAN_H level and CAN_L level is then in a range of 2 V. Of the international standard l50118981:2015 are a minimum of 1.5 V required. The transition from the recessive to the dominant state or returns thereby taking place as symmetrically as possible around the virtual zero line, which at Vcc / 2 It aligns. As a result, the sum of the levels of CAN_H and CAN_L remains as close to 5 V as possible. A major problem is that small deviations in the mV range are already clear result in electromagnetic emissions, which cause EMC disturbances (EMC = cause electromagnetic compatibility of other electrical devices. Therefore, there are regulations for maximum permissible electromagnetic _ 3 _ emissions, which every transmitting / receiving device (transceiver) must comply with. However, These requirements for electromagnetic emissions pose a very major challenge. Compared to CAN FD, for transceivers for CAN-SIC or transceivers for CAN- XL in the arbitration phase, which is also referred to as SIC mode or SIC operating mode, alongside the recessive (rec) and dominant (dom) states a third state, the state sic, are generated. To meet the emission requirements of standard |EC62228-3, must have a common-mode voltage from the bus lines for the signals CAN_H, CAN_L in three transmission states, namely recessive, dominant, sic, within narrow limits be held. The common-mode voltage is generated at a DC throttle, which particularly in a certification measurement for testing compliance with the standard EC62228-3 is used. The DC throttle is also known as a common mode choke. (called CMC). The DC throttle is tasked with differential signals (DNI=differential mode) to allow as much as possible without influence and to complete common-mode signals (CM=common mode) as much as possible suppress. However, in practice, the DC throttle generates from a differential signal without common mode component at the input a differential signal with an unwanted common-mode signal at the output. This is unfavorable, because this is fed directly into the CAN bus on the bus side and is visible to other CAN modules. The challenges are all the greater in mixed operation when on the bus at least one participant station with a transmitting / receiving device (transceiver) is present, which in the dominant state drives other voltage levels for CAN_H and CAN_L than transmitting / receiving devices (transceivers) of other participating stations. The reasons The for this are as follows. When parameters of the Physical Layer are changed, restoring is Interoperability between the participating stations is usually very labor-intensive. Therefore, is it is desirable that a 3.3V CAN bus functions just like the 5V CAN bus, except that the voltages on the bus differ. The Physical Layer corresponds to the bit transfer layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model). _ 4 _ So a 3.3V node (participant station) for the dominant state must be on the bus the CAN_H signal to approximately 3V and the CAN_L signal clearly below 1V to exceed the specified minimum level difference of 1.5 V. A peculiarity of mixed functioning is that a 5V node is in the recessive phase. sets the bus to 2.5 V, while a 3V node targets the bus at approx. 1.65 V. By a increasing the CAN_L voltage at 3.3VCAN in the direction of 1V can the voltage in the recessive state be increased to approx. 1.9 V. However, a difference of remains approx. 500-600mV exist between the 5V and 3.3V nodes. The bus takes a such a configuration applies a voltage somewhere between 1.9 V and 2.5 V and flows a constant current towards the 3.3V node, which, however, is on the order of a few microampere lies. However, when a participant station (node) starts transmitting and in the when the dominant state occurs, the participant station (node) does not do so from its side. zero line, but from that of the mixed operation. As a result, the sum of the changes levels of CAN_H and CAN_L when switching, and again when switching back. This predictably leads to high EMC emissions. As a result, mixed operation is not so as simple as possible. Revelation of the invention It is therefore the task of the present invention to provide a transmitting module and a method. to provide for the transmission of differential signals in a serial bus system, which solve the aforementioned problems. In particular, the transmitter module and must the method for transmitting differential signals in a serial bus system enable compensation of disturbing variables that influence the emission behavior of the transmitter module. The task is solved by a transmitter module for transmitting differential signals. in a serial bus system with the characteristics of conclusion 1. The transmitter module has a first transmitting stage for generating transmit currents for an initial signal, which goes to to transmit a bus of the bus system is, a second transmitting stage for generating transmit currents for a second signal, which acts as a differential signal with respect to the first signal to send to the bus is, a third transmitting stage for generating _ 5 _ transmit currents for the first signal, and a fourth transmit stage for generating transmit currents for the second signal, where the first to fourth transmit stages in a are fully bridge connected, with the first and fourth transmitting stages in series switched and the third and second transmitting stages are connected in series, where each of the first to fourth transmitting stage comprises at least two current stages, which are parallel to are connected to one another, whereby each of at least two current stages a includes switchable resistor, where the switchable resistors of a transmitter stage have different resistance values, where the first to fourth transmitting stages each have include reverse polarity diode for protection against positive feedback in a connection for the bus voltage supply and a negative feedback from a connection for ground, where the polarity reversal diode of the first transmitter stage and the third each transmitting stage is a switched reverse polarity diode that can be bridged or short-circuited be, and where the repolarization diode of the second transmitting stage and the fourth transmitting stage each is a pn-based polarity reversal diode, which is a parasite of a transistor and fixed is wired so that the reverse polarity diode cannot be bridged or short-circuited. The described transmitter module also generates a with a power supply of 3.3 V Operation in a bus system according to international CAN standards is possible. Moreover, operation in a bus system is also possible, in which 3.3V- participant stations and 5V participant stations are present and therefore a mixed operation takes place. In addition, even combined operation in a CANbus system occurs. easily ensured that the required limit values ​​for the emission of a transmitter / receiving device can also be complied with for CAN XL. The transmitter module complies in particular with standard |EC622283, which must be observed establishes limit values ​​for the bus states dom, sic, and rec. For example, the previously described transmitter module can have the impedance in the sic state. adapt very well between the bus lines for the CAN_H and CAN_L signals to the characteristic wave resistance or impedance of the bus cable used. For the For the impedance Zw of the bus line used, Zw = 100 Ohm or Zw = 120 applies. Ohm. As a result, the transmitter module prevents reflections and thus allows the operation in the bus system at higher bit rates. The described transmitting module makes, through a division of its four transmitting stages into n share a time-spaced and controlled switching operation possible and can in the in particular display the required 3V-CAN levels. In addition, activation according to the _ 6 _ Gauss error function realizable. This makes a setting of soft behavior at the activation action possible. Moreover, the possible variation of time steps is prevented. upon switching on, the occurrence of a narrowband frequency line in the radiation frequency spectrum. Alternatively, it is possible to use the described transmitter module for a distributed and to perform a controlled switching operation over fixed time steps and varied voltage steps. As a result, the emission behavior of the transmitter module can be such that be influenced that the prescribed limit values ​​are complied with. Moreover, the described transmitter module can reduce effects resulting from asymmetrical behavior of the transmitting stages, which can be dom, sic, rec in the transmitting states occur and worsen the emission. The transmitter module prevents inconsistent behavior. of components in transmitter stages A, B (Effect 1) of a complete bridge, such that in the dom state a change in common-mode voltage compared to the REC condition is minimized or prevented. Furthermore, the transmitter module can Uneven behavior of components in transmitter stages A / D and C / B of the entire bridge occur (Effect 2), such that in the sic state a change of the common mode stress compared to the rec state is minimized or prevented. This is particularly advantageous, because only if from the common-mode level of the rec state the common levels in the dom state and in the sic state correspond with that of the REC condition, a sufficient emission result can be achieved, but the causes leading to the behavior of Effect 1 may be different from those to Effect 2 lead. Economical further versions of the transmitter module are described in the dependent conclusions. The output connections of the entire bridge can be provided for connection to a bus termination resistor. In one embodiment, the first to fourth transmitting stages each have a reverse polarity diode for protection against positive feedback in a connection for the bus voltage supply and negative feedback from a connection for ground, where the polarity reversal diode of the first transmitting stage and the third transmitting stage each a is a switched polarity reversal diode that can be bridged or short-circuited, and where _ 7 _ the polarity reversal diode of the second transmitting stage and the fourth transmitting stage each a pn based reverse polarity diode, which is a parasite of a transistor and is hardwired, so that the reverse polarity diode cannot be bridged or short-circuited. In one configuration, the output connections of the complete bridge are provided. for connection to a bus termination resistor. It is conceivable that the polarity reversal diodes are configured for setting a bus center voltage of approximately 1.9 V when the transmitter module operates with a voltage supply of approximately 3.3 V. In an embodiment, the first transmitting stage and the third transmitting stage each have a polarity reversal circuit, which the polarity reversal diode, a first transistor, a second comprises a transistor and a resistor, where the second transistor is a has a switching resistance value that is much smaller than a resistance value of resistance. In this case, the drain terminal of the first transistor can be connected to the anode of the polarity reversal diode, where the source terminals of the first and second transistors are connected to the cathode of the polarity reversal diode, where the The gate terminal of the first transistor is connected to the drain terminal of the second transistor and via the resistor with the connection for ground, where the gate- The connection of the second transistor is connected to the connection for the bus power supply. Optionally, the path from gate connection to source connection of the first has Transistor: a filter for protection against pulse-like interference. Possibly, a number n of the at least two flow stages for each of the first the same up to the fourth transmitting stage, where n is a natural number greater than 1. In an implementation, each of the at least two flow stages has a CMOS Transistor for switching the resistor of the current stage. According to an implementation example, the CMOS transistor of the current stages of the first transmitting stage a PMOS transistor, where the CMOS transistor of the current stages of the second transmitting stage is an NMOS transistor, where the CMOS- transistor of the current stages of the third transmitting stage is a PMOS transistor, and _ 8 _ where the CMOS transistor of the current stages of the fourth transmitting stage is an NMOS- transistor is. In addition, each from the first to the fourth transmitting stage can have a reverse polarity diode. include for protection against positive feedback in a connection for the bus voltage supply and a negative feedback from a connection for mass, and at least one cascode for the protection of the CMOS transistors. According to another implementation example, at least two cascades are parallel to interconnected, where a number y of the cascades for each of the first to fourth transmitting stage is the same, where y is a natural number greater than 1, and where the the switching resistance of at least two casings is different. The transmitter module can additionally have at least one first current limiting module as include a current source, which is located between a connection for the bus voltage supply and the entire bridge is switched, and at least one second current limiting module as a current well, which is connected between a ground connection and the entire bridge. According to an implementation example, at least two first current limiting modules connected in parallel, of which the switching resistance is different, where at least two second current limiting modules are connected in parallel, of which the switching resistance is different, and where the number x of the first current limiting modules is equal to the number x of the second current limiting modules, where x is a natural number greater than 1. The transmitter module may also include a control circuit for controlling switchable components from the first to the fourth transmitter stage dependent on a digital transmission signal and of an operating mode set for the transmitter module. It is possible the control circuit configured for the time-spaced and controlled switching of the resistance values ​​of at least two current stages. The previously described transmitter module can be part of a transmitter- / receiving device for a participant station for a serial bus system, which moreover, includes a receiving module for receiving signals from the bus. _ 9 _ The transmitting / receiving device may be part of a participant station for a serial bus system, which also includes a communication control device for controlling communication in the bus system and for generating a Digital transmission signal for controlling the first to fourth transmission stages. The participant station may be configured for communication in a bus system. in which at least temporarily an exclusive, collision-free access of a participant station until the bus of the bus system is guaranteed. Moreover, the aforementioned task is solved by a method for the transmitting differential signals in a serial bus system with the characteristics of Conclusion 19. The procedure is carried out using a transmitter module, whereby the The method involves the steps: generating transmission currents with a first transmitting stage. for an initial signal to be sent to a bus of the bus system; generate, with a second transmitting stage, of transmitting currents for a second signal that as a to send a differential signal relative to the first signal to the bus; generate, with a third transmitting stage, transmit currents for the first signal; and generate, with a fourth transmitting stage, transmit currents for the second signal, where the first to fourth transmitting stages are connected in a full bridge, where the first and the fourth transmitting stage is connected in series and the third and second transmitting stages are in series switched, whereby each of the first to fourth transmitting stages has at least two comprises current stages connected in parallel, where each of the ten at least two current stages comprises a switchable resistor, and where the switchable resistors of a transmitter stage have different resistance values, where the first to fourth transmitting stages each use a reverse polarity diode for protection against positive feedback in a connection for the bus voltage supply and negative feedback from a connection for ground, where the polarity reversal diode of the first transmitting stage and the third transmitting stage each a is a switched polarity reversal diode that can be bridged or short-circuited, and where the polarity reversal diode of the second transmitting stage and the fourth transmitting stage each a pn based reverse polarity diode, which is a parasite of a transistor and is hardwired, so that the reverse polarity diode cannot be bridged or short-circuited. The method offers the same advantages as mentioned earlier with regard to the transmitter module. _ 10 _ Other possible implementations of the invention also do not explicitly include mentioned combinations of characteristics described earlier or below or implementation forms relating to the execution examples. In this regard, the professional will also individual aspects such as improvements or additions to the respective add basic form of the invention. Drawings The invention is described in further detail below, with reference to the attached drawing and based on execution examples. These show: Fig. 1 a simplified block diagram of a bus system according to a first example of implementation; Fig. 2 a diagram illustrating the structure of a message that by a first participant station of the bus system according to the first implementation example can be sent; Fig. 3 shows the time course of a digital transmission signal in the operation of the bus system at the first and / or second participant station, with at least one first participating station is connected to the same bus of the bus system; Fig. 4 shows the time course of bus signals CAN_H and CAN_L at the second participant station according to the first implementation example; Fig. 5 shows the time course of a differential voltage VDIFF of the bus signals CAN_H and CAN_L at the first and second participant stations according to the first example of implementation; Fig. 6 a time course of a digital reception signal that the first or second The participant station generates a signal received from the bus, which is based on the transmission signal of Fig. 3; Fig. 7 shows the time course of bus signals CAN_H and CAN_L, which are transmitted by the first participant station can be on the bus according to the first implementation example generated, based on the transmission signal in Fig. 3; _ 11 _ Fig. 8 an example of the time course of a digital transmission signal, which in a arbitration phase (SIC operating mode of a transmitter module) in bus signals CAN_H, CAN_L must be converted for a bus of the bus system in Fig. 1; Fig. 9 the time course of the bus signals CAN_H, CAN_L during the transition of a recessive bus status to a dominant bus status and back to the recessive bus status, which in the arbitration phase (SIC operating mode) due to the transmission signal from Fig. 8 to be sent by bus; Fig. 10 a circuit diagram of a transmitter module for a participant station of the bus system according to the first implementation example; Fig. 11 a time diagram showing the switching on of various current stages of a transmitting stage for a first specific example of the transmitter module of Fig. 10; Fig. 12 a detail of a transmitting stage for a second specific example of the transmitter module of Fig. 10; and Fig. 13 a circuit diagram of a transmitter module for a participant station of the bus system according to a second implementation example. In the figures, elements are equal or functionally equal, unless otherwise indicated, provided with the same reference numbers. Description of the implementation examples Fig. 1 shows a bus system 1, which is, for example, at least partially a CAN bus system, a CAN-FD bus system, etc., can be. Bus system 1 can be in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc. be used. In Fig. 1, bus system 1 has a large number of participating stations 10, 20, 30, each of which are connected to a bus 40 or bus line with a first bus conductor 41 and a second _ 12 _ bus line 42. Bus lines 41 and 42 can also be CANH and CANL in a CANbus system. are designated for conducting signals CAN_H, CAN_L on bus 40. Via bus 40, messages 45, 46, 47 can be transmitted in the form of signals between the Individual participant stations 10, 20, 30 are being transferred. The participant stations 10, 20, 30 are, for example, control devices or display devices of a motor vehicle As shown in Fig. 1, participant stations 10, 30 each have a communication control device 11 and a transmit / receive device 12. The transmit / receiving device 12 has a transmitting module 121 and a receiving module 122. The Participant station 10 uses a supply voltage of 3.3 V, minimum 3.0 V. Ten at least one of the participant stations 20, 30 uses a supply voltage of 5 V. Ter illustration shows the following versions an example of a network or bus system 1, where participant station 20 has a supply voltage of 5V and the participant stations 10 and 30 have a voltage of 3.3V, minimum 3.0V. Others Constellations are also conceivable. Participant station 20 has a communication control device 21 and a transmit- / receiving device 22. The transmitting / receiving device 22 has a transmitting module 221 and a receiving module 222. The transmitting / receiving devices 12 of the participant stations 10, 30 and the transmitting / receiving facility 22 of participant station 20 are each directly on bus 40 connected, even though this is not shown in Fig. 1. Communication control devices 11, 21 each serve to control a communication from the respective participant station 10, 20, 30 on bus 40 with ten at least one other participant station of participant stations 10, 20, 30, which are on the bus 40 are connected. The communication control devices 11 make and read first messages 45, 47, which for example, modified CAN messages 45, 47 are. Here, the modified CAN messages 45, 47, for example, are structured based on the CAN XL format. The transmitting / receiving device 12 is used for sending and receiving messages 45, 47 of the bus. Transmitter module 121 receives a by the _ 13 _ communication control device 11 for one of the messages 45, 47 made digital transmission signal TXD and converts this into signals on bus 40, as further described with with regard to Fig. 3, Fig. 4 and Fig. 7. The digital transmission signal TXD can at least temporarily or partially be a pulse width modulation signal. The receiving module 121 receives on bus 40 transmitted signals in accordance with messages 45 to 47 and generates a digital reception signal RXD from this, for which an example is in Fig. 6 shown. Receiver module 122 sends the receive signal RXD to the communication control device 11. In addition, the communication control device 11 can optionally be configured for the making and reading second messages 46, which are for example CAN FD messages 46. The transmitting / receiving device 12 can be configured accordingly. The communication control device 21 can be implemented as a conventional CAN- controller according to ISO 11898-12015, i.e. as a CAN FD tolerant Classical CAN- controller or a CAN FD Controller or a CAN SIC Controller. The communication control device 21 creates and reads second messages 46, for example CAN FD messages or CAN SIC messages. Transmitter / receiver device 22 serves for the sending and receiving messages 46 from bus 40. Transmitter module 221 receives a digital transmission signal TXD generated by communication control device 21 and converts this into signals for a message 46 on bus 40, as further described with with regard to Fig. 3 and Fig. 4. Receiver module 222 receives on bus 40 sent signals in accordance with messages 45 to 47 and generates therefrom a digital reception signal RXD, an example of which is shown in Fig. 6. The transmit / receiving device 22 may be implemented as a conventional CAN FD transceiver or CAN-SIC transceiver. For sending messages 45, 46, 47 with CAN SIC or CAN XL, tested properties adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, particularly frame structure with identifier and Arbitration in accordance with the well-known CSMA / CR method, as described in further detail below. With the two participant stations 10, 30, there is a formation and subsequent transmission of messages. 45, 46, 47 with various CAN formats, notably the CAN FD format or the CAN SIC _ 14 _ format or the CAN XL format, as well as the reception of such messages 45, 46, 47 feasible. This is described in more detail below in message 45. Fig. 2 shows a frame 450 for message 45, which is specifically a CAN XL frame, such as the by the communication control device 11 for the transmitting / receiving device 12 is delivered to be sent on bus 40. In doing so, the communication control device 11 the frame 450 in the current implementation example Compatible with CAN FD. Alternatively, frame 450 is compatible with any successor standard for CAN FD. According to Fig. 2, frame 450 is subdivided for CAN communication on bus 40. in various communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start bit SOF, an arbitration field 453, a steering field 454, a first switch field 455, a data field 456, a checksum field 457, a second switching field 458 and a frame end field 459, containing a marking EOF (EOF = End of Frame) is present. The checksum field 457, the second switch field 458 and the frame-end field 459 form a frame-end phase 457, 458, 459 of frame 450. In the frame-end field 459 may contain an acknowledgment field (ACK = Acknowledge), which contains at least one ACK bit and is not shown in the figures. In contrast to frame 450 in Fig. 2, in a CAN FD frame, that the participant station 20 used for the second message 46, no switching fields 455, 458 present. For all previously mentioned CAN versions, it applies that in the arbitration phase 451 with the help of an identifier (ID) in the arbitration field 453 bit by bit between the participant stations 10, 20, 30 are being negotiated as to which participant station 10, 20, 30 the message 45, 46, 47 with the highest priority Want to send and therefore for the following time for sending in the subsequent data phase 452 exclusive access to the bus 40 of bus system 1 receives. In arbitration phase 451, a Physical Layer is as used with CAN and CAN-FD. The Physical Layer corresponds to the bit transfer layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model). _ 15 _ During phase 451, the well-known CSMA / CR method is used, which simultaneous allows access from participant stations 10, 20, 30 to bus 40, without it Higher priority messages 45, 46, and 47 are destroyed. As a result, relatively simply add extra bus participant stations 10, 20, 30 to bus system 1 added, which is very advantageous. The CSMA / CR method results in so-called recessive states on the bus 40 must be, which is passed by other participant stations 10, 20, 30 with dominant levels or dominant states on bus 40 can be overridden. In the recessive condition prevails at the individual participant station 10, 20, 30 high impedance ratios, which in combination with the parasites of the bus cabling results in longer time constants. This leads to a limitation of the maximum bit rate of the current CAN-FD-Physical-Layer to currently approximately 2 megabits per second in real vehicle applications. At the end of arbitration phase 451, the switch is made to the data phase. 452. With CAN XL, the switching takes place using the first switching field 455 of Fig. 2. In data phase 452, at CAN XL, next to a part of the first switching field 455 the useful data of the CAN-XL frame 450 or the message 45 from the data field 456 as well as checksum field 457 and part of the second switching field 458 is transmitted. With CAN FD, the useful data of the CAN-FD- frame of message 46 from data field 456 as well as checksum field 457 sent. At the end of data phase 452, it switches back to the arbitration phase 451. At CAN XL, the switchover takes place using the second switching field 458 of Fig. 2. A sender of message 45 only starts transmitting bits of the data phase 452 on bus 40 when the participant station 10 as the transmitter the arbitration has won and participant station 10 as the broadcaster, thereby granting exclusive has access to bus 40 of bus system 1. _ 16 _ In the frame end field EOF, a bit sequence is provided, which the end of the frame 450 marks. With this, the bit sequence of the end field (EOF) serves to mark the end of the to indicate frame 450. The end field (EOF) ensures that at the end of the In frame 450, a number of 7 recessive bits is transmitted. Together with an optional The existing ACK Delimiter in the unshown confirmation field is at the end of frame 450 transmitted a number of 8 recessive bits. The mentioned bit sequence of recessive bits is a bit sequence that cannot occur within frame 450. This allows participant stations 10, 30 to safely reach the end of frame 450. be recognized. Participant station 10 operates from a time or a time t1, starting more precisely with time tl, for a duration T_Ml a measurement of the bus potential or the bus voltage out, which is present on bus 40. The measurement is performed after a event E1 has taken place. The event Elis is that a predetermined number of immediately consecutive recessive bits at the end of the frame 450, acted more accurately in the final field (EOF). Optionally, the participant station can, from a time t2, more accurately starting with the time t2, during a duration T_M2 a measurement of the bus potential or the perform bus voltage present on bus 40. The measurement is performed after an event E2 has occurred. Event E2 is that at the end of the first communication phase (arbitration phase 451) the participating station has determined that in the next second communication phase (data phase 452) the exclusive access to the bus 40 has and is therefore allowed to send its message. These measurements are described using the figures below. After the end field (EOF), which has 7 bits, an interframe interval follows in frame 450. (IFS Inter Frame Space), which is not shown in Fig. 2. This interframe interval (IFS) has been implemented for CAN FD in accordance with ISO 11898-1:2015. The interframe interval (IFS Interframe space) has at least 3 bits. Incidentally, the mentioned fields and bits are known from ISO 1118:1:2015 and are Therefore, not described in further detail here. _ 17 _ 20 use participant stations 10, 30 in the arbitration phase 451 as the first communication phase partially, specifically up to and including the FDF bit (inclusive), one of CAN / CAN-FD known format according to ISO1898122015. However, compared to CAN or CAN FD, is in the data phase 452 as second communication phase an increase of the net Data transfer speed, particularly up to above 10 megabits per second, is possible. Moreover, an increase in the size of the useful data per frame, particularly to approximately 2 kbyte or any other random value, possibly. Figs. 3, 5 and 6 illustrate as examples the signals that occur during the operation of the Bus system 1 is generated at participant stations 10, 20, and 30. Fig. 4 illustrates this. as an example, the signals that during the operation of bus system 1 by the participant station 20 on bus 40 are sent. As mentioned earlier, uses the participant station 20 a supply voltage of 5 V. Fig. 7 shows the bus signals that each of the participant stations 10, 30 instead of the bus signals shown in Fig. 4 generates. As mentioned earlier, participant stations 10, 30 use a Supply voltage of approximately 3.3 V, minimum 3.0 V. During the operation of bus system 1, each of the transmitter modules 121, 221 of Fig. 1 a transmission signal TxD from the associated communication control device 11 serial conversion into corresponding signals CAN_H, CAN_L for CAN or CAN FD for the bus wires 41, 42 and these signals at the connections for CAN_H and CAN_L on the transmit bus 40. The respective communication control device 11, 21 transmits it transmission signal TxD from Fig. 3 over time t (serial) to the corresponding transmitting module 121, 221, as shown in Fig. 1. As shown as an example in Fig. 3, the transmission signal TxD has the voltage levels H (High) and L (Low) with a corresponding voltage U. The Individual bits of the signal TxD have a bit time t_bt1, as in Fig. 3 for the arbitration phase 451 shown. With CAN FD and CAN XL, the bits of the TXD signal can be the data phase 452 with a shorter bit time t_bt2 be transmitted, as in Fig. 4 illustrated. The sequence of states H, L of the transmission signal TxD in Fig. 3 and the resulting resulting states 401, 402 for the signals CAN_H, CAN_L in Fig. 4 as well as the The resulting voltage curve of the VDIFF in Fig. 5 serves only for _ 18 _ illustration of the function of participant station 10. The order of the Data sheets for bus sheets 401 and 402 are selectable as needed. According to the example in Fig. 4, the signals CAN_H and CAN_L have at least in the arbitration phase 451 the dominant and recessive bus levels or bus states 401, 402, such as known from CAN. Because participant station 20 has a supply voltage of 5 V used, for the dominant condition 401 it drives the CAN_H level to approx. 3.5 V and the CAN_L level to approx. 1.5 V, as shown in Fig. 4. The recessive state 402 sets to 2.5 V, which is equal to the bus center voltage Vcm = 2.5 V. As in Fig. 5 for the differential voltage VDIFF: CAN_H CAN_L on bus 40 shown, the difference between CAN_H level and CAN_L level lies for the dominant condition 401 then in a range of 2 V. Receiver modules 122, 222 form CAN_H from the signals received from bus 40. and CAN_L, which are shown in Fig. 4, respectively the differential voltage VDIFF of Fig. 5 a received RXD signal according to Fig. 6. For the generation of the digital The reception signal RXD of Fig. 6 uses the respective receiving module 122, 222 reception waves as known. The reception signal RXD is in Fig. 6 without Loop time delay displayed. Receiver module 122 outputs this receive signal RXD by to the associated communication control device 11, 21, as in Fig. 1 shown. According to ISO 11898-1:2015, the communication control device compares 11, 21 her, according to a frame 450 and a transmission signal TXD (Fig. 3), herself transmitted bits on the sampling point AP (Sample-Point) (Fig. 4 and Fig. 5) with the on the bus 40 observed bits according to the received signal RXD (Fig. 6). A difference is represented as a considered erroneous, except for arbitration and the ACK bit. In contrast to Fig. 4, Fig. 7 shows the signals CAN_H and CAN_L, which the participant stations 10, 30 in the arbitration phase 451 and the data phase 452 on bus 40 generate. At least in the arbitration phase 451, the dominant and recessive are bus levels or bus states 401, 402 used, as already shown in Fig. 4. Since in the example mentioned, participant stations 10, 30, a supply voltage of 3.3 V use, they send the CAN_H level to approx. 2.9 V for the dominant state 401. and the CAN_L level to approx. 0.9 V, as shown in Fig. 7. The recessive condition 402 _ 19 _ sets itself to 1.9 V, which is equal to the bus center voltage Vcm = 1.9 V. In the For data phase 452, a different physical layer 452_P can be used for CAN XL than the physical layer 451_P in arbitration phase 451. Accordingly, the CAN_H- levels are directed to values ​​for states LV1, LVO, as in Fig. 7 shown. In arbitration phase 451, a physical layer is used as in CAN and CAN-FD used. The physical layer corresponds to the bit transfer layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model). Transmitter module 121 generates the signals for the transmission signal TXD in Fig. 3. CAN_H, CAN_L in Fig. 7 for bus lines 41, 42 such that the condition LVO for a state LW (Low : Low) is formed. Moreover, state LV1 is formed for a state HI (High) formed. To increase the data speed for CAN XL, the transmitting / receiving devices can 12 are configured for CAN SIC. As shown in more detail in Fig. 8 and Fig. 9, transmitter module 121 generates at CAN SIC for the transmission signal TXD of Fig. 8 the signals CAN_H, CAN_L according to Fig. 9 for the bus conductors 41, 42 with a bus intermediate voltage Vcm_sic = 1.9 V and such that there moreover, a state 403 (sic) is present. The state 403 (SIC) can differ be long, as shown with state 403_0 (sic) at the transition from state 402 (rec) to state 401 (dom) and state 403_1 (sic) at the transition of the state 401 (dom) to state 402 (rec). State 403_0 (sic) is shorter in time than condition 403_1 (sic). To generate signals according to Fig. 9, the Transmitter module 121 switched to SIC operating mode. Running through the short SIC state 403_0 is not required in CiA610-3 and the The condition depends on the nature of the implementation. The duration of the "long" State 403_1 (sic) applies to CAN-SIC as well as the SIC operating mode for CANXL. specified as t_sic < 530ns, starting with the rising edge at the transmission signal TXD of Fig. 8. Participant station 10, in particular transmit-receive device 12, operates from a time or a time t3, more precisely starting with the time t3, after an event E3 has taken place, during a duration T_M3 a measurement of the bus potential or the bus voltage present on bus 40. Event E3 is that _ 20 _ state 401(dom) is left or from state 401(dom) to state 403 (sic) is switched. Depending on the measurement result, it sets participant station 10 in that bus medium voltage Vcm is either 2.5 V (Fig. 4) or 1.9 V (Fig. 7) if bus bias is applied to bus 40. The setting on the bus bias at bus 40 or the potential 2.5 V can occur particularly during bit 7 of the frame endfield EOF or one of the following 4 recessive bits occurs. In the "long" state, transmitter module 121 must the impedance between the Adapt bus lines 41 (CANH) and 42 (CANL) as closely as possible to the characteristic Wave resistance Zw of the bus line used. Here, Zw = 1000hm or 1200hm. This adjustment prevents reflections and thus enables operation at higher bitrates possible. For simplification, reference is hereinafter always made to the condition 403 (sic) or sic condition 403. Transmitter module 121 can be used to generate signals for the bus. 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL. type states) states CAN-XL Arbitration or Arbitrage and dom, sic, rec dom, sic, rec Data field for the case that there is no switch to the Fast operating mode takes place Table 1: CAN_Types for transmitter module 121 The transmitter module state sic can therefore not only be at CAN-SIC or CAN-XL (xl_sic) generated. The transmitter module state sic can also be generated at CAN-FD. In However, with CAN-FD, the time for the transmitter module state sic can be shorter than with CANSIC. or CAN-XL. _ 21 _ Fig. 10 shows the basic structure of transmitter module 121 for one of the participant stations 10, 30. Transmitter module 12 can receive CAN_H, CAN_L signals according to Fig. 9. with states 401, 402, 403 and signals CAN_H, CAN_L according to Fig. 7 with the Generate states L0, L1. Transmitter module 121 has four transmitter stages, namely a first transmitter stage 121A, a second transmitting stage 121B, a third transmitting stage 121C and a fourth transmitting stage 121D. As in Shown in Fig. 10, the transmitting stages 121A to 121D are connected as a full bridge. Furthermore, transmitter module 121 has current limiting modules 1211, 1212. The control of current limiting modules 1211, 1212 and of others to be specified components of transmitter stages 121A to 121D are connected via at least one control unit 124. At least one control unit 124 controls at least one signal to control terminals 125, on which the current limiting modules 1211, 1212 and / or the components of transmitter stages 121A to 121D are connected. For For the sake of clarity, not all pipe connections are shown in Fig. 10. Transmitter module 121 is connected to bus 40, more specifically to the first bus conductor. 41 for CAN_H or CAN-XL_H and the second bus conductor 42 for CAN_L or CAN-XL_L. Each Transmitter stages 121A to 121D are connected to bus 40. The power supply for the first is provided via at least one connection 43. and to supply electrical energy to second bus conductor 41, 42, in particular with the CAN-Supply voltage of 3.3V. The connection to ground or CAN_GND has been established. via a connection 44. The first and second bus wires 41, 42 are connected with a Termination resistor 49 terminated. Termination resistor 49 is terminated as an external resistor in the entire bridge. Load resistance switched. Resistor 49 is in the bridge branch between the connections. Switched for bus lines 41, 42. The first transmitting stage 121A of Fig. 10 has a reverse polarity circuit D_A, a transistor HVP_A and a parallel circuit 121A1, where a first to nth current stage in parallel is switched, where n is a natural number > 1. Furthermore, there is a control circuit T_A is present. The first current stage has a series connection of a resistor R_A1. and a transistor P_A1. The nth stage has a series connection of a resistor R_An and a transistor P_An. The transistor HVP_A can be a CMOS transistor. are, in particular, a PMOS transistor. Transistors P_A1 to P_An are CMOS. transistors, in particular PMOS transistors. The abbreviation "CMOS" refers to a _ 22 _ semiconductor element where both p-channel and n-channel IVIOSFETs on a common substrate are used. The abbreviation CMOS stands for the English term "Complementary metal-oxide semiconductor", which translated means "complementary / self-complementing metal oxide semiconductor". The abbreviation "MOSFET" stands for metal oxide field-effect transistor. The control circuit T_A drives the transistors P_A1 to P_An from the first to the n-th current stage on according to the transmission signal TXD and the set operating mode SIC, FAST_TX of the transmitting module 121. The second transmitting stage 1218 of Fig. 10 has a reverse polarity diode D_B, a transistor HVN_B and a parallel circuit 121B1, where a first to nth current stage in parallel is connected, where n is the natural number > 1. Moreover, there is a Control circuit T_B is present. The first current stage Sl has a series connection of a resistor R_Bl and a transistor N_Bl. The n-th current stage has a Series connection of a resistor R_Bn and a transistor N_Bn. The transistor HVP_B can be a CMOS transistor, in particular an NMOS transistor. The transistors N_B1 Up to N_Bn are CMOS transistors, in particular NMOS transistors. The Control circuit T_B drives transistors N_Bl to N_Bn from the first to the n-th Current trap on according to the transmission signal TXD and the set operating mode SIC, FAST_TX of transmitter module 121. The third transmitting stage 121C of Fig. 10 has a reverse polarity circuit D_C, a transistor HVP_C and a parallel circuit 121C1, where a first to nth current stage in parallel is connected, where n is the natural number > 1. Moreover, there is a control circuit T_C present. The first current stage has a series connection of a resistor R_C1 and a transistor P_C1. The n-th current stage has a Series connection of a resistor R_An and a transistor P_An. The transistor HVP_C can be a CMOS transistor, in particular a PMOS transistor. The transistors P_C1 Up to P_Cn are CMOS transistors, in particular PMOS transistors. The control circuit T_C drives transistors P_C1 to P_Cn of the first to n-th current stage according to the transmission signal TXD and the set operating mode SIC, FAST_TX of the transmitter module 121. The fourth transmitting stage 121D of Fig. 10 has a reverse polarity diode D_D, a transistor HVN_D and a parallel circuit 121D1, where a first to n-th current stage in parallel is connected, where n is the natural number > 1. Moreover, there is a _ 23 _ control circuit T_D is present. The first current stage has a series connection of a resistor R_D1 and a transistor N_D1. The n-th current stage has a Series connection of a resistor R_Dn and a transistor P_Dn. The transistor HVP_D can be a CMOS transistor, in particular an NMOS transistor. The transistors N_D1 Up to N_Dn are CMOS transistors, in particular NMOS transistors. The Control circuit T_D drives transistors N_D1 to N_Dn from the first to the nth. Current trap on according to the transmission signal TXD and the set operating mode SIC, FAST_TX of transmitter module 121 on. The current stages Sl to Sn of the transmitting stages 121A to 121D are therefore as resistance levels implemented. The resistance levels are set by the selection of the resistance value of the respective current stage, for example by the choice of the resistors R_A1 to R_An for the transmitting stage 121A, and so on. As a result of the setting the resistance values ​​of the resistors becomes current stages set. The number n is arbitrarily selectable. In particular, the number n and thus the number of stages or the number of resistance stages or current stages between 1 and 60 be chosen. Alternatively, however, a number greater than 60 can be chosen for n. Each of the polarity reversal diodes D_B, D_D protects the corresponding transmitting stage 121B, 121D against a positive feedback on connection 44 (CAN-Supply) and a negative feedback on connection 43 (CAN_GND). Each of the polarity reversal diodes D_B, D_D can also be referred to as blocking diodes. Each of the repolarization diodes D_B, D_D can be a pn-based diode, which has a parasitic pn is the transition of a (silicon) transistor, which is fixed-wired, so that the transistor never is driven and the diode cannot be short-circuited / bridged. In the Particularly noteworthy is the forward voltage of each of the polarity reversal diodes D_B, D_D approximately 0.7 V. Each of the polarity reversal circuits D_A, D_C protects the corresponding transmitting stage. 121A, 121C against positive feedback on connection 44 (CAN-Supply) and a negative feedback on connection 43 (CAN_GND). Each of the Reversing polarity circuits D_A, D_C can also be referred to as blocking circuits. The first polarity reversal circuit D_A has a diode D1, a first transistor TR1, a second transistor TR2, a resistor R1 and optionally a capacitor C1. The diode D1 arises parasitically from transistor TR1. Transistor TR2 has its own parasitic _ 24 _ diode, which is not shown in Fig. 10. Transistors TR1 and TR2 are PMOS transistors. The anode of diode D1 is connected to the drain terminal of the first transistor TR1. The cathode of diode D1 is connected to the source terminal of the first transistor TR1 and with the source connection of the second transistor TR2. The The gate terminal of the first transistor TR1 is connected to the drain terminal of the second transistor TR2, with a connection of resistor R1, and with a connection of the optional capacitor C1. The other connection of resistor R1 is connected to ground, in particular terminal 44 (GND). Furthermore, the other is connection of the optional capacity C1 to ground, in particular connection 44 (GND), connected. The gate terminal of the second transistor TR2 is connected to the supply voltage VCC on terminal 43. Diode D1 is conducting in operation and is short-circuited using transistors TR1, TR2 and resistor R1, with In other words, bridged. As mentioned, the gate connection of the first transistor TR1 is to ground, in the In particular, connection 44 (GND) was made. As the source connection of the transistors TR1, TR2 voltage rises, in particular due to the power supply with VCC_min=3.0V, becomes the channel parallel to diode D1, i.e. across transistor TR1, conducting. As a result the forward voltage of diode D1 is omitted. With a power supply with VCC_min=3.0V under all circumstances under consideration, the levels according to Fig. 7 can be generated. Just as with the polarity reversal diodes D_B, D_D, the same applies to the polarity reversal circuit D_A feedback protection provided. As described, transistor TR2 is a PMOS- transistor. The transistor TR2 conducts when on its gate terminal, which with the connection 43 is connected, at least a threshold voltage below the potential at the source connection of transistor TR2 is present. If the voltage on the rises cathode of diode D1, which is equal to the potential of the source terminal of the second transistor TR2, with approximately a transistor threshold voltage above the voltage VCC on terminal 43, then transistor TR2 becomes conductive, the rises voltage on the gate of transistor TR1 and blocks transistor TR1. As a result of this, the parasitic diode D1 becomes effective. As a result, the feedback protection provided. _ 25 _ For this purpose, transistors TR1 and TR2 are designed in such a way that the the turn-on resistor value of the second transistor TR2 is much smaller than the resistance value of resistor R1. Therefore, it holds that: Ron_TR2 << R1. Optionally, the gate source paths of transistors TR1 and TR2 are filtered, in the special with an RC filter, which is formed by the resistor R1 and the capacitance C1. As a result, the polarity reversal circuit D_A is robust against pulse-like interference, in the special DPI, ISO pulses, etc. The second polarity reversal circuit D_C has a diode D2, a first transistor TR3, a second transistor TR4, a resistor R2 and optionally a capacitor C2. The diode D2 arises parasitically from transistor TR3. Transistor TR4 has its own parasitic diode, which is not shown in Fig. 10. Transistors TR3 and TR4 are PMOS transistors. The The anode of diode D2 is connected to the drain terminal of the first transistor. TR3. The cathode of diode D2 is connected to the source terminal of the first transistor TR3 and with the source connection of the second transistor TR4. The gate- The connection of the first transistor TR3 is connected to the drain connection of the second transistor TR4, with a connection of resistor R2 and with a connection of the optional capacitor C2. The other connection of resistor R2 is to ground, in particular connection 44 (GND), connected. Furthermore, the other connection of capacitor C2 to ground, in particular connection 44 (GND), connected. The gate terminal of the second transistor TR4 is connected to the supply voltage VCC on terminal 43. Diode D2 is conducting in operation and is with the aid of transistors TR3, TR4 and resistor R2 short-circuited, with other words bridged. As mentioned, the gate connection of the first transistor TR3 is to ground, in the in particular connection 44 (GND), installed. Increases the source connection of the transistors TR3, TR4 in voltage, in particular through the power supply with VCC_min=3.0V, then the channel parallel to diode D2, i.e. across transistor TR3, becomes conducting. As a result, the forward voltage of diode D2 is lost. In a power supply with VCC_min=3.0V the levels can be measured under all conceivable circumstances according Fig. 7 are generated. Just as with the polarity reversal diodes D_B, D_D, the same applies to the polarity reversal circuit D_C feedback protection provided. As described, transistor TR4 is a PMOS- _ 26 _ transistor. The transistor TR4 conducts when on its gate terminal, which with the connection 43 is connected, at least a threshold voltage below the potential at the source connection of transistor TR4 is present. If the voltage on the rises cathode of diode D2, which is equal to the potential of the source terminal of the second transistor TR4, with approximately a transistor threshold voltage above the voltage VCC on terminal 43, then transistor TR4 becomes conductive, the rises voltage on the gate of transistor TR3 and blocks transistor TR3. As a result of this, the parasitic diode D2 becomes effective. As a result, the feedback protection provided. For this purpose, transistors TR3 and TR4 are designed in such a way that the the turn-on resistor value of the second transistor TR4 is much smaller than the resistance value of resistor R3. Therefore, it holds that: Ron_TR4 << R2. Optionally, the gate source paths of transistors TR3 and TR4 are filtered, in the special with an RC filter, which is formed by the resistor R2 and the capacitance C2. As a result, the polarity reversal circuit D_C is robust against pulse-like interference, in the special DPI, ISO pulses, etc. Each of the parallel circuits 121A1, 12181, 121C1, 121D1, more specifically the associated control circuit T_A, T_B, T_C, T_D, sets a resistance value for the corresponding transmitter stage 121A, 121B, 121C, 121D depending on the operating mode (SLOW or SIC, FAST_TX) of transmitter module 121 and the transmission signal TxD. The resistance value of the individual transmitting stage 121A, 1218, 121C, 121D is therefore depending on the operating mode (SLOW or SIC, FAST_TX) of transmitter module 121 and the TXD transmission signal adjustable. This is described in more detail below based on of Fig. 11 and Fig. 12 as well as Table 2 and Table 3. Each of the transistors HVP_A, HVN_B, HVP_C, HVN_D is an HV cascode and can also be used as HV standoff device are indicated. The transistor HVP_A protects the CMOS- transistors P_A1 to P_An of the assigned parallel circuit 121A1, because the transistor HVP_A absorbs high voltage drops. Each of the transistors HVN_8, HVP_C, HVN_D has the same function for the CMOS transistors of the respective assigned parallel circuit 12181, 121C1, 121D1. Each of the transistors HVP_A, HVN_B, HVP_C, HVN_D is connected to terminal 125 with its control terminal. Thus, _ 27 _ each of the transistors HVP_A, HVN_B, HVP_C, HVN_D by at least one control 124 steerable. The current limiting modules 1211 and 1212 are each implemented as transistors. The Current limiting modules 1211, 1212 in the example of Fig. 10 are each CMOS transistors. The current limiting module 1211 in Fig. 10 is a PMOS transistor. Thus the current limiting module 1211 forms a current source. The Current limiting module 1212 in Fig. 10 is an NMOS transistor. Thus, the current limiting module 1212 a flow pit. The current limiting modules 1211, 1212 are intended for the protection of transmitter module 121 and the external components, in particular other components of participant station 10 and / or bus 40. The arrangement of current limiting modules 1211, 1212 in the circuit of transmitting stage 121 is suitable for the dom state 401 and for the SIC state 403 from Fig. 9. In the dom state, 401 flows twice according to design and specification. as much electric current as in the sic state, however the current flows in the dom- state 401 only over one path of transmitter module 121. In contrast, flows in the sic-state the current in two paths of transmitter module 121. The two paths are equal designed or configured. This results in the current limiting modules 1211, 1212 same voltage drop. With transmitter module 121, transmitter stage 121A is between connection 43 for the power supply and connection 41 (CANH) for the CAN_H signal switched. The transmitting stage 121C is between terminal 43 for the power supply and the connection 42 (CAN L) and connection 43 for ground respectively connection 44 (CAN_GND) switched. Transmitter stage 121D is between terminal 41 (CANH) for the signal CAN_H and connection 43 for ground and connection 44 respectively (CAN_GND) switched. Transmitter stage 1218 is between connection 42 (CANL) for the signal CAN_L and connection 43 for ground and connection 44 respectively (CAN_GND) switched. Thus, with transmitter module 121, on the one hand, the transmitter stage 121A is in the CANH path switched. On the other hand, transmitter stage 121D is switched in the CANH path. In The CANL path is connected to transmitting stage 121C on the one hand. On the other hand, transmitting stage 1218 is connected. switched in the CANL path. For example, transmitter module 121 in the CANH path and in the CANL path consists of a parallel connection 121A1, 12181, 121C1, 121D1 of a certain number of current stages. A single current stage is realized by a series connection consisting of a _ 28 _ CMOS switch and a resistor, as described earlier. The parallel connection of all current stages are in the CANH path and in the CANL path in series with an HV kascode HVP_A, HVN_B, HVP_C, HVN_D and a polarity reversal diode D_A, D_B, D_C, D_D connected, as described earlier. The HV cascades HVP_A, HVN_B, HVP_C, HVN_D make the Compliance with limit values ​​(maximum rating parameters) is possible, such as voltage on CANH and CANL -27V to +40V. The operation of the circuit in Fig. 10 depends on the operating mode of the transmitter module 121 and bus status 401 (dom), 403 (sic), 402 (rec) in SIC operating mode (arbitration phase 451) and L0, L1 in the data phase 452 is based on the following Table 2 explained. Table 2 shows, depending on the state of transmitter module 121 and the operating mode of phases 451, 452 the required impedance depending on the state of transmitter module 121 as well as the impedance of transmitter stages 121A / 121B and impedance of the transmitter stages 121C / 121D on. Operating mode of the CAN-FD, CAN-SIC, CAN-XL CAN-XL (xl_fasttx) transmitter module 121 (xl_sic) (Send- (Send operating mode in operating mode in arbitration phase 451) data phase 452) v (v) _ Required approximately about impedance in Not 120, ter 120, ter 120, ter ohm (0) between specified tuning infinite tuning min tuning min bus artery 41 ceerd with Zw of g with Zw g with Zw (CANH) and 42 41, 42 of 41, 42 of 41, 42 Æ (CANL Transmitter stairs CU 0- 121A / 121B: approximately approximately approximately Ê infinite infinite Typical values ​​30 120 60 in Ohm (Q) Transmitter stairs 121C / 121D: approximately approximately infinite infinite Typical values ​​120 60 in Ohm (Q _ 29 _ Resulting impedance in ohm (O) between about about _ _ about about bus core 41 60 120 instant 120 120 (CANH) and 42 (CANL) Table 2: Required impedance depending on transmit state If the impedance is "infinite", the transmitter module is 121 or the respective transmitter stage is 121A, 1218, 121C, 121D switched off or non-conducting. The division of each parallel circuit 121A1, 12181, 121C1, 121D1 of Fig. 10 into n parts or the n current stages makes a time-spaced and controlled Switching operation between bus states 401, 402, 403 in the arbitration phase (SIC- operating mode) 451 or bus states L0, L1 of data phase 452 possible. For this are the resistance values ​​of the resistors of the n current stages set, as illustrated in Fig. 11 in a specific example. Fig. 11 shows an example of the current level per switching stage or current stage Sl tot 512. In the example shown, therefore, twelve current stages become 51, SZ to 56 to 512 for each of the parallel circuits 121A1, 12181, 121C1, 121D1 is used. Thus, n holds = 12. The value of the current | (vertical axis in Fig. 10) or I1, I2, I6, I12 etc. is set by the selection of the series resistance value of the respective current stage 51 to 512. The individual current stages 51 to 512 (horizontal axis in Fig. 11) therefore have different resistance values. For generating bus statements 401, 402, 403 in the arbitration phase (SIC- operating mode) 451 or the bus states L0, L1 of data phase 452 become the separate current stages 51 to 512 using the CMOS transistors of the current stages Sl to 512 switched on or off in time. As a result, flows into the CANH path or CANL path, in which the overarching transmitting stage 121A, 1218, 121C, 121D is switched, a corresponding electric current I. _ 30 _ In general, it is advantageous to have the spread (stagger stages) and resistances per to design switching stage or current stage 51 to 512 such that the shape of the The differential signal VDIFF follows the Gaussian error function. With this, the analytical least emissions generated. For the transition from a state 402 (recessive) to a state 401 (dominant), which corresponds to a rising edge of the differential voltage VDIFF of Fig. 5, is by the time-shifted switching on of the resistors of the parallel connections 121A1, 12181, 121C1, 121D1 the current in the CANHpad and in the CANL path for generating a dominant level on bus 40 stepwise increased. The transition from a state 401 (dominant) to a state 402 (recessive), which corresponds to a falling edge of the differential voltage VDIFF of Fig. 5, takes place accordingly by the time-shifted switching off of the resistors of the parallel circuits 121A1, 12181, 121C1, 121D1, whereby the current in the CANH and CANL path is reduced in steps. The total current, which is given by the sum of the currents I1 to I12 or |1 to In of all flow stages 51 to Sn, flows during state 401 (dominant). Here are all current stages 51 to Sn of the parallel circuits 121A1, 12181, 121C1, 121D1 switched on and the total current for generating the dominant level of nominal VDIFF = 2V flows through the bus resistor or termination resistor 49. By the time setting and by the selection of the current levels of the individual current stages 51 to 512 by setting the resistance values ​​of their resistors, as described earlier, it is possible to the bus signals CAN_H, to align CAN_L at the transition between states 401 and 402, so that the symmetrical configuration of CAN_H and CAN_L according to Fig. 7, or for transmitter module 221 according to Fig. 4, is realized. The structure of transmitter module 121 makes a in the time-shifted switching on of the individual current stages of the Parallel connections 121A1, 12181, 121C1, 121D1 are possible. Due to this time control, it is possible to adjust the signal shape of CAN_H and CAN_L as required according to Fig. 7 or Fig. 9 or Fig. 4. It is possible to the signal curves for CAN_H and CAN_L to be shaped. Overall, the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 of the data phase 452 are formed depending on the specifications. _ 31 _ The resistances of the individual current stages Sl to Sn of the parallel connections 121A1, 12181, 121C1, 121D1 and thus their respective share in the Total current can be selected in various ways to achieve the lowest possible to achieve possible emission, in particular a low emission from transmitter module 121. It is advantageous for low emissions to at the beginning and the end of a switching operation between bus states 401, 402 low current I (high resistance value) to add or remove and in the middle of the shifting action a lot to add or remove current (low resistance value). Therefore, your Fig. 11 shown setting of the currents of the current stages Sl to 512 very advantageous. In contrast to a realization with identical resistances in current stages 51 to Sn of the parallel connections 121A1, 12181, 121C1, 121D1, avoids the configuration according to Fig. 10 a current increase during switching off, the transition of the state 401 (dominant) to state 402 (recessive). The granularity of the time distribution (staggering) for switching the on or off separate current stages 51 to 512 lie in a range of approximately 2 ns. Such small steps or steps for time dispersion cause little common mode malfunctions and have little negative impact on emissions. In addition, the voltage steps, which are across the resistors or resistance stages of the current stages S1, 52 to 56 to 512 are set, held and the time distribution varied, so that the behavior during the activation process is as gentle as possible arises (according to the Gaussian error function). The variation of the time steps or time stages moreover, prevents the occurrence of a narrowband frequency line in the radiation frequency spectrum. Alternatively, the spreading steps (staggering steps) can be performed over fixed time steps and varied tension steps. Due to the shown structure of transmitter module 121, symmetrical switching is enabled. of the bus signals CAN_H and CAN_L (Fig. 7 or 9 or 4) at steep switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or bus states L0, L1 of data phase 452 made possible. On the one hand, due to the shown structure of transmitter module 121 by the use of fast CIVIOS switches or CMOS transistors much steeper switching edges between _ 32 _ the bus statements 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus statements L0, L1 of data phase 452 is realized. On the other hand, during the switching operations necessary for compliance with the emission limit values Symmetry of the time course of the bus signals CAN_H and CAN_L achieved. A Matching of the characteristics is achieved by the choice of whether the use of the resistors from the parallel circuits 121A1, 12181, 121C1, 121D1. As a result, the matching of the characteristics is less dependent on parameters of the transistors used in the parallel circuits 121A1, 12181, 121C1, 121D1. The CMOS transistors of transmitting stages 121A1, 12181, 121C1, 121D1 are used as switches operated, i.e. with a maximum voltage between the gate terminal and The source connection. The matching of the individual transmitter stages 121A1, 12181, 121C1, 121D1 therefore depends mainly on the tuning (matching) of the resistors R_A1 to R_An, R_81 to R_Bn , R_C1 to R_Cn , R_D1 to R_Dn and no longer from transistors P_A1 to P_An and P_C1 to P_Cn (PMOS) to the bus wire 41 (CANH) and transistors N_D1 to N_Dn and N_Bl to N_Bn (NMOS) on the bus wire 42 (CANL). The dominant state 401 (dom) is determined by a matching of the resistors R_A1 to R_An (transmitter stage 121A) with the resistors R_81 to R_Bn (transmitter stage 1218). Here and also in the following, the term "tuning" means according to one possibility is an active trim step. According to another possibility, this means alignment so that the resistance values ​​match as closely as possible, which happens by default without an adjustment or trim step. The Sic state (sic) is determined by a matching of the resistors R_A1 to R_An (transmitter stage 121A) with resistors R_C1 to R_Cn (transmitter stage 121C) and matching of resistors R_D1 to R_Dn (transmitter stage 121D) with resistors R_81 to R_Bn (transmitter stage 1218). In XL-Fast operating mode, the LO state is determined by a tuning. (matching) of the resistors R_A1 to R_An (transmitter stage 121A) with the resistors R_81 to R_Bn (transmitter stage 1218). State L1 is determined by a tuning. (matching) of the resistors R_C1 to R_Cn (transmitter stage 121C) with the resistors R_D1 to R_Dn (transmitter stage 121D). _ 33 _ The turn-on resistor Ron of the respective transistors of the transmitter stages 121A1, 12181, 121C1, 121D1 must be significantly smaller than those connected in series. resistance of the individual current stages of the transmitting stages 121A1, 12181, 121C1, 121D1. Fig. 12 shows a specific example of the construction of transmitting stage 1218 from Fig. 10. Accordingly, the transmitting stage 1218 in the parallel circuit 12181 has three current stages S_I, S_II, S_III. The first current stage S_I has a resistor R_81_I and a series-connected transistor N_81_l. The second current stage 5_|I has a resistor R_81_Il and a series-connected transistor N_81_II. The third current stage 5_|I| has a resistor R_81_III and a series-connected transistor N_81_III. For the following description of the circuit in Fig. 10 with the configuration according to In Fig. 11, it is assumed that each of the transmitting stages 121A, 121C, 121D is also in their respective parallel connection 121A1, 121C1, 121D1 three current stages S_I, S_II, 5_|I| according to the example of Fig. 12 has. The following Table 3 shows the control of the three transistors N_81_|, N_81_II, N_81_l|l of the transmitting stage 1218 of Fig. 12 as well as the corresponding transistors of the transmitting stages 121A, 121C, 121D of Fig. 10, each dependent on the transmitting stages 121A / 1218 and the transmitter stages 121C, 121D. Operating mode CAN-FD, CAN-SIC, CAN-XL CAN-XL (xl_fasttx) of the (xl_sic) transmitter module (Transmitter- 121 (Send operating mode in operating mode in arbitration phase 451) data phase 452) 121A / 1218: Typical approximately approximately approximately __ __ __ infinite infinite Value in Ohm (O) 120 60 _ 34 _ _ Table 3: Required impedance depending on transmit state In this way, the required steeper flanks can be added to the bus signals CAN_H and CAN_L are generated and the emission limit values ​​can be complied with. Alternatively, more than three current stages in the respective transmitting stages can be 121A, 1218, 121C, 121D are used, as described earlier. Fig. 13 shows a transmitter module 1210 in a second configuration. The Transmitter module 1210 is constructed in many respects in the same way as the Transmitter module 121 according to the first embodiment. Therefore, only the differences with the first version described. Unlike the first version, the 1210 transmitter module has, according to the current implementation of transmitter stages 121A0, 12180, 121C0, 121D0. The transmitter stages 121A0, 12180, 121C0, 12100 are connected as a complete bridge. The termination resistor 49 is connected in the bridge branch between the connections for bus lines 41, 42. Moreover, the transmitter module has 1210, instead of the current limiting modules. 1211, 1212, a first to x-the current limiting module 1211_1 to 1211x and a first to x-th current limiting module 1212_1 to 1212_x . Here, x is a natural number > 1. The current limiting modules 1211_1 to 1211_x, 1212_1 to 1212_x are each as transistor-implemented. The current limiting modules 1211_1 to 1211_x, 1212_1 to 1212_x in the example of Fig. 13 are each CMOS transistors. The Current limiting modules 1211_1 to 1211_x in Fig. 13 are each a PMOS transistor. Thus, current limiting modules 1211_1 to 1211_x each constitute a current source. The Current limiting modules 1212_1 to 1212_x in Fig. 13 are each an NMOS transistor. Thus, current limiting modules 1212_1 to 1212_x each form a current well. In contrast to the transmitting stage 121A of the first embodiment, which the transistor HVP_A has, the transmitting stage 121A0 has a first to y-th transistor HVP_A1 to HVP_Ay, where y is a natural number > 1. Each of the first to y-th transistors _ 35 _ HVP_A1 to HVP_Ay is a CMOS transistor, specifically a PMOS transistor, such as previously described for the transistor HVP_A in connection with Fig. 10. In contrast to the transmitting stage 1218 of the first embodiment, which the transistor HVN_B has, the transmitting stage 12180 has a first to y-th transistor HVN_81 to HVN_By, where y is the natural number > 1. Each of the first to y-th transistors HVN_81 to HVN_By is a CMOS transistor, in particular an NMOS transistor, as previously described for transistor HVP_B in connection with Fig. 10. In contrast to the transmitting stage 121C of the first embodiment, which the transistor HVP_C has, the transmitting stage 121C0 has a first to yth transistor HVP_C1 to HVP_Cy, where y is the natural number > 1. Each of the first to y transistors HVP_C1 to HVP_Cy is a CMOS transistor, specifically a PMOS transistor, such as previously described for the transistor HVP_C in connection with Fig. 10. In contrast to the transmitting stage 121D of the first embodiment, which the transistor HVN_D has, the transmitting stage 121D0 has a first to y-th transistor HVN_D1 to HVN_Dy, where y is the natural number > 1. Each of the first to y-th transistors HVN_D1 to HVN_Dy is a CMOS transistor, in particular an NMOS transistor, as described earlier for the transistor HVP_D in connection with Fig. 10. In addition to the functions of transmitter module 121 according to the first version, the Transmitter module 1210 of Fig. 13 has the following functions. Due to its design, transmitter module 1210 is capable of effects resulting from to reduce asymmetric behavior of the transmitting stages, which in the transmitting states dom (401), sic (403), rec (402) can occur and increase the overshoot and thereby worsen the emission. Transmitter module 1210 prevents atypical behavior of components in the transmitting stages 121A0, 12180 (Effect 1) of the complete bridge of Fig. 13, so that in the dom state 401 a change of the common-mode voltage in comparison with rec state 402 is minimized or prevented. To prevent Effect 1, the resistance Ron (turn-on resistor) of the cascades is changeable in the transmitter stages 121A0, 12180, in particular by control with the respective control circuit T_A, T_B. This is done by a change of the transistors connected in parallel to y HVP_A1 to HVP_Ay and / or the transistors connected in parallel to y _ 36 _ switched transistors HVN_81 to HVN_By. To the symmetry of the two series connections of transmitter stages 121A0, 121D0 and transmitter stages 121C0, 12180 not to change in the SIC state 403, the cascades of the transmitting stages must also 121D0, 121C0 undergo the same change. Therefore, the ones to y also become parallel connected transistors HVN_D1 to HVP_Dy and / or the transistors connected to y in parallel transistors HVP_C1 to HVP_Cy modified accordingly. For this purpose, each of the transistors HVP_A1 to HVP_Ay, HVN_81 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVP_Dy is connected to its control terminal (gate connection) on connection 125. This is how it is each of these transistors controllable by at least one control unit 124. The intervention for the correction of the common-mode level in the dom state 401 happens through an equal or the same change from HVP_A1 to HVP_Ay and HVP_C1 to HVP_Cy or by an equal or the same change from HVP_D1 to HVN_Dy and HVP_Bl to HVN_By. Moreover, transmitter module 1210 can detect uneven behavior of components in transmitting stages 121AO / 121DO and 121C0 / 12180 of the entire bridge occur (Effect 2), such that in the sic state a change of the common-mode voltage in comparison with rec state 402 is minimized or prevented. For this, the resistance Ron (turn-on resistor) of the current limiting is used. transistors or current limiting modules 1211, 1212 changeable. This is done by the current limiting modules 1211_1 to 1211_x connected in parallel to x and / or the to x parallel connected current limiting modules 1212_1 to 1212_x , in the particular due to control by at least one control unit 124. The intervention for The correction of the common-mode level in the sic state 403 is performed by the up to x parallel connected current limiting modules 1211_1 to 1211_x or the to x parallel switched current limiting modules 1212_1 to 1212_x . For example, x = 4. In In this case, four different levels of the resistance Ron (turn-on resistor) can be used. of the current limiting transistors or current limiting modules 1211, 1212) be set. This prevention of Effect 2 is particularly advantageous, because only if, assuming the common-mode level of the rec-state 402, the common levels in the dom- state 401 and in the sic state 403 correspond to those of the rec state 402, a sufficient emission result can be achieved, but the causes leading to the Behavior leading to Effect 1 may be different from that leading to Effect 2. _ 37 _ The design of transmitter module 1210 prevents that in particular substrate current losses in the polarity reversal circuits D_A and D_C lead to the common-mode level in the dom state 401 is no longer correct. In the sic state are the polarity reversal circuit D_A and the polarity reversal diode D_B less strongly energized and moreover, both polarity reversal circuits are D_A, D_C and both polarity reversal diodes are D_B, D_D of the four transmitting stages 121A0, 12180, 121C0, 121D0 active. The transmitting module 1210 it can occur that there are different common-mode levels in the dumb state and in the SIC condition be present. Moreover, it can be prevented that qualitatively equal effects are generated by unequal behavior in the cadmium codes. As a result, transmitter module 1210 can monitor the effects on the emission values ​​of the transmitter- / receiving device 12 positively influence, which is mainly caused by the transmitting module 1210 will be affected. All previously described versions of transmitter module 121, 1210, the transmitter- / receiving facilities 12, 22, the participant stations 10, 20, 30, the bus system 1 and the method carried out therein according to the first and second implementation examples and Their modifications can be used individually or in all possible combinations. Moreover, the following modifications in particular are conceivable. The previously described bus system 1 according to the first and second An implementation example is described based on the CAN protocol. based bus system. Bus system 1 according to the first and / or second However, an implementation example can also be another type of communication network, where the signals are transmitted as differential signals. It is advantageous, but not necessary that, for bus system 1, at least for certain periods, a exclusive, collision-free access from a participant station 10, 20, 30 to bus 40 is guaranteed. Bus system 1 according to the first and / or second implementation example and their modifications are specifically a CAN bus system or a CAN-HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. The bus system 1 can, however, be another communication network, where the signals act as differential signals are transmitted serially over the bus. _ 38 _ For example, the functionality of the previously described implementation examples is applicable to transmitting / receiving devices 12, 22 which are in a CANbus system or a CAN-HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus systems can be used. It is possible that for the two bus states 401, 402, at least temporarily, there will be no dominant and recessive bus state is used, but instead a first bus state and a second bus state be used, both of which are powered An example An example of such a bus system is a CAN XL bus system. The number and arrangement of participant stations 10, 20, 30 in bus system 1 according to the first and second implementation examples and their modifications is arbitrary. In The particular thing is whether there are only participant stations 10 or only participant stations 30. present in bus systems 1 of the first or second implementation example. _ 39 _

Claims

1) Transmitter module (121; 1210) for transmitting differential signals in a serial bus system (1), with a first transmitting stage (121A; 121A0) for generating transmitting currents (I1 to In) for an initial signal (CAN_H), which goes to a bus (40) of the bus system (1) is to be transmitted, a second transmitting stage(121B; 12180) for generating transmit currents (|1 to In) for a second signal (CAN_L) that as a differential signal with respect to the first signal (CAN_H) to the bus (40) is to be sent, a third transmitting stage (121C; 121C0) for generating transmitting currents (I1 to In) for the first signal (CAN_H), and a fourth transmitting stage (121D; 121D0) for generating transmit currents (|1 to In) for the second signal (CAN_L) and where the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) are connected in a full bridge, where the first and fourth transmitting stages (121A, 121D; 121A0, 121D0) are connected in series and the third and second transmitting stage (121C, 1218; 121C0, 12180) are connected in series, where each of the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) comprises at least two current stages (51 to Sn), which parallel to are linked together, where each of the at least two current stages (51 to Sn) a switchable resistor (R_A1 to R_An; R_Bl to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) includes, where the switchable resistors (R_A1 to R_An; R_Bl to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of a transmitting stage (121A to 121D; 121A0 to 121D0) have different resistance values, where the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) each include a reverse polarity diode (D1; D_B; D2; D_D) for protection against a positive feedback in a connection (43) for the bus voltage supply and negative feedback from a connection (44) for mass, where the polarity reversal diode (D1; D2) of the first transmitting stage (121A; 121A0) and the third transmitting stage (121C; 121C0) each a switched reverse polarity diode (D1; D2) is, which can be bypassed or short-circuited, and _ 40 _ where the polarity reversal diode (D_B; D_D) of the second transmitting stage (1218; 12180) and the fourth transmitting stage (121D; 121D0) each a pn-based repolarization diode (D_B; D_D) is, which is a parasite of a transistor and fixed is wired so that the polarity reversal diode (D_B; D_D) is not bridged or short-circuited can be. 2) Transmitter module (121; 1210) according to claim 1, where the output connections (41, 42) of the entire bridge are provided for connection to a termination resistor (49) of the bus (40). 3) Transmitter module (121; 1210) according to one of the preceding claims, where the Reversing diodes (D1; D_B; D2; D_D) are configured for setting a bus intermediate voltage (Vcm) of approximately 1.9 V during operation of the transmitting module (121; 1210) with a voltage supply of approximately 3.3 V. 4) Transmitter module (121; 1210) according to one of the preceding claims, where the first transmitting stage (121A; 121A0) and the third transmitting stage (121C; 121C0) each comprise a reverse polarity circuit (D_A; D_C), which the repolarization diode (D1; D2), a first transistor (TR1; TR3), a second transistor (TR2; TR4) and a resistor (R1; R2) comprise, where the second transistor (TR2; TR4) has a turn-on resistor value has, which is much smaller than a resistance value of the resistor (R1; R2). 5) Transmitter module (121; 1210) according to claim 4, where the drain connection of the first transistor is (TR1; TR3) connected to the anode of the polarity reversal diode (D1; D2), where the source connections of the first and second transistor (TR1, TR2; TR3, TR4) are connected to the cathode of the polarity reversal diode (D1; D2), where the gate connection of the first transistor is (TR1; TR3) connected to the drain terminal of the second transistor (TR2; TR4) and via the resistor (R1; R2) with the connection (44) for ground, where the gate connection of the second transistor is (TR2; TR4) connected to the connection (43) for the bus power supply. _ 41 _ 6) Transmitter module (121; 1210) according to claim 4 or 5, where the path of gate- connection to source terminal of the first transistor (TR1; TR3) a filter (R1, C1; R2, C2) includes for protection against pulse-like disturbances. 7) Transmitter module (121; 1210) according to one of the preceding claims, where a number n of the at least two current stages (51 to Sn) for each of the first to fourth transmitting stage (121A to 121D; 121A0 to 121D0) is the same, where n is a natural number greater than 1. 8) Transmitter module (121; 1210) according to one of the preceding claims, where each of the at least two current stages (51 to Sn) a CMOS transistor comprises for switching the resistor (R_A1 to R_An; R_Bl to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the current stage (51 to Sn). 9) Transmitter module (121; 1210) according to one of the preceding claims, where the CMOS transistor of the current stages (51 to Sn) of the first transmitting stage (121A; 121A0) is a PMOS transistor, where the CMOS transistor of the current stages (51 to Sn) of the second transmitting stage (1218; 12180) is an NlVIOS transistor, where the CMOS transistor of the current stages (51 to Sn) of the third transmitting stage (121C; 121C0) is a PMOS transistor, and where the CMOS transistor of the current stages (51 to Sn) of the fourth transmitting stage (121D; 121D0) is an NMOS transistor. 10) Transmitter module (121; 1210) according to one of claims 8 or 9, where each of the first to fourth transmitting stage (121A to 121D; 121A0 to 121D0) moreover at at least one cash code (HVP_A; HVN_8; HVP_C; HVN_D) for the protection of the CMOS transistors. 11) Transmitter module (1210) according to claim 10, where at least two cash codes (HVP_A; HVN_B; HVP_C; HVN_D) are connected in parallel, where a number y of the cascade codes (HVP_A; HVN_B; HVP_C; HVN_D) for each of the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) is the same, where y is a natural number greater than 1, and _ 42 _ where the switching resistance of at least two cascades (HVP_A; HVN_B; HVP_C; HVN_D) is different. 12) Transmitter module (121; 1210) according to one of the preceding claims, moreover with at least one first current limiting module (1211) as a current source, which between the connection (43) for the bus voltage supply and the entire bridge is connected, and at least one second current limiting module (1212) as a flow well, which is connected between the ground connection (44) and the entire bridge. 13) Transmitter module (1210) according to claim 12, where at least two primary current limiting modules (1211_1 to 1211_x) are connected in parallel, of which the switching resistor is different, where at least two second current limiting modules (1212_1 up to 1211_x) are connected in parallel, of which the switching resistor is different, and where the number x of the first current limiting modules (1211_1 up to 1211_x) is equal to the number x of the second current limiting modules (1212_1 to 1211_x), where x is a natural number greater than 1. 14) Transmitter module (121; 1210) according to one of the preceding claims, moreover with a control circuit (T_A; T_B; T_C; T_D) for controlling switchable components of the first to fourth transmitting stage (121A to 121D; 121A0 to 121D0) dependent on a digital transmission signal (TxD) and on a for the transmitter module (121; 1210) set operating mode (SIC; FAST_TX). 15) Transmitter module (121; 1210) according to claim 14, where the control circuit (T_A; T_B; T_C; T_D) is configured for the time-spread and controlled switching the resistance values ​​of at least two current stages (51 to Sn). 16) Transmitter / receiver (12; 22) for a participant station (20) for a serial bus system (1), with a transmitting module (121; 1210) according to one of the preceding claims, and _ 43 _ a receiving module (122) for receiving signals from the bus (40). 17) Participant station (10; 20; 30) for a serial bus system (1), with a transmitting / receiving device (12; 22) according to claim 16, and a communication control device (11; 21) for controlling the communication in the bus system (1) and for generating a digital transmission signal (TxD) for controlling the first to fourth transmission stages (121A to 121D;121A0 to 121D0). 18) Participant status (10; 20; 30) according to claim 17, where the participant station (10; 20; 30) is configured for communication in a bus system (1) in which at least temporarily an exclusive, collision-free access from a participating station (10, 20, 30) to the bus (40) of the bus system (1) is guaranteed. 19) Method for transmitting differential signals in a serial bus system (1), where the method is carried out with a transmitting module (121; 1210), and where the method includes the steps, generating, with a first transmitting stage (121A; 121A0), of transmitting currents (l1 to In) for an initial signal (CAN_H), which to a bus (40) of the bus system (1) is to be transmitted, generating, with a second transmitting stage (1218; 12180), transmitting currents (I1 to In) for a second signal (CAN_L) that acts as a differential signal relative to the first signal (CAN_H) to be sent to the bus (40), generate, with a third transmitting stage(121C;121C0), of transmitting currents (|1 until In) for the first signal (CAN_H), and generate, with a fourth transmitting stage (121D; 121D0) of transmitting currents (I1 until In) for the second signal (CAN_L), where the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) are connected in a full bridge, where the first and fourth transmitting stages (121A, 121D; 121A0, 121D0) are connected in series and the third and second transmitting stage (121C, 1218; 121C0, 12180) are connected in series, where each of the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) comprises at least two current stages (51 to Sn), which parallel to are linked together, _ 44 _ where each of the at least two current stages (51 to Sn) a switchable resistor (R_A1 to R_An; R_81 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) includes, where the switchable resistors (R_A1 to R_An; R_81 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of a transmitting stage (121A to 121D; 121A0 to 121D0) have different resistance values, where the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) use a polarity reversal diode (D1; D_B; D2; D_D) in each for protection against a positive feedback in a connection (43) for the bus voltage supply and negative feedback from a connection (44) for mass, where the polarity reversal diode (D1; D2) of the first transmitting stage (121A; 121A0) and the third transmitting stage (121C; 121C0) each a switched reverse polarity diode (D1; D2) is, which can be bypassed or short-circuited, and where the polarity reversal diode (D_B; D_D) of the second transmitting stage (1218; 12180) and the fourth transmitting stage (121D; 121D0) each a pn-based repolarization diode (D_B; D_D) is, which is a parasite of a transistor and fixed is wired so that the polarity reversal diode (D_B; D_D) is not bridged or short-circuited can be.

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