Method of synchronizing an internal clock signal of a target device
NL2040240B1Active Publication Date: 2026-07-08NEXPERIA BV
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Patent Information
- Authority / Receiving Office
- NL · NL
- Patent Type
- Patents
- Current Assignee / Owner
- NEXPERIA BV
- Filing Date
- 2025-04-23
- Publication Date
- 2026-07-08
Abstract
According to a first example of the disclosure, a method of synchronizing an internal clock signal of a target device is disclosed. The target device (slave) comprising an internal clock signal source (typically an oscillator). The internal clock signal of a target device is synchronized with an external clock signal provided by a controller device (master) comprising an external clock signal source in a serial bus network. The serial bus network comprises the controller device communicatively connected with the least one target device. The method according to this example of the disclosure comprises the following steps: a. receiving the external clock signal by the target device provided by the controller device; b. generating a clock gating signal based on the external clock signal and measuring the internal clock signal frequency by counting the internal clock signal pulses received during duration of the clock gating signal. C. calculating a relative frequency value of the external clock signal to the internal clock signal. The relative frequency measurement is over a certain amount of clock pulses from the external communication signal. Certain means here, that the count of clock cycles must be high enough to guarantee a good accuracy of the relative frequency measurement. d. calculating a tuning word value using the relative frequency value or incrementally change the internal clock value. Figure 1
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