RFID demodulator and RFID modulation pulse shaping circuit

Abstract

The RFID demodulator has an input signal terminal (RF) connected via an input resistor (Rin) to the gate of the first transistor (T1). Its drain is connected to the supply voltage source (HRV), and its source is simultaneously connected to the circuit ground (GND) via a time constant resistor (Rt) and to the gate of the second transistor (T2). The second transistor (T2) has its source connected to the circuit ground (GND), and its drain is simultaneously connected to the supply voltage source (HRV) via a second resistor (R2) and to the first demodulator output (STR) via a pulse shaper (SH1). The drain of the second transistor (T2) is also connected to the second demodulator output (END) via a differentiator amplifier (WR), and then via a second pulse shaper (SH2). The differentiator amplifier (WR) contains an inverter (R3, T3) and a high-pass RC filter formed by a capacitance (Chp) and two resistors (R3, Rhp).

Description

[0001] RFID demodulator and RFID modulation pulse shaping circuit

[0002] The invention concerns an RFID demodulator and an RFID modulation pulse shaping circuit intended especially for NFC tags.

[0003] From the Chinese invention CN111181498A, there is known an RFID demodulator. The invention discloses a metal oxide thin film transistor ASK demodulation circuit and a chip, and the circuit comprises a rectifier which is used for recognizing an ASK signal envelope and supplying power to a post-stage circuit, a low-pass filter, which is used for carrying out low-pass filtering on the signal output by the rectifier, a zero threshold comparator, which is used for amplifying the signal output by the low-pass filter, and an output buffer for driving a load according to an output signal of the zero threshold comparator, wherein the post-stage circuit comprises a low-pass filter, a zero threshold comparator and an output buffer; the low-pass filter is an RC filter comprising a third capacitor and a resistor unit; and the resistor unit is composed of two transistors stacked in opposite directions. The RC filter is formed by manufacturing a large resistor unit on a small area through two reversely stacked transistors, so an ASK demodulation circuit manufactured by using a metal oxide thin film transistor is realized. The method can be widely applied to the ASK chip technology.

[0004] In the state of the art, e.g., from the publication Yueh-Hua Yu, Yuan- Jiang Lee, Yu- Hsuan Li, Chung-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu, Yi-Jan Emery Chen, „An LTPS TFT Demodulator for RFID Tags Embeddable on Panel Displays”, IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 5, pp. 1356-1361, May 2009, DOI: 10.1109 / TMTT.2009.2017312, an RFID demodulator is known. This paper presents an amplitude-shift-keying (ASK) demodulator for RF identification tags, which can be embedded on panel displays. The ASK demodulator was implemented in 3- / m low- temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) technology. Since the threshold voltages of LTPS TFTs are higher than CMOS transistors, the conventional demodulator implementation will degrade the demodulator sensitivity significantly. The novel full-wave demodulator circuit was proposed to resolve the issue of high threshold voltage and reduce the ripples of the demodulated envelope. Operated at 8 V, the demodulator consumes 1.6 mW of power. The input carrier frequency was tested up to 13.56 MHz, and the highest ASK modulated data rate is 100 kb / s. The circuit size of the LTPS TFT demodulator is 500 z / m times 450 z / m.

[0005] From the American invention US3522454A, there is known a modulation pulse shaping circuit comprising (a) a series connection extending from a first voltage supply terminal through the current electrodes of a first MOS transistor, then through the current electrodes of a second MOS transistor and then through a load resistance to a second voltage supply terminal; (b) a timing branch including a series circuit of a capacitance and a resistance and extending from the junction between said second MOS transistor and said load resistance to said second supply terminal; (c) the gate of said first MOS transistor being connected to the junction between said capacitance and resistance of said timing branch; (d) means for supplying to the gate of said first MOS transistor a clamping potential within the oncondition of said first MOS transistor, said means being such as to limit the difference between said clamping potential and the threshold potential at said gate to a value small in comparison with the voltage across said first and second supply terminals; (e) input means connected to the gate of said second MOS, transistor; and (f) output means connected to the junction between said first and said second MOS transistors.

[0006] It is known from the German invention DE2620187A1, a monostable multivibrator circuit with a capacitor, a charging arrangement for charging the capacitor, an input arrangement for controlling the charging arrangement in dependence on an input signal and with an output arrangement for generating an output pulse, characterized in that the charging arrangement contains a first, second and third field effect transistor, that the first and second field effect transistor are each connected in series with their source-drain path and form a path between two terminals of an energy source, that the gate and drain electrodes of the first two transistors are connected to one another, that the gate electrode of the third field effect transistor is connected to a point in said path, that the first and second field effect transistor are each connected with their source-drain path between the first terminal of the energy source and a first terminal of the capacitor, that said input device is connected to a second terminal of the capacitor, that the output device is connected to the first terminal of the capacitor, and that the circuit is constructed such that during operation in response to an input signal applied to said input device an output pulse is generated in the output device and that the source-drain path of the third transistor supplies a substantially constant current whereby the charging of the capacitor begins and that the output pulse is terminated when the voltage across the capacitor reaches a predetermined value.

[0007] In the state-of-the-art, especially in electronics engineering, there are known (remote) radio-frequency identification (RFID) systems, and in particular near-field communication (NFC). There are known in the art field-effect transistors (FETs) with an insulated gate, thin- film transistors (TFTs), as well as transistors based on indium-gallium zinc oxide (IGZO or InGaZnO - from: indium (In), gallium (Ga), zinc (Zn), oxygen (O)). It is also known that the designation of the drain and source of these transistors is conventional, because due to the symmetrical structure of the transistor, changing these designations does not affect the functionality of the transistor or the circuit in which it is located; however, this nomenclature is of an ordering nature.

[0008] The aim of the invention is to create a demodulator compliant with the NFC standard, together with a pulse shaping circuit for the demodulator, which will solve the implementation problem in the technology of flexible integrated circuits, with relatively low power demand, small circuit area and low sensitivity to supply voltage disturbances.

[0009] In a demodulator containing transistors of one type, according to the invention, the input signal terminal is connected to the gate of a first transistor, whose drain is connected to a supply voltage source, and the source is connected to the circuit ground through a time constant resistor and to the gate of a second transistor, whose source is connected to the circuit ground, and the drain is connected to the supply voltage source through a second resistor (R2) and to the first output of the demodulator.

[0010] The effect of such a construction is that the signal at the input signal terminal is initially suppressed by the gate-source capacitance of the first transistor and the RC circuit formed by the parallel connection of the time constant resistor, and the gate-source capacitance of the second transistor.

[0011] Advantageously, the input signal terminal is connected to the gate of the first transistor through an input resistor. As a result, the RF signal is initially additionally attenuated by the RC circuit formed by the input resistor and the gate-source capacitance of the first transistor.

[0012] Advantageously, the drain of the second transistor is connected to the first output of the demodulator through a pulse shaping circuit. For that reason, the signal is shaped for use by subsequent digital circuits.

[0013] Advantageously, the drain of the second transistor is connected to the control output of the demodulator. This makes it possible to monitor the original signal before it was shaped.

[0014] Advantageously, the drain of the second transistor is connected to the second output of the demodulator through a delay circuit or a differentiating amplifier. By the use of the delay circuit, the signal at the second output of the demodulator is delayed in permanent and defined way in relation to the signal at the first output of the demodulator. On the other hand, by the use of the differentiating amplifier, the signal passes through a high-pass RC filter.

[0015] Advantageously, the delay circuit comprises a cascade of inverters connected between its input and its output. This makes it possible to set a specific delay between the demodulator outputs.

[0016] Advantageously, the differentiating amplifier comprises two transistors, two resistors and a capacitor, wherein the gate of the first transistor of the differentiating amplifier constitutes its input, the source of this transistor is connected to the circuit ground, and its drain is connected to the supply voltage source through the first resistor of the differentiating amplifier and to the output of the amplifier through the capacitor, where the capacitor and the output of the amplifier are also connected to the circuit ground through the second resistor of the amplifier, which is connected in parallel to the second transistor of the amplifier, the gate of which is connected to the circuit ground. The effect of such a differentiating amplifier is an amplifying-inverting circuit constructed from the first transistor of the amplifier and the first resistor of the amplifier, as well as the differentiating circuit constructed from the amplifier capacitor, the second resistor of the amplifier, and the diode in the form of the second transistor of the amplifier.

[0017] Advantageously, the delay circuit or the differentiating amplifier is connected to the second output of the demodulator through a pulse shaping circuit. For that reason, the signal is shaped for the purpose of subsequent digital circuits.

[0018] Advantageously, the RFID carrier frequency divider operates substantially at a frequency of 13.56 MHz of the input signal. For that reason, it is possible to use the circuit to implement the NFC standard.

[0019] Advantageously, the supply of the circuit is the voltage derived from harvesting the radio signal. The voltage from the harvesting of a radio signal is usually a voltage far from the ideal supply voltage because the carrier frequency signal disturbs it, and its amplitude can vary depending on the distance between the antenna and the source, the received modulation, and the modulation performed. Therefore, the system must be immune to such interferences and disturbances.

[0020] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0021] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow to manufacture cheap and / or flexible integrated circuits.

[0022] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0023] Advantageously, the transistors contain indium-gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0024] Advantageously, the channel width of the second transistor ranges from 20 to 50 micrometers, while the resistance of the time constant resistor ranges from 1 to 5 megaohms. The large width of the second transistor determines the large gate-source capacitance, which cooperates with the resistance of the resistor connected between the gate and the source of the transistor.

[0025] Advantageously, the differentiating amplifier time constant, being the product of the value of the second amplifier resistor and the value of the amplifier capacitor, ranges from 0.5 to 2 microseconds. The high-pass RC filter formed of capacitance and resistance achieves the best timing parameters.

[0026] In an RFID modulation pulse shaping circuit having an input connected to the gate of a first transistor, whose drain is connected to the supply voltage source of the circuit through a first resistor, and the drain is connected to a capacitor, according to the invention, the source of the first transistor is connected to the circuit ground, the drain of the first transistor is connected to the circuit ground through a second transistor, and the drain of the first transistor is connected to the gate of a third transistor through the capacitor. The gate of the third transistor is also connected to the supply voltage source through a second resistor, the source of the third transistor is connected to the circuit ground, and the drain of the third transistor is connected to the supply voltage source through a third resistor and to the gate of a fourth transistor. The source of the fourth transistor is connected to the circuit ground, and its drain is connected to the source of the supply voltage of the circuit through a fourth resistor and to an output terminal. The gate of the fourth transistor is also connected to the gate of the second transistor, the gate of the third transistor is also connected to the reference voltage terminal through a limiting diode formed of a transistor, whose gate is connected to its source and the gate of the third transistor.

[0027] The effect of such a construction is the ability to adjust the output signal parameters to the requirements of digital circuits connected to the outputs of the pulse shaping circuits. In this circuit, the first transistor and resistor form an amplifying-inverting circuit, so as the third transistor, and the resistor, the fourth transistor, and an additional resistor. On the other hand, the capacitor and the second resistor, with the reference voltage and the limiting diode, form the pulse width regulation circuit. Advantageously, the first resistor is connected to the supply voltage source of the circuit through a diode formed of a transistor, whose gate is connected to the supply voltage source of the circuit, furthermore, the node connecting the first resistor with this diode is also connected to the circuit ground through a filtering capacitor. This allows the transistor drain voltage levels to be immune to supply voltage fluctuations at the terminal.

[0028] Advantageously, the gate of the third transistor is connected to the ground of the circuit through a diode or a cascade of diodes. For that reason, the process of recharging the capacitance connected to the diodes always starts from the same voltage level, helping to reduce the fluctuations in the width of the generated pulses.

[0029] Advantageously, the drain of the fourth transistor is connected to the output terminal through a buffer containing two additional transistors of the circuit, the fifth and the sixth, and a fifth resistor, wherein the drain of the fourth transistor is connected to the gate of the sixth transistor, whose source is connected to the ground of the circuit, and the drain is connected to the output and to the supply voltage source of the circuit through a parallelly connected the fifth resistor and the fifth transistor, whose gate is connected to the gate of the fourth transistor. Due to the fact that the last two transistors are connected to the supply voltage, the ground and that their operation is mutual, a high slew rate of the output pulse is achieved.

[0030] Advantageously, the supply of the circuit is the voltage derived from harvesting the radio signal. The voltage from the harvesting of a radio signal is usually a voltage far from the ideal supply voltage because the carrier frequency signal disturbs it, and its amplitude can vary depending on the distance between the antenna and the source, the received modulation, and the modulation performed. Therefore, the system must be immune to such interferences and disturbances.

[0031] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0032] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow to manufacture cheap and / or flexible integrated circuits.

[0033] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0034] Advantageously, the transistors contain indium-gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0035] Advantageously, the capacitance of the capacitor ranges from 200 to 800 femtofarads and the value of the second resistor ranges from 5 to 20 megaohms. This ensures the subcircuit pulse lengths depend solely on the time constant resulting from the capacitance and resistance values, and the output pulses are therefore immune to changes in the radio field strength.

[0036] Advantageously, the diode cascade consists of exactly two diodes connected in series, implemented using two transistors, which have their gates connected to their sources. For that reason, the initial voltage at the terminal of the capacitor connected to the diode cascade, connected to the gate of the third transistor of the circuit, at the moment of initialization of the shaping circuit is shifted down approximately three times of the threshold voltage of the third transistor gate of the circuit. This has a direct effect on the width of the pulses generated by the circuit.

[0037] The invention has been described below in detail, with reference to the attached figures. Fig. 1 presents a schematic diagram of an RFID demodulator with a delay circuit, Fig. 2 presents a schematic diagram of an RFID demodulator with a differential amplifier, and Fig. 3 - a schematic diagram of a modulation pulse shaping circuit.

[0038] RFID demodulator in the embodiment shown in Fig. 1 comprises two transistors T1 and T2, three resistors Rin, Rt and R2, a delay circuit UO, two pulse shaping circuits SHI and SH2, one input signal terminal RF, three output terminals ENV, STR and END, as well as a supply voltage terminal HRV and circuit ground gnd.

[0039] The input signal terminal RF is connected to the gate of the first transistor T1 via the input resistor Rin. The drain of the first transistor T1 is connected to the supply voltage source HRV, and the transistor source is connected to the circuit ground gnd via the time constant resistor Rt and to the gate of the second transistor T2. The source of the second transistor T2 is connected to the circuit ground gnd, and the transistor drain is connected to the supply voltage source HRV via the second resistor R2 and to the first output of the demodulator STR via the pulse shaping circuit SHI. Furthermore, the drain of the second transistor T2 is also connected to the control output ENV. The drain of the second transistor T2 is also connected to the second output END of the demodulator via the delay circuit UO and then via the second pulse shaping circuit SH2.

[0040] The delay circuit UO can be implemented in a simple way by a cascade of inverters, which will add a constant delay between the first STR and the second END output of the demodulator. A simple implementation of an inverter requires only one resistor and one transistor.

[0041] RFID demodulator in the embodiment shown in Fig. 2 is substantially the same as the demodulator in the embodiment of Fig. 1, with the difference that instead of the delay circuit UO, a differentiating amplifier WR is used, which comprises two transistors T3 and T4, two resistors R3 and Rhp, and a capacitor Chp.

[0042] The gate of the first transistor T3 of the amplifier constitutes its input, the source of this transistor is connected to the circuit ground gnd, and its drain is connected to the source of the supply voltage HRV through the first resistor of the amplifier R3 and to the output of the amplifier through the capacitor Chp. The capacitor Chp and the output of the amplifier are also connected to the circuit ground gnd through the second resistor Rhp of the amplifier connected in parallel with the second transistor of the amplifier T4. The gate of the second transistor of the amplifier T4 is connected to the circuit ground gnd.

[0043] In the presented circuits of demodulators, the RF signal is initially attenuated by an RC circuit formed by the Rin resistor, gate-source capacitance of the T1 transistor and a parallel connection of the Rt resistor and gate-source capacitance of the T2 transistor. The gate-source capacitance of the T2 transistor is intentionally designed to be high, and the way to achieve this is the large width of the channel of the a-IGZO TFT transistor, which was set to 35 pm with the minimum allowed channel length of the transistor - 0.8 pm. This leads to a high momentary transconductance of the T2 transistor (high gain) and proper filtering of the carrier frequency. Transistor T1 acts as a voltage follower, which operates in the saturation region for the upper halves of a sine-wave signal at RF and falls into the cut-off region for the lower halves. The gate-source capacitance of T2 transistor together with the Rt resistance are responsible for the discharge constant necessary to obtain the AM envelope of the signal at RF, which can be observed at the control output ENV. This binary signal is passed to the next subcircuit - to a symbol detector.

[0044] Each time a carrier reappears at RF, a short positive pulse at ENV is generated from the drain of the transistor T2. These pulses are used to generate a signal at END, which is crucial for the timing of the entire RFID tag. In addition, another analog circuit in the tag requires short pulses to appear at STR each time OOK (on-off keying) modulation starts and the carrier disappears at RF. The AM demodulator generates pulses at END after a specified time from the appearance of the signal at STR. These signals are necessary to properly initialize the symbol detector circuit between consecutive OOK modulations.

[0045] In order to increase the slew rate of the envelope edges, the signal at ENV, which comes from the drain of the transistor T2, reaches the gate of the second stage transistor T3 and finally goes through the high-pass RC filter formed by the capacitance Chp, and resistances R3 and Rhp This way a short positive pulse is generated each time a carrier reappears at RF. In this case, the AM demodulator generates pulses at END of 2 ps duration each time the modulation level of the NFC reader reaches approximately 0%.

[0046] RFID modulation pulse shaping circuit in the embodiment shown in Fig. 3 comprises six transistors T5, T6, T7, T8, T9 and T10, four diodes made of transistors Tdl, Td2, Td3 and Tl, five resistors R5, Rec, R7, R8 and RIO, two capacitors Cb and Cec, an input terminal IN, an output terminal OUT, a supply voltage terminal HRV, a reference voltage terminal REF and ground gnd.

[0047] The input of the circuit IN is connected to the gate of the first circuit transistor T5, whose source is connected to the circuit ground gnd. The drain of the first circuit transistor T5 is connected to the circuit supply voltage source HRV through the first circuit resistor R5 and then through a diode in the form of transistor Tdl, whose gate is connected to the supply voltage source of the circuit. The drain of the first circuit transistor T5 is also connected to the ground gnd through the second circuit transistor T6 and to the gate of the third circuit transistor T7 through the capacitor Cec. The node connecting the first circuit resistor R5 with the diode in the form of transistor Tdl is also connected to the circuit ground gnd through the filtering capacitor Cb.

[0048] The gate of the third transistor T7 of the circuit is also connected to the supply voltage source HRV through the second resistor Rec of the circuit. The source of the third circuit transistor T7 is connected to the circuit ground gnd, and the drain of the third circuit transistor T7 is connected to the supply voltage source HRV through the third circuit resistor R7 and to the gate of the fourth circuit transistor T8. The source of the fourth circuit transistor T8 is connected to the ground gnd, and the drain is connected to the supply voltage source HRV through the fourth circuit resistor R8 and to the output terminal of the circuit OUT. Furthermore, the gate of the fourth circuit transistor T8 is also connected to the gate of the second circuit transistor T6. The gate of the third circuit transistor T7 is also connected to the reference voltage terminal REF through a limiting diode in the form of a transistor Tl, which gate is connected to its source, and therefore to the gate of the third circuit transistor T7. The gate of the third circuit transistor T7 is also connected to the circuit ground gnd via a cascade of diodes in the form of transistors Td2 and Td3, which have their gates connected to their sources.

[0049] The drain of the fourth circuit transistor T8 is connected to the circuit output terminal OUT through a buffer comprising the fifth circuit transistor T9 and the sixth circuit transistor T10 as well as the fifth circuit resistor RIO. The drain of the fourth circuit transistor T8 is connected to the gate of the sixth circuit transistor T10. The source of the sixth circuit transistor T10 is connected to the circuit ground gnd. The drain of the sixth circuit transistor T10 is connected to the circuit output OUT and to the supply voltage source HRV through the fifth circuit resistor RIO connected in parallel with the fifth circuit transistor T9. The gate of the fifth circuit transistor T9 is connected to the gate of the fourth circuit transistor T8.

[0050] In order to generate both signals at the outputs END and STR, the modulation pulse shaping subcircuit is used, which has a slight resemblance to a modified Eccles-Jordan monostable circuit. The modulation pulse shaping circuits SHI and SH2 are triggered by positive pulses on the gate of T5 transistor. The R5 resistor at the drain of T5 and the first stage of the circuit (i.e., T6 transistor) are supplied by the filtering capacitor Cb and Tdl transistor (operating as a diode). This way, the drain voltage levels at T5 and T6 are immune to fluctuations in the supply voltage at the HRV terminal. Therefore, the pulses’ lengths of the subcircuits depend solely on the time constant resulting from the values of Cec and Rec, and thus the pulses at END and STR are immune to changes in electromagnetic field. In order to ensure stable Cec charging conditions, the maximum gate voltages at the second stage of the subcircuit (i.e., T7 transistor) are limited by a sum of internal tag reference voltage at REF (which is 1. 1 V) and the threshold voltage of transistor T1 (acting as a diode limiting the Cec voltage). In order to maintain a high slew-rate of the pulses at the STR and END, the second stage of the subcircuit is buffered by an RTL (resistor-transistor logic) inverter using T8 transistor and R8 resistor and the push-pull operation of the T9 and T10 transistors.

[0051] The invention allows for demodulation of the RF signal carrier wave, providing the ability to receive communication from the transmitter. It also allows for shaping pulses from the RF signal carrier wave demodulator, in particular in NFC RFID tags, providing the ability to work with digital tag circuits. The industrial application of the invention is in the industry and market of products requiring individual electronic markings.

Claims

Claims1. An RFID demodulator having an input signal terminal (RF), containing transistors of one type, characterized in that the input signal terminal (RF) is connected to the gate of a first transistor (Tl), whose drain is connected to a supply voltage source (HRV), and the source is connected to the circuit ground (gnd) through a time constant resistor (Rt) and to the gate of a second transistor (T2), whose source is connected to the circuit ground (gnd), and the drain is connected to the supply voltage source (HRV) through a second resistor (R2) and to the first output of the demodulator (STR).

2. The RFID demodulator according to claim 1, characterized in that the input signal terminal (RF) is connected to the gate of the first transistor (Tl) through an input resistor (Rin).

3. The RFID demodulator according to claim 1 or 2, characterized in that the drain of the second transistor (T2) is connected to the first output of the demodulator (STR) through a pulse shaping circuit (SHI).

4. The RFID demodulator according to claim 1 or 2 or 3, characterized in that the drain of the second transistor (T2) is connected to the control output of the demodulator (ENV).

5. The RFID demodulator according to any of the claims from 1 to 4, characterized in that the drain of the second transistor (T2) is connected to the second output of the demodulator (END) through a delay circuit (UO) or a differentiating amplifier (WR).

6. The RFID demodulator according to claim 5, characterized in that the delay circuit (UO) comprises a cascade of inverters connected between its input and its output.

7. The RFID demodulator according to claim 5, characterized in that the differentiating amplifier (WR) comprises two transistors (T3, T4), two resistors (R3, Rhp) and a capacitor (Chp), wherein the gate of the first transistor of the differentiating amplifier (T3) constitutes its input, the source of this transistor is connected to the circuit ground (gnd), and its drain is connected to the supply voltage source (HRV) through the first resistor of the differentiating amplifier (R3) and to the output of the amplifier through the capacitor (Chp), where the capacitor and the output of the amplifier are also connected to the circuit ground (gnd) through the second resistor (Rhp) of the amplifier, which isconnected in parallel to the second transistor of the amplifier (T4), the gate of which is connected to the circuit ground (gnd).

8. The RFID demodulator according to claim 5 or 6 or 7, characterized in that the delay circuit (UO) or the differentiating amplifier (WR) is connected to the second output of the demodulator (END) through a pulse shaping circuit (SH2).

9. The RFID demodulator according to any of the claims from 1 to 8, characterized in that it operates substantially at a frequency of 13.56 MHz of the input signal.

10. The RFID demodulator according to any of the claims from 1 to 9, characterized in that the supply of the circuit is the voltage derived from harvesting the radio signal.

11. The RFID demodulator according to any of the claims from 1 to 10, characterized in that all transistors in the circuit are the FETs of "n" type.

12. The RFID demodulator according to any of the claims from 1 to 11, characterized in that all transistors in the circuit are TFT-type transistors.

13. The RFID demodulator according to any of the claims from 1 to 12, characterized in that the transistor channels are made of amorphous semiconductor material.

14. The RFID demodulator according to any of the claims from 1 to 13, characterized in that the transistors contain indium-gallium zinc oxide.

15. The RFID demodulator according to any of the claims from 1 to 14, characterized in that the channel width of the second transistor (T2) ranges from 20 to 50 micrometers, while the resistance of the time constant resistor (Rt) ranges from 1 to 5 megaohms.

16. The RFID demodulator according to any of the claims from 7 to 15, characterized in that the differentiating amplifier (WR) time constant, being the product of the value of the second amplifier resistor (Rhp) and the value of the amplifier capacitor (Chp), ranges from 0.5 to 2 microseconds.

17. An RFID modulation pulse shaping circuit having an input (IN) connected to the gate of a first transistor (T5), whose drain is connected to the supply voltage source of the circuit (HRV) through a first resistor (R5), and the drain is connected to a capacitor (Cec), characterized in that the source of the first transistor (T5) is connected to the circuit ground (gnd), the drain of the first transistor (T5) is connected to the circuit ground (gnd) through a second transistor (T6), and through the capacitor (Cec) the drain of the first transistor (T5) is also connected to the gate of a third transistor (T7), wherein the gate of the third transistor (T7) is also connected to the supply voltage source (HRV) through a second resistor (Rec), the source of the third transistor (T7) is connected to the circuit ground (gnd), and the drain of the third transistor (T7) is connected to the supply voltage source (HRV) through a third resistor (R7) and to the gate of a fourth transistor (T8), which has the source connected to the circuit ground (gnd), and its drain is connected to the source of the supply voltage of the circuit (HRV) through a fourth resistor (R8) and to an output terminal (OUT), moreover, the gate of the fourth transistor (T8) is also connected to the gate of the second transistor (T6), the gate of the third transistor (T7) is also connected to the reference voltage terminal (REF) through a limiting diode formed of atransistor (Tl), whose gate is connected to its source and to the gate of the third transistor (T7).

18. The RFID modulation pulse shaping circuit according to claim 17, characterized in that the first resistor (R5) is connected to the supply voltage source of the circuit (HRV) through a diode formed of a transistor (Tdl), whose gate is connected to the supply voltage source of the circuit (HRV), furthermore, the node connecting the first resistor (R5) with this diode is also connected to the circuit ground (gnd) through a filtering capacitor (Cb).

19. The RFID modulation pulse shaping circuit according to claim 17 or 18, characterized in that the gate of the third transistor (T7) is connected to the ground of the circuit (gnd) through a diode or a cascade of diodes (Td2, Td3).

20. The RFID modulation pulse shaping circuit according to claim 17 or 18 or 19, characterized in that the drain of the fourth transistor (T8) is connected to the output terminal (OUT) through a buffer containing two additional transistors of the circuit, the fifth (T9) and the sixth (T10), and a fifth resistor (RIO), wherein the drain of the fourth transistor (T8) is connected to the gate of the sixth transistor (T10), whose source is connected to the ground of the circuit (gnd), and the drain is connected to the output (OUR) and to the supply voltage source of the circuit (HRV) through a parallelly connected the fifth resistor (RIO) and the fifth transistor (T9), whose gate is connected to the gate of the fourth transistor (T8).

21. The RFID modulation pulse shaping circuit according to any of the claims from 17 to20, characterized in that the supply of the circuit is the voltage derived from harvesting the radio signal.

22. The RFID modulation pulse shaping circuit according to any of the claims from 17 to21, characterized in that all transistors in the circuit are the FETs of "n" type.

23. The RFID modulation pulse shaping circuit according to any of the claims from 17 to22, characterized in that all transistors in the circuit are TFT-type transistors.

24. The RFID modulation pulse shaping circuit according to any of the claims from 17 to23, characterized in that the transistor channels are made of amorphous semiconductor material.

25. The RFID modulation pulse shaping circuit according to any of the claims from 17 to24, characterized in that the transistors contain indium-gallium zinc oxide.

26. The RFID modulation pulse shaping circuit according to any of the claims from 17 to25, characterized in that the capacitance of the capacitor (Cec) ranges from 200 to 800 femtofarads and the value of the second resistor (Rec) ranges from 5 to 20 megaohms.

27. The RFID modulation pulse shaping circuit according to any of the claims from 19 to26, characterized in that the diode cascade consists of exactly two diodes connected in series, implemented using two transistors (Td2, Td3), which have their gates connected to their sources.