RFID carrier frequency divider and bistable flip-flop

Abstract

An RFID carrier frequency divider having at least two flip-flops (D1, D2, D3, D4) with differential inputs and differential outputs connected in series such that the outputs of the previous flip-flop in series (D1, D2, D3) are connected sequentially to the inputs of the next flip-flop in series (D2, D3, D4). In this divider, the input terminal (RF) is connected simultaneously to the non-inverted input of the first flip-flop (D1) and, via a phase inverting circuit (Ri, Ti), to the non-inverted input of the first flip-flop (D1), and at least one output of the last flip-flop in series (D4) is connected to the divider output. The input terminal of the divider (RF) is connected to the non-inverted input of the first flip-flop (D1) via a coupling capacitor (C1). The non-inverted input of the first flip-flop (D1) is connected to the circuit ground (gnd) via a resistor (R1).The non-negated input of the first flip-flop (D1) is connected to the supply voltage source (HRV) via at least one diode (Td1a, Td1b) and to the circuit ground (gnd) via at least one diode (Td1c). Between at least two subsequent flip-flops (D1, D2), the outputs of the preceding flip-flop (D1) are connected to the input of the following flip-flop (D2) via forming resistors (Rf1, Rf2) and a pair of two series-connected inverters (Ri1, Ti1) and (Ri3, Ti3) and (Ri2, Ti2) and (Ri4, Ti4).

Description

[0001] RFID carrier frequency divider and bistable

[0002] The invention concerns an RFID carrier frequency divider intended especially for NFC circuits and a master-slave type bistable flip-flop intended especially for frequency dividers used in NFC RFID tags.

[0003] In the state of the art, e.g., from the publication Meister, T., Ishida, K., Sou, A., Carta, C., & Ellinger, F. „3.93-MHz / 328-pW dynamic frequency divider in flexible a-IGZO TFT technology”, IEEE Solid-State Circuits Letters, 3, pp. 134-137, 2020, DOI: 10.1109 / LSSC.2020.3008027, an RFID carrier frequency divider is known. The implementation of a dynamic frequency divider in a fully flexible amorphous indium- gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology on a sub-15 pm polyimide substrate is presented. This frequency divider is regenerative and is also known as a Miller divider. In this letter, it is implemented using only a Gilbert cell with minimumsize LO transistors. The publication shows that the presented circuit is more energy efficient than previous work in similar technologies and that it can be used as a fourth and later frequency divider stage in a 13.56 MHz RFID or NFC tag.

[0004] From the American invention US2009289671 Al, there is known a frequency divider circuit comprising a plurality of T flip-flops, a first transmission gate, a second transmission gate and an inverter. The plurality of T flip-flops is connected in series. The output of the inverter is connected to a clock input of a first T flip-flop. The first transmission gate connects a clock signal and the other clock input of the first T flip-flop and the input of the inverter. The second transmission gate connects the inverted signal of the clock signal and the output of the first transmission gate. In this solution, the input signals are differentially connected to the inputs of the flip-flops - a simple CLK input and a negated CLK input.

[0005] From the German invention DEI 02004009283 Al, there is known a bistable flipflop circuit, in which the switching between the master and slave blocks is not carried out by switching the respective current sources on and off in the actual sense, but rather by impressing a switching compensation current. The compensation current compensates for the current of those current sources whose associated differential or holding stage is deactivated. The proposed principle makes it possible to reduce the supply voltage and at the same time, due to the low parasitic capacitances of the circuit, to create a frequency divider for the gigahertz range that can be fully integrated into MOS circuit technology.

[0006] In particular, the flip-flop circuit known from this invention has two pairs of differential circuits in which MOS transistors of the same type have sources connected and whose drains are connected to the supply voltage through resistors, where the gates of the transistors are connected to the drains of complementary transistors in a pair, and whose gates are connected mutually to the drains of successive transistors in another pair. The flipflop also has a third and fourth pair of transistors in which MOS transistors of the same type are connected by sources and whose drains are connected respectively to the drains of the transistors of the first two pairs. Moreover, the gates of the transistors of the third pair are connected respectively to the drains of the transistors of the fourth pair, and the gates of the transistors of the fourth pair are connected in reverse order to the drains of the transistors of the third pair.

[0007] From the Japanese invention JPH0730381A, there is known a master-slave type bistable flip-flop. The purpose of an invention is to obtain the master-slave type flip-flop which can be increased in maximum toggle frequency while suppressing an increase in layout area and an increase in power consumption. Constitution: the master-slave type flipflop has a master-side latch circuit equipped with plural FETs, a slave-side latch circuit, and a buffer circuit. The gate width of FETs constituting the master-side latch circuit, slave-side latch circuit, and buffer circuit is so determined that the master-side latch circuit's fan-out number becomes equal to the master-side latch circuit's fan-out number.

[0008] In the state-of-the-art, especially in electronics engineering, there are known (remote) radio-frequency identification (RFID) systems, and in particular near-field communication (NFC). There are known in the art field-effect transistors (FETs) with an insulated gate, thin-film transistors (TFTs), as well as transistors based on indium-gallium zinc oxide (IGZO or InGaZnO - from: indium (In), gallium (Ga), zinc (Zn), oxygen (O)). It is also known that the designation of the drain and source of these transistors is conventional, because due to the symmetrical structure of the transistor, changing these designations does not affect the functionality of the transistor or the circuit in which it is located; however, this nomenclature is of an ordering nature.

[0009] The aim of the invention is to create a fast divider, including a bistable, which will solve the problem of too slow operation of a-IGZO TFT technology for RFID and NFC purposes, with relatively low power consumption, small circuit area, and low sensitivity to supply voltage disturbances.

[0010] In an RFID carrier frequency divider having at least two flip-flops with differential inputs and differential outputs connected in a cascade so that the outputs of the previous flip-flop in the cascade are connected respectively to the inputs of the next flip-flop in the cascade, in which divider the input terminal is connected simultaneously to the non-inverted input of the first flip-flop and through a phase inverting circuit to the inverted input of the first flip-flop, and at least one output of the last flip-flop in the cascade is connected to the output of the divider, according to the invention, the input terminal of the divider is connected to the non-inverted input of the first flip-flop through a coupling capacitor, and that the non-inverted input of the first flip-flop is connected to the ground of the circuit through a resistor. Moreover, according to the invention, the non-inverted input of the first flip-flop is connected to the supply voltage source through at least one diode, and that the non-inverted input of the first flip-flop is connected to the ground of the circuit through at least one diode.

[0011] The technical advantage of this circuit is to condition the RF input signal for the needs of the frequency divider. By using the diodes, the RF signal level is limited to a level acceptable by the first stage of the divider, and by the use of the capacitance and resistance, an additional RF voltage offset is obtained, which has a positive effect on the switching speed of the first stage of the divider.

[0012] Advantageously, at least the first flip-flop has an additional charge injection input, which is connected to the input terminal of the divider through a coupling capacitor and to the circuit ground through a resistor. The charge injection input is connected to the supply voltage source through at least one diode and is connected to the circuit ground through at least one diode. The technical advantage of this circuit is to condition the RF input signal for the purpose of charge injection into the first stage of the divider. The diodes limit the RF signal to an acceptable level, and the capacitance and resistance ensure an additional RF voltage offset.

[0013] Advantageously, between at least two subsequent flip-flops, the non-inverted output of the preceding flip-flop is connected to the non-inverted input of the following flipflop through two serially-connected inverters, and the inverted output of the preceding flipflop is connected to the inverted input of the following flip-flop through two other serially- connected inverters. By the use of inverters connected in sequence, the outputs of the preceding flip-flop are not significantly loaded, and the signals are amplified.

[0014] Advantageously, the non-inverted output of the preceding flip-flop is connected to the input of the inverter through a forming resistor, and the inverted output of the preceding flip-flop is connected to the input of the inverter through another forming resistor. For that reason, the phase of the differential signal is aligned to maximize the peak-to-peak voltage.

[0015] Advantageously, at least one flip-flop is a D-type flip-flop. This allows for an easy and cost-effective implementation of a differential flip-flop.

[0016] Advantageously, the RFID carrier frequency divider operates substantially at a frequency of 13.56 MHz of the input signal. For that reason, it is possible to use the circuit to implement the NFC standard.

[0017] Advantageously, the supply of the circuit is the voltage derived from harvesting the radio signal. The voltage from the harvesting of a radio signal is usually a voltage far from the ideal supply voltage because the carrier frequency signal disturbs it, and its amplitude can vary depending on the distance between the antenna and the source, the received modulation, and the modulation performed. Therefore, the system must be immune to such interferences and disturbances.

[0018] Advantageously, the outputs of the last flip-flop in the cascade are connected to the divider output through a desymmetrization circuit. This ensures a high fan-out of the divider output and a proper slew rate of the clock signal in the entire NFC tag.

[0019] Advantageously, the desymmetrization circuit comprises two transistors connected in series between a supply voltage and ground in such a way that the first transistor has its drain connected to the supply voltage, its gate connected to the non-inverted output of the flip-flop, and the source connected to the drain of a second transistor, while the second transistor has its gate connected to the inverted output of the flip-flop and the source connected to the ground. This ensures identical rise and fall times of the signal edges at the divider output while maintaining minimal energy losses. Advantageously, at least one flip-flop has a state-setting signal input connected to an external terminal. This makes it possible to adjust the clock phase of the divider output signal to the subsequent tag circuits.

[0020] Advantageously, at least one diode is made from a transistor by connecting its gate to the source. This makes using a common technological process for active and passive elements possible.

[0021] Advantageously, at least one inverter is made in the RTL technique, in which a resistor is connected between the supply voltage and the drain of the transistor, the source of the transistor is connected to the ground, the gate of the transistor is the input of the inverter, and the drain of the transistor is the output of the inverter. This design of the inverters allows for relatively low input capacitance, and it is possible to shape the transient characteristic of the inverter easily.

[0022] Advantageously, the divider is built of a cascade of 4 flip-flops. This makes it possible to divide the carrier wave frequency by 16, the fundamental operating frequency for many NFC tag subcircuits.

[0023] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0024] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow to manufacture cheap and / or flexible integrated circuits.

[0025] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0026] Advantageously, the transistors contain indium-gallium zinc oxide. Using indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0027] In a bistable having a first pair of transistors and a second pair of transistors, wherein the drains of the transistors are connected to a supply voltage terminal through resistors, in which pairs the transistors sources are connected to each other, and each transistor gate is connected to the drain of the other transistor in the pair, and having a third pair of transistors and a fourth pair of transistors, wherein the transistors sources in the pairs are connected to each other, and the connected sources are connected to the drains of clock transistors in such way that the sources of the third pair of transistors are connected to a clock transistor, which gate is connected to the non-inverted input terminal, and the sources of the fourth pair of transistors are connected to the clock transistor, which gate is connected to the inverted input terminal, wherein the drains of the transistors of the third pair are connected respectively to the drains of the transistors of the first pair, and the drains of the transistors of the fourth pair are connected respectively to the drains of the transistors of the second pair, while the gates of the transistors of the third pair are connected respectively to the drains of the transistors of the fourth pair, and the gates of the transistors of the fourth pair are connected in reverse order to the drains of the transistors of the third pair, where the non-inverted output terminal is connected to the drain of the second transistor of the fourth pair, and the inverted output terminal is connected to the drain of the first transistor of the fourth pair, according to the invention, the transistors sources of the first and second pair are connected to the circuit ground, and in that the sources of the clock transistors are connected to the circuit ground, and in that the charge injection terminal is connected to the drain of the second clock transistor.

[0028] The technical advantage of this circuit is that the flip-flop is two-stage, differential, D-type and does not require additional subcircuits, and as result, it has a minimal number of components; it is also fast and energy-efficient. Moreover, the possibility of charge injection allows for obtaining an additional speed boost of the circuit.

[0029] Advantageously, the bistable is equipped with a control input set terminal, which is connected to the gates of two transistors, the sources of which are connected to the circuit ground, and the drain of the first transistor is connected to the drain of the first transistor of the fourth pair, while the drain of the second transistor is connected to the drain of the first transistor of the third pair. This makes it possible to pre-set the logical value of the flip-flop.

[0030] Advantageously, the bistable operates substantially at a frequency of 13.56 MHz of the input signal. For that reason, it is possible to use the circuit to implement the NFC standard.

[0031] Advantageously, the supply of the circuit is the voltage derived from harvesting the radio signal. The voltage from the harvesting of a radio signal is usually a voltage far from the ideal supply voltage because the carrier frequency signal disturbs it, and its amplitude can vary depending on the distance between the antenna and the source, the received modulation, and the modulation performed. Therefore, the system must be immune to such interferences and disturbances.

[0032] Advantageously, all transistors in the circuit are the FETs of "n" type. The use of one type of FETs with insulated gates simplifies the technological process of implementing a circuit.

[0033] Advantageously, all transistors in the circuit are TFT-type transistors. TFTs allow to manufacture cheap and / or flexible integrated circuits.

[0034] Advantageously, the transistor channels are made of amorphous semiconductor material. The use of amorphous semiconductor material ensures low cost of manufacturing transistors (at relatively low temperatures).

[0035] Advantageously, the transistors contain indium-gallium zinc oxide. The use of indium gallium zinc oxide (IGZO) provides a relatively high carrier mobility parameter.

[0036] Advantageously, the transistors of the first and second pairs are the same with respect to the ratio of the channel width to the length, and in that the transistors of the third pair are the same with respect to the ratio of the channel width to the length, with this ratio being from 2 to 4 times greater with respect to the transistors of the first two pairs, and in that the transistors of the fourth pair are the same with respect to the ratio of the channel width to the length, with this ratio being from 1.5 to 2.5 times greater with respect to the transistors of the first two pairs, and in that the clock transistors have a ratio of the channel width to the length 3 to 5 times greater with respect to the transistors of the first two pairs. Such ratios of the transistor dimensions ensure that the settling and holding times for writing data to the master and slave sections are minimized. Furthermore, the quiescent power of the flip-flop is low.

[0037] The invention has been described below in detail, with reference to the attached figures. Fig. 1 presents a schematic diagram of a carrier frequency divider, Fig. 2 presents a schematic diagram of a carrier frequency divider with a low load-driving circuit for the first stage, and Fig. 3 - a schematic diagram of a bistable.

[0038] RFID carrier frequency divider in the embodiment shown in Fig. 1 comprises four D-type flip-flops: DI, D2, D3, and D4, with differential inputs and differential outputs connected in a cascade so that the outputs of the previous flip-flop in the cascade DI, D2, and D3 are connected respectively to the inputs of the next flip-flop in the cascade D2, D3, and D4. The first flip-flop in the cascade DI has an additional charge injection input (CI), and the remaining three flip-flops have state setting signal inputs (Set) connected to their corresponding external terminals S2, S3, S4. The divider has an RF input terminal connected simultaneously to the non-inverted input of the first flip-flop DI and the inverted input of the first flip-flop DI via a phase inverting circuit in the form of an inverter Ri and Ti. The divider input terminal RF is connected to the non-inverted input of the first flip-flop DI via a coupling capacitor Cl. The non-inverted input of the first flip-flop DI is connected to the ground of the circuit gnd via resistor Rl. The non-inverted input of the first flip-flop DI is connected to the supply voltage source HRV via two diodes connected in-series implemented using transistors Tdla and Tdlb, which have their gates connected to their sources. The non-inverted input of the first flip-flop DI is connected to the ground of the circuit gnd via a diode in the form of transistor Tdlc, which has its gate connected to the source. The additional charge injection input of the first flip-flop DI is connected to the input terminal RF of the divider via coupling capacitor C2 and to the ground of the circuit gnd via resistor R2. The charge injection input is also connected to the supply voltage source HRV via two diodes connected in series implemented using transistors Td2a and Td2b, which have their gates connected to the sources, and to the ground of the circuit gnd via a diode in the form of transistor Td2c, which has its gate connected to the source. The outputs of the last flip-flop D4 are connected to the output of the divider CLK via a desymmetrization circuit, which has two transistors connected in cascade between the supply voltage HRV and the ground gnd. The drain of the first transistor Tbl is connected to the supply voltage HRV, the gate is connected to the non-inverted output of the flip-flop D4, and the source is connected to the drain of the second transistor Tb2. The gate of the second transistor Tb2 is connected to the inverted output of the flip-flop D4, and the source is connected to the ground gnd.

[0039] The RFID carrier frequency divider in the embodiment shown in Fig. 2 is similar to the divider shown in Fig. 1; however, it has been expanded with an edge-shaping circuit connected between the first two flip-flops, DI and D2. The non-inverted output of the first flip-flop DI is connected to the non-inverted input of the second flip-flop D2 via a forming resistor Rfl and two serially-connected inverters Ril and Til as well as Ri3 and Ti3, while the inverted output of the first flip-flop DI is connected to the negated input of the second flip-flop D2 via a second forming resistor Rf2 and two further serially-connected inverters Ri2 and Ti2 as well as Ri4 and Ti4.

[0040] The frequency divider is one of the crucial components of an RFID tag, especially NFC Type-1, as it must operate at a carrier frequency of 13.56 MHz, and it provides the time base for many subcircuits of the tag - for example, a symbol detector, which requires a signal CLK at the frequency of the input signal RF divided by 16. To comply with the NFC standard recommendation for the time between the end of the last reader command frame and the beginning of the first tag response frame, the counter is preset on the first pulse with a fixed three-bit value - three zeros. This way, the entire tag adjusts its timing to meet the timing constraint. The digital subsystems of the tag use only two clock domains, whose frequencies are a divisor of the input frequency by 16 and 64, respectively, with most of the logic in the second domain to save area and power. The frequency divider is therefore responsible for the clock signal of the entire NFC tag chip. The main difficulty in its construction results from the fundamental limitations of an IGZO transistor, namely its electron mobility and cutoff frequency. Transistors with a relatively high width-to-length W / L ratios and low-value drain resistors should be used to obtain drain currents sufficient to reach the carrier frequency. However, the increase in width causes an increase in the gatesource capacitance of the transistors, which in turn is proportional to the increase in the drain current. Therefore, transistors with a higher W / L ratio, together with parasitics, increase the circuit dynamic power dissipation, which should be as small as possible. For this reason, the divider consists of four single-bit counter stages, with different transistor sizes and operating currents, resulting from the operating frequency of each stage.

[0041] Each divider stage contains a D-flip-flop with a differential primary-secondary loop. Therefore, the first stage, operating at the input frequency, requires an additional carrier signal inverter Ti and Ri, since the signal from the antenna is single-ended. To increase the maximum positive driving voltage of the RF signal applied to the transistor gates of the first stage, we shifted the signal offset using NMOS diodes Tdla, Tdlb, and Tdlc and the coupling capacitor Cl with resistor Rl. This way, the clock inverter transistor Ti together with the first-stage flip-flop transistors DI, at the non-inverted clock input of the first stage, enter a deep inversion much faster, allowing the operation at the NFC carrier frequency with relatively low average power dissipated. Moreover, each divider stage is implemented according to its requirements, i.e., it uses transistors of different sizes.

[0042] The main differences between the first stage of the divider DI and the remaining stages D2, D2, and D4 are the additional charge injection mechanism CI and the routing topography of the integrated circuit minimizing parasitic capacitances. The first stage DI uses the upper metallization layers to minimize parasitic capacitances at the intersections of lower metallization paths. The charge injection mechanism CI utilizes additional C2 and R2 elements to increase the slew rate of the inverted RF input signal. Each divider stage is implemented according to its requirements, i.e., it uses transistors of different sizes.

[0043] The gate of the inverter transistor Ti and the inputs of the non-inverted first flip-flop DI (and therefore the driven transistor in the flip-flop) are driven directly from the RF antenna (with additional Cl coupling), which provides higher currents responsible for the charge flow of their gate-source capacitances, in opposite to the gate-source capacitance of the input transistor of the flip-flop at the inverted input, which is driven indirectly by the inverter Ri and Ti. To speed up the switching of the first stage DI, the C2 capacitor is used, injecting additional charge into the gate-source capacitance of the corresponding transistors in the first stage during the falling edge of the RF signal via the additional input CI.

[0044] The use of diodes in the form of transistors Tdla, Tdlb and Tdlc as well as Td2a, Td2b and Td2c limits the maximum peak value of the RF signal and creates a constant voltage shift that reduces the turn-on times of the transistors located at the inputs of the first- stage flip-flop DI. Nevertheless, the use of an additional capacitance C2 compensates for the capacitive nature of the drain load of the transistor located at the negated input of the first flip-flop and thus accelerates its switching process.

[0045] The first divider stage, the DI flip-flop, has to provide a high-speed operation at the RF carrier frequency, and therefore this stage is not designed to efficiently drive large capacitive loads with a slew rate of half the carrier frequency. For this reason, the RTL buffering and phase-regulating stage is essential, amplifying and maximizing the instantaneous differential voltage at the input of the second stage D2.

[0046] Both the inverted nQ and non-inverted Q outputs of first stage DI are then buffered by pairs of cascaded resistor-transistor logic (RTL) inverters Til and Ril, Ti3 and Ri3, as well as Til and Til, Ti4 and Ti4, and passed to the symmetrical clock input of second stage D2. Moreover, resistors Rfl and Rfl equalize the phase of differential signals to maximize the peak-to-peak voltage of the inverted and non-inverted clock signals at a frequency divided by two.

[0047] The three further divider stages D2, D3 and D4 are of identical architecture and allow for a preload of the divider with logical values, using terminals S2, S3, S4, to adjust subsequent devices' CLK output clock timing phase. To optimize the energy consumption of the entire divider, the W / L ratio of the transistors and their corresponding drain resistors vary with the stage number (and the resulting frequency at which the stage must operate). The frequency divider output is buffered by the de-symmetrizer Tbl and Tb2 to ensure high fan-out of the divider output and an proper slew-rate of the clock signal across the NFC tag.

[0048] Bistable in the embodiment shown in Fig. 3 comprises the first two pairs of transistors T2 and T3 as well as T7 and T8 connected by the drains to the HRV supply terminal through resistors Rl, R2, R3 and R4. The transistors in the pairs are connected by the sources T2 and T3, as well as T7 and T8, which are connected to the ground gnd. Each transistor gate is connected to the drain of the other transistor in a given pair. The flip-flop also has the following two pairs of transistors T1 and T4 as well as T6 and T9, where the transistors in the pairs are connected to each other by the sources, and the sources are connected to the drains of clock transistors T5 and T10, which sources are connected to the ground gnd. The gate of the first clock transistor T5 is connected to the non-inverted CLK input terminal of the flip-flop, and the gate of the second T10 to the inverted nCLK input terminal. The drains of the third pair of transistors T1 and T4 are connected respectively to the drains of the first pair of transistors T2 and T3. The drains of the fourth pair of transistors T6 and T9 are connected to the drains of the second pair of transistors T7 and T8, respectively. The gates of the third pair of transistors T1 and T4 are connected respectively to the drains of the fourth pair of transistors T6 and T9, and the gates of the fourth pair of transistors T6 and T9 are connected in reverse order to the drains of the third pair of transistors T1 and T4. The non-inverted Q output terminal of the flip-flop is connected to the drain of the second transistor of the fourth pair T9, and the inverted nQ output terminal is connected to the drain of the first transistor of the fourth pair T6. The charge injection terminal CI is connected to the second clock transistor T10 drain. The flip-flop is also equipped with a control input set terminal Set, which is connected to the gates of two transistors, Tsl and Ts2, whose sources are connected to the ground of the circuit, and the drain of the first transistor, Tsl is connected to the drain of the first transistor of the fourth pair T6, while the drain of the second transistor Ts2 is connected to the drain of the first transistor of the third pair Tl.

[0049] Although the overall design of the flip-flop is similar to the subsequent divider stages to which the flip-flop is dedicated, each divider stage is implemented according to its requirements, i.e., it uses different sizes of transistors - for example, different sizes of transistors T2, T3, T7, T8 to hold (within the positive feedback loop) and switch logical states (transistors Tl, T4, T6, T9) during active clock edges. The use of the minimum allowed transistor sizes (W = 5 pm, L = 0.8 pm) in the feedback loops of the flip-flop and larger sizes of transistors (W > 8 pm, L = 0.8 pm) for dynamic data switching minimizes the static power consumption of the entire divider.

[0050] Furthermore, depending on whether the flip-flop is used as the first or subsequent stage, the main differences are the additional charge injection mechanism CI and the integrated circuit topography minimizing parasitic capacitances. The first, fastest stage uses the upper metallization layers to minimize parasitic capacitances at the intersections of the metallization paths of the lower layers. In the case when the flip-flop is used as the first stage, the gate of transistor T5 of the non-negated input CLK will be driven directly from the radio antenna, which provides higher instantaneous currents responsible for the flow of charge in their gate-source capacitances, in contrast to the gate-source capacitance of transistor T10 at the negated input nCLK, which must be driven indirectly by the inverting circuit. To speed up the switching of this transistor T10 through the CI input, an additional charge is injected into the gate-source capacitances of transistors T6 and T9 during the falling edge of the radio signal.

[0051] A logical one on the CLK clock pulls down the sources of transistors Tl and T4, bringing Tl to the triode region of operation, causing the rapid voltage drop on Tl, causing the cut-off of T3 and and the initiation of the switching process in the pair of T2-T3 transistors. The beginning of the T2-T3 switching process is visible when the drain voltage of transistor T3 begins to rise, and the positive feedback loop tends to overdrive the gate of T2, accelerating the cut-off of T3. This process remains uninterrupted till the adjacent logical one is at the non-negated input of the CLK clock. However, the opposite situation, i.e., a logical ‘ 1’ at the inverted input of the nCLK clock, pulls down the sources of T6 and T9, and eventually turns on T6 due to a recent toggle at the T3 drain. The whole switching process repeats every half period of the carrier wave.

[0052] Due to the relatively high gate-source capacitances of T6 and T9 transistors forming a load of the drain of the T10 transistor and the presence of its gate-drain capacitance, a compensation mechanism with the use of the CI input is proposed. Each time the clock forces the rising slope at the gate of T10, and the drain of T10 pulls down the capacitances of T6 and T9, the falling edge at the radio signal is present. Therefore, it is recommended to use an additional capacitance between the radio signal and the CI input to compensate for the capacitive nature of the drain load of T10 and, therefore, to accelerate the switching process of T10.

[0053] It should also be noted that the slave block of the flip-flop, i.e., T7-T8, is designed to operate at the carrier frequency with minimal power dissipation. Therefore, the outputs of the entire master-slave flip-flop, i.e. Q and nQ, (i.e. drains of T8 and T7) of the first divider stage are not intended to effectively drive high capacitive loads with the slew-rate corresponding to half of the carrier frequency. For this reason, using these outputs at the boundary frequencies of the circuit may require additional amplification of the signals.

[0054] Using the Set input allows for the initial preload of the logical value of the flip-flop, which, with many stages of this type in the frequency divider, allows for adjusting the phase of the divider's clock signal. It is also possible to optimize power consumption depending on the frequency at which a given stage (flip-flop) must operate. This is done by selecting the W / L ratio of the transistors and their corresponding drain resistors.

[0055] The invention allows for obtaining a clock signal from a radio signal for the entire RFID circuit and tag subcircuits using slow transistors of one type - in particular, a technological process using a-IGZO TFT. The industrial application of the invention is in the industry and the market of products requiring individual electronic markings.

Claims

Claims1. An RFID carrier frequency divider having at least two flip-flops (DI, D2, D3, D4) with differential inputs and differential outputs connected in a cascade so that the outputs of the previous flip-flop in the cascade (DI, D2, D3) are connected respectively to the inputs of the next flip-flop in the cascade (D2, D3, D4), in which divider the input terminal (RF) is connected simultaneously to the non-inverted input of the first flip-flop (DI) and through a phase inverting circuit (Ri, Ti) to the inverted input of the first flipflop (DI), and at least one output of the last flip-flop in the cascade (D4) is connected to the output of the divider, characterized in that the input terminal of the divider (RF) is connected to the non-inverted input of the first flip-flop (DI) through a coupling capacitor (Cl), and that the non-inverted input of the first flip-flop (DI) is connected to the ground of the circuit (gnd) through a resistor (Rl), and that the non-inverted input of the first flip-flop (DI) is connected to the supply voltage source (HRV) through at least one diode (Tdla, Tdlb), and that the non-inverted input of the first flip-flop (DI) is connected to the ground of the circuit (gnd) through at least one diode (Tdlc).

2. The RFID carrier frequency divider according to claim 1, characterized in that at least the first flip-flop (DI) has an additional charge injection input, which is connected to the input terminal of the divider (RF) through a coupling capacitor (C2) and to the circuit ground (gnd) through a resistor (R2), and in that the charge injection input is connected to the supply voltage source (HRV) through at least one diode (Td2a, Td2b) and is connected to the circuit ground (gnd) through at least one diode (Td2c).

3. The RFID carrier frequency divider according to claim 1 or 2, characterized in that between at least two subsequent flip-flops (DI, D2), the non-inverted output of the preceding flip-flop (DI) is connected to the non-inverted input of the following flip-flop (D2) through two serially-connected inverters (Ril, Til), (Ri3, Ti3), and the inverted output of the preceding flip-flop (DI) is connected to the inverted input of the following flip-flop (D2) through two other serially-connected inverters (Ri2, Ti2), (Ri4, Ti4).

4. The RFID carrier frequency divider according to claim 3, characterized in that the non-inverted output of the preceding flip-flop (DI) is connected to the input of the inverter (Ril, Til) through a forming resistor (Rfl), and the inverted output of thepreceding flip-flop (DI) is connected to the input of the inverter (Ri2, Ti2) through another forming resistor (Rf2).

5. The RFID carrier frequency divider according to any of the claims from 1 to 4, characterized in that at least one flip-flop is a D-type flip-flop.

6. The RFID carrier frequency divider according to any of the claims from 1 to 5, characterized in that it operates substantially at a frequency of 13.56 MHz of the input signal.

7. The RFID carrier frequency divider according to any of the claims from 1 to 6, characterized in that the supply of the circuit is the voltage derived from harvesting the radio signal.

8. The RFID carrier frequency divider according to any of the claims from 1 to 7, characterized in that the outputs of the last flip-flop in the cascade (D4) are connected to the divider output (CLK) through a desymmetrization circuit (Tbl, Tb2).

9. The RFID carrier frequency divider according to claim 8, characterized in that the desymmetrization circuit comprises two transistors connected in series between a supply voltage and ground in such a way that the first transistor (Tbl) has its drain connected to the supply voltage (HRV), its gate connected to the non-inverted output of the flip-flop (D4), and the source connected to the drain of a second transistor (Tb2), while the second transistor (Tb2) has its gate connected to the inverted output of the flip-flop (D4) and the source connected to the ground (gnd).

10. The RFID carrier frequency divider according to any of the claims from 1 to 9, characterized in that at least one flip-flop (D2, D3, D4) has a state-setting signal input connected to an external terminal (S2, S3, S4).

11. The RFID carrier frequency divider according to any of the claims from 1 to 10, characterized in that at least one diode is made from a transistor by connecting its gate to the source (Tdla, Tdlb, Tdlc, Td2a, Td2b, Td2c).

12. The RFID carrier frequency divider according to any of the claims from 1 to 11, characterized in that at least one inverter (Ril, Til), (Ri2, Ti2), (Ri3, Ti3), (Ri4, Ti4) is made in the RTL technique, in which a resistor (Ril, Ri2, Ri3, Ri4) is connected between the supply voltage (HRV) and the drain of the transistor (Til, Ti2, Ti3, Ti4), the source of the transistor (Til, Ti2, Ti3, Ti4) is connected to the ground (gnd), the gate of the transistor (Til, Ti2, Ti3, Ti4) is the input of the inverter, and the drain of the transistor (Til, Ti2, Ti3, Ti4) is the output of the inverter.

13. The RFID carrier frequency divider according to any of the claims from 1 to 12, characterized in that it is built of a cascade of 4 flip-flops.

14. The RFID carrier frequency divider according to any of the claims from 1 to 13, characterized in that all transistors in the circuit are the FETs of "n" type.

15. The RFID carrier frequency divider according to any of the claims from 1 to 14, characterized in that all transistors in the circuit are TFT-type transistors.

16. The RFID carrier frequency divider according to any of the claims from 1 to 15, characterized in that the transistor channels are made of amorphous semiconductor material.

17. The RFID carrier frequency divider according to any of the claims from 1 to 16, characterized in that the transistors contain indium-gallium zinc oxide.

18. A bistable having a first pair of transistors (T2, T3) and a second pair of transistors (T7, T8), wherein the drains of the transistors (T2, T3, T7, T8) are connected to a supply voltage terminal (HRV) through resistors (Rl, R2, R3, R4), in which pairs the transistors sources are connected to each other (T2, T3), (T7, T8), and each transistor gate is connected to the drain of the other transistor in the pair, and having a third pair of transistors (Tl, T4) and a fourth pair of transistors (T6, T9), wherein the transistors sources in the pairs are connected to each other (Tl, T4), (T6, T9), and the connected sources are connected to the drains of clock transistors in such way that the sources of the third pair of transistors (Tl, T4) are connected to a clock transistor (T5), which gate is connected to the non-inverted input terminal (CLK), and the sources of the fourth pair of transistors (T6, T9) are connected to the clock transistor (T10), which gate is connected to the inverted input terminal (nCLK), wherein the drains of the transistors of the third pair (Tl, T4) are connected respectively to the drains of the transistors of the first pair (T2, T3), and the drains of the transistors of the fourth pair (T6, T9) are connected respectively to the drains of the transistors of the second pair (T7, T8), while the gates of the transistors of the third pair (Tl, T4) are connected respectively to the drains of the transistors of the fourth pair (T6, T9), and the gates of the transistors of the fourth pair (T6, T9) are connected in reverse order to the drains of the transistors of the third pair (Tl, T4), where the non-inverted output terminal (Q) is connected to the drain of the second transistor of the fourth pair (T9), and the inverted output terminal (nQ) is connected to the drain of the first transistor of the fourth pair (T6), characterized in that the transistors sources of the first and second pair (T2, T3, T7, T8) are connected to the circuit ground (gnd), and in that the sources of the clock transistors (T5, T10) are connected to the circuit ground (gnd), and in that the charge injection terminal (CI) is connected to the drain of the second clock transistor (T10).

19. The bistable according to claim 18, characterized in that it is equipped with a control input set terminal (Set) which is connected to the gates of two transistors (Tsl, Ts2), the sources of which are connected to the circuit ground, and the drain of the first transistor (Tsl) is connected to the drain of the first transistor of the fourth pair (T6), while the drain of the second transistor (Ts2) is connected to the drain of the first transistor of the third pair (Tl).

20. The bistable according to claim 18 or 19, characterized in that it operates substantially at a frequency of 13.56 MHz of the input signal.

21. The bistable according to claim 18 or 19 or 20, characterized in that the supply of the circuit is the voltage derived from harvesting the radio signal.

22. The bistable according to any of the claims from 18 to 21, characterized in that all transistors in the circuit are the FETs of "n" type.

23. The bistable according to any of the claims from 18 to 22, characterized in that all transistors in the circuit are TFT-type transistors.

24. The bistable according to any of the claims from 18 to 23, characterized in that the transistor channels are made of amorphous semiconductor material.

25. The bistable according to any of the claims from 18 to 24, characterized in that the transistors contain indium-gallium zinc oxide.

26. The bistable according to any of the claims from 18 to 25, characterized in that the transistors of the first and second pairs (T2, T3), (T7, T8) are the same with respect to the ratio of the channel width to the length, and in that the transistors of the third pair (Tl, T4) are the same with respect to the ratio of the channel width to the length, with this ratio being from 2 to 4 times greater with respect to the transistors of the first two pairs, and in that the transistors of the fourth pair (T6, T9) are the same with respect to the ratio of the channel width to the length, with this ratio being from 1.5 to 2.5 times greater with respect to the transistors of the first two pairs, and in that the clock transistors (T5, T10) have a ratio of the channel width to the length 3 to 5 times greater with respect to the transistors of the first two pairs.