Device for selecting components of power plants in the electrical network

Claims

A device for selecting components of power installations in an electrical network, containing: a group of m meters 31…3 m , a clock pulse generator (CPG) 1, the output of which is connected to the first input of the first AND element 2, the second input of which is connected to the starting input of device 33, and the output is connected to the input of counter 31, a group of m second AND elements 41…4 m , the third element of I 28, the fourth group of elements of I 24, the group of m first 51…5 m , the second 61…6 m and the third 81…8 m registers, m first 71…7 m and the second 91…9 m multiplication blocks, the first 11 and second 18 adders, the first comparison circuit 12, the fourth register 13, the second comparison circuit 26, the fifth register 25, the output of each counter 3 i (i = 1 … m) is connected to the first inputs of the AND element group 4 i , to the first input of the first multiplication block 7 i and to the first input of the second multiplication block 9 i the second input of the multiplication block 9 iconnected to the output of the third register 8 i , and the output is connected to the same-named input of the first adder 11, the output of which is connected to the first input of the first comparison circuit 12, the second input of which is connected to the output of the fourth register 13, and the output is connected to the first input of the third AND element 28, the output of which is connected to the first input of the fourth group of AND elements 24 and to the second inputs of the groups of AND elements 4 i (i = 1…m), the output of each of which is connected to the input of the first register 5 i , the output of every second register is 6 i connected to the second input of the first multiplication block 7 i, the output of which is connected to the same-named input of the second adder 18, the output of which is connected to the first input of the second comparison circuit 26, to the second input of the fourth group of AND elements 24, the output of which is connected to the input of the fifth register 25, the output of which is connected to the second input of the second comparison circuit 26, the output of which is connected to the second input of the AND element 28, the overflow output of counter 3 i (i = 1 … (m-1)) is connected to the input of counter 3 i+1 counter overflow output 3 m connected to the inverse input of the first element AND 2, characterized in that it additionally includes sixth registers 101...10 m , m blocks of raising a number to the power 141…14 m , the first delay element is 15, m second delay elements are 161…16 m , m groups of fifth elements And 171…17 m, first OR element 19, third multiplication block 20, second OR element 21, seventh register 22, third delay element 23, fourth delay element 27, fifth delay element 29, output of every sixth register 10 i (i = 1,…m) is connected to the first input of the block for raising a number to the power of 14 i , the second input of which is connected to the output of register 5 i and the third input - to the output of the first delay element 15, the input of which is connected to the overflow output of counter 3 т , the output of the block for raising a number to the power of 14 i (i = 1,…m) is connected to the first input of the fifth AND element 17 i , the second input of which is connected to the output of the second delay element 16 i (i=1,…m), and the output is connected to the same-named input of the first OR element 19, the output of which is connected to the first input of the third multiplication block 20, the output of the first delay element 15 is connected to the inputs of the second delay elements 16 i(i=1,…m), the output of which is connected to the input of the second OR element 21 of the same name, the output of which is connected to the control input of the multiplication block 20, the output of which is connected to the first input of the seventh register 22, the control input of which is connected to the output of the third delay element 23, the output of the second delay element 16 m connected to the inputs of the third 23 and fourth 27 delay elements, the output 30 of which is the output of the device, the output of the first AND element 2 is connected to the input of the fifth delay element 29, the output of which is connected to the control input of the first comparison circuit 12 and to the control input of the second adder 18.