A device for calculating the reliability indicators of redundant systems with recovery and threshold control of parameters

Abstract

This utility model pertains to computing and can be used for scientific research that requires calculating such reliability indicators of a redundant system with recovery as failure rate, mean time between failures, and availability. The device is designed to directly calculate the failure rate, mean time between failures, and availability of a redundant system with recovery, with the ability to monitor input parameters. The purpose of this utility model is to create a technical tool for a specific purpose (calculating reliability indicators—failure rate, mean time between failures, and availability—of a redundant system with recovery, with the ability to threshold-basedly monitor input parameters).The implementation and use of the proposed utility model improves the operational reliability of the prototype device by introducing automatic input parameter verification for compliance with acceptable ranges before the computational process begins, eliminating incorrect results when calculating the reliability indicators of redundant systems with recovery. The technical result achieved by this utility model consists of implementing new functionality in the prototype device through design modifications that enable threshold monitoring of a number of parameters used in calculating the reliability indicators of redundant systems with recovery. The presented device is designed for connection to other technical systems or simulation systems through the provision of information inputs and outputs.The described device can be implemented using units and blocks known in the field of radio electronics, connected to each other, ensuring constructive and functional unity.

Description

[0001] The utility model relates to the field of computer engineering and can be used for scientific research that requires calculating such reliability indicators of a redundant system with recovery as failure rate, mean time between failures, and availability factor.

[0002] The device is designed to directly calculate the failure rate, mean time between failures and availability factor of a redundant system with recovery with the ability to control input parameters.

[0003] A device for linearly combining independent reliability estimates for similar products with known variances is known (Russian Federation Patent for Utility Model No. 57478, published October 10, 2006, Bulletin No. 28). This device allows for automated combining of independent reliability estimates for similar products with known variances. However, this device does not allow for calculating reliability indicators such as failure rate, mean time between failures, and system availability.

[0004] A device for calculating the reliability index of redundant systems with recovery is known (Russian Federation Patent for Utility Model No. 214231, published October 17, 2022, Bulletin No. 29). This device is intended to directly calculate the failure rate of a redundant system with recovery. However, this device does not allow for calculating the mean time between failures and the availability factor of a redundant system with recovery.

[0005] A device for calculating the reliability indicators of redundant systems with recovery is known (Russian Federation Patent for Utility Model No. 217823, published April 19, 2023, Bulletin No. 11). This device is designed to directly calculate the failure rate of a redundant system with recovery and the mean time between failures of this system. However, this device does not allow for calculating the system availability factor.

[0006] The closest analogue (prototype) to the claimed solution in technical implementation and functions performed is a device for calculating the reliability indicators of redundant systems with recovery (Russian Federation Patent for Utility Model No. 226755, published on 20.06.2024, Bulletin No. 17), including a first register intended for recording the number of main elements of the system, a second register intended for recording the number of backup elements of the system, a third register intended for recording the value of the failure rate of one element, a fourth register intended for recording the value of the recovery rate of one element, a fifth register intended for recording a single value upon receipt of a single signal at its input, an adder intended for summing the data coming from the first and second registers, an increment unit, the first and second exponentiation units, the first and second factorial calculation units, a subtraction unit,first, second, third and fourth blocks of AND elements, a subtraction from unity block, first and second multiplication blocks, first, second and third division blocks, a delay element, a first information input intended for inputting data on the number of main elements of the system into the first register, a second information input intended for inputting data on the number of reserve elements of the system into the second register, a third information input intended for inputting data on the value of the failure rate of one element into the third register, a fourth information input intended for inputting data on the value of the recovery rate of one element into the fourth register, a fifth information input intended for transmitting a single signal to the fifth register, a first information output intended for outputting the value of the failure rate of the system, a second information output intended for outputting the value of the average time between failures of the system, wherein the first, second, third,the fourth and fifth information inputs are connected to the first, second, third, fourth and fifth registers respectively, the output of the first register is connected to the input of the adder, the output of the second register is connected in parallel to the inputs of the adder, the increment block, the first exponentiation block, the first factorial calculation block and the subtraction block, the output of the third register is connected to the input of the second exponentiation block, the output of the fourth register is connected to the input of the first exponentiation block, the output of the fifth register is connected in parallel to the inputs of the fourth AND element block and the third division block, the output of the adder is connected in parallel to the inputs of the second factorial calculation block and the subtraction block, the output of the increment block is connected to the input of the second exponentiation block, the outputs of the first exponentiation block and the first factorial calculation block are connected through the first AND element block to the inputs of the first multiplication block,the output of the subtraction unit is connected to the input of the unit subtraction unit, the outputs of the second factorial calculation unit and the unit subtraction unit are connected to the inputs of the first division unit, the outputs of the first division unit and the second exponentiation unit are connected through the second block of AND elements to the inputs of the second multiplication unit, the outputs of the first and second multiplication units are connected through the third block of AND elements to the inputs of the second division unit, the output of the second division unit is connected to the input of the delay element, the output of the delay element is the first information output of the device, the output of the third division unit is the second information output of the device, characterized in that a sixth register intended for recording the value of the system recovery wait time, a fifth block of AND elements, a second adder intended for summing the data coming through the fifth block of AND elements from the sixth register and from the third division unit, a fourth division unit are introduced into the device,a second delay element, a sixth information input intended for transmitting a single signal to the fifth block of AND elements, a seventh information input intended for inputting data on the value of the system recovery wait time, a third information output intended for outputting the value of the system readiness coefficient, wherein the seventh information input is connected to the sixth register, the sixth information input and the output of the sixth register are connected to the inputs of the fifth block of AND elements, the output of the third division block is connected in parallel to the inputs of the second delay element, the second adder and the fourth division block, the output of the fifth block of AND elements is connected to the input of the second adder, the output of the second adder is connected to the input of the fourth division block, the output of the second delay element is the second information output of the device, the output of the fourth division block is the third information output of the device.

[0007] The device is designed to directly calculate the value of reliability indicators of redundant systems with recovery, such as failure rate, mean time between failures and availability factor.

[0008] However, this device does not implement the ability to automatically control input parameters before starting the computing process, which allows for the possibility of obtaining incorrect results when calculating the reliability indicators of redundant systems with recovery.

[0009] The purpose of creating a utility model is to create a technical tool for a specific purpose (calculation of reliability indicators - failure rate, mean time between failures and the availability factor of a redundant system with restoration with the possibility of threshold control of input parameters).

[0010] The technical result that the utility model is aimed at achieving consists of the implementation of new functionality in the prototype device due to design changes that make it possible to implement the threshold control function for a number of parameters used in calculating the reliability indicators of redundant systems with recovery.

[0011] To achieve this technical result in the known device for calculating the reliability indicators of redundant systems with recovery, a seventh register, a first, second, third and fourth comparators, a sixth, seventh, eighth and ninth blocks of AND elements, a block of OR elements, an eighth information input, a control output of the device are additionally introduced, wherein the eighth information input is connected to the seventh register, the output of the first register is connected in parallel to the inputs of the first comparator and the sixth block of AND elements, the output of the second register is connected in parallel to the inputs of the second comparator and the seventh block of AND elements, the output of the third register is connected in parallel to the inputs of the third comparator and the eighth block of AND elements, the output of the fourth register is connected in parallel to the inputs of the fourth comparator and the ninth block of AND elements, the output of the eighth register is connected in parallel to the inputs of the first, second, third and fourth comparators, the first outputs of the first,the second, third and fourth comparators are connected to the inputs of the OR element block, the second output of the first comparator is connected to the input of the sixth AND element block, the second output of the second comparator is connected to the input of the seventh AND element block, the second output of the third comparator is connected to the input of the eighth AND element block, the second output of the fourth comparator is connected to the input of the ninth AND element block, the output of the sixth AND element block is connected to the input of the first adder, the output of the seventh AND element block is connected in parallel to the inputs of the first adder, the increment block, the subtraction block, the first exponentiation block, the first factorial calculation block, the output of the eighth AND element block is connected to the input of the second exponentiation block, the output of the ninth AND element block is connected to the input of the first exponentiation block, the output of the OR element block is the control output of the device, connecting the first register to the first adder,the second register with the first adder, the increment block, the first exponentiation block, the first factorial calculation block and the subtraction block, the third register with the second exponentiation block, the fourth register with the first exponentiation block are excluded.

[0012] The proposed device, like the prototype device, allows for the calculation of such reliability indicators as the system failure rate (λ рс ), mean time between failures of the system and the system availability factor (K Г ).

[0013] Determination of failure rate (λ рс ) of the redundant system is carried out according to the formula

[0014]

[0015] where N is the number of system elements;

[0016] n - the number of backup system elements;

[0017] λ ии - failure rate of one element of the system;

[0018] μ ou- the intensity of restoration of one element of the system.

[0019] Determination of mean time between failures the redundant system is carried out according to the formula

[0020]

[0021] Determination of the readiness factor (K Г ) of the redundant system is carried out according to the formula

[0022]

[0023] where - recovery waiting time.

[0024] To implement the threshold control function of parameters in the presented device, the following were selected as the most critical parameters affecting the accuracy of calculating the reliability indicators of redundant systems with recovery: the number of main elements of the system (N), the number of backup elements of the system (n), the failure rate of one element (λ ии ), the intensity of recovery of one element (μ ou). Monitoring these parameters allows for a significant increase in the accuracy of calculating the reliability indicators of redundant systems with recovery due to a slight increase in the number of structural elements and the complexity of the device circuit.

[0025] The control criterion of parameter N is determined by the expression

[0026] N>N min ,

[0027] where N min - the minimum permissible value of the number of basic elements of the system.

[0028] The control criterion of parameter n is determined by the expression,

[0029] where n min - the minimum permissible value of the number of reserve elements of the system.

[0030] Control criterion of parameter λ ии is determined by the expression

[0031]

[0032] where - the minimum permissible value of the failure rate of one element of the system.

[0033] Control criterion of the parameter μ ou is determined by the expression

[0034]

[0035] where - the minimum permissible value of the intensity of restoration of one element of the system.

[0036] Fig. 1 shows a structural diagram of the device. The device contains the first register 1, intended for recording the number of main elements of the system, the second register 2, intended for recording the number of backup elements of the system, the third register 3, intended for recording the value of the failure rate of one element, the fourth register 4, intended for recording the value of the recovery rate of one element, the fifth register 5, intended for recording a single value when a single signal is received at its input, the sixth register 6, intended for recording the value of the waiting time for system recovery, the seventh register 40, intended for recording the minimum value of the monitored parameter, the first adder 7, intended for summing up the data coming from the first and second registers 1, 2 through the sixth and seventh blocks of AND elements 42, 47, the second adder 27, intended for summing up the data,coming through the fifth block of AND elements 26 from the sixth register 6 and from the third division block 23, the increment block 8, the first and second exponentiation blocks 9, 10, the first and second factorial calculation blocks 11, 14, the subtraction block 12, the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth blocks of AND elements 13, 18, 20, 21, 26, 42, 47, 48, 49, the subtraction from unity block 15, the first and second multiplication blocks 16, 19, the first, second, third and fourth division blocks 17, 22, 23, 28, the first and second delay elements 24, 25, the block of OR elements 46, the first comparator 41 intended for direct comparison of the minimum value of the controlled parameter received from the seventh register 40, and the value of the number of the main elements of the system received from the first register 1, the second comparator 43, designed for direct comparison of the minimum value of the controlled parameter received from the seventh register 40,and the value of the number of reserve elements of the system received from the second register 2, the third comparator 44, intended for direct comparison of the minimum value of the monitored parameter received from the seventh register 40, and the value of the failure rate of one element of the system received from the third register 3, the fourth comparator 45, intended for direct comparison of the minimum value of the monitored parameter received from the seventh register 40, and the value of the recovery rate of one element of the system received from the fourth register 4, the first information input 29, intended for inputting data on the number of main elements of the system into the first register 1, the second information input 30, intended for inputting data on the number of reserve elements of the system into the second register 2, the third information input 31, intended for inputting data on the value of the failure rate of one element into the third register 3,a fourth information input 32 intended for inputting data on the value of the intensity of restoration of one element into the fourth register 4, a fifth information input 33 intended for transmitting a single signal to the fifth register 5, a sixth information input 34 intended for transmitting a single signal to the fifth block of AND elements 26, a seventh information input 35 intended for inputting data on the value of the waiting time for the system restoration into the sixth register 6, an eighth information input 39 intended for inputting data on the minimum value of the monitored parameters into the seventh register 40, a first information output 36 intended for outputting the value of the intensity of system failures, a second information output 37 intended for outputting the value of the average time between failures of the system, a third information output 38 intended for outputting the value of the system readiness coefficient, a control output of the device 50,designed to generate a control signal in the event of a discrepancy between the controlled parameters and the threshold values.

[0037] The first, second, third, fourth, fifth and seventh data inputs 29-33, 35 are connected to the first, second, third, fourth, fifth and sixth registers 1-6 respectively, the sixth data input is connected to the fifth block of AND elements 26, the output of the fifth register 5 is connected in parallel to the inputs of the fourth block of AND elements 21 and the third division block 23, the output of the sixth register 6 is connected to the input of the fifth block of AND elements 26, the output of the adder 7 is connected in parallel to the inputs of the second factorial calculation block 14 and the subtraction block 12, the output of the increment block 8 is connected to the input of the second exponentiation block 10, the outputs of the first exponentiation block 9 and the first factorial calculation block 11 are connected through the first block of AND elements 13 to the inputs of the first multiplication block 16, the output of the subtraction block 12 is connected to the input of the subtraction block from units 15,the outputs of the second factorial calculation unit 14 and the unit subtraction unit 15 are connected to the inputs of the first division unit 17, the outputs of the first division unit 17 and the second unit of raising to the power of 10 are connected through the second block of AND elements 18 to the inputs of the second multiplication unit 19, the outputs of the first and second multiplication units 16, 19 are connected through the third block of AND elements 20 to the second division unit 22, the output of the second division unit 22 is connected in parallel to the inputs of the first delay element 24 and the fourth block of AND elements 21, the output of the fourth block of AND elements 21 is connected to the input of the third division unit 23, the output of the fifth block of AND elements 26 is connected to the input of the second adder 27, the output of the third division unit 23 is connected in parallel to the inputs of the second delay element 25, the second adder 27 and the fourth division unit 28, the output of the second adder 27 is connected to the input of the fourth division unit 28, the output of the first delay element 24 is the first information output of device 36,the output of the second delay element 25 is the second information output of device 37, the output of the fourth division block 28 is the third information output of device 38, the eighth information input is connected to the seventh register 40, the output of the first register 1 is connected in parallel to the inputs of the first comparator 41 and the sixth block of AND elements 42, the output of the second register 2 is connected in parallel to the inputs of the second comparator 43 and the seventh block of AND elements 47, the output of the third register 3 is connected in parallel to the inputs of the third comparator 44 and the eighth block of AND elements 48, the output of the fourth register 4 is connected in parallel to the inputs of the fourth comparator 45 and the ninth block of AND elements 49, the output of the eighth register 40 is connected in parallel to the inputs of the first, second, third and fourth comparators 41, 43, 44, 45, the first outputs of the first, second, third and fourth comparators 41, 43, 44, 45 are connected to the inputs of the OR element block 46,the second output of the first comparator 41 is connected to the input of the sixth block of AND elements 42, the second output of the second comparator 43 is connected to the input of the seventh block of AND elements 47, the second output of the third comparator 44 is connected to the input of the eighth block of AND elements 48, the second output of the fourth comparator 45 is connected to the input of the ninth block of AND elements 49, the output of the sixth block of AND elements 42 is connected to the input of the first adder 7, the output of the seventh block of AND elements 47 is connected in parallel to the inputs of the first adder 7, the increment block 8, the subtraction block 12, the first exponentiation block 9, the first factorial calculation block 11, the output of the eighth block of AND elements 48 is connected to the input of the second exponentiation block 10, the output of the ninth block of AND elements 49 is connected to the input of the first exponentiation block 9, the output of the block of OR elements 46 is the control output of device 50.,

[0038] It is possible to use a factorial calculator as a factorial calculator [USSR Patent for Invention No. 1297071].

[0039] The device operates as follows. The first, second, third and fourth information inputs 29-32 receive data on the number of main system elements (N), the number of backup system elements (n), the failure rate of one element (λ ии ) and the value of the intensity of recovery of one element (μ ou ), which are written into the first, second, third and fourth registers 1-4, respectively. If it is necessary to calculate the mean time between failures of the system A single signal is applied to the fifth information input 33. If there is no single signal at the fifth information input 33, the system's mean time between failures will not be calculated. If it is necessary to calculate the system's availability factor (K г) a single signal is sent to the sixth information input 34, and data on the system recovery waiting time is sent to the seventh information input 35 In the absence of a single signal at the sixth information input 34, the system readiness factor will not be calculated.

[0040] Data on the minimum value of the controlled parameters is received at the eighth information input 39 and written to the seventh register 40. From the eighth register 40, data on the minimum value of the controlled parameters is sent to the first, second, third and fourth comparators 41, 43, 44, 45.

[0041] From the first register 1, the data on the number of main elements of the system are sent to the first comparator 41. In the event that the value of the number of main elements of the system is greater than the minimum value of the controlled parameters, the first comparator 41 sends a signal to the sixth block of AND elements 42, while the data on the number of main elements of the system from the first register 1 are sent through the sixth block of AND elements 42 to the first adder 7. In the event that the value of the number of main elements of the system is less than the minimum value of the controlled parameters, the first comparator 41 sends a signal to the block of OR elements 46.

[0042] From the second register 2, the data on the number of reserve elements of the system is sent to the second comparator 43. In the event that the value of the number of reserve elements of the system is greater than the minimum value of the controlled parameters, the second comparator 43 sends a signal to the seventh block of AND elements 47, while the data on the number of reserve elements of the system from the second register 2 are sent through the seventh block of AND elements 47 to the first adder 7, to the increment block 8, to the first exponentiation block 9, as the power of the number being raised, to the first factorial calculator block 11, and to the subtraction block 12, as the number being subtracted. In the event that the value of the number of reserve elements of the system is less than the minimum value of the controlled parameters, the second comparator 43 sends a signal to the block of OR elements 46.

[0043] From the third register 3, the failure rate data for one system element is sent to the third comparator 44. If the failure rate for one system element is greater than the minimum value of the monitored parameters, the third comparator 44 sends a signal to the eighth AND block 48. The failure rate data for one system element from the third register 3 is sent through the eighth AND block 48 to the second raising-to-the-power-of-10 block, as the number being raised to the power. If the failure rate for one system element is less than the minimum value of the monitored parameters, the third comparator 44 sends a signal to the OR block 46.

[0044] From the fourth register 4, the data on the recovery rate of one system element is sent to the fourth comparator 45. If the recovery rate of one system element is greater than the minimum value of the controlled parameters, the fourth comparator 45 sends a signal to the ninth block of AND elements 49. The data on the recovery rate of one system element from the fourth register 4 is sent through the ninth block of AND elements 49 to the first exponentiation block 9, as a number being raised to a power. If the recovery rate of one system element is less than the minimum value of the controlled parameters, the fourth comparator 45 sends a signal to the block of OR elements 46.

[0045] If ​​signals are received by the OR element block 46 from the first, second, third or fourth comparators 41, 43, 44, 45, the OR element block 46 sends a signal to the control output of device 50. The receipt of a signal from the control output of device 50 indicates that one of the monitored parameters does not correspond to the threshold value.

[0046] From the increment block 8, the data is fed to the second raising-to-the-power block 10, as the power of the number being raised. From the adder 7, the data is fed to the second factorial calculation block 14 and to the subtraction block 12, as the minuend. From the first raising-to-the-power block 9 and the first factorial calculation block 11, the data is fed through the first block of AND elements 13 to the first multiplication block 16. From the subtraction block 12, the data is fed to the subtraction-from-one block 15. From the subtraction-from-one block 15, the data is fed to the first division block 17, as the divisor. From the second factorial calculation block 14, the data is fed to the first division block 17, as the dividend. From the first division block 17 and the second raising to the power of 10 block, the data is fed through the second block of AND elements 18 to the second multiplication block 19. From the first multiplication block 16, the data is fed through the third block of AND elements 20 to the second division block 22, as a divisor.From the second multiplication block 19, the data is fed through the third block of AND elements 20 to the second division block 22 as the dividend. From the second division block 22, the data represents the failure rate of the redundant system (λ). рс ), through the first delay element 24, they are fed to the first information output of the device 36.

[0047] When a one signal is received at the fifth information input 33, the value of one is written to the fifth register 5. From the fifth register 5, the data through the fourth block of AND elements 21 is fed to the input of the third division block 23, as a dividend, while from the second division block 22, the calculation result is fed through the fourth block of AND elements 21 to the third division block 23, as a divisor. From the third division block 23, the data representing the value of the mean time between failures of the system through the second delay element 25 they are fed to the second information output of the device 37.

[0048] When a single signal is received at the sixth information input 24, and data about the system recovery waiting time is received at the seventh information input The waiting time data is written into the sixth register 6 and from the sixth register 6 through the fifth block of AND elements 26 goes to the second adder 27. The data from the third division block 23 goes to the second adder 27 and to the fourth division block 28, as a dividend. From the second adder 27, the data goes to the fourth division block 28 as a divider. From the fourth division block 28, the data representing the value of the system readiness factor (K г ), are sent to the third information output of device 38.

[0049] Thus, when creating a utility model, the technical problem of creating a tool for a specific purpose (calculation of reliability indicators - failure rate, mean time between failures and the availability factor of a redundant system with restoration with the possibility of threshold control of input parameters) was solved.

[0050] The claimed utility model is a technical solution related to a device, as the utility model formula contains a set of essential features related to the device (namely, a list of the elements used and the relationships between them) sufficient to solve the stated problem and achieve the technical result. These features are considered essential because they affect the possibility of achieving the technical result, i.e., they are causally related to the stated result. The absence of one or more features will render the device inoperable and prevent the claimed result from being achieved.

[0051] The implementation and use of the proposed utility model allows for increasing the reliability of the prototype device by introducing a function for automatically monitoring input parameters for compliance with acceptable ranges before the start of the computing process, which eliminates the possibility of obtaining incorrect results when calculating the reliability indicators of redundant systems with recovery.

[0052] The presented device is designed with the possibility of connection to other technical systems or modeling systems due to the presence of information inputs and outputs.

[0053] The described device for calculating the reliability indicators of redundant systems with recovery with threshold control of parameters can be implemented using nodes and blocks known in the field of radio electronics, connected to each other, ensuring constructive and functional unity.

Claims

A device for calculating the reliability indicators of redundant systems with recovery with threshold control of parameters, including a first register intended for recording the number of main elements of the system, a second register intended for recording the number of backup elements of the system, a third register intended for recording the value of the failure rate of one element, a fourth register intended for recording the value of the recovery rate of one element, a fifth register intended for recording a single value upon receipt of a single signal at its input, a sixth register intended for recording the value of the system recovery wait time, an adder intended for summing up the data coming from the first and second registers through the sixth and seventh blocks of AND elements, a second adder intended for summing up the data coming through the fifth block of AND elements from the sixth register and from the third division block,an increment unit, first and second exponentiation units, first and second factorial calculation units, a subtraction unit, first, second, third, fourth and fifth AND element units, a subtraction-from-one unit, first and second multiplication units, first, second, third and fourth division units, first and second delay elements, a first information input intended for entering data on the number of primary system elements into the first register, a second information input intended for entering data on the number of backup system elements into the second register, a third information input intended for entering data on the failure rate of one element into the third register, a fourth information input intended for entering data on the recovery rate of one element into the fourth register, a fifth information input intended for transmitting a single signal to the fifth register, a sixth information input,designed to transmit a single signal to the fifth block of AND elements, a seventh information input designed to input data on the value of the system recovery waiting time into the sixth register, a first information output designed to output the value of the system failure rate, a second information output designed to output the value of the mean time between failures of the system, a third information output designed to output the value of the system availability factor, wherein the first, second, third, fourth and fifth information inputs are connected to the first, second, third, fourth and fifth registers respectively, the output of the fifth register is connected in parallel to the inputs of the fourth block of AND elements and the third division unit, the output of the adder is connected in parallel to the inputs of the second factorial calculation unit and the subtraction unit, the output of the increment unit is connected to the input of the second exponentiation unit,the outputs of the first exponentiation block and the first factorial calculation block are connected via the first block of AND elements to the inputs of the first multiplication block, the output of the subtraction block is connected to the input of the subtraction-from-one block, the outputs of the second factorial calculation block and the subtraction-from-one block are connected to the inputs of the first division block, the outputs of the first division block and the second exponentiation block are connected via the second block of AND elements to the inputs of the second multiplication block, the outputs of the first and second multiplication blocks are connected via the third block of AND elements to the inputs of the second division block, the output of the second division block is connected in parallel to the inputs of the delay element and the fourth block of AND elements, the output of the fourth block of AND elements is connected to the input of the third division block, the output of the delay element is the first information output of the device, the seventh information input is connected to the sixth register,the sixth information input and the output of the sixth register are connected to the inputs of the fifth block of AND elements, the output of the third division block is connected in parallel to the inputs of the second delay element, the second adder and the fourth division block, the output of the fifth block of AND elements is connected to the input of the second adder, the output of the second adder is connected to the input of the fourth division block, the output of the second delay element is the second information output of the device, the output of the fourth division block is the third information output of the device, characterized in that a seventh register intended for recording the minimum value of the controlled parameter, sixth, seventh, eighth and ninth blocks of AND elements, a block of OR elements, a first comparator intended for direct comparison of the minimum value of the controlled parameter received from the seventh register and the value of the number of main elements of the system received from the first register, a second comparator are introduced into the device,designed for direct comparison of the minimum value of the monitored parameter received from the seventh register and the value of the number of reserve elements of the system received from the second register, a third comparator designed for direct comparison of the minimum value of the monitored parameter received from the seventh register and the value of the failure rate of one element of the system received from the third register, a fourth comparator designed for direct comparison of the minimum value of the monitored parameter received from the seventh register and the value of the recovery rate of one element of the system received from the fourth register, an eighth information input designed for inputting data on the minimum value of the monitored parameters, a control output of the device designed to issue a control signal in the event of non-compliance of the monitored parameters with the threshold values,wherein the eighth information input is connected to the seventh register, the output of the first register is connected in parallel to the inputs of the first comparator and the sixth block of AND elements, the output of the second register is connected in parallel to the inputs of the second comparator and the seventh block of AND elements, the output of the third register is connected in parallel to the inputs of the third comparator and the eighth block of AND elements, the output of the fourth register is connected in parallel to the inputs of the fourth comparator and the ninth block of AND elements, the output of the eighth register is connected in parallel to the inputs of the first, second, third and fourth comparators, the first outputs of the first, second, third and fourth comparators are connected to the inputs of the block of OR elements, the second output of the first comparator is connected to the input of the sixth block of AND elements, the second output of the second comparator is connected to the input of the seventh block of AND elements, the second output of the third comparator is connected to the input of the eighth block of AND elements,the second output of the fourth comparator is connected to the input of the ninth block of AND elements, the output of the sixth block of AND elements is connected to the input of the first adder, the output of the seventh block of AND elements is connected in parallel to the inputs of the first adder, the increment block, the subtraction block, the first exponentiation block, the first factorial calculation block, the output of the eighth block of AND elements is connected to the input of the second exponentiation block, the output of the ninth block of AND elements is connected to the input of the first exponentiation block, the output of the block of OR elements is the control output of the device.

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