Device for assessing the reliability indicators of redundant systems with recovery

Abstract

This utility model pertains to computing and can be used for scientific research that requires evaluating such reliability indicators of a redundant system with recovery as failure rate, mean time between failures, and system availability. The device is designed to directly calculate the failure rate, mean time between failures, and system availability of a redundant system with recovery, as well as to evaluate their values ​​according to specified criteria. The purpose of this utility model is to create a technical tool for a specific purpose (calculating reliability indicators—failure rate, mean time between failures, and system availability—of a redundant system with recovery, followed by evaluating them according to specified criteria).The implementation and use of the proposed utility model enables the calculation of reliability indicators for redundant systems with recovery (failure rate, mean time between failures, system availability) based on a set of initial data, as well as the evaluation of the obtained indicators in accordance with established criteria. The technical result achieved by this utility model is to expand the scope of application of the prototype device through design modifications that enable the automatic evaluation of the obtained reliability indicators for redundant systems with recovery based on specified criteria. The described device can be implemented using components and units known in the field of electronics, interconnected to ensure structural and functional integrity.

Description

[0001] The utility model relates to the field of computer engineering and can be used for scientific research that requires assessing such reliability indicators of a redundant system with recovery as failure rate, mean time between failures, and the availability factor of this system.

[0002] The device is designed to directly calculate the failure rate, mean time between failures and availability factor of a redundant system with recovery, as well as to evaluate their values ​​according to specified criteria.

[0003] A device for linearly combining independent reliability estimates for similar products with known variances is known (Russian Federation Patent for Utility Model No. 57478, published October 10, 2006, Bulletin No. 28). This device allows for automated combining of independent reliability estimates for similar products with known variances. However, this device does not calculate or evaluate reliability indicators such as failure rate, mean time between failures, and system availability.

[0004] A device for calculating the reliability indicators of redundant systems with recovery is known (Russian Federation Patent for Utility Model No. 217823, published April 19, 2023, Bulletin No. 11). The device is designed to directly calculate the failure rate of a redundant system with recovery and the mean time between failures of this system. However, this device does not allow for calculating the system availability factor or evaluating the resulting indicators.

[0005] The closest analog (prototype) to the claimed solution in terms of technical implementation and functionality is a device for calculating the reliability indicators of redundant systems with recovery (Russian Federation Patent for Utility Model No. 226755, published June 20, 2024, Bulletin No. 11). This device calculates reliability indicators such as failure rate, mean time between failures, and the availability factor of a redundant system with recovery. However, this device does not allow for automated evaluation of the obtained indicators.

[0006] The technical result that the utility model is aimed at achieving / consists in expanding the scope of application of the prototype device due to design changes that make it possible to evaluate the obtained reliability indicators of redundant systems with automatic recovery according to specified criteria.

[0007] In order to achieve this technical result, in a known device for calculating the reliability indicators of redundant systems with recovery, comprising a first register intended to record the number of main elements of the system, a second register intended to record the number of backup elements of the system, a third register intended to record the value of the failure rate of one element, a fourth register intended to record the value of the recovery rate of one element, a fifth register intended to record a single value upon receipt of a single signal at its input, a sixth register intended to record the value of the system recovery wait time, an adder intended to sum the data coming from the first and second registers, an increment unit, a second adder intended to sum the data coming through the fifth block of AND elements from the sixth register and from the third division unit,first and second exponentiation units, first and second factorial calculation units, subtraction unit, first, second, third, fourth and fifth AND element units, unit subtraction unit, first and second multiplication units, first, second, third and fourth division units, first and second delay elements, first information input for entering data on the number of primary system elements into the first register, second information input for entering data on the number of backup system elements into the second register, third information input for entering data on the failure rate of one element into the third register, fourth information input for entering data on the recovery rate of one element into the fourth register, fifth information input for transmitting a single signal to the fifth register, sixth information input,designed to transmit a single signal to the fifth block of AND elements, a seventh information input designed to input data on the value of the system recovery waiting time, a first information output designed to output the value of the system failure rate, a second information output designed to output the value of the mean time between failures of the system, a third information output designed to output the value of the system availability factor, wherein the first, second, third, fourth and fifth information inputs are connected to the first, second, third, fourth and fifth registers respectively, the output of the first register is connected to the input of the adder, the output of the second register is connected in parallel to the inputs of the adder, the increment block, the first exponentiation block, the first factorial calculation block and the subtraction block, the output of the third register is connected to the input of the second exponentiation block,the output of the fourth register is connected to the input of the first exponentiation block, the output of the fifth register is connected in parallel to the inputs of the fourth block of AND elements and the third division block, the output of the adder is connected in parallel to the inputs of the second factorial calculation block and the subtraction block, the output of the increment block is connected to the input of the second exponentiation block, the outputs of the first exponentiation block and the first factorial calculation block are connected through the first block of AND elements to the inputs of the first multiplication block, the output of the subtraction block is connected to the input of the subtraction from unity block, the outputs of the second factorial calculation block and the subtraction from unity block are connected to the inputs of the first division block, the outputs of the first division block and the second exponentiation block are connected through the second block of AND elements to the inputs of the second multiplication block, the outputs of the first and second multiplication blocks are connected through the third block of AND elements to the inputs of the second division block,the output of the second division block is connected to the input of the delay element, the output of the delay element is the first information output of the device, the output of the third division block is the second information output of the device, the seventh information input is connected to the sixth register, the sixth information input and the output of the sixth register are connected to the inputs of the fifth block of AND elements, the output of the third division block is connected in parallel to the inputs of the second delay element, the second adder and the fourth division block, the output of the fifth block of AND elements is connected to the input of the second adder, the output of the second adder is connected to the input of the fourth division block, the output of the second delay element is the second information output of the device, the output of the fourth division block is the third information output of the device, the seventh, eighth and ninth registers, the first, second and third comparators, the eighth, ninth and tenth information inputs, the fourth, fifth, sixth, seventh,the eighth and ninth information outputs of the device, wherein the eighth, ninth and tenth information inputs are connected to the seventh, eighth and ninth registers respectively, the output of the seventh register is connected to the input of the first comparator, the output of the first delay element is additionally connected to the input of the first comparator, the output of the eighth register is connected to the input of the third comparator, the output of the ninth register is connected to the input of the second comparator, the output of the second delay element is additionally connected to the input of the second comparator, the output of the fourth division unit is additionally connected to the input of the third comparator, the first output of the first comparator is the fourth information output of the device, the second output of the first comparator is the fifth information output of the device, the first output of the second comparator is the sixth information output of the device, the second output of the second comparator is the seventh information output of the device,the first output of the third comparator is the eighth information output of the device, the second output of the third comparator is the ninth information output of the device.,

[0008] The purpose of creating a utility model is to create a technical means for a specific purpose (calculation of reliability indicators - failure rate, mean time between failures and the availability factor of a redundant system with recovery, followed by their assessment in accordance with specified criteria).

[0009] Determination of failure rate (λ рс ) of the redundant system is carried out according to the formula:

[0010]

[0011] where N is the number of system elements;

[0012] n - the number of backup system elements;

[0013] - failure rate of one element of the system;

[0014] - the intensity of restoration of one element of the system.

[0015] Determination of mean time between failures the redundant system is carried out according to the formula:

[0016]

[0017] Determination of the readiness factor (K Г ) of the redundant system is carried out according to the formula:

[0018]

[0019] where - recovery waiting time.

[0020] To evaluate the calculated value of the failure rate of a redundant system with recovery, the following evaluation criterion is formulated:

[0021]

[0022] where - the maximum (specified) value of the failure rate of a redundant system with recovery.

[0023] To evaluate the calculated value of the mean time between failures of a redundant system with recovery, the following evaluation criterion is formulated:

[0024]

[0025] where - minimum (specified) value of the mean time between failures of a redundant system with recovery.

[0026] To evaluate the calculated value of the availability factor of a redundant system with recovery, the following evaluation criterion is formulated:

[0027]

[0028] where - minimum (specified) value of the availability coefficient of the redundant system with recovery.

[0029] The calculation of reliability indicators in the presented device is implemented in accordance with the relations (1)-(3), and their assessment is in accordance with the criteria (4)-(6).

[0030] The figure in Fig. 1 shows the structural diagram of the device.

[0031] The device comprises a first register 1 intended for recording the number of main elements of the system, a second register 2 intended for recording the number of backup elements of the system, a third register 3 intended for recording the value of the failure rate of one element, a fourth register 4 intended for recording the value of the recovery rate of one element, a fifth register 5 intended for recording a single value upon receipt of a single signal at its input, a sixth register 6 intended for recording the value of the system recovery waiting time, a seventh register 40 intended for recording the maximum (specified) value of the failure rate of the redundant system with recovery, an eighth register 43 intended for recording the minimum (specified) value of the availability coefficient of the redundant system with recovery, a ninth register 45,designed to record the minimum (specified) value of the mean time between failures of the redundant system with recovery, adder 7 designed to sum the data coming from the first and second registers 1, 2, the second adder 27 designed to sum the data coming through the fifth block of AND elements 26 from the sixth bis register of the third division block 23, increase by one block 8, the first and second exponentiation blocks 9, 10, the first and second factorial calculation blocks 11, 14, subtraction block 12, the first, second, third, fourth and fifth blocks of AND elements 13, 18, 20, 21, 26, subtraction from unity block 15, the first and second multiplication blocks 16, 19, the first, second, third and fourth division blocks 17, 22, 23, 28, the first and second delay elements 24, 25, the first information input 29, designed for entering data on the number of main elements of the system into the first register 1, the second information input 30,intended for inputting data on the number of redundant elements of the system into the second register 2, the third information input 31, intended for inputting data on the value of the failure rate of one element into the third register 3, the fourth information input 32, intended for inputting data on the value of the recovery rate of one element into the fourth register 4, the fifth information input 33, intended for transmitting a single signal to the fifth register 5, the sixth information input 34, intended for transmitting a single signal to the fifth block of AND elements 26, the seventh information input 35, intended for inputting data on the value of the waiting time for system recovery, the eighth information input 39, intended for inputting data on the maximum (specified) value of the failure rate of the redundant system with recovery into the seventh register 40, the ninth information input 42,intended for inputting data on the minimum (specified) value of the availability coefficient of the redundant system with restoration into the eighth register 43, the tenth information input 44, intended for inputting data on the minimum (specified) value of the mean time between failures of the redundant system with restoration into the ninth register 45, the first comparator 41, intended for direct comparison of the maximum (specified) value of the failure rate of the redundant system with restoration, received from the seventh register 40, and the calculated value of the failure rate of the system, received from the delay element 24, the second comparator 46, intended for direct comparison of the minimum (specified) value of the mean time between failures of the redundant system with restoration, received from the ninth register 45, and the calculated value of the mean time between failures of the system, received from the second delay element 25, the third comparator 47,designed for direct comparison of the minimum (specified) value of the redundant system availability factor with recovery received from the eighth register 43 and the calculated value of the system availability factor received from the fourth division block 28, the first information output 36 designed to output the value of the system failure rate, the second information output 37 designed to output the value of the system average time between failures, the third information output 38 designed to output the value of the system availability factor, the fourth information output 48 designed to output a single value in the event that the calculated value of the system failure rate received from the delay element 24 is less than or equal to the maximum (specified) value of the redundant system failure rate with recovery received from the seventh register 40, the fifth information output 49,designed to output a single value in the event that the calculated value of the system failure rate received from the delay element 24 is greater than the maximum (specified) value of the failure rate of the redundant system with recovery received from the seventh register 40, the sixth information output 50, designed to output a single value in the event that the calculated value of the mean time between failures of the system received from the second delay element 25 is greater than or equal to the minimum (specified) value of the mean time between failures of the redundant system with recovery received from the ninth register 45, the seventh information output 51, designed to output a single value in the event that the calculated value of the mean time between failures of the system received from the second delay element 25 is less than the minimum (specified) value of the mean time between failures of the redundant system with recovery,received from the ninth register 45, the eighth information output 52, intended for outputting a single value, in the event that the calculated value of the system readiness factor received from the fourth division block 28 is greater than or equal to the minimum (specified) value of the readiness factor of the redundant system with recovery received from the eighth register 43, the ninth information output 53, intended for outputting a single value, in the event that the calculated value of the system readiness factor received from the fourth division block 28 is less than the minimum (specified) value of the readiness factor of the redundant system with recovery received from the eighth register 43.,

[0032] The first, second, third, fourth, fifth and seventh information inputs 29-33, 35 are connected to the first, second, third, fourth, fifth and sixth registers 1-6 respectively, the sixth information input 34 is connected to the fifth block of AND elements 26, the eighth, ninth and tenth information inputs 39, 42, 44 are connected to the seventh, eighth and ninth registers 40, 43, 45 respectively, the output of the first register 1 is connected to the input of the adder 7, the output of the second register 2 is connected in parallel to the inputs of the adder 7, the increment block 8, the first exponentiation block 9, the first factorial calculation block 11 and the subtraction block 12, the output of the third register 3 is connected to the input of the second exponentiation block 10, the output of the fourth register 4 is connected to the input of the first exponentiation block to the power of 9, the output of the fifth register 5 is connected in parallel with the inputs of the fourth block of AND elements 21 and the third division block 23,the output of the sixth register 6 is connected to the input of the fifth block of AND elements 26, the output of the adder 7 is connected in parallel to the inputs of the second factorial calculation block 14 and the subtraction block 12, the output of the increase-by-one block 8 is connected to the input of the second exponentiation block 10, the outputs of the first exponentiation block 9 and the first factorial calculation block 11 are connected through the first block of AND elements 13 to the inputs of the first multiplication block 16, the output of the subtraction block 12 is connected to the input of the subtraction from one block 15, the outputs of the second factorial calculation block 14 and the subtraction from one block 15 are connected to the inputs of the first division block 17, the outputs of the first division block 17 and the second exponentiation block 10 are connected through the second block of AND elements 18 to the inputs of the second multiplication block 19, the outputs of the first and second multiplication blocks 16, 19 are connected through the third block of AND elements 20 to the second division block 22,the output of the second division unit 22 is connected in parallel to the inputs of the first delay element 24 and the fourth block of AND elements 21, the output of the fourth block of AND elements 21 is connected to the third division unit 23, the output of the fifth block of AND elements 26 is connected to the input of the second adder 27, the output of the third division unit 23 is connected in parallel to the inputs of the second delay element 25, the second adder 27 and the fourth division unit 28, the output of the second adder 27 is connected to the input of the fourth division unit 28, the output of the first delay element 24 is the first information output of the device 36, the output of the second delay element 25 is the second information output of the device 37, the output of the fourth division unit 28 is the third information output of the device 38, the output of the seventh register 40 is connected to the input of the first comparator 41, the output of the first delay element 24 is additionally connected to the input of the first comparator 41, the output of the eighth register 43 is connected to the input of the third comparator 47,the output of the ninth register 45 is connected to the input of the second comparator 46, the output of the second delay element 25 is additionally connected to the input of the second comparator 46, the output of the fourth division block 28 is additionally connected to the input of the third comparator 47, the first output of the first comparator 41 is the fourth information output of the device 48, the second output of the first comparator 41 is the fifth information output of the device 49, the first output of the second comparator 46 is the sixth information output of the device 50, the second output of the second comparator 46 is the seventh information output of the device 51, the first output of the third comparator 47 is the eighth information output of the device 52, the second output of the third comparator 47 is the ninth information output of the device 53.,

[0033] The factorial calculating device can be used as a factorial calculating unit [USSR Patent for Invention No. 1297071].

[0034] The device operates as follows. The first, second, third, and fourth information inputs 29-32 receive data on the number of primary system elements, the number of backup system elements, and the failure rate of one element. and the value of the intensity of recovery of one element which are written into the first, second, third, and fourth registers 1-4, respectively. If it is necessary to calculate the mean time between failures of the system A single signal is applied to the fifth information input 33. If there is no single signal at the fifth information input 33, the system's mean time between failures will not be calculated. If it is necessary to calculate the system's availability factor (K Г ) a single signal is sent to the sixth information input 34, and data on the system recovery waiting time is sent to the seventh information input 35 In the absence of a single signal at the sixth information input 34, the system availability factor will not be calculated. The eighth, ninth, and tenth information inputs 39, 42, 44 receive data on the maximum (specified) failure rate of the redundant system with recovery, the minimum (specified) availability factor of the redundant system with recovery, and the minimum (specified) mean time between failures of the redundant system with recovery, which are recorded in the seventh, ninth, and eighth registers 39, 44, 43, respectively.

[0035] From the first register 1, the data on the number of primary system elements is sent to the first adder 7. From the second register 2, the data on the number of backup system elements is sent to the first adder 7, to the incrementing unit 8, to the first exponentiation unit 9, as the power of the number being raised, to the first factorial calculation unit 11, and to the subtraction unit 12, as the number being subtracted. From the third register 3, the data on the failure rate of one element is sent to the second exponentiation unit 10, as the number being raised to the power. From the incrementing unit 8, the data is sent to the second exponentiation unit 10, as the power of the number being raised. From the fourth register 4, the data on the recovery rate of one element is sent to the first exponentiation unit 9, as the number being raised to the power.From adder 7, data goes to second factorial calculation block 14 and to subtraction block 12, as a minuend. From first raising to the power of 9 block and first factorial calculation block 11, data goes through the first block of AND elements 13 to first multiplication block 16. From subtraction block 12, data goes to subtraction from one block 15. From subtraction from one block 15, data goes to first division block 17, as a divisor. From second factorial calculation block 14, data goes to first division block 17, as a dividend. From first division block 17 and second raising to the power of 10 block, data goes through the second block of AND elements 18 to second multiplication block 19. From first multiplication block 16, data goes through the third block of AND elements 20 to second division block 22, as a divisor. From the second multiplication block 19, the data is fed through the third block of AND elements 20 to the second division block 22 as a dividend.From the second division block 22 data representing the value of the failure rate of the redundant system (λ. рс ), through the first delay element 24, they are fed to the first information output of the device 36.

[0036] When a one signal is received at the fifth information input 33, the value of one is written to the fifth register 5. From the fifth register 5, the data through the fourth block of AND elements 21 is fed to the input of the third division block 23 as a dividend, while from the second division block 22, the calculation result is fed through the fourth block of AND elements 21 to the third division block 23 as a divisor. From the third division block 23, the data representing the value of the mean time between failures of the system through the second delay element 25 they are fed to the second information output of the device 37.

[0037] When a single signal is received at the sixth information input 34, and data on the system recovery waiting time is received at the seventh information input The waiting time data is written to the sixth register bis of the sixth register 6 through the fifth block of AND elements 26 and goes to the second adder 27. The data from the third division block 23 goes to the second adder 27 and to the fourth division block 28 as a dividend. From the second adder 27, the data goes to the fourth division block 28 as a divider. From the fourth division block 28, the data representing the value of the system readiness factor (K Г ), are sent to the third information output of device 38.

[0038] From the seventh register 40, the data on the maximum (set) value of the failure rate of the redundant system with recovery, as well as the data on the calculated value of the failure rate of the system from the first delay unit 24 are sent to the first comparator 41. In the event that the calculated value of the failure rate of the system is less than or equal to the maximum (set) value of the failure rate of the redundant system with recovery, the first comparator outputs a value of one to the fourth information output of the device 48. In the event that the calculated value of the failure rate of the system is greater than the maximum (set) value of the failure rate of the redundant system with recovery, the first comparator outputs a value of one to the fifth information output of the device 48.

[0039] From the eighth register 43, the data on the minimum (set) value of the readiness factor of the redundant system with recovery, as well as the data on the calculated value of the readiness factor of the system from the fourth division block 28 are sent to the third comparator 47. In the case when the calculated value of the readiness factor of the system is greater than or equal to the minimum (set) value of the readiness factor of the redundant system with recovery, the third comparator 47 outputs a value of one to the eighth information output of the device 52. In the case when the calculated value of the readiness factor of the system is less than the minimum (set) value of the readiness factor of the redundant system with recovery, the third comparator 47 outputs a value of one to the ninth information output of the device 53.

[0040] From the ninth register 45, the data on the minimum (set) value of the mean time between failures of the redundant system with recovery, as well as the data on the calculated value of the mean time between failures of the system from the second delay unit 25 are sent to the second comparator 46. In the case when the calculated value of the mean time between failures of the system is greater than or equal to the minimum (set) value of the mean time between failures of the redundant system with recovery, the second comparator 46 outputs a value of one to the sixth information output of the device 50. In the case when the calculated value of the mean time between failures of the system is less than the minimum (set) value of the mean time between failures of the redundant system with recovery, the second comparator 46 outputs a value of one to the seventh information output of the device 51.

[0041] Thus, when creating a utility model, the technical problem of creating a tool for a specific purpose (calculation of reliability indicators - failure rate, mean time between failures and the availability factor of a redundant system with recovery with their subsequent evaluation in accordance with specified criteria) was solved.

[0042] The claimed utility model is a technical solution related to a device, as the utility model formula contains a set of essential features related to the device (namely, a list of the elements used and the relationships between them) sufficient to solve the stated problem and achieve the technical result. These features are considered essential because they affect the possibility of achieving the technical result, i.e., they are causally related to the stated result. The absence of one or more features will render the device inoperable and prevent the claimed result from being achieved.

[0043] The implementation and use of the proposed utility model allows for the calculation of reliability indicators of redundant systems with recovery (failure rate, mean time between failures, system availability factor) taking into account a set of initial data, as well as the evaluation of the obtained indicators in accordance with the established criteria.

[0044] The described device can be implemented using units and blocks known in the field of radio electronics, connected to each other, ensuring constructive and functional unity.

Claims

A device for calculating the reliability indicators of redundant systems with recovery, comprising a first register intended for recording the number of main elements of the system, a second register intended for recording the number of backup elements of the system, a third register intended for recording the failure rate of one element, a fourth register intended for recording the recovery rate of one element, a fifth register intended for recording a single value upon receipt of a single signal at its input, an adder intended for summing data coming from the first and second registers, an increment unit, first and second exponentiation units, first and second factorial calculation units, a subtraction unit, first, second, third and fourth AND element units, a subtraction from unity unit, first and second multiplication units, first, second and third division units, a delay element, a first information input,designed to input data on the number of main elements of the system into the first register, a second information input designed to input data on the number of backup elements of the system into the second register, a third information input designed to input data on the value of the failure rate of one element into the third register, a fourth information input designed to input data on the value of the recovery rate of one element into the fourth register, a fifth information input designed to transmit a single signal to the fifth register, a first information output designed to output the value of the failure rate of the system, a second information output designed to output the value of the average time between failures of the system, a sixth register designed to record the value of the waiting time for the recovery of the system, a fifth block of AND elements, a second adder designed to sum the data,coming through the fifth block of AND elements from the sixth register and from the third division block, the fourth division block, the second delay element, the sixth information input intended for transmitting a single signal to the fifth block of AND elements, the seventh information input intended for inputting data on the value of the system recovery waiting time, the third information output intended for outputting the value of the system readiness coefficient, wherein the first, second, third, fourth and fifth information inputs are connected to the first, second, third, fourth and fifth registers respectively, the output of the first register is connected to the input of the adder, the output of the second register is connected in parallel to the inputs of the adder, the increment block, the first exponentiation block, the first factorial calculation block and the subtraction block, the output of the third register is connected to the input of the second exponentiation block,the output of the fourth register is connected to the input of the first exponentiation block, the output of the fifth register is connected in parallel to the inputs of the fourth block of AND elements and the third division block, the output of the adder is connected in parallel to the inputs of the second factorial calculation block and the subtraction block, the output of the increment block is connected to the input of the second exponentiation block, the outputs of the first exponentiation block and the first factorial calculation block are connected through the first block of AND elements to the inputs of the first multiplication block, the output of the subtraction block is connected to the input of the subtraction from unity block, the outputs of the second factorial calculation block and the subtraction from unity block are connected to the inputs of the first division block, the outputs of the first division block and the second exponentiation block are connected through the second block of AND elements to the inputs of the second multiplication block, the outputs of the first and second multiplication blocks are connected through the third block of AND elements to the inputs of the second division block,the output of the second division block is connected to the input of the delay element, the output of the delay element is the first information output of the device, the seventh information input is connected to the sixth register, the sixth information input and the output of the sixth register are connected to the inputs of the fifth block of AND elements, the output of the third division block is connected in parallel to the inputs of the second delay element, the second adder and the fourth division block, the output of the fifth block of AND elements is connected to the input of the second adder, the output of the second adder is connected to the input of the fourth division block, the output of the second delay element is the second information output of the device, the output of the fourth division block is the third information output of the device, characterized in that a seventh register intended for recording the maximum (specified) value of the failure rate of the redundant system with recovery, an eighth register are introduced into the device,designed to record the minimum (specified) value of the availability coefficient of the redundant system with recovery, the ninth register designed to record the minimum (specified) value of the mean time between failures of the redundant system with recovery, the eighth information input designed to enter data on the maximum (specified) value of the failure rate of the redundant system with recovery into the seventh register, the ninth information input designed to enter data on the minimum (specified) value of the availability coefficient of the redundant system with recovery into the eighth register, the tenth information input designed to enter data on the minimum (specified) value of the mean time between failures of the redundant system with recovery into the ninth register, the first comparator designed to directly compare the maximum (specified) value of the failure rate of the redundant system with recovery,received from the seventh register and the calculated value of the system failure rate received from the delay element, the second comparator, designed for direct comparison of the minimum (specified) value of the mean time between failures of the redundant system with restoration, received from the ninth register, and the calculated value of the system mean time between failures, received from the second delay element, the third comparator, designed for direct comparison of the minimum (specified) value of the availability factor of the redundant system with restoration, received from the eighth register, and the calculated value of the system availability factor, received from the fourth division block, the fourth information output, designed to output a single value, in the case when the calculated value of the system failure rate, received from the delay element, is less,or equal to the maximum (specified) value of the failure rate of the redundant system with recovery received from the seventh register, the fifth information output, intended for outputting a single value, in the case when the calculated value of the failure rate of the system received from the delay element is greater than the maximum (specified) value of the failure rate of the redundant system with recovery received from the seventh register, the sixth information output, intended for outputting a single value, in the case when the calculated value of the mean time between failures of the system received from the second delay element is greater, or equal to the minimum (specified) value of the mean time between failures of the redundant system with recovery received from the ninth register, the seventh information output, intended for outputting a single value, in the case when the calculated value of the mean time between failures of the system,received from the second delay element is less than the minimum (specified) value of the mean time between failures of the redundant system with recovery received from the ninth register, the eighth information output, intended for outputting a single value, in the event that the calculated value of the system availability factor received from the fourth division block is greater than or equal to the minimum (specified) value of the system availability factor with recovery received from the eighth register, the ninth information output, intended for outputting a single value, in the event that the calculated value of the system availability factor received from the fourth division block is less than the minimum (specified) value of the system availability factor with recovery received from the eighth register, wherein the eighth, ninth and tenth information inputs are connected to the seventh,the eighth and ninth registers, respectively, the output of the seventh register is connected to the input of the first comparator, the output of the first delay element is additionally connected to the input of the first comparator, the output of the eighth register is connected to the input of the third comparator, the output of the ninth register is connected to the input of the second comparator, the output of the second delay element is additionally connected to the input of the second comparator, the output of the fourth division block is additionally connected to the input of the third comparator, the first output of the first comparator is the fourth information output of the device, the second output of the first comparator is the fifth information output of the device, the first output of the second comparator is the sixth information output of the device, the second output of the second comparator is the seventh information output of the device, the first output of the third comparator is the eighth information output of the device,the second output of the third comparator is the ninth information output of the device.,

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