Wideband two-stage low-noise distributed gain amplifier

Abstract

The utility model relates to the field of ultra-high-frequency radio electronics. The technical result consists in expanding the operating frequency range to 67 GHz and is achieved in that the broadband two-stage low-noise distributed gain amplifier contains the first and second stages connected to the power supply circuits, connected in series through a decoupling capacitor (40). Each stage contains an input (3, 4, 5) and output (37, 38, 39) transmission lines and four cascode cells (41, 42, 43, 44) connected thereto. The transistors of the cascode cells with a common gate (6, 7, 8, 9) and a common source (10, 11, 12, 13) are made with a gate width of 25 μm, which reduces the parasitic capacitance of the gate, increases the maximum operating frequency of the transistors and ensures operation of the amplifier in the frequency range from 13 to 67 GHz. 4 z.p. f-ly, 8 ill.

Description

[0001] Technical field

[0002] The utility model relates to the field of ultra-high frequency (UHF) radio electronics, namely to microwave signal amplification devices, and can be used in microwave transceiver units, in particular in control and measuring equipment.

[0003] Technology Level

[0004] A two-stage distributed gain amplifier from MACOM Technology Solutions (URL: https: / / cdn.macom.com / datasheets / XD1001-BD.pdf, accessed 01 / 31 / 2026) is known. It is implemented in a monolithic integrated design, provides a gain of 17 dB in the frequency band of 18 - 50 GHz, a noise figure of 5 - 5.5 dB in the frequency band of 18 - 30 GHz. The amplifier circuit contains two gain cascades connected in series through a coupling capacitor, each of which is built according to the distributed gain scheme. The power supply circuits for the two cascades are combined and include series-connected resistors and grounded capacitors to provide filtering of the alternating signal.

[0005] The main disadvantage of the above solution is the use of the classic distributed amplification scheme, which, in turn, leads to a sharp deterioration in the gain, as well as a deterioration in the noise figure in the frequency range of 40 - 50 GHz due to the Miller effect.

[0006] A two-stage distributed gain amplifier is known (AA Babenko, G. Lasser, Z. Popovic "0.01-22-GHz Feedback-Stabilized Single-Supply GaAs Cascode Distributed Amplifiers", IEEE Microwave and Wireless Components Letters, 2021), which is closest in essence to the claimed device, in which each stage is implemented in the form of a cascode distributed gain amplifier containing five cascode cells, and the two-stage device is formed by two identical cascades connected via an interstage capacitor. For stabilization, an RC feedback circuit is used in each cascode cell, connected between the drain and gate of a transistor with a common gate.

[0007] The disadvantage of the prototype is the inability to expand the operating frequency range to 67 GHz.

[0008] The essence of the utility model

[0009] The main technical task is to create a broadband two-stage low-noise amplifier with distributed gain, which will eliminate the shortcomings of the prototype.

[0010] The technical result is to expand the operating frequency range to 67 GHz.

[0011] The technical result is achieved due to the fact that in a broadband two-stage low-noise distributed gain amplifier, containing the first and second stages of the distributed gain amplifier connected to the power supply circuits, connected in series through a separating capacitor, wherein each stage contains an input transmission line, an output transmission line and cascode cells connected to them, according to the proposed solution, the number of cascode cells is equal to four, and the gate width of the cascode cell transistors is 25 μm.

[0012] In a particular case of implementation, stabilizing resistors are connected in parallel to the corresponding sections of the output transmission line.

[0013] In a particular case of implementation, additional voltage dividers are connected in parallel to the power supply and bias circuits of the cascades.

[0014] In a particular case of implementation, RC circuits are connected to the gates of transistors with a common gate of cascode cells.

[0015] In a particular case of implementation, the bias circuit of transistors with a common source contains a voltage divider with connection points to the first and second stages.

[0016] Brief description of drawings

[0017] The implementation of the claimed utility model is explained by graphic materials, which show:

[0018] Fig. 1 - electrical circuit of one stage of a distributed gain amplifier;

[0019] Fig. 2 - electrical circuit of the power supply circuit Vd and the bias circuit Vg2;

[0020] Fig. 3 - electrical circuit of the bias circuit Vg1;

[0021] in Fig. 4 - frequency dependence of the gain coefficient obtained during operation of the device;

[0022] in Fig. 5 - frequency dependence of return losses at the input, obtained during operation of the device;

[0023] in Fig. 6 - frequency dependence of return losses at the output, obtained during operation of the device;

[0024] in Fig. 7 - frequency dependence of the noise figure obtained during operation of the device;

[0025] Fig. 8 - frequency dependence of the output power with compression of 1 dB, obtained during operation of the device.

[0026] The claimed device is designated as follows:

[0027] 1 - cascade input;

[0028] 2 - input decoupling capacitor;

[0029] 3, 4, 5 - sections of the input transmission line;

[0030] 6, 7, 8, 9 - transistors connected in a common gate circuit;

[0031] 10, 11, 12, 13 - transistors connected in a common source circuit;

[0032] 14, 15, 16, 17, 18, 19, 20 - resistors decoupling the DC and microwave bias circuits of Vg2;

[0033] 21, 22, 23, 24 - resistors of the bias circuits of the gates of transistors 6, 7, 8, 9, respectively, of the Vg2 circuit;

[0034] 25, 26, 27, 28 - resistors connecting the nodes of the Vg2 bias circuits with the gates of transistors 6, 7, 8, 9, respectively;

[0035] 29, 30, 31, 32 - capacitors of the bias circuits of the gates of transistors 6, 7, 8, 9, respectively;

[0036] 33, 34, 35 - stabilizing resistors of the power supply circuit Vd;

[0037] 36 - a capacitor connecting the output transmission line to the common bus;

[0038] 37, 38, 39 - sections of the output transmission line;

[0039] 40 - output decoupling capacitor;

[0040] 41, 42, 43, 44 - cascode cells;

[0041] 45 - cascade output;

[0042] 46, 47, 48 - supply voltage divider resistors Vd;

[0043] 49 - bias circuit resistor Vg2;

[0044] 50, 51 - sections of supply voltage lines Vd;

[0045] 52, 53, - filter capacitors of the power supply circuit Vd;

[0046] 54 - bias circuit filter capacitor Vg2;

[0047] 55, 56, 57 - bias circuit voltage divider resistors Vg1;

[0048] 58, 59 - resistors decoupling the DC and microwave bias circuits of Vg1;

[0049] 60, 61 - filter capacitors of the bias circuit Vg1;

[0050] TL - transmission line;

[0051] Vd - power supply circuit;

[0052] Vg1, Vg2 - bias circuits;

[0053] GND - ground.

[0054] The claimed broadband two-stage low-noise distributed amplifier contains first and second stages of a distributed amplifier, made of the same type according to the electrical circuit (Fig. 1), connected to the power supply circuit Vd and the bias circuit Vg2 (Fig. 2), and to the bias circuit Vg1 (Fig. 3).

[0055] Each cascade contains input 1, connected via input coupling capacitor 2 to the input transmission line formed by sections 3, 4 and 5. Transistors 10, 11, 12 and 13, connected in a common-source configuration, are connected to the nodes of the input transmission line. Together with transistors 6, 7, 8 and 9, connected in a common-gate configuration, transistors 10, 11, 12 and 13 form the first, second, third and fourth cascode cells 41, 42, 43 and 44, respectively. The implementation of each cascade with four cascode cells ensures a reduction in the total parasitic capacitive load of the input and output transmission lines and contributes to a shift in the upper limit of the operating range to higher frequencies.

[0056] Transistors 6, 7, 8, 9, 10, 11, 12, and 13 are designed with a gate width of 25 µm. This gate width was chosen to expand the amplifier's operating frequency range. With a fixed gate length determined by the transistor's manufacturing technology, the gate width determines the area of ​​the gate region and, consequently, affects the gate capacitance. Decreasing the gate width reduces the gate area and associated parasitic capacitive components. Reducing the gate capacitance increases the transistor's maximum operating frequency. Therefore, designing transistors with a gate width of 25 µm helps expand the amplifier's operating frequency range as a whole.

[0057] The gates of transistors 6, 7, 8 and 9, connected in a common gate circuit, are connected to the bias circuit Vg2 through resistors 14, 15, 16, 17, 18, 19 and 20, which form a decoupling line for direct current and microwave, as well as through individual bias nodes made on resistors 21, 22, 23 and 24, resistors 25, 26, 27 and 28 and capacitors 29, 30, 31 and 32. In this case, resistors 25, 26, 27 and 28 and capacitors 29, 30, 31 and 32 form RC circuits connected to the gates of transistors 6, 7, 8 and 9.

[0058] The output transmission line of the first and second amplifier stages is formed by sections 37, 38, and 39, with stabilizing resistors 33, 34, and 35 of the Vd power supply circuit connected in parallel. One end of the output transmission line is connected to the common bus via capacitor 36, and the other end is connected to output 45 via output coupling capacitor 40 to the next stage. Cascode cells 41, 42, 43, and 44 are connected to the corresponding nodes of the output transmission line.

[0059] The power supply Vd and bias Vg2 circuits (Fig. 2) contain resistors 46, 47 and 48, which form a voltage divider of the power supply Vd circuit. In this case, resistor 47 connects the Vd node to the upper filtering node, which is connected to the power supply circuit of the first stage through a section of the transmission line 50 and through a capacitor 52 to the common bus. Resistor 46 connects the Vd power supply node to the lower filtering node, which is connected to the power supply circuit of the second stage through a section of the line 51 and through a capacitor 53 to the common bus. Resistor 48 connects the Vd power supply node to the Vg2 bias node. The Vg2 node is connected to the common bus through resistor 49 and capacitor 54.

[0060] The bias circuit Vg1 (Fig. 3) contains resistors 55, 56 and 57, which form a voltage divider of the bias circuit Vg1 with connection points to the first and second stages. The bias of the first stage is connected through resistor 59 to the first node of the bias circuit, which is connected through resistor 55 to node Vg1 and through capacitor 61 to the common bus. The bias of the second stage is connected through resistor 58 to the second node of the bias circuit, which is connected through resistor 57 to node Vg1 and through capacitor 60 to the common bus. Resistor 56 connects node Vg1 to the common bus.

[0061] The claimed amplifier operates as follows.

[0062] Bias voltage Vg1 from the bias circuit (Fig. 3) is applied to the gates of transistors 10, 11, 12 and 13, connected in a common-source configuration and included in cascode cells 41, 42, 43 and 44. Bias voltage Vg1 is formed by a voltage divider formed by resistors 55, 56 and 57, and through resistors 58 and 59, which decouple DC and microwave along the Vg1 circuit, it is supplied, respectively, to the first and second stages of the amplifier, setting the required operating modes of transistors 10, 11, 12 and 13 in each stage.

[0063] The supply voltage Vd and the bias voltage Vg2 are simultaneously generated from the power supply node (Fig. 2). The supply voltage Vd is supplied through resistors 46, 47, sections of lines 50, 51 and filter capacitors 52, 53 to the power supply circuits of the cascades, and then to the cascode cells 41, 42, 43 and 44. The bias voltage Vg2 is generated from the Vd node through the resistor 48, while the Vg2 node is connected to the common bus through the resistor 49 and the capacitor 54. Then, the bias voltage Vg2 is supplied through resistors 14, 15, 16, 17, 18, 19 and 20 to the bias circuits of the gates of transistors 6, 7, 8 and 9, connected in a circuit with a common gate.

[0064] The input microwave signal is fed to input 1 of the first stage and transmitted through the input decoupling capacitor 2 to the input transmission line formed by sections 3, 4 and 5. From the input transmission line, the signal is sequentially fed to transistors 10, 11, 12 and 13. In each cascode cell 41, 42, 43 and 44, the signal is amplified by a pair of transistors consisting of a corresponding common-source transistor 10, 11, 12, 13 and a corresponding common-gate transistor 6, 7, 8, 9. Since each stage contains four cascode cells 41, 42, 43 and 44, the total parasitic capacitive load on the input and output transmission lines is reduced compared to a more multi-link structure of the cascade, as a result of which the signal attenuation in the upper part of the frequency band and the upper limit of the operating range are reduced shifts to the region of higher frequencies.

[0065] Transistors 6, 7, 8, 9, 10, 11, 12, and 13 are designed with a gate width of 25 µm. When a signal passes through the cascode cells, this gate width reduces the gate area and associated parasitic capacitance components, thereby increasing the transistors' maximum operating frequency. This allows the cascode cells to maintain performance at higher frequencies, which helps expand the amplifier's overall operating range and reduces the noise figure in the 18-50 GHz band (less than 5.5 dB).

[0066] The amplified signals from the cascode cells enter the output transmission line formed by sections 37, 38, and 39, where they are summed in phase. The amplified signal is then transferred via output coupling capacitor 40 and output 45 of the first stage to the second stage, where the signal is similarly amplified. The amplified signal is then fed to the device output. Stabilizing resistors 33, 34, and 35, connected in parallel to the corresponding sections 37, 38, and 39 of the output transmission line, provide additional stabilization of the stages. RC circuits formed by resistors 25, 26, 27, 28 and capacitors 29, 30, 31, 32 and connected to the gates of transistors 6, 7, 8 and 9 provide increased stability at limiting frequencies by increasing the real component of the gate impedance, as well as damping potential oscillations, preventing self-excitation.

[0067] Using stabilizing resistors 33-35 connected in parallel to the corresponding sections of the output transmission line helps to increase the stability of the device during operation, as they increase real losses and weaken parasitic positive feedback.

[0068] Example of execution.

[0069] As an example of a specific implementation, prototypes of the claimed utility model in a monolithic integrated circuit were developed and manufactured. Testing of the prototypes showed that the claimed utility model provides an operating frequency range of 13-67 GHz and a noise figure of less than 5.5 dB in the frequency band of 18-50 GHz (Figs. 4-8), confirming the claimed result.

Claims

1. A broadband two-stage low-noise distributed gain amplifier comprising first and second stages of the distributed gain amplifier connected to power supply circuits and connected in series through a decoupling capacitor, wherein each stage comprises an input transmission line, an output transmission line and cascode cells connected to them, characterized in that the number of cascode cells is four, and the gate width of the cascode cell transistors is 25 μm.

2. A broadband two-stage low-noise distributed amplifier according to claim 1, characterized in that stabilizing resistors are connected in parallel to the corresponding sections of the output transmission line.

3. A broadband two-stage low-noise distributed amplifier according to claim 1, characterized in that additionally introduced voltage dividers are connected in parallel to the power supply and bias circuits of the stages.

4. A broadband two-stage low-noise distributed gain amplifier according to claim 1, characterized in that RC circuits are connected to the gates of the transistors with a common gate of the cascode cells.

5. A broadband two-stage low-noise distributed gain amplifier according to claim 1, characterized in that the bias circuit of the transistors with a common source contains a voltage divider with connection points to the first and second stages.

Images