Phase-locked loop

Abstract

This utility model relates to oscillation generation technology and can be used to stabilize the parameters of oscillators. The technical result consists of reducing the hardware costs of implementing the device's automatic loop. A phase-locked loop (PLL) device is proposed for this purpose. It comprises a phase detector, the first input of which is the device input, and the second input is connected to the device output and connected to the output of a controlled oscillator. The oscillator's control input is connected to the output of a summing device, the inputs of which are separately connected to the outputs of an integrator and a proportional link. The output of the phase detector is connected to the inputs of a unipolar pulse generator and a bipolar voltage generator. The output of the bipolar voltage generator is connected to the data input of a resettable integrator, the reset input of which is connected to the output of a unipolar pulse generator.The output of the resettable integrator is connected to the inputs of the integrator and the proportional link. 5 fig.

Description

[0001] Technical field

[0002] The utility model relates to radio and measuring equipment and can be used to stabilize the parameters of autogenerators.

[0003] Technology Level

[0004] A phase-locked loop device is known [1], which provides high precision synchronization of the reference and adjustable oscillations and a wide capture band due to the use of reset integrators (zeroable integrators) in the control circuit, which provide a nonlinear change in the output voltage.

[0005] Because the control voltages in this device are generated by different nonlinear resettable integrators, whose parameters are difficult to ensure are identical, it is impossible to implement these voltages with identical waveforms but different signs for the same durations of phase differences of different signs. Therefore, with a periodic change in the sign of the phase difference with a time interval equal to the period of the reference oscillation, which is typical of the synchronization mode of the phase-locked loop (PLL), the voltages at the outputs of the integrators generating control voltages of different signs will differ in magnitude (modulus). Moreover, during the regulation process, the average component of the phase difference between the synchronized reference and adjusted oscillations will differ from zero due to the different effects on the controlled oscillator. This leads to an increase in the steady-state phase error of the reference and adjusted oscillations.

[0006] The closest to the claimed utility model (prototype) is a PLL device [2] containing a phase detector 1 (Fig. 1), the first input of which is the input of the device, and the second input is connected to the output of the device and is connected to the output of the controlled generator 2. The output of the adder 3, the inputs of which are separately connected to the outputs of the integrator 4 and the proportional (static) link 5, is connected to the control input of the generator 2. The output of the phase detector 1 is connected to the inputs of the unipolar pulse generator 8 and the bipolar voltage generator 6, the output of which is connected to the first information input of the resettable integrator 7, the reset input of which is connected to the output of the unipolar pulse generator 8. The output of the resettable integrator 7 is connected to the input of the voltage amplifier 9, the output of which is connected to the second information input of the resettable integrator 7 and the combined inputs integrator 4 and proportional link 5.

[0007] The prototype uses a single nonlinear reset integrator to generate the control signal, implemented using blocks 7 and 9, generating both positive and negative voltages. The use of a single nonlinear resettable integrator improves the synchronization accuracy of the PLL. However, implementing a nonlinear resettable integrator in the PLL requires two blocks. The first block, 7, integrates the input voltage and resets the voltage accumulated by the integrator capacitor. The second block, 9, inverts the output voltage of integrator 7 and forms a positive feedback loop, enabling the implementation of a nonlinear voltage change law at the output of voltage amplifier 9.

[0008] The circuit diagram of the resettable integrator, containing the specified blocks, made on the basis of operational amplifiers (OP), is shown in Fig. 2, where DA1, DA2 are operational amplifiers, R1÷R4 are resistors, C is a capacitor, K is a key, U вх and U вых - input and output voltage, U сбр - integrator reset signal. Implementing positive feedback in the very first block of the resettable integrator by modifying its circuitry will eliminate the need for a second block. In other words, in this case, the disadvantage will be the hardware redundancy of the resettable integrator circuitry.

[0009] Disclosure of the essence of the utility model

[0010] The technical result of the utility model consists in reducing the number of component elements of the PLL device by reducing the hardware redundancy of the resettable integrator, which ensures a reduction in the costs of implementing the device.

[0011] The technical result is achieved by the fact that in the phase-locked loop device, it is proposed to use a modified integrator circuit [3] as a resettable integrator circuit, which is implemented on one operational amplifier DA in a non-inverting connection circuit (Fig. 3). The remaining elements of the circuit in Fig. 3 have designations corresponding to the designations of the elements in Fig. 2.

[0012] If we consider the circuit of the resettable integrator (Fig. 3) in relation to the voltage U c , formed on the capacitor C, it can be seen that the op-amp and resistors R1 and R2 implement a non-inverting voltage amplifier circuit, and when R1 = R2, the gain of this circuit is equal to 2. That is, the output voltage of the integrator will be determined by the formula U вых =2U c , and the potential difference between the “+” input and the output of the operational amplifier will always remain equal to U c .

[0013] The capacitor C is charged by currents, the first of which i1 is determined by the input voltage U вх (let's assume that the voltage U вх =const) and the value of resistance R3. The second current i2 is determined by the output voltage of the integrator U вых and the value of resistance R4. That is, i c =i1+i2(we neglect the current flowing into the op-amp through its “+” input due to its smallness).

[0014] Considering that in the initial state the voltage on the capacitor U c =0 (the integrator is reset by closing the capacitor plates with the contacts of the key K), at U вх >0 current i1=U вх / R3, and current i2=U вых / R4=0. When the contacts of the key K are opened at i1>i2, the capacitor is charged and the voltage U c on it increases, and, as a consequence, U increases вых and i2.

[0015] For case R4 <R3по мере нарастания напряжения U c on the capacitor and its value approaches U вх current i1 tends to zero, and current i2=Uc / R4 has a tendency to increase constantly. The integrator's output voltage also has a tendency to increase. Moreover, at U с >U вх current i1 changes its direction, that is, i2=i1+i с . At the same time, the current i2 grows significantly faster than the current i1, since R4 <R3, и существенная доля тока i2определяет ток заряда конденсатора i с . The latter leads to an increase in the nonlinearity of the integrator's output voltage rise. The proposed integrator operates similarly in the case where U вх <0.

[0016] Thus, the proposed design of a resettable integrator allows for the formation of a voltage at its output with a nonlinear change law similar to the change law of the voltage at the output of the resettable integrator of the prototype, but the resettable integrator itself is implemented using only one op-amp, while in the prototype two op-amps are used for this purpose.

[0017] Implementation of a utility model

[0018] The technical result is achieved in a phase-locked loop device (Fig. 4) containing a phase detector 1, the first input of which is the input of the device, and the second input is connected to the output of the device and is connected to the output of the controlled generator 2. The control input of the generator is connected to the output of the adder 3, the inputs of which are separately connected to the outputs of the integrator 4 and the proportional link 5. The output of the phase detector 1 is connected to the inputs of the unipolar pulse former 8 and the bipolar voltage former 6, the output of the bipolar voltage former 6 is connected to the information input of the resettable integrator 7, the reset input of which is connected to the output of the unipolar pulse former 8. The output of the resettable integrator 7 is connected to the inputs of the integrator 4 and the proportional link 5.

[0019] Integrator with reset when R1=R2=R3=R and R4 <R (фиг. 3) обеспечивает нелинейную форму выходного сигнала, что позволяет при малом времени интегрирования входного напряжения выходное напряжение изменять незначительно. При большом времени интегрирования в интеграторе будет наблюдаться существенное нарастание выходного напряжения.

[0020] Timing diagrams explaining the operating mechanism of the utility model are shown in Fig. 5, where the variables U фд , U фои , U фдн , U у - denote the voltages generated at the output of the phase detector, unipolar pulse generator, bipolar voltage generator, and resettable integrator, respectively. The variables +U and -U denote the bipolar voltage levels.

[0021] The voltage diagrams shown in Fig. 5 show that with frequent changes in the signal at the output of the phase detector, a low level of influence on the controlled generator is ensured (the formation of small in magnitude, identical in shape, but different in sign control voltages U у3 , U у4 ), which results in a low level of phase synchronization noise. With a rare change in the signal at the output of the phase detector, the impact level U y1 The generator's output voltage increases significantly due to the nonlinear increase in voltage at the integrator's output with reset, which ensures greater stability of the PLL and an expanded locking bandwidth. Moreover, these properties are achieved by implementing the PLL with a smaller number of components.

[0022] BIBLIOGRAPHICAL LIST

[0023] 1. A.s. SU No. 1415441 IPC H03L 7 / 00. Phase-locked loop device. / V.F. Odinokov, S.I. Kholopov, M.V. Petrov. Declared 15.12.1986; published 07.08.1988, BI No. 29.

[0024] 2. Patent RU No. 2849752 IPC H03L 7 / 00. Phase-locked loop device. / S.I. Kholopov. Claimed 13.02.2025; published 28.10.2025, BI No. 31.

[0025] 3. Panent US 3470495, Feedback integrator with grounded capacitor / GJ Deboo. Filed Dec. 28.1967; Sept. 30.1969.

Claims

A phase-locked loop device comprising a phase detector, the first input of which is the input of the device, and the second input, connected to the output of the device, is connected to the output of a controlled generator, the input of which is connected to the output of a voltage adder, to the inputs of which the outputs of an integrator and a proportional link are separately connected, the output of the detector is connected to the inputs of a bipolar voltage generator and a unipolar pulse generator, characterized in that a resettable integrator is introduced, implemented on an operational amplifier, the output of which, which is the output of the resettable integrator, is connected to the inputs of the integrator and the proportional link and is connected through the first and second resistors to the inverting and non-inverting inputs of the operational amplifier, respectively, the inverting input of the operational amplifier is connected through a third resistor to a common bus, and the non-inverting input of the operational amplifier is connected to the terminals of an electronic switch and a capacitor,the second terminals of which are connected to the common bus, and through the fourth resistor is connected to the input of the resettable integrator connected to the output of the bipolar voltage generator, the control input of the electronic key is connected to the output of the unipolar pulse generator, the resistance of the second resistor is set to be less than the resistance of the fourth resistor.

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