Class ab gallium arsenide differential stage
By integrating additional bipolar transistors and transient process correction circuits into the GaAs differential cascade, the GaAs operational amplifiers achieve enhanced dynamic performance and increased slew rates, overcoming the limitations of existing GaAs technologies.
Patent Information
- Authority / Receiving Office
- RU · RU
- Patent Type
- Patents
- Current Assignee / Owner
- FEDERALNOE GOSUDARSTVENNOE BYUDZHETNOE OBRAZOVATELNOE UCHREZHDENIE VYSSHEGO OBRAZOVANIYA DONSKOJ GOSUDARSTVENNYJ TEKHNICHESKIJ UNIV DGTU
- Filing Date
- 2025-10-06
- Publication Date
- 2026-06-30
AI Technical Summary
Existing gallium arsenide (GaAs) operational amplifiers face limitations due to the absence of n-p-n transistors, restricting their operation in class AB mode and limiting maximum output voltage slew rates, which impedes their use in high-temperature applications.
Incorporation of additional bipolar transistors and transient process correction circuits, such as p-n junctions and capacitors, into the GaAs differential cascade to enable class AB operation, enhancing dynamic performance.
The proposed solution significantly increases the maximum output voltage slew rate by an order of magnitude, enabling improved dynamic performance in operational amplifiers.
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Abstract
Description
[0001] The proposed invention relates to the microelectronic element base of communication systems, computing technology, instrument making and automation, including those operating at high temperatures.
[0002] In Russian and foreign microelectronics, increased attention is paid to gallium arsenide integrated circuits [1]. However, the features of gallium arsenide technological processes impose significant limitations on the types of transistors implemented and their characteristics [2,3]. A promising gallium arsenide technological process, mastered by the Minsk Research Institute of Radio Materials (https: / / mniirm.by / ) in the interests of the Union State, ensures the creation of only pnp BJT and nJFet transistors. The absence of n-p-n transistors creates problems in the construction of high-temperature GaAs op amps, which are in demand in a number of important branches of science and technology - space instrumentation, oil and gas, automotive and aviation industries. In analog microelectronics, input differential cascades (IDC) on field-effect transistors with a control p-n junction (JFET) with their cascode connection have become widespread [4-8]. The proposed invention belongs to this class of IDC.The practical application of classical cascode JFET DCs in GaAs operational amplifiers (OPA) with low static current consumption does not allow obtaining increased values of the maximum output voltage rise rate (SR).
[0003] The closest prototype of the claimed device is a GaAs differential cascade presented in the article by Bugakov A.V., Dvornikov O.V., Prokopenko N.N., Chekhovsky V.A., Kleimenkin D.V. “Circuitry Features of Designing High-Temperature Analog Microcircuits on GaN and GaAs Transistors” / / Bulletin of SFedU. Technical Sciences. - 2024. - No. 2. - P 202-220. DOI 10.18522 / 2311-3103-2024-2-202-220, Fig. 24”. It contains (Fig.1) the first 1 and second 2 inputs of the device, the first 3 and second 4 current outputs matched with the first 5 power supply bus, the first 6 input field-effect transistor, the gate of which is connected to the first 1 input of the device, the second 7 input field-effect transistor, the gate of which is connected to the second 2 input of the device, the first 8 output field-effect transistor, the source of which is connected to the drain of the first 6 input field-effect transistor, the second 9 output field-effect transistor, the source of which is connected to the drain of the second 7 input field-effect transistor, wherein the combined gates of the first 8 and second 9 output field-effect transistors are connected to the combined sources of the first 6 and second 7 input field-effect transistors, the combined sources of the first 6 and second 7 input field-effect transistors are connected to the second 10 power supply bus through the main 11 reference current source.
[0004] A significant drawback of the prototype differential stage is that it does not operate in class AB mode. Consequently, the maximum output currents of the known differential stage do not exceed the numerical values of the reference current source current in the common source circuit of the input field-effect transistors. This prevents the differential stage from achieving higher maximum output voltage slew rates, given its low static current consumption and its use in operational amplifier designs.
[0005] The primary objective of the proposed invention is to develop a class AB gallium arsenide differential stage (DS) circuit, implemented using a combined GaAs process technology that allows for the creation of only pn-p bipolar and nJFet field-effect transistors. Practical application of the proposed DS in the structure of operational amplifiers allows for significant improvement of its dynamic performance in large-signal mode.
[0006] The stated task is achieved by the fact that in the gallium arsenide differential cascade of Fig. 1, comprising first 1 and second 2 inputs of the device, first 3 and second 4 current outputs matched with the first 5 power supply bus, the first 6 input field-effect transistor, the gate of which is connected to the first 1 input of the device, the second 7 input field-effect transistor, the gate of which is connected to the second 2 input of the device, the first 8 output field-effect transistor, the source of which is connected to the drain of the first 6 input field-effect transistor, the second 9 output field-effect transistor, the source of which is connected to the drain of the second 7 input field-effect transistor, wherein the combined gates of the first 8 and second 9 output field-effect transistors are connected to the combined sources of the first 6 and second 7 input field-effect transistors, the combined sources of the first 6 and second 7 input field-effect transistors are connected to the second 10 power supply bus through the main 11 reference current source,new elements and connections are provided - the first 12 and second 13 additional bipolar transistors are introduced into the circuit, the base of the first 12 additional bipolar transistor is connected to the first 1 input of the device, its collector is connected to the second 10 bus of the power source, and the emitter is connected to the source of the second 9 output field-effect transistor through the first 14 circuit of correction of the transient process, the base of the second 13 additional bipolar transistor is connected to the second 2 input of the device, its collector is connected to the second 10 bus of the power source, and the emitter is connected to the source of the first 8 output field-effect transistor through the second 15 circuit of correction of the transient process, and the first 14 and second 15 circuits of the transient process have three variants of practical implementation: in the first variant of practical implementation (Fig. 2) the first 14 circuit of correction of the transient process contains the first 16 p-n junction and the first 17 matching resistor connected in series,and the second 15 transient correction circuit contains a series-connected second 18 p-n junction and a second 19 matching resistor; in the second embodiment of practical implementation (Fig. 3), the first 14 transient correction circuit is made in the form of a first 23 additional capacitor, wherein the emitter of the first 12 additional bipolar transistor is connected to the first 5 power supply bus through the second 24 additional reference current source, the second 15 transient correction circuit is made in the form of a second 25 additional capacitor, wherein the emitter of the second 13 additional bipolar transistor is connected to the first 5 power supply bus through the third 26 additional reference current source; in the third embodiment of practical implementation (Fig. 4), the first 14 transient correction circuit contains a first 34 additional correction capacitor and a first 35 additional correction resistor connected in parallel,and the second 15 transient process correction circuit contains a second 36 additional correction capacitor and a second 37 additional correction resistor connected in parallel.
[0007] The drawing in Fig. 1 shows a GaAs differential cascade prototype.
[0008] The drawing in Fig. 2 shows a diagram of the claimed GaAs differential stage of class AB for a high-speed op amp in accordance with paragraph 1 of the formula of the invention for the case when the first 14 transient process correction circuit contains a first 16 p-n junction and a first 17 matching resistor connected in series, and the second 15 transient process correction circuit contains a second 18 p-n junction and a second 19 matching resistor connected in series.
[0009] The drawing in Fig. 3 shows a diagram of the claimed GaAs differential cascade of class AB in accordance with paragraph 1 of the formula of the invention for the case when the first 14 transient process correction circuit is made in the form of the first 23 additional capacitor, wherein the emitter of the first 12 additional bipolar transistor is connected to the first 5 power supply bus through the second 24 additional reference current source, the second 15 transient process correction circuit is made in the form of the second 25 additional capacitor, wherein the emitter of the second 13 additional bipolar transistor is connected to the first 5 power supply bus through the third 26 additional reference current source.
[0010] The drawing in Fig. 4 shows the claimed GaAs DC according to claim 1 of the formula of the invention for the case when the first 14 transient process correction circuit contains a first 34 additional correction capacitor and a first 35 additional correction resistor connected in parallel, and the second 15 transient process correction circuit contains a second 36 additional correction capacitor and a second 37 additional correction resistor connected in parallel.
[0011] The drawing in Fig. 5 shows an example of constructing an operational amplifier based on a DC according to paragraph 1 of the formula of the invention (Fig. 4) with a third embodiment of the transient process correction circuits 14 and 15. This circuit uses a current mirror on transistors 27, 28, an intermediate output stage on transistor 29, an auxiliary reference current source 30 and a buffer amplifier 31, the potential output of which 33 is the output of the operational amplifier.
[0012] The drawing Fig. 6 shows the claimed DC according to paragraph 2 of the invention formula.
[0013] The drawing Fig. 7 shows an example of constructing an operational amplifier based on the DC of Fig. 6 according to paragraph 2 of the formula of the invention.
[0014] The drawing in Fig. 8 shows the static mode of the transistors of the DC in Fig. 2 in the LTspice environment at t=27°C, I1=200 μA, R1=R2=1 kOhm, Rload1=Rload2=1 Ohm, Vcc=-Vee=5 V.
[0015] The drawing in Fig. 9 shows the transfer characteristic of the DC in Fig. 8 in the LTspice environment at t=27°C, I1=200 μA, R1=R2=500 Ohm, 1 kOhm, 2 kOhm, Rload1=Rload2=10 M, Vinp1=±5 V, Vcc=-Vee=5 V (with an increased scale of the input voltage).
[0016] The drawing in Fig. 10 shows the transfer characteristic of the DC in Fig. 8 in the LTspice environment at t=27°C, I1=200 μA, R1=R2=500 Ohm, 1 kOhm, 2 kOhm, Rload1=Rload2=10M, Vinp1=±1.5 V, Vcc=-Vee=5 V (with a reduced scale of the input voltage).
[0017] The drawing in Fig. 11 shows the static mode of the transistors of the DC circuit in the drawing in Fig. 6 in the LTspice environment at t=27°C, I0=20 μA, I1=200 μA, R1=R2=500 Ohm, R3=0 Ohm, Rload1=Rload2=1 Ohm, Vcc=-Vee=5 V.
[0018] The drawing in Fig. 12 shows the transfer characteristic of the DC in the drawing in Fig. 11 in the LTspice environment at t=27°C, I0=20 μA, I1=200 μA, R1=R2=500 Ohm, Rload1=Rload2=1 Ohm, Vcc=-Vee=5 V and different resistances of the resistor R3 (R3=0 Ohm, 20 kOhm, 100 kOhm).
[0019] The drawing in Fig. 13 shows the static mode of the op-amp circuit in the drawing in Fig. 7 in the LTspice environment at t=27°C, I1=200 μA, I2=20 μA, I3=180 μA, R1=R2=500 Ohm, R3=100 kOhm, Ck=1 pF, Vcc=-Vee=5 V.
[0020] The drawing in Fig. 14 shows the static mode of the operational amplifier transistors (Fig. 5) based on the differential cascade of Fig. 4 in the LTspice environment at t=27°C, I1=I2=200 μA, Ck=1 pF, R1=R2=100 kOhm, Ck1=Ck2=1 pF, Vcc=-Vee=5 V.
[0021] The drawing in Fig. 15 shows the logarithmic amplitude-frequency characteristic of the voltage gain of the op-amp in the drawing in Fig. 14 in the LTspice environment at t=27°C, I1=I2=200 μA, R1=R2=100 kOhm, Ck=1 pF, C к1 =С к2 =0, 1, 20, 50 pF, Vcc=-Vee=5 V.
[0022] The drawing in Fig. 16 shows the leading edge of the transient process in the op-amp of Fig. 14 in the LTspice environment at t=27°C, I1=14=200 μA, I2=I3=100 μA, Ck=1 pF, different values of the capacitance of the capacitors C к1 =С к2 =0, 1, 20, 50 pF, Vcc=-Vee=5 V.
[0023] The drawing in Fig. 17 shows the trailing edge of the transient process in the op-amp in the drawing in Fig. 14 in the LTspice environment at t=27°C, 11=14=200 μA, 12=13=100 μA, Ck=1 pF, different values of the capacitance of the capacitors C к1 =С к2 =0, 1, 20, 50 pF, Vcc=-Vee=5 V.
[0024] The gallium arsenide differential stage of class AB of Fig. 2 comprises first 1 and second 2 device inputs, first 3 and second 4 current outputs matched with the first 5 power supply bus, a first 6 input field-effect transistor, the gate of which is connected to the first 1 input of the device, a second 7 input field-effect transistor, the gate of which is connected to the second 2 input of the device, a first 8 output field-effect transistor, the source of which is connected to the drain of the first 6 input field-effect transistor, a second 9 output field-effect transistor, the source of which is connected to the drain of the second 7 input field-effect transistor, wherein the combined gates of the first 8 and second 9 output field-effect transistors are connected to the combined sources of the first 6 and second 7 input field-effect transistors, the combined sources of the first 6 and second 7 input field-effect transistors are connected to the second 10 power supply bus through the main 11 reference current source.The first 12 and second 13 additional bipolar transistors are introduced into the circuit, the base of the first 12 additional bipolar transistor is connected to the first 1 input of the device, its collector is connected to the second 10 bus of the power supply, and the emitter is connected to the source of the second 9 output field-effect transistor through the first 14 circuit of correction of the transient process, the base of the second 13 additional bipolar transistor is connected to the second 2 input of the device, its collector is connected to the second 10 bus of the power supply, and the emitter is connected to the source of the first 8 output field-effect transistor through the second 15 circuit of correction of the transient process, wherein the first 14 and second 15 circuits of the transient process have three variants of practical implementation: in the first variant of practical implementation (Fig.2) the first 14 transient correction circuit contains a first 16 p-n junction and a first 17 matching resistor connected in series, and the second 15 transient correction circuit contains a second 18 p-n junction and a second 19 matching resistor connected in series; in the second embodiment of practical implementation (Fig. 3), the first 14 transient correction circuit is made in the form of a first 23 additional capacitor, wherein the emitter of the first 12 additional bipolar transistor is connected to the first 5 power supply bus through the second 24 additional reference current source, the second 15 transient correction circuit is made in the form of a second 25 additional capacitor, wherein the emitter of the second 13 additional bipolar transistor is connected to the first 5 power supply bus through the third 26 additional reference current source; in the third embodiment of practical implementation (Fig.4) - the first 14 transient process correction circuit contains a first 34 additional correction capacitor and a first 35 additional correction resistor connected in parallel, and the second 15 transient process correction circuit contains a second 36 additional correction capacitor and a second 37 additional correction resistor connected in parallel.
[0025] In the drawing of Fig. 6, in accordance with paragraph 2 of the formula of the invention, the combined gates of the first (8) and second (9) output field-effect transistors are connected to the combined sources of the first (6) and second (7) input field-effect transistors through the first (20) additional resistor, wherein the combined sources of the first (6) and second (7) input field-effect transistors are connected to the base of the third (21) additional bipolar transistor, the emitter of which is connected to the first (5) power supply bus through the first (22) additional reference current source, and the collector is connected to the combined gates of the first (8) and second (9) output field-effect transistors.
[0026] In the drawing of Fig. 5, which illustrates an example of the inclusion of the proposed differential cascade in the structure of a high-speed op amp, auxiliary transistors 27, 28 and 29 are used, the emitters of which are connected to the first 5 bus of the power supply, and the collector of transistor 29 is connected to the second 10 bus of the power supply through an auxiliary current mirror 30 and is connected to the input of buffer amplifier 31, whose output 33 is connected to the base of auxiliary transistor 29 through a correction capacitor 32.
[0027] Let us consider the operation of the claimed differential cascade of class AB taking into account the results of its computer modeling, as well as the modeling of the op amp based on it, presented in the drawings of Fig. 9, Fig. 10, Fig. 12, Fig. 15, Fig. 16 and Fig. 17.
[0028] The static mode of the DC circuit of Fig. 2 is established by the reference current source 11. In this case, due to the construction of the first 14 and second 15 transient process correction circuits on the first 16 p-n junction, the first 17 matching resistor and the second 18 p-n junction and the second 19 matching resistor, the influence of the first 12 and second 13 additional bipolar transistors on the static mode is minimized (see Fig. 9, Fig. 10).
[0029] If a positive increment of the input differential voltage relative to input 2 is applied to input 1, this increment is transferred to the source circuit of the first 6 and second 7 input field-effect transistors, as well as to the gate circuit of the first 8 output field-effect transistor. As a result, the source and drain current of the first 8 output field-effect transistor increase, which creates an increment of current in the load R н1 (see Fig. 9, Fig. 10).
[0030] The differential cascade circuit in Fig. 11 and the results of its computer simulation in Fig. 12 show that by changing the resistance of resistor R3, it is possible to vary the dead zone on the pass characteristic (Fig. 12) within a wide range. This makes it possible to significantly reduce the influence of the dead zone ("shelf") of the pass characteristic on SR [9].
[0031] In the drawing of Fig. 4, in accordance with paragraph 1 of the formula of the invention, the first 14 and second 15 transient process correction circuits contain a first 34 additional correction capacitor, a first 35 additional correction resistor and a second 36 additional correction capacitor, a second 37 additional correction resistor.
[0032] The static mode of the op-amp of Fig. 5 is shown in the drawing of Fig. 14. In this case, the drawing of Fig. 15 shows the logarithmic amplitude-frequency characteristic of the voltage gain of the op-amp of Fig. 14, and the drawings of Fig. 16 and Fig. 17 show the leading (Fig. 16) and trailing (Fig. 17) edges of the transient process, from which it follows that in the op-amp with the proposed input stage the “average” value of SR increases from 174 V / μs to 667 V / μs. If the SR calculation is performed according to the formula as the maximum derivative of the op-amp output voltage, then the claimed circuit solutions ensure an increase in the op-amp response speed by more than an order of magnitude.
[0033] Thus, the proposed differential cascade has significant advantages in comparison with the DK prototype and operates in class AB mode, which allows increasing the speed of operational amplifiers based on it.
[0034] BIBLIOGRAPHICAL LIST
[0035] 1. Dvornikov O.V., Pavlyuchik A.A., Prokopenko N.N., Chekhovsky V.A., Kunz A.V., Chumakov V.E. Gallium arsenide analog base crystal / / Problems of developing promising micro- and nanoelectronic systems (MES). 2021. Issue 2. pp. 47-54. doi: 10.31114 / 2078-7707-2021-2-47-54
[0036] 2. W. Liu, D. Hill, D. Costa and J. S. Harris, "High-performance microwave AlGaAs-InGaAs Pnp HBT with high-DC current gain," in IEEE Microwave and Guided Wave Letters, vol. 2, no. 8, pp. 331-333, Aug. 1992, doi: 10.1109 / 75.153604.
[0037] 3. KW Kobayashi, DK Umemoto, JR Velebir, DC Streit and AK Oki, "Integrated complementary HBT microwave push-pull and Darlington amplifiers with PNP active loads," GaAs IC Symposium Technical Digest 1992, 1992, pp. 313-316, doi: 10.1109 / GAAS. 1992.247281.
[0038] 4. US Patent 4,121,169, Fig. 5, 1978
[0039] 5. Bugakova AV, Dvornikov O.V., Prokopenko N.N., Chekhovsky V.A., Kleimenkin D.V. Circuit design features of high-temperature analog microcircuits on GaN and GaAs transistors / / Bulletin of SFedU. Technical sciences. - 2024. - No. 2. - P 202-220. DOI 10.18522 / 2311-3103-2024-2-202-220, Fig. 24
[0040] 6. Sedra AS, Smith K.S. Microelectronic Circuits. Seventh Edition. New York, Oxford University Press, 2015, 1824 p.
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Claims
1. A gallium arsenide differential stage of class AB, comprising first (1) and second (2) device inputs, first (3) and second (4) current outputs matched with a first (5) power supply bus, a first (6) input field-effect transistor, the gate of which is connected to the first (1) device input, a second (7) input field-effect transistor, the gate of which is connected to the second (2) device input, a first (8) output field-effect transistor, the source of which is connected to the drain of the first (6) input field-effect transistor, a second (9) output field-effect transistor, the source of which is connected to the drain of the second (7) input field-effect transistor, wherein the combined gates of the first (8) and second (9) output field-effect transistors are connected to the combined sources of the first (6) and second (7) input field-effect transistors, the combined sources of the first (6) and second (7) input field-effect transistors are connected to the second (10) power supply bus through the main (11) source reference current, characterized in thatthat the first (12) and second (13) additional bipolar transistors are introduced into the circuit, the base of the first (12) additional bipolar transistor is connected to the first (1) input of the device, its collector is connected to the second (10) power supply bus, and the emitter is connected to the source of the second (9) output field-effect transistor through the first (14) transient correction circuit, the base of the second (13) additional bipolar transistor is connected to the second (2) input of the device, its collector is connected to the second (10) power supply bus, and the emitter is connected to the source of the first (8) output field-effect transistor through the second (15) transient correction circuit, wherein the first (14) and second (15) transient circuits have three variants of practical implementation: in the first variant of practical implementation, the first (14) transient correction circuit contains a first (16) p-n junction and a first (17) matching resistor connected in series,and the second (15) transient correction circuit comprises a series-connected second (18) p-n junction and a second (19) matching resistor; in the second embodiment of practical implementation, the first (14) transient correction circuit is implemented in the form of a first (23) additional capacitor, wherein the emitter of the first (12) additional bipolar transistor is connected to the first (5) power supply bus via the second (24) additional reference current source, the second (15) transient correction circuit is implemented in the form of a second (25) additional capacitor, wherein the emitter of the second (13) additional bipolar transistor is connected to the first (5) power supply bus via the third (26) additional reference current source; in the third embodiment of practical implementation, the first (14) transient correction circuit comprises a parallel-connected first (34) additional correction capacitor and a first (35) additional correction resistor,and the second (15) transient process correction circuit contains a second (36) additional correction capacitor and a second (37) additional correction resistor connected in parallel.
2. A gallium arsenide differential stage of class AB according to claim 1, characterized in that the combined gates of the first (8) and second (9) output field-effect transistors are connected to the combined sources of the first (6) and second (7) input field-effect transistors through the first (20) additional resistor, wherein the combined sources of the first (6) and second (7) input field-effect transistors are connected to the base of the third (21) additional bipolar transistor, the emitter of which is connected to the first (5) power supply bus through the first (22) additional reference current source, and the collector is connected to the combined gates of the first (8) and second (9) output field-effect transistors.