Method for simultaneously writing and reading data to / from storage device while simultaneously receiving and transmitting data

Abstract

FIELD: computer technology and information technology.SUBSTANCE: invention relates to designing solid-state storage devices. The method of recording with direct playback comprises: setting the parameters of the RX path, setting the logical block recording queue by writing the required sequence of logical blocks for recording and reading into the register, recording the number of logical blocks in the recording queue, writing the command to start recording into the storage device in the register, setting a certain bit value indicating the readiness of the device to receive the data stream along the RX path, feeding the incoming data stream to the RX path, the storage device storing the incoming data until the end of the logical block queue and transmitting them upon receipt of at least four logical blocks.EFFECT: writing some data while reading other data, as well as reading some data while writing other data, and thereby increasing the performance of the computing device.6 cl, 5 dwg

Description

[0001] Technical field

[0002] The invention relates to the field of constructing solid-state storage devices, namely to methods of recording and reading data to / from a storage device(s), and is aimed at solving the problem of simultaneously recording some data to a storage device and reading other data from the storage device.

[0003] Technology Level

[0004] Currently, most solid-state drives do not provide the ability to simultaneously read and write data, performing them alternately, which limits the characteristics of computing devices (systems) using solid-state drives for data storage.

[0005] One of the ways to improve the performance of computing devices (systems) is to simultaneously perform data reading and writing operations.

[0006] A known analogue is a method of operating a data storage device (RU 2677366 C1, G06F 12 / 14, published 2019.01.16), including: transmitting an encrypted command to control access from an independent access controller to the control and protection unit, after which the data is sequentially transmitted to the data integrity verification unit, where the results of diagnostics and integrity verification of the received data are recorded in an independent memory block, the received data is transmitted to the decryption unit, where the data is decrypted into an access control command to the memory array - NAND, and the command goes to the decision-making unit, from which the correct control command is transmitted to the block for recording correct commands, and the incorrect control command to the block for recording incorrect commands, and a record is made in the access log in an independent memory block, then the correct control command is transmitted to the command filtering unit,where the type of command is determined: to allow reading of information from the memory array or to allow writing of information to the memory array, then reading or writing of information from the memory array is allowed, and if the command contains permission to read from the memory array, then, using the control and protection unit, the memory array control unit is turned on with permission to only read data from the memory array and prohibit the possibility of writing, and if the command contains permission to access writing, then the control and protection unit turns on the memory array control unit with permission to only write data to the memory array, then, depending on the received command, the memory array control unit is turned on / off and again they go to the command reception unit to wait for a new command.

[0007] An analogue is known - a memory system and a method for operating it (US 11556276 B2, G06F 12 / 10, published 2023.01.17), including: putting commands received from the host in the first priority; putting commands from the first queue in the second queue and retrieving commands from the queue to a FIFO storage device; when the logical address corresponding to the write command, in response to which the software operation is performed, matches the logical address of the read command put in the first priority, delaying the operation of putting the read command in the second queue until the software operation is successfully completed; and determining whether to put a subsequent read command, which is put in the first priority after the read command, in the second priority, if putting the read command in the second queue is delayed.Provides for maintaining a list of logical addresses of write commands for which a software operation is performed and determining whether a read command should be placed in the second queue if placing a read command in the second queue is delayed, and determining whether subsequent read commands should be placed in the second queue.

[0008] The closest analogue is known – a method of writing data into memory based on 3D NAND flash memory (RU 2813620 C1, G06F 12 / 14, published 2024.02.14), including: a method for writing data to a memory based on 3D NAND flash memory, including searching for an entry point and writing data from a controller to 3D NAND flash memory, where the data is written in files, wherein at the beginning of file creation a file name is formed, the file is divided into parts the size of NAND blocks, where in the first page of each piece (part of the file written in one block) there is a file header with a link to the parent (previous part) and the descendant (next part), a subheader for data is allocated in the RAM of the controller, the size of the page, the size of the written data is fixed - the remainder of free pages in the bank is checked, the records are checked for Error Correction Code (ECC) errors, if there is a record with errors, this data bank is marked and a transition to a new entry point is made with the addition of a link to the next bank, and the header is saved by forming a copy of the initial header with a link to the parent.Several files are written and read simultaneously, the number of which is limited by the size of the microcontroller's RAM and the recording time requirement.

[0009] The disadvantage of the above solutions is: the inability to ensure the writing / reading of some data while reading / writing other data, which leads to low performance of the computing device.

[0010] The technical result of the invention is to provide the ability to write some data (for example, files) while reading other data, and vice versa - the ability to read some data while writing other data, and thereby increase the performance of the computing device (system), as well as to ensure an increase in the utilization factor of the channel bandwidth, and the overall performance of computing devices and systems using solid-state storage devices.

[0011] The disadvantages inherent in the prototypes considered are overcome in the proposed method of simultaneously writing and reading data to / from an information storage device(s), which can be implemented, for example, as part of high-load computing devices and systems for various purposes for data processing.

[0012] The technical result achieved is achieved by proposing a method for simultaneously recording and reading data from / to an information storage device(s), characterized in that the storage device receives and records data, reads and transmits the same data simultaneously, while:

[0013] a) initialization of the drive presentation layer structures from physical to logical (FTL), during which only polling of the drive status is allowed;

[0014] b) setting up the receiving path RX and transmitting path TX of the drive;

[0015] c) erasing blocks: for this, the block erasing queue is set by writing the erase_queue register array, and the number of blocks in the erase queue is written to the erase_queue_size register;

[0016] d) writing data to the drive: to do this, set the parameters of the RX receiving path, set the block writing queue by writing the required sequence of blocks for writing to the write_queue register array, and write the number of blocks in the write queue to the write_queue_size register, and start writing;

[0017] e) reading data from the storage device: to do this, set the parameters of the TX transmit path, set the block reading queue by writing the required sequence of blocks for reading into the read_queue register array, and write the number of blocks in the read queue into the read_queue_size register, and start reading:

[0018] f) recording with direct playback: for this, the parameters of the RX receiving path are set, the block writing queue is set by writing the required sequence of blocks for writing and reading to the write_queue register array, and the number of blocks in the write queue is written to the write_queue_size register, the command to start writing to the START_TRANSIT drive is written to the device_command register, the FLASH_Flags:Writing bit is read, where setting the bit to 1 indicates that the device is ready to receive a data stream along the RX path, the incoming data stream is fed to the RX path and the drive will store the incoming data until the end of the block queue and transmit them upon receipt of at least four logical blocks, and at step b), the following is performed: setting the parameters of the receiving and transmitting path in the transceiver registers, where the channel throughput, the number of the channel to be included, the buffer operating mode are specified in the parameters, the transceiver module is initialized by writing to the register device_command,set the parameters for checking the correctness of the high-speed interface packet fields for the receiver and transmitter, initialize the receiver and transmitter module by writing to the device_command register.

[0019] In a preferred embodiment, a read is started while a write is in progress, or a write is started while a read is in progress.

[0020] In the preferred embodiment, at step d), the following is performed: writing a command to begin writing the entire queue, START_WRITE, into the device_command register, writing a command to begin writing a section of the queue, START_WRITE_COMPOSE, into the device_command register, writing the index of the first file block in the queue to the param1 register, writing the number of pages of all file blocks to the param2 register, reading the FLASH_Flags:Writing bit, setting the bit to 1 indicates that the device is ready to receive a data stream along the RX path, feeding the incoming data stream to the RX path, and the drive stores the incoming data until the end of the block queue.

[0021] In the preferred embodiment, at step e), the following is performed: writing a command to begin reading the entire queue START_READ into the device_command register, and the drive controller will begin sending a data stream via the transmitting interface, writing a command to begin reading a section of the queue START_READ_COMPOSE into the device_command register, writing the index of the starting page of the file in the queue to the param1 register, the number of pages in the file to the param2 register, the file identifier to the param3 register, and the drive controller sends the data stream via the transmitting path TX.

[0022] In the preferred embodiment, step g) is carried out to read data via the redundant control interface (CI) of the storage controller; for this, the page number is set in the storage_meta_addr register, the START_META_READ CI read command is written to the device_command register, the contents of the storage_meta_data registers are read via the command interface, and the reading of data via the CI is performed page by page.

[0023] In the preferred embodiment, step h) is carried out: recording by the UI, for this purpose the contents of the storage_meta_data registers are written through the command interface, the page number is specified in the storage_meta_addr register, the START_META_WRITE UI recording command is written to the device_command register, and the recording of data by the UI is performed page by page, and is permitted only in the pages of previously erased blocks.

[0024] Comparison with other technical solutions shows that the proposed method has features that make it possible to achieve an improvement in the characteristics of computing devices (systems) in terms of the efficient use of the bandwidth of the communication channel with information storage devices.

[0025] The conducted analysis of the state of the art allows us to determine that the proposed technical solution is new and has an inventive level, and the possibility of its use in industry determines it as industrially applicable.

[0026] These and other aspects will become apparent and will be explained with reference to the drawings and the embodiment described hereinafter.

[0027] The invention is explained by the following graphic materials:

[0028] Fig. 1a – a diagram explaining the claimed method of simultaneous recording and reading of data, where a graph of the transitions of the KA for receiving data via TX and writing them to NAND is shown.

[0029] Fig. 1b is a diagram explaining the claimed method of simultaneous recording and reading of data, where a transition graph of the KA for reading data from NAND and transmitting data via TX is shown.

[0030] Fig. 1c is a diagram explaining the claimed method of simultaneous recording and reading of data, where the transition graph of the CA of the “Recording with direct playback” mode is shown.

[0031] Fig. 1d – a diagram explaining the claimed method of simultaneous recording and reading of data, where the transition graph of the embedded CA for reading and transmitting data is shown

[0032] Fig. 2 – structural diagram of the software and hardware implementation of the drive implementing the claimed method.

[0033] Implementation of the invention

[0034] The method for simultaneously writing and reading data involves the computing device (system) informing the storage device of the logical address space areas to be read and the logical address space areas to be written, and then beginning to write some data and read others. These data areas can be, for example, files of a file system supported by the computing device (system).

[0035] The claimed method can be hardware implemented in the device (100) shown in Fig. 2, which contains: a data storage controller (80) containing RAM (60), a data reception / recording channel (10), a data receiver (50), a data transmitter (70), a data transmission / reading channel (30), a control channel (20), and non-volatile memory (90).

[0036] The device (Fig. 2) operates as follows. The areas of the drive's logical address space to be written to are written by the computing device via the control channel to the drive controller's RAM. Areas to be read are written in a similar manner.

[0037] A device for simultaneously recording and reading data from / to an information storage device(s), implementing the method, contains an interconnected storage device controller, non-volatile memory, where the control channel, the receiving channel and the transmitting channel are separate physical channels of different types or of the same type or combined in different combinations, while there is the possibility of full-duplex data transmission.

[0038] The storage controller prepares the receiver to receive data and writes it to non-volatile memory as it arrives. It prepares the transmitter for data transmission, reads data from non-volatile memory, and sends it when the transmitter is ready. Simultaneous read and write operations to non-volatile memory are ensured by different physical addresses corresponding to areas of the logical address space defined by the computing device (system).

[0039] The drive simultaneously receives and writes data to be written, while reading and transmitting data to be read. To ensure maximum data read and write speeds, a "structural block" entity was introduced—a group of 64 physical blocks, one on each crystal. A structural block is an indivisible working unit and is assigned to a logical block accessible to a higher-level device. The assignment of structural blocks to logical blocks is performed by Flash Translation Layer (FTL) algorithms (the NAND FLASH (NF) non-volatile memory) representation layer from physical to logical.

[0040] In general, the claimed method is implemented as follows.

[0041] Initialization. Initialization of FTL structures, during which only polling of the drive status is allowed. After the FTL recovery time has elapsed, the drive is able to process all commands.

[0042] Setting up the receiving path.

[0043] Receive path setup algorithm:

[0044] 1. Set the parameters of the transmit-receive path in the transceiver registers. The parameters specify the channel bandwidth, the number of the channel to be enabled, and the elastic buffer operating mode.

[0045] 2. Initialize the transceiver module by writing the Setup Transceiver command to the device_command register.

[0046] 3. Set the parameters for checking the correctness of the high-speed interface packet fields for the receiver.

[0047] 4. Initialize the receiver module by writing the Setup Receiver command to the device_command register.

[0048] Setting up the transmission path.

[0049] Transmission path setup algorithm:

[0050] 1. Set the parameters of the transmit-receive path in the transceiver registers. The parameters specify the channel bandwidth, the number of the channel to be enabled, and the elastic buffer operating mode.

[0051] 2. Initialize the transceiver module by writing the Setup Transceiver command to the device_command register.

[0052] 3. Set the parameters for generating high-speed interface packet fields for the transmitter.

[0053] 4. Initialize the transmitter module by writing the Setup Transmitter command to the device_command register.

[0054] Erasing blocks in storage.

[0055] Block erasure algorithm:

[0056] 1. Set the block erase queue by writing to the erase_queue register array. Each register stores two logical block numbers (the register size is 32 bits, the block number size is 16 bits). The block number with the lower index is placed in the lower part of the register. The erase_queue_size register stores the number of blocks in the erase queue.

[0057] 2. In the device_command register, write the START_ERASE command to start erasing blocks.

[0058] 3. Wait for the "Ready" signal. During the erase process, the drive displays the "Erase in progress" status, followed by "Waiting." The approximate erase time for one logical block is 10 ms.

[0059] 4. Upon receiving the "Fault" signal, read the NAND_status_low and NAND_status_high registers.

[0060] Writing data to storage device.

[0061] Drive writing algorithm:

[0062] 1. Set the parameters of the RX receiving path.

[0063] 2. Set the block write queue by writing the required sequence of blocks to be written to the write_queue register array. The write_queue_size register is filled with the number of blocks in the write queue.

[0064] 3. Start recording:

[0065] a. Write the START_WRITE command to the device_command register to begin writing the entire queue.

[0066] b. Write the START_WRITE_COMPOSE command to start writing a section of the queue into the device_command register, the index of the first file block in the queue into the param1 register, and the number of pages of all file blocks into the param2 register.

[0067] 4. Read the FLASH_Flags:Writing bit. Setting this bit to 1 indicates the device is ready to receive a data stream via the RX path.

[0068] 5. Apply the incoming data stream to the RX path. The drive will store incoming data until the end of the block queue.

[0069] 6. If it is necessary to interrupt writing before the end of the queue or section, issue the STOP_WRITE command in the device_command register.

[0070] 7. Wait for the "Ready" signal, check for the FLASH_Flags:Writing bit to be cleared. Read the receiver statuses by reading the rx_counters registers. NAND write error diagnostics are not performed.

[0071] Writing data is only possible in pre-erased blocks. Writing to a block that has not been pre-erased will corrupt the data in that block. The master device must monitor the erase / write order.

[0072] Two data writing mechanisms are provided: writing the entire block queue and writing a portion of the block queue. In the first case, the data volume is specified in blocks, and the entire queue is processed with the START_WRITE command, after which it is emptied. In the second case, the data volume is specified in pages as a multiple of a block, the index (starting with zero) of the first block in the queue is specified, and the START_WRITE_COMPOSE command processes the specified portion of the queue. The queue remains unchanged, allowing another portion to be written.

[0073] Reading data from storage device.

[0074] Reading algorithm from storage device:

[0075] 1. Set the parameters of the TX transmit path.

[0076] 2. Set the block read queue by writing the required sequence of blocks to be read into the read_queue register array. Write the number of blocks in the read queue into the read_queue_size register.

[0077] 3. Start reading:

[0078] a. Write the START_READ command to the device_command register to begin reading the entire queue. The drive will begin sending a data stream over the transmit interface.

[0079] b. Write the START_READ_COMPOSE command to begin reading a section of the queue into the device_command register, the index of the starting page of the file in the queue into the param1 register, the number of pages in the file into the param2 register, and the file identifier into the param3 register (the starting page index is the product of the number of pages in the block and the number of blocks in the queue before the start of the section and the starting page of the file in the block). The drive will begin sending the data stream along the transmit path.

[0080] 4. If it is necessary to interrupt reading before the end of the queue or section, issue the STOP_READ command in the device_command register.

[0081] 5. Wait for the “Ready” signal, check that the FLASH_Flags:Reading bit is cleared.

[0082] 6. Check the value in the ecc_err_counter register. If it's 0, all data was read successfully. If not, troubleshooting read errors is required.

[0083] Readable pages must first be written. Reading unwritten pages will result in ECC errors in the read data.

[0084] Two data reading mechanisms are provided: reading the entire block queue and reading a portion of the block queue. In the first case, the data volume is specified in blocks, and the entire queue is processed with the START_READ command, after which it is emptied. In the second case, the data volume is specified in pages. The starting page of the file in the queue, the number of pages in the file, and the file identifier are specified, and the specified portion of the queue is processed with the START_READ_COMPOSE command. The queue remains unchanged, allowing another portion to be read.

[0085] Recording with direct playback.

[0086] Launch algorithm:

[0087] 1. Set the parameters of the RX receiving path.

[0088] 2. Set the block write queue by writing the required sequence of blocks to be written and read into the write_queue register array. The write_queue_size register is used to store the number of blocks in the write queue.

[0089] 3. In the device_command register, write the command to start writing to the drive START_TRANSIT.

[0090] 4. Read the FLASH_Flags:Writing bit. Setting this bit to 1 indicates the device is ready to receive a data stream via the RX interface.

[0091] 5. Apply the incoming data stream to the RX path. The drive will store incoming data until the end of the block queue and transmit it when at least four logical blocks have arrived.

[0092] 6. If you need to interrupt writing before the end of the queue, issue the STOP_WRITE_TRANSIT command in the device_command register. The drive will interrupt data writing and continue playing back the received data. If you need to stop both writing and reading, issue the STOP_TRANSIT command in the device_command register. The drive will interrupt both writing and playing back the data.

[0093] 7. Wait for the "Ready" signal, check that the FLASH_Flags:Reading bit is cleared. Read the receiver status by reading the rx_counters registers, and the ECC error count by reading the ecc_err_counter register.

[0094] Direct playback recording differs from standard recording in that it automatically initiates data transfer from logical blocks queued for recording. The drive's RAM capacity is insufficient to temporarily store even a single block of data, so received data is written to NAND. Data transfer begins after the first four logical blocks have been written.

[0095] Start test data generator.

[0096] The drive is equipped with a test data generator function, which can transmit a constant, a counter, and a pseudo-random sequence of numbers via the TX path.

[0097] Launch algorithm:

[0098] 1. Set the parameters of the TX transmit path.

[0099] 2. Set the generator operating mode by writing to the tx_control register.

[0100] 3. Set the initial value and generated data volume by writing the tx_generator_data, tx_generator_count, tx_generator_count_MSW registers.

[0101] 4. Start the transmission of test data by writing the START_DATA_GENERATOR command to the device_command register.

[0102] Reading data from UI (control interface).

[0103] Reading algorithm:

[0104] 1. Set the page number in the storage_meta_addr register.

[0105] 2. Write the START_META_READ reading command to the device_command register.

[0106] 3. Wait at least 300 µs, read the contents of the storage_meta_data registers via the command interface.

[0107] Reading data from the UI is performed page by page.

[0108] Registration by UI.

[0109] Recording algorithm:

[0110] 1. Write the contents of the storage_meta_data registers via the command interface.

[0111] 2. Set the page number in the storage_meta_addr register.

[0112] 3. Write the START_META_WRITE write command to the device_command register.

[0113] Recording data on the UI is also performed page by page, and is only allowed in pages of previously erased blocks.

[0114] The modes for simultaneously writing and reading data from / to the drive when receiving and writing data and reading and transmitting the same data simultaneously are described in more detail below.

[0115] After power is applied, the hardware bootloader starts. It retrieves the configuration and main firmware (MFI) of the drive from the NAND flash memory array and loads it into Tightly Coupled Memory (TCM – processor memory), after which it transfers control to the main firmware at the address specified by the configuration. The main firmware receives control at the entry point, clears the processor core registers, initializes the stack pointer, writes the exception entry point address to the register, calls the startup function, and then calls the FTL control function. During FTL initialization, commands to read the status register are executed (other commands are disabled).Next, the state array of the Logical Unit finite state machine (FSM) (logical device, memory crystal, logical devices on ONFI controllers (Open NAND-Flash Interface (interface for communication between the controller and NF memory) in the device) is initialized, and a copy of the Logical Block Addressing (LBA) table is searched. The drive is ready for operation.

[0116] Flash Translation Layer (the physical-to-logical representation layer of NF memory). The mapping of structural blocks to logical blocks is stored in the LBA table, each element of which contains the structural block number and a flag indicating the presence of physical block substitutions in this structural block. The table is built at power-on using the _ftl_init_lba_table function based on the values ​​written to the SpareArea of ​​the zero page of each physical block. When logical blocks are erased and NAND is formatted, the table is rebuilt using the NAND wear-leveling algorithm.

[0117] Information about faulty blocks and their replacement spare blocks is stored in the master block of each NAND crystal in the bad block table. Each individual NAND crystal can only perform one operation at a time: erase a block, receive data via the ONFI path for writing, write a page, read a page, and transmit read data via the ONFI path. Information about the tasks assigned to a crystal (erase, write, or read) is stored in the TLUN array.

[0118] FTL initialization is performed by the FTL_Init function every time the drive is powered on. This function resets the logical block table, read and write caches, master block table, and chip bad block count table, then searches for master blocks, reads bad block tables from the NAND, and initializes the logical block table. Implemented by two KAs, this allows the processor core to be distracted by processing status register read commands and requires a cyclic call until logical block table initialization is complete.

[0119] Register read and write commands are implemented via a call chain. Accumulator commands are executed by the following functions: start write, start composite write, start pass-through mode, start composite read, configure channel, configure receiver, configure transmitter, configure data generator, reset receiver, reset transmitter, and set initial value.

[0120] Commands to the flash memory controller are executed by the corresponding call chain. Commands: start erase, start pass-through mode, stop write in pass-through mode, stop pass-through mode, start write, start composite write, stop write, start read, start composite read, stop read, start write by UI, start read by UI, format NAND array.

[0121] To perform erase, write, and read operations, the upstream device must write the block numbers to be erased, written, or read into virtual registers. Upon commands to initiate erase, write, read, or "Write with Direct Playback" mode, these numbers are copied to the corresponding queue, represented by an array in the TCM. In addition to queues, ring buffers for writing and reading are also used.

[0122] As blocks are processed, the numbers of the next blocks are retrieved from the corresponding queue. When writing and reading data, in addition to queues, block caches are used—FTL_LBA_Cach structures that store the numbers of the physical blocks that make up the structural block assigned to the logical block being processed. Storing all the numbers of the physical blocks that make up the structural block is necessary because of the substitution of faulty blocks. When writing and reading, the first four logical blocks from the queue are cached, and when processing of a block is completed during writing or reading, the next one from the queue is cached.

[0123] Erase logical blocks.

[0124] A logical block is a chain of 64 physical blocks, one on each NAND crystal. The numbers of the physical blocks that make up the logical block are stored in the FTL_LBA_Table.LBA table.

[0125] Erasing a logical block is performed by the corresponding function. Before erasing each physical block, its age and the label of the logical block using this physical block are subtracted from the logical block's age. The physical block is then erased and the physical and logical ages, increased by one, are written to it.

[0126] The crystals are sorted by the end-to-end nLun numbers from 0 to 63, the first 32 are set for erasure immediately, the last 32 - after the completion of the earliest running erasure of the ongoing ones.

[0127] During the erase process, the success of the erase and the success of the age recording are checked. If unsuccessful, after completing the scan of all crystals, two more attempts are made to erase the problematic block and record the age. If the block is still not erased or if the age recording fails, the block is considered failed, a replacement is selected, and a new entry is added to the bad block table for the corresponding crystal.

[0128] Writing data.

[0129] Receiving data via the RX channel and writing to NAND is performed using RAM banks, DMA RX, and ADDR_MONITOR, ADDR_REPLACER, and WRITE_REPEATER blocks.

[0130] When a data write command is received, the RX data receiving and data writing to NAND are started, as shown in Fig. 1a.

[0131] As the DMA RX block transmits received data along the RX path to the RAM banks, ADDR_MONITOR is triggered. The values ​​it outputs are monitored by the CA implemented by the CheckWriting() function, which tasks the filled bank with writing the next page of data to the desired LUN. This task is processed by the LUN_Process() function. The ADDR_REPLACER block replaces the addresses accessed by DMA RX so that the data always ends up in a circular buffer assembled from RAM banks. The WRITE_REPEATER block restarts DMA RX as needed – DMA RX can only be started for 4 MB, then it must be restarted. WRITE_REPEATER can restart DMA RX as many times as necessary.

[0132] Reading data.

[0133] Data transfer from NAND to the TX path is performed using eight 16 KB RAM banks, DMA TX, and the ADDR_MONITOR and ADDR_REPLACER blocks. The WRITE_REPEATER block is not used in data transfer.

[0134] Data readiness control is used to transfer only data that has been reliably read from NAND.

[0135] When a data read command is received, the KA is started to read data from NAND and transmit data via TX, as shown in Fig.1b.

[0136] The KA copies logical block numbers from the queue to the ring buffer in 250-block chunks (the last chunk may be smaller), caches the logical blocks, pre-loads data pages using the nested KA, then determines the amount of data to be transferred and starts DMA TX of 128 KB of data, or less if less than 16 pages are requested rather than blocks.

[0137] Copying block numbers is divided into sections to avoid distracting the processor core from checking the address monitor flags indicating data received via RX for writing. The incoming stream cannot be paused, so data reception and writing are prioritized.

[0138] The remainder of the length of the transmitted data is stored in the length field of the DMA_TX_data structure

[0139] As the DMA TX block passes data through the RAM banks, ADDR_MONITOR is triggered. The units it sets are monitored by the CAM implemented by the CheckReading() function, which assigns the freed bank to the task of reading the next data page from the desired LUN and resets the buffer ready flag in the desired element of the DMA_TX_data.buffer_ready field. The ready flag is set by the LUN_Process() function upon completion of reading a data page from NAND, when the LUN CAM transitions from the LUN_DMA_RECEIVE state to the LUN_IDLE or LUN_WAIT state.

[0140] Buffers are assigned to data page read tasks during prefetching and reading, taking into account the read queue segment from an arbitrary page of an arbitrary logical block. The remainder of the arbitrary page number divided by the number of RAM buffers for data transfer is passed as an argument to the AddBuffRD function. This argument is taken into account when calculating the local variables SetPageAddr and nLun.

[0141] After the DMA TX block has completed transferring the specified amount of data, the TX_DMA_Handler() interrupt handler is triggered, which, if the remaining length is non-zero, calls the DMA TX restart function restart_DMA_TX().

[0142] The restart_DMA_TX() function implements a "greedy" algorithm: it initiates DMA TX on a ready data volume, taking into account the packet payload size. The ready volume is determined by the DMA_TX_data.buffer_ready field. If there is ready data, DMA TX is initiated on the ready volume and the fields of the DMA_TX_data structure are updated.

[0143] If there is no ready data, the DMA_TX_data.restart flag is set. The CA checks this flag; if it is present, the restart_DMA_TX() function is called again.

[0144] When transferring the remaining data, the DMA stops allocating free RAM banks for reading data pages. After waiting for a message indicating the completion of the remaining data transfer from the TX_DMA_Handler() interrupt handler, the DMA enters the IDLE state.

[0145] DMA TX transfers data in 64-byte transactions. ADDR_REPLACER replaces the addresses read by the DMA TX block. The ADDR_REPLACER increment is equal to the DMA TX transaction size, so only the transaction's starting address appears on the AXI bus after the address replacement. The ADDR_MONITOR block can monitor any address multiple of 4, but should be configured to monitor addresses multiple of 64.

[0146] Recording with direct playback.

[0147] Direct playback recording mode is described in two versions: the data write speed is higher than the data read speed and the data write speed is lower than the data read speed.

[0148] The pass-through mode is initiated by the START_TRANSIT command (code 0x17). The command is executed when no writing or reading is in progress, i.e., when the data write CAM is in the W_IDLE state and the read / transmit CAM is in the RT_IDLE state. The mode is implemented by the CAM as shown in Fig. 1c.

[0149] The KA copies logical block numbers from the write queue to the read and write ring buffers and caches the logical blocks. It receives the first four logical blocks and begins reading and transmitting the four received blocks. It then restarts reading and transmitting the remaining blocks. After receiving all blocks from the write queue, the KA transmits the remaining blocks.

[0150] Data reading is performed by the nested CA called from the WRITING_READING and READING states, as shown in Fig.1d.

[0151] The embedded CA handles data page prefetching, data reading and transmission, and restarting prefetching and reading when there are blocks ready to be transmitted. The CA uses the existing DMA TX restart algorithm and the existing CA for data page prefetching.

[0152] The main complexity of both satellites stems from the need to process end-to-end mode stop commands—complete mode stop and data write-only stop. A mode stop command can be issued at any time—during the reception of the first four blocks, during data reception and transmission, or during the transmission of the remaining data—so the state of the main and nested satellites must be analyzed in the stop command processing code.

[0153] When executing the START_TRANSIT command, the TransitModeActive flag is set, blocking the execution of normal write and read commands, including queue sections. The flag is cleared after the end-to-end mode is completed when the KA transitions from the READING to the IDLE state.

[0154] As the DMA TX block passes data through the RAM banks, ADDR_MONITOR is triggered. The ones it sets in the TDATA_MONITOR->INT.int_non_msked register are monitored by the CA implemented by the CheckTransit() function. Using the CheckTransit->Sub_FSM_reading->ProcessTXFlags->AddBuffRead->AddBuffRD chain, this function assigns the freed bank to the task of reading the next data page from the desired LUN and resets the buffer ready flag in the desired element of the DMA_TX_data.buffer_ready field, as well as the ones in the TDATA_MONITOR->INT.int_non_msked register. The RAM buffer ready flag is set by the LUN_Process() function upon completion of reading a data page from NAND upon the transition of the LUN CA from the LUN_DMA_RECEIVE state to the LUN_IDLE or LUN_WAIT state.

[0155] When the transfer of the last pages of the finished section of the queue is completed, in the RTS_FINISHING state, the ProcessTXFlags function is not called, therefore, after stopping TX_DMA, the address monitor flags are cleared directly by calling MONITOR_clear_interrupt_mask(TDATA_MONITOR, 0xFFFF0000UL).

[0156] The "Pass-through mode" command is processed similarly to the "Start reading" command, with the difference that in most cases there will be multiple data transfer starts - depending on the speed ratio and the write queue length.

[0157] Transferring data from the storage device in the "Record with direct playback" mode.

[0158] The write stop command (command code 0x18) stops data reception and writing, and all data received up to the time the command was received is transmitted. The command fills the remainder of the current RAM buffer with 0xFF, writes it to NAND, and then continues data transmission. If the command is received while the CAM is in the READING state, nothing happens, as the write has already completed.

[0159] The stop mode command (command code 0x19) stops data reception and transmission. The remainder of the current RAM buffer is filled with 0xFF values, written to NAND, and waits for the DMA TX block, which was launched to transfer the data portion read from NAND, to complete. Both queues and both logical block caches are cleared.

[0160] The CA of the "Record with immediate playback" mode is implemented by the CheckTransit function, a switch statement, the bodies of whose branches are extracted into separate functions. The condition for the transition from WRITING to WRITING_READING is the reception of four logical blocks: FSM_Transit.RX_blocks_cnt = RSS_LBA_SIZE. The condition for the transition from WRITING_READING to READING is the completion of the reception of all blocks from the write queue: (FTL_LBA_WriteCach.Count = 0) & (FLASH_CmdWritePipe.Count = 0). The condition for the transition from READING to IDLE is the termination of the nested CA. Transitions to and from the FINISHING state are performed upon receipt of stop commands for the cut-through mode. The transition from PREPARING to IDLE is more hypothetical than practical - it is very unlikely that a command to stop the mode will be received while the spacecraft is in the PREPARING state.

[0161] The embedded FSM is implemented by the Sub_FSM_reading function. In the data prefetch state, it calls the page prefetch FSM until the prefetch is complete, after which it starts DMA TX for the required data volume and initiates the DMA TX restart algorithm.

[0162] In the LOAD state, checks data transfer and starts reading pages using the ProcessTXFlags function and restarts DMA TX if necessary. The condition for transitioning to FINISH is transferring all blocks of the received section or all pages of the remainder of the received data: ((!FSM_Transit.volume_pages_flag) & (volume.block_qty = 0)) || (FSM_Transit.volume_pages_flag & ((page_count[READ_CNT] - (volume.initial_index * (PAGE_QTY * LUN_QTY))) = volume.pages_qty)).

[0163] In the FINISH state, restarts DMA TX if necessary and checks for completion of the remaining data transfer. If the remaining data has been transferred, clears the address monitor flags and determines whether there is more data to transfer. If not, transitions to IDLE; otherwise, transitions to PRELOAD. The condition for transition to PRELOAD is the presence of the "Record with immediate playback" mode flag, reception of all data and transfer of some data, or the presence of the stop flag and transfer of some pages, absence of the flag of completed page processing and the flag of exiting the WRITING state: TransitModeActive & (( (page_count[WRITE_CNT] == vr_write_queue_size * (PAGE_QTY * LUN_QTY) ) & (page_count[READ_CNT] < page_count[WRITE_CNT])) || (volume.stop & (page_count[READ_CNT] < page_count[WRITE_CNT])) ) & (!(volume.pages_processed || volume.early)).When this condition is met, the presence of the flag for working in pages or the reception of more than four logical blocks and not all pages yet read is checked; based on the results, the volume of the next transferred section in pages or blocks is determined - the fields volume.pages_qty, volume.block_qty, volume.initial_index are set.

[0164] Command processing is performed in the fc_iface_process function. It consists of checking for the presence of the "Record with immediate playback" mode flag TransitModeActive and the states of the "Record with immediate playback" mode CA and the nested CA. Stopping the recording checks the WRITING and WRITING_READING states, while a full stop also checks the READING state.

[0165] Using the proposed method also ensures uninterrupted writing and reading of data from / to the NAND drive with guaranteed information security.

[0166] The above-mentioned means implementing the steps of the proposed method may comprise firmware elements—a set of software instructions for which a repeatable signal set response is provided to a processing element, and the processing element is instructed to execute the software instructions. The software instructions may be loaded into the cache memory of an integrated circuit containing a processing element, which provides a fully integrated functional test device. The software instructions may be recorded on a computer-readable medium and may generate their own pseudo-random code streams for use in a device for writing and reading data from / to the storage medium. Examples of software instructions may include machine language codes, such as codes generated by a compiler, high-level language codes that can be executed using an interpreter, and the like.

[0167] In an embodiment of the invention, software and logic blocks, subblocks, and modules for recording and processing are used to implement the proposed method, for example, based on a programmable logic integrated circuit (FPGA) or a very large-scale integrated circuit (VLSI). It is obvious to those skilled in the art that the above-mentioned means can be implemented using a memory element that records the data being processed and a processing processor, which can be a general-purpose processor, a machine-readable medium, a finite-state machine or other hardware-programmable logic device, a discrete logic element or transistor logic, or any combination thereof, to perform the operations of the method described above.

[0168] The embodiments of the invention are not exhaustive and are given only for the purpose of explanation and confirmation of industrial applicability, and specialists in this field of technology are able to create alternative embodiments of it without departing from the scope of the formula, but within the scope of the invention reflected in the description.

Claims

1. A method for simultaneously writing and reading data to / from a storage device(s) while simultaneously receiving and transmitting data, characterized in that the storage device receives and writes data, reads and transmits the same data simultaneously, while: a) initialization of the physical-to-logical (FTL) drive presentation level structures, during which only drive status polling is allowed; b) erasing blocks: for this, a block erasing queue is set by writing an array of registers, and the number of blocks in the erasing queue is written into the register; c) set the parameters of the channel capacity, the number of the channel to be included, the buffer operating mode, initialize the register, set the parameters for checking the correctness of the interface packet fields for the receiver (RX) and transmitter (TX), initialize the receiver and transmitter modules by writing to the register; d) writing data to the storage device: for this, the parameters of the RX receiving path are set, the block writing queue is set by writing the required sequence of blocks for writing into the register array, and the number of blocks in the writing queue is written into the register, and the writing is started; e) reading data from the storage device: to do this, set the parameters of the TX transmit path, set the reading queue for logical blocks by recording the required sequence of logical blocks for reading and record the number of logical blocks in the reading queue, and start reading; f) recording with direct playback: for this, the parameters of the RX path are set, the logical block recording queue is set by writing the required sequence of logical blocks for recording and reading into the register, and the number of logical blocks in the recording queue is recorded, a command to start recording is written to the storage device in the register, bits are read, where setting a certain bit value indicates the readiness of the device to receive a data stream along the RX path, an incoming data stream is fed to the RX path, and the storage device stores the incoming data until the end of the logical block queue and transmits them upon receipt of at least four logical blocks.

2. The method according to claim 1, characterized in that reading is started during the writing being performed or writing is started during the reading being performed.

3. The method according to paragraph 1, characterized in that at step d) additionally: a command to begin recording the entire queue is written into the register, a command to begin recording a section of the queue, the index of the first file block in the queue, and the number of pages of all file blocks are written into the register, bits are read, the bit is set to a certain value that indicates the readiness of the device to receive a data stream along the RX path, an incoming data stream is fed to the RX path, and the drive stores the incoming data until the end of the logical block queue.

4. The method according to paragraph 1, characterized in that at step e) additionally: a command to begin reading the entire queue is written into the register and the drive controller begins sending the data stream along the TX path, a command to begin reading a section of the queue is written into the register, and the index of the starting page of the file in the queue, the number of pages in the file, and the file identifier.

5. The method according to any one of paragraphs 1-4, characterized in that step g) of reading data via the redundant control interface (CI) of the drive controller is additionally carried out, for this purpose the page number is set in the register, a read command is written via the CI, the contents of the registers are read via the command interface, and the reading of data via the CI is performed page by page.

6. The method according to any one of paragraphs 1-5, characterized in that the step h) of recording according to the UI is additionally carried out; for this, the contents of the registers are recorded via the command interface, the page number in the register is specified, the command for recording according to the UI is recorded in the register, and the recording of data according to the UI is performed page by page.

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